[linux-2.6-block.git] / drivers / pwm / pwm-atmel-hlcdc.c

/*
 * Copyright (C) 2014 Free Electrons
 * Copyright (C) 2014 Atmel
 *
 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/atmel-hlcdc.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/regmap.h>

#define ATMEL_HLCDC_PWMCVAL_MASK	GENMASK(15, 8)
#define ATMEL_HLCDC_PWMCVAL(x)		(((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
#define ATMEL_HLCDC_PWMPOL		BIT(4)
#define ATMEL_HLCDC_PWMPS_MASK		GENMASK(2, 0)
#define ATMEL_HLCDC_PWMPS_MAX		0x6
#define ATMEL_HLCDC_PWMPS(x)		((x) & ATMEL_HLCDC_PWMPS_MASK)

struct atmel_hlcdc_pwm_errata {
	bool slow_clk_erratum;
	bool div1_clk_erratum;
};

struct atmel_hlcdc_pwm {
	struct pwm_chip chip;
	struct atmel_hlcdc *hlcdc;
	struct clk *cur_clk;
	const struct atmel_hlcdc_pwm_errata *errata;
};

static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct atmel_hlcdc_pwm, chip);
}

static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
				  struct pwm_device *pwm,
				  int duty_ns, int period_ns)
{
	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	struct atmel_hlcdc *hlcdc = chip->hlcdc;
	struct clk *new_clk = hlcdc->slow_clk;
	u64 pwmcval = duty_ns * 256;
	unsigned long clk_freq;
	u64 clk_period_ns;
	u32 pwmcfg;
	int pres;

	if (!chip->errata || !chip->errata->slow_clk_erratum) {
		clk_freq = clk_get_rate(new_clk);
		clk_period_ns = (u64)NSEC_PER_SEC * 256;
		do_div(clk_period_ns, clk_freq);
	}

	/* Errata: cannot use slow clk on some IP revisions */
	if ((chip->errata && chip->errata->slow_clk_erratum) ||
	    clk_period_ns > period_ns) {
		new_clk = hlcdc->sys_clk;
		clk_freq = clk_get_rate(new_clk);
		clk_period_ns = (u64)NSEC_PER_SEC * 256;
		do_div(clk_period_ns, clk_freq);
	}

	for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
		/* Errata: cannot divide by 1 on some IP revisions */
		if (!pres && chip->errata && chip->errata->div1_clk_erratum)
			continue;

		if ((clk_period_ns << pres) >= period_ns)
			break;
	}

	if (pres > ATMEL_HLCDC_PWMPS_MAX)
		return -EINVAL;

	pwmcfg = ATMEL_HLCDC_PWMPS(pres);

	if (new_clk != chip->cur_clk) {
		u32 gencfg = 0;
		int ret;

		ret = clk_prepare_enable(new_clk);
		if (ret)
			return ret;

		clk_disable_unprepare(chip->cur_clk);
		chip->cur_clk = new_clk;

		if (new_clk == hlcdc->sys_clk)
			gencfg = ATMEL_HLCDC_CLKPWMSEL;

		ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(0),
					 ATMEL_HLCDC_CLKPWMSEL, gencfg);
		if (ret)
			return ret;
	}

	do_div(pwmcval, period_ns);

	/*
	 * The PWM duty cycle is configurable from 0/256 to 255/256 of the
	 * period cycle. Hence we can't set a duty cycle occupying the
	 * whole period cycle if we're asked to.
	 * Set it to 255 if pwmcval is greater than 256.
	 */
	if (pwmcval > 255)
		pwmcval = 255;

	pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);

	return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
				  ATMEL_HLCDC_PWMCVAL_MASK |
				  ATMEL_HLCDC_PWMPS_MASK,
				  pwmcfg);
}

static int atmel_hlcdc_pwm_set_polarity(struct pwm_chip *c,
					struct pwm_device *pwm,
					enum pwm_polarity polarity)
{
	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	struct atmel_hlcdc *hlcdc = chip->hlcdc;
	u32 cfg = 0;

	if (polarity == PWM_POLARITY_NORMAL)
		cfg = ATMEL_HLCDC_PWMPOL;

	return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
				  ATMEL_HLCDC_PWMPOL, cfg);
}

static int atmel_hlcdc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
{
	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	struct atmel_hlcdc *hlcdc = chip->hlcdc;
	u32 status;
	int ret;

	ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PWM);
	if (ret)
		return ret;

	while (true) {
		ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
		if (ret)
			return ret;

		if ((status & ATMEL_HLCDC_PWM) != 0)
			break;

		usleep_range(1, 10);
	}

	return 0;
}

static void atmel_hlcdc_pwm_disable(struct pwm_chip *c,
				    struct pwm_device *pwm)
{
	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	struct atmel_hlcdc *hlcdc = chip->hlcdc;
	u32 status;
	int ret;

	ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PWM);
	if (ret)
		return;

	while (true) {
		ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
		if (ret)
			return;

		if ((status & ATMEL_HLCDC_PWM) == 0)
			break;

		usleep_range(1, 10);
	}
}

static const struct pwm_ops atmel_hlcdc_pwm_ops = {
	.config = atmel_hlcdc_pwm_config,
	.set_polarity = atmel_hlcdc_pwm_set_polarity,
	.enable = atmel_hlcdc_pwm_enable,
	.disable = atmel_hlcdc_pwm_disable,
	.owner = THIS_MODULE,
};

static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
	.slow_clk_erratum = true,
};

static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
	.div1_clk_erratum = true,
};

static const struct of_device_id atmel_hlcdc_dt_ids[] = {
	{
		.compatible = "atmel,at91sam9x5-hlcdc",
		.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
	},
	{
		.compatible = "atmel,sama5d3-hlcdc",
		.data = &atmel_hlcdc_pwm_sama5d3_errata,
	},
	{ /* sentinel */ },
};

static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct device *dev = &pdev->dev;
	struct atmel_hlcdc_pwm *chip;
	struct atmel_hlcdc *hlcdc;
	int ret;

	hlcdc = dev_get_drvdata(dev->parent);

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	ret = clk_prepare_enable(hlcdc->periph_clk);
	if (ret)
		return ret;

	match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
	if (match)
		chip->errata = match->data;

	chip->hlcdc = hlcdc;
	chip->chip.ops = &atmel_hlcdc_pwm_ops;
	chip->chip.dev = dev;
	chip->chip.base = -1;
	chip->chip.npwm = 1;
	chip->chip.of_xlate = of_pwm_xlate_with_flags;
	chip->chip.of_pwm_n_cells = 3;
	chip->chip.can_sleep = 1;

	ret = pwmchip_add(&chip->chip);
	if (ret) {
		clk_disable_unprepare(hlcdc->periph_clk);
		return ret;
	}

	platform_set_drvdata(pdev, chip);

	return 0;
}

static int atmel_hlcdc_pwm_remove(struct platform_device *pdev)
{
	struct atmel_hlcdc_pwm *chip = platform_get_drvdata(pdev);
	int ret;

	ret = pwmchip_remove(&chip->chip);
	if (ret)
		return ret;

	clk_disable_unprepare(chip->hlcdc->periph_clk);

	return 0;
}

static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
	{ .compatible = "atmel,hlcdc-pwm" },
	{ /* sentinel */ },
};

static struct platform_driver atmel_hlcdc_pwm_driver = {
	.driver = {
		.name = "atmel-hlcdc-pwm",
		.of_match_table = atmel_hlcdc_pwm_dt_ids,
	},
	.probe = atmel_hlcdc_pwm_probe,
	.remove = atmel_hlcdc_pwm_remove,
};
module_platform_driver(atmel_hlcdc_pwm_driver);

MODULE_ALIAS("platform:atmel-hlcdc-pwm");
MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2b4984be BB	1	/*
	2	* Copyright (C) 2014 Free Electrons
	3	* Copyright (C) 2014 Atmel
	4	*
	5	* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/clk.h>
	21	#include <linux/delay.h>
	22	#include <linux/mfd/atmel-hlcdc.h>
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/pwm.h>
	26	#include <linux/regmap.h>
	27
	28	#define ATMEL_HLCDC_PWMCVAL_MASK GENMASK(15, 8)
	29	#define ATMEL_HLCDC_PWMCVAL(x) (((x) << 8) & ATMEL_HLCDC_PWMCVAL_MASK)
	30	#define ATMEL_HLCDC_PWMPOL BIT(4)
	31	#define ATMEL_HLCDC_PWMPS_MASK GENMASK(2, 0)
	32	#define ATMEL_HLCDC_PWMPS_MAX 0x6
	33	#define ATMEL_HLCDC_PWMPS(x) ((x) & ATMEL_HLCDC_PWMPS_MASK)
	34
39e046f2 BB	35	struct atmel_hlcdc_pwm_errata {
	36	bool slow_clk_erratum;
	37	bool div1_clk_erratum;
	38	};
	39
2b4984be BB	40	struct atmel_hlcdc_pwm {
	41	struct pwm_chip chip;
	42	struct atmel_hlcdc *hlcdc;
	43	struct clk *cur_clk;
39e046f2	44	const struct atmel_hlcdc_pwm_errata *errata;
2b4984be BB	45	};
	46
	47	static inline struct atmel_hlcdc_pwm to_atmel_hlcdc_pwm(struct pwm_chip chip)
	48	{
	49	return container_of(chip, struct atmel_hlcdc_pwm, chip);
	50	}
	51
	52	static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
	53	struct pwm_device *pwm,
	54	int duty_ns, int period_ns)
	55	{
	56	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	57	struct atmel_hlcdc *hlcdc = chip->hlcdc;
	58	struct clk *new_clk = hlcdc->slow_clk;
	59	u64 pwmcval = duty_ns * 256;
	60	unsigned long clk_freq;
	61	u64 clk_period_ns;
	62	u32 pwmcfg;
	63	int pres;
	64
39e046f2 BB	65	if (!chip->errata \|\| !chip->errata->slow_clk_erratum) {
	66	clk_freq = clk_get_rate(new_clk);
	67	clk_period_ns = (u64)NSEC_PER_SEC * 256;
	68	do_div(clk_period_ns, clk_freq);
	69	}
2b4984be	70
39e046f2 BB	71	/* Errata: cannot use slow clk on some IP revisions */
	72	if ((chip->errata && chip->errata->slow_clk_erratum) \|\|
	73	clk_period_ns > period_ns) {
2b4984be BB	74	new_clk = hlcdc->sys_clk;
	75	clk_freq = clk_get_rate(new_clk);
	76	clk_period_ns = (u64)NSEC_PER_SEC * 256;
	77	do_div(clk_period_ns, clk_freq);
	78	}
	79
39e046f2 BB	80	for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
	81	/* Errata: cannot divide by 1 on some IP revisions */
	82	if (!pres && chip->errata && chip->errata->div1_clk_erratum)
	83	continue;
	84
2b4984be BB	85	if ((clk_period_ns << pres) >= period_ns)
2b4984be BB	86	break;
39e046f2	87	}
2b4984be BB	88
	89	if (pres > ATMEL_HLCDC_PWMPS_MAX)
	90	return -EINVAL;
	91
	92	pwmcfg = ATMEL_HLCDC_PWMPS(pres);
	93
	94	if (new_clk != chip->cur_clk) {
	95	u32 gencfg = 0;
	96	int ret;
	97
	98	ret = clk_prepare_enable(new_clk);
	99	if (ret)
	100	return ret;
	101
	102	clk_disable_unprepare(chip->cur_clk);
	103	chip->cur_clk = new_clk;
	104
	105	if (new_clk == hlcdc->sys_clk)
	106	gencfg = ATMEL_HLCDC_CLKPWMSEL;
	107
	108	ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(0),
	109	ATMEL_HLCDC_CLKPWMSEL, gencfg);
	110	if (ret)
	111	return ret;
	112	}
	113
	114	do_div(pwmcval, period_ns);
	115
	116	/*
	117	* The PWM duty cycle is configurable from 0/256 to 255/256 of the
	118	* period cycle. Hence we can't set a duty cycle occupying the
	119	* whole period cycle if we're asked to.
	120	* Set it to 255 if pwmcval is greater than 256.
	121	*/
	122	if (pwmcval > 255)
	123	pwmcval = 255;
	124
	125	pwmcfg \|= ATMEL_HLCDC_PWMCVAL(pwmcval);
	126
	127	return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
	128	ATMEL_HLCDC_PWMCVAL_MASK \|
	129	ATMEL_HLCDC_PWMPS_MASK,
	130	pwmcfg);
	131	}
	132
	133	static int atmel_hlcdc_pwm_set_polarity(struct pwm_chip *c,
	134	struct pwm_device *pwm,
	135	enum pwm_polarity polarity)
	136	{
	137	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	138	struct atmel_hlcdc *hlcdc = chip->hlcdc;
	139	u32 cfg = 0;
	140
	141	if (polarity == PWM_POLARITY_NORMAL)
	142	cfg = ATMEL_HLCDC_PWMPOL;
	143
	144	return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
	145	ATMEL_HLCDC_PWMPOL, cfg);
	146	}
	147
	148	static int atmel_hlcdc_pwm_enable(struct pwm_chip c, struct pwm_device pwm)
	149	{
	150	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
	151	struct atmel_hlcdc *hlcdc = chip->hlcdc;
152	u32 status;
153	int ret;
154
155	ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PWM);
156	if (ret)
157	return ret;
158
159	while (true) {
160	ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
161	if (ret)
162	return ret;
163
164	if ((status & ATMEL_HLCDC_PWM) != 0)
165	break;
166
167	usleep_range(1, 10);
168	}
169
170	return 0;
171	}
172
173	static void atmel_hlcdc_pwm_disable(struct pwm_chip *c,
174	struct pwm_device *pwm)
175	{
176	struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
177	struct atmel_hlcdc *hlcdc = chip->hlcdc;
178	u32 status;
179	int ret;
180
181	ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PWM);
182	if (ret)
183	return;
184
185	while (true) {
186	ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
187	if (ret)
188	return;
189
190	if ((status & ATMEL_HLCDC_PWM) == 0)
191	break;
192
193	usleep_range(1, 10);
194	}
195	}
196
197	static const struct pwm_ops atmel_hlcdc_pwm_ops = {
198	.config = atmel_hlcdc_pwm_config,
199	.set_polarity = atmel_hlcdc_pwm_set_polarity,
200	.enable = atmel_hlcdc_pwm_enable,
201	.disable = atmel_hlcdc_pwm_disable,
202	.owner = THIS_MODULE,
203	};
204
39e046f2 BB	205	static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_at91sam9x5_errata = {
	206	.slow_clk_erratum = true,
	207	};
	208
	209	static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = {
	210	.div1_clk_erratum = true,
	211	};
	212
	213	static const struct of_device_id atmel_hlcdc_dt_ids[] = {
	214	{
	215	.compatible = "atmel,at91sam9x5-hlcdc",
	216	.data = &atmel_hlcdc_pwm_at91sam9x5_errata,
	217	},
	218	{
	219	.compatible = "atmel,sama5d3-hlcdc",
	220	.data = &atmel_hlcdc_pwm_sama5d3_errata,
	221	},
	222	{ /* sentinel */ },
	223	};
	224
2b4984be BB	225	static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
2b4984be BB	226	{
39e046f2	227	const struct of_device_id *match;
2b4984be BB	228	struct device *dev = &pdev->dev;
	229	struct atmel_hlcdc_pwm *chip;
	230	struct atmel_hlcdc *hlcdc;
	231	int ret;
	232
	233	hlcdc = dev_get_drvdata(dev->parent);
	234
	235	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	236	if (!chip)
	237	return -ENOMEM;
	238
	239	ret = clk_prepare_enable(hlcdc->periph_clk);
	240	if (ret)
	241	return ret;
	242
39e046f2 BB	243	match = of_match_node(atmel_hlcdc_dt_ids, dev->parent->of_node);
	244	if (match)
	245	chip->errata = match->data;
	246
2b4984be BB	247	chip->hlcdc = hlcdc;
	248	chip->chip.ops = &atmel_hlcdc_pwm_ops;
	249	chip->chip.dev = dev;
	250	chip->chip.base = -1;
	251	chip->chip.npwm = 1;
	252	chip->chip.of_xlate = of_pwm_xlate_with_flags;
	253	chip->chip.of_pwm_n_cells = 3;
	254	chip->chip.can_sleep = 1;
	255
	256	ret = pwmchip_add(&chip->chip);
	257	if (ret) {
	258	clk_disable_unprepare(hlcdc->periph_clk);
	259	return ret;
	260	}
	261
	262	platform_set_drvdata(pdev, chip);
	263
	264	return 0;
	265	}
	266
	267	static int atmel_hlcdc_pwm_remove(struct platform_device *pdev)
	268	{
	269	struct atmel_hlcdc_pwm *chip = platform_get_drvdata(pdev);
	270	int ret;
	271
	272	ret = pwmchip_remove(&chip->chip);
	273	if (ret)
	274	return ret;
	275
	276	clk_disable_unprepare(chip->hlcdc->periph_clk);
	277
	278	return 0;
	279	}
	280
	281	static const struct of_device_id atmel_hlcdc_pwm_dt_ids[] = {
	282	{ .compatible = "atmel,hlcdc-pwm" },
	283	{ /* sentinel */ },
	284	};
	285
	286	static struct platform_driver atmel_hlcdc_pwm_driver = {
	287	.driver = {
	288	.name = "atmel-hlcdc-pwm",
	289	.of_match_table = atmel_hlcdc_pwm_dt_ids,
	290	},
	291	.probe = atmel_hlcdc_pwm_probe,
	292	.remove = atmel_hlcdc_pwm_remove,
	293	};
	294	module_platform_driver(atmel_hlcdc_pwm_driver);
	295
	296	MODULE_ALIAS("platform:atmel-hlcdc-pwm");
	297	MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
	298	MODULE_DESCRIPTION("Atmel HLCDC PWM driver");
	299	MODULE_LICENSE("GPL v2");