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af873fce | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f0f05b1c AM |
2 | /* |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
5 | * Author: Arun R Murthy <arun.murthy@stericsson.com> | |
f0f05b1c AM |
6 | */ |
7 | #include <linux/err.h> | |
8 | #include <linux/platform_device.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/pwm.h> | |
f0f05b1c | 11 | #include <linux/mfd/abx500.h> |
ee66e653 | 12 | #include <linux/mfd/abx500/ab8500.h> |
eb12a679 | 13 | #include <linux/module.h> |
f0f05b1c AM |
14 | |
15 | /* | |
16 | * PWM Out generators | |
17 | * Bank: 0x10 | |
18 | */ | |
19 | #define AB8500_PWM_OUT_CTRL1_REG 0x60 | |
20 | #define AB8500_PWM_OUT_CTRL2_REG 0x61 | |
21 | #define AB8500_PWM_OUT_CTRL7_REG 0x66 | |
22 | ||
6173f8f4 TR |
23 | struct ab8500_pwm_chip { |
24 | struct pwm_chip chip; | |
eb41f334 | 25 | unsigned int hwid; |
f0f05b1c AM |
26 | }; |
27 | ||
eb41f334 UKK |
28 | static struct ab8500_pwm_chip *ab8500_pwm_from_chip(struct pwm_chip *chip) |
29 | { | |
30 | return container_of(chip, struct ab8500_pwm_chip, chip); | |
31 | } | |
32 | ||
acf3402d UKK |
33 | static int ab8500_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
34 | const struct pwm_state *state) | |
f0f05b1c | 35 | { |
acf3402d | 36 | int ret; |
f0f05b1c | 37 | u8 reg; |
acf3402d | 38 | unsigned int higher_val, lower_val; |
eb41f334 | 39 | struct ab8500_pwm_chip *ab8500 = ab8500_pwm_from_chip(chip); |
acf3402d UKK |
40 | |
41 | if (state->polarity != PWM_POLARITY_NORMAL) | |
42 | return -EINVAL; | |
43 | ||
44 | if (!state->enabled) { | |
45 | ret = abx500_mask_and_set_register_interruptible(chip->dev, | |
46 | AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, | |
eb41f334 | 47 | 1 << ab8500->hwid, 0); |
acf3402d UKK |
48 | |
49 | if (ret < 0) | |
50 | dev_err(chip->dev, "%s: Failed to disable PWM, Error %d\n", | |
51 | pwm->label, ret); | |
52 | return ret; | |
53 | } | |
f0f05b1c AM |
54 | |
55 | /* | |
56 | * get the first 8 bits that are be written to | |
57 | * AB8500_PWM_OUT_CTRL1_REG[0:7] | |
58 | */ | |
acf3402d | 59 | lower_val = state->duty_cycle & 0x00FF; |
f0f05b1c AM |
60 | /* |
61 | * get bits [9:10] that are to be written to | |
62 | * AB8500_PWM_OUT_CTRL2_REG[0:1] | |
63 | */ | |
acf3402d | 64 | higher_val = ((state->duty_cycle & 0x0300) >> 8); |
f0f05b1c | 65 | |
eb41f334 | 66 | reg = AB8500_PWM_OUT_CTRL1_REG + (ab8500->hwid * 2); |
f0f05b1c | 67 | |
6173f8f4 | 68 | ret = abx500_set_register_interruptible(chip->dev, AB8500_MISC, |
f0f05b1c AM |
69 | reg, (u8)lower_val); |
70 | if (ret < 0) | |
71 | return ret; | |
acf3402d | 72 | |
6173f8f4 | 73 | ret = abx500_set_register_interruptible(chip->dev, AB8500_MISC, |
f0f05b1c | 74 | (reg + 1), (u8)higher_val); |
acf3402d UKK |
75 | if (ret < 0) |
76 | return ret; | |
f0f05b1c | 77 | |
6173f8f4 | 78 | ret = abx500_mask_and_set_register_interruptible(chip->dev, |
f0f05b1c | 79 | AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, |
eb41f334 | 80 | 1 << ab8500->hwid, 1 << ab8500->hwid); |
f0f05b1c | 81 | if (ret < 0) |
622fc5d4 | 82 | dev_err(chip->dev, "%s: Failed to enable PWM, Error %d\n", |
f0f05b1c | 83 | pwm->label, ret); |
f0f05b1c | 84 | |
acf3402d | 85 | return ret; |
f0f05b1c | 86 | } |
f0f05b1c | 87 | |
6173f8f4 | 88 | static const struct pwm_ops ab8500_pwm_ops = { |
acf3402d | 89 | .apply = ab8500_pwm_apply, |
fa0abee9 | 90 | .owner = THIS_MODULE, |
6173f8f4 | 91 | }; |
f0f05b1c | 92 | |
3e9fe83d | 93 | static int ab8500_pwm_probe(struct platform_device *pdev) |
f0f05b1c | 94 | { |
6173f8f4 TR |
95 | struct ab8500_pwm_chip *ab8500; |
96 | int err; | |
97 | ||
eb41f334 UKK |
98 | if (pdev->id < 1 || pdev->id > 31) |
99 | return dev_err_probe(&pdev->dev, EINVAL, "Invalid device id %d\n", pdev->id); | |
100 | ||
f0f05b1c AM |
101 | /* |
102 | * Nothing to be done in probe, this is required to get the | |
103 | * device which is required for ab8500 read and write | |
104 | */ | |
482467ad | 105 | ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL); |
a2fc1db6 | 106 | if (ab8500 == NULL) |
f0f05b1c | 107 | return -ENOMEM; |
6173f8f4 TR |
108 | |
109 | ab8500->chip.dev = &pdev->dev; | |
110 | ab8500->chip.ops = &ab8500_pwm_ops; | |
6173f8f4 | 111 | ab8500->chip.npwm = 1; |
eb41f334 | 112 | ab8500->hwid = pdev->id - 1; |
6173f8f4 | 113 | |
14ac9e17 | 114 | err = devm_pwmchip_add(&pdev->dev, &ab8500->chip); |
482467ad | 115 | if (err < 0) |
2e978a45 | 116 | return dev_err_probe(&pdev->dev, err, "Failed to add pwm chip\n"); |
6173f8f4 TR |
117 | |
118 | dev_dbg(&pdev->dev, "pwm probe successful\n"); | |
6173f8f4 | 119 | |
f0f05b1c AM |
120 | return 0; |
121 | } | |
122 | ||
123 | static struct platform_driver ab8500_pwm_driver = { | |
124 | .driver = { | |
125 | .name = "ab8500-pwm", | |
f0f05b1c AM |
126 | }, |
127 | .probe = ab8500_pwm_probe, | |
f0f05b1c | 128 | }; |
6173f8f4 | 129 | module_platform_driver(ab8500_pwm_driver); |
f0f05b1c | 130 | |
f0f05b1c AM |
131 | MODULE_AUTHOR("Arun MURTHY <arun.murthy@stericsson.com>"); |
132 | MODULE_DESCRIPTION("AB8500 Pulse Width Modulation Driver"); | |
37b7bf67 | 133 | MODULE_ALIAS("platform:ab8500-pwm"); |
f0f05b1c | 134 | MODULE_LICENSE("GPL v2"); |