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a7e1abad JL |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* Copyright (c) 2020 Facebook */ | |
3 | ||
1132bb29 | 4 | #include <linux/bits.h> |
a7e1abad JL |
5 | #include <linux/err.h> |
6 | #include <linux/kernel.h> | |
7 | #include <linux/module.h> | |
f67bf662 | 8 | #include <linux/debugfs.h> |
a7e1abad JL |
9 | #include <linux/init.h> |
10 | #include <linux/pci.h> | |
773bda96 JL |
11 | #include <linux/serial_8250.h> |
12 | #include <linux/clkdev.h> | |
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/platform_device.h> | |
0cfcdd1e | 15 | #include <linux/platform_data/i2c-xiic.h> |
69dbe107 | 16 | #include <linux/platform_data/i2c-ocores.h> |
a7e1abad | 17 | #include <linux/ptp_clock_kernel.h> |
773bda96 JL |
18 | #include <linux/spi/spi.h> |
19 | #include <linux/spi/xilinx_spi.h> | |
69dbe107 | 20 | #include <linux/spi/altera.h> |
773bda96 JL |
21 | #include <net/devlink.h> |
22 | #include <linux/i2c.h> | |
23 | #include <linux/mtd/mtd.h> | |
0cfcdd1e | 24 | #include <linux/nvmem-consumer.h> |
3c3673bd | 25 | #include <linux/crc16.h> |
a7e1abad | 26 | |
3a35e53a JL |
27 | #define PCI_VENDOR_ID_FACEBOOK 0x1d9b |
28 | #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400 | |
773bda96 | 29 | |
81fa652e VF |
30 | #define PCI_VENDOR_ID_CELESTICA 0x18d4 |
31 | #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008 | |
32 | ||
69dbe107 VF |
33 | #define PCI_VENDOR_ID_OROLIA 0x1ad7 |
34 | #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000 | |
35 | ||
773bda96 | 36 | static struct class timecard_class = { |
773bda96 JL |
37 | .name = "timecard", |
38 | }; | |
a7e1abad JL |
39 | |
40 | struct ocp_reg { | |
41 | u32 ctrl; | |
42 | u32 status; | |
43 | u32 select; | |
44 | u32 version; | |
45 | u32 time_ns; | |
46 | u32 time_sec; | |
47 | u32 __pad0[2]; | |
48 | u32 adjust_ns; | |
49 | u32 adjust_sec; | |
50 | u32 __pad1[2]; | |
51 | u32 offset_ns; | |
52 | u32 offset_window_ns; | |
773bda96 JL |
53 | u32 __pad2[2]; |
54 | u32 drift_ns; | |
55 | u32 drift_window_ns; | |
56 | u32 __pad3[6]; | |
57 | u32 servo_offset_p; | |
58 | u32 servo_offset_i; | |
59 | u32 servo_drift_p; | |
60 | u32 servo_drift_i; | |
2f23f486 VF |
61 | u32 status_offset; |
62 | u32 status_drift; | |
a7e1abad JL |
63 | }; |
64 | ||
65 | #define OCP_CTRL_ENABLE BIT(0) | |
66 | #define OCP_CTRL_ADJUST_TIME BIT(1) | |
67 | #define OCP_CTRL_ADJUST_OFFSET BIT(2) | |
773bda96 JL |
68 | #define OCP_CTRL_ADJUST_DRIFT BIT(3) |
69 | #define OCP_CTRL_ADJUST_SERVO BIT(8) | |
a7e1abad JL |
70 | #define OCP_CTRL_READ_TIME_REQ BIT(30) |
71 | #define OCP_CTRL_READ_TIME_DONE BIT(31) | |
72 | ||
73 | #define OCP_STATUS_IN_SYNC BIT(0) | |
773bda96 | 74 | #define OCP_STATUS_IN_HOLDOVER BIT(1) |
a7e1abad JL |
75 | |
76 | #define OCP_SELECT_CLK_NONE 0 | |
773bda96 | 77 | #define OCP_SELECT_CLK_REG 0xfe |
a7e1abad JL |
78 | |
79 | struct tod_reg { | |
80 | u32 ctrl; | |
81 | u32 status; | |
82 | u32 uart_polarity; | |
83 | u32 version; | |
065efcc5 | 84 | u32 adj_sec; |
a7e1abad JL |
85 | u32 __pad0[3]; |
86 | u32 uart_baud; | |
87 | u32 __pad1[3]; | |
88 | u32 utc_status; | |
89 | u32 leap; | |
90 | }; | |
91 | ||
a7e1abad JL |
92 | #define TOD_CTRL_PROTOCOL BIT(28) |
93 | #define TOD_CTRL_DISABLE_FMT_A BIT(17) | |
94 | #define TOD_CTRL_DISABLE_FMT_B BIT(16) | |
95 | #define TOD_CTRL_ENABLE BIT(0) | |
1132bb29 | 96 | #define TOD_CTRL_GNSS_MASK GENMASK(3, 0) |
a7e1abad JL |
97 | #define TOD_CTRL_GNSS_SHIFT 24 |
98 | ||
1132bb29 | 99 | #define TOD_STATUS_UTC_MASK GENMASK(7, 0) |
9f492c4c VF |
100 | #define TOD_STATUS_UTC_VALID BIT(8) |
101 | #define TOD_STATUS_LEAP_ANNOUNCE BIT(12) | |
102 | #define TOD_STATUS_LEAP_VALID BIT(16) | |
a7e1abad | 103 | |
773bda96 JL |
104 | struct ts_reg { |
105 | u32 enable; | |
106 | u32 error; | |
107 | u32 polarity; | |
108 | u32 version; | |
109 | u32 __pad0[4]; | |
110 | u32 cable_delay; | |
111 | u32 __pad1[3]; | |
112 | u32 intr; | |
113 | u32 intr_mask; | |
114 | u32 event_count; | |
115 | u32 __pad2[1]; | |
116 | u32 ts_count; | |
117 | u32 time_ns; | |
118 | u32 time_sec; | |
119 | u32 data_width; | |
120 | u32 data; | |
121 | }; | |
122 | ||
123 | struct pps_reg { | |
124 | u32 ctrl; | |
125 | u32 status; | |
0d43d4f2 JL |
126 | u32 __pad0[6]; |
127 | u32 cable_delay; | |
773bda96 JL |
128 | }; |
129 | ||
130 | #define PPS_STATUS_FILTER_ERR BIT(0) | |
131 | #define PPS_STATUS_SUPERV_ERR BIT(1) | |
132 | ||
133 | struct img_reg { | |
134 | u32 version; | |
135 | }; | |
136 | ||
e1daf0ec JL |
137 | struct gpio_reg { |
138 | u32 gpio1; | |
139 | u32 __pad0; | |
140 | u32 gpio2; | |
141 | u32 __pad1; | |
142 | }; | |
143 | ||
6baf2925 JL |
144 | struct irig_master_reg { |
145 | u32 ctrl; | |
146 | u32 status; | |
147 | u32 __pad0; | |
148 | u32 version; | |
149 | u32 adj_sec; | |
150 | u32 mode_ctrl; | |
151 | }; | |
152 | ||
153 | #define IRIG_M_CTRL_ENABLE BIT(0) | |
154 | ||
155 | struct irig_slave_reg { | |
156 | u32 ctrl; | |
157 | u32 status; | |
158 | u32 __pad0; | |
159 | u32 version; | |
160 | u32 adj_sec; | |
161 | u32 mode_ctrl; | |
162 | }; | |
163 | ||
164 | #define IRIG_S_CTRL_ENABLE BIT(0) | |
165 | ||
166 | struct dcf_master_reg { | |
167 | u32 ctrl; | |
168 | u32 status; | |
169 | u32 __pad0; | |
170 | u32 version; | |
171 | u32 adj_sec; | |
172 | }; | |
173 | ||
174 | #define DCF_M_CTRL_ENABLE BIT(0) | |
175 | ||
176 | struct dcf_slave_reg { | |
177 | u32 ctrl; | |
178 | u32 status; | |
179 | u32 __pad0; | |
180 | u32 version; | |
181 | u32 adj_sec; | |
182 | }; | |
183 | ||
184 | #define DCF_S_CTRL_ENABLE BIT(0) | |
185 | ||
b325af3c JL |
186 | struct signal_reg { |
187 | u32 enable; | |
188 | u32 status; | |
189 | u32 polarity; | |
190 | u32 version; | |
191 | u32 __pad0[4]; | |
192 | u32 cable_delay; | |
193 | u32 __pad1[3]; | |
194 | u32 intr; | |
195 | u32 intr_mask; | |
196 | u32 __pad2[2]; | |
197 | u32 start_ns; | |
198 | u32 start_sec; | |
199 | u32 pulse_ns; | |
200 | u32 pulse_sec; | |
201 | u32 period_ns; | |
202 | u32 period_sec; | |
203 | u32 repeat_count; | |
204 | }; | |
205 | ||
2407f5d6 JL |
206 | struct frequency_reg { |
207 | u32 ctrl; | |
208 | u32 status; | |
209 | }; | |
9c44a7ac VF |
210 | |
211 | struct board_config_reg { | |
212 | u32 mro50_serial_activate; | |
213 | }; | |
214 | ||
2407f5d6 JL |
215 | #define FREQ_STATUS_VALID BIT(31) |
216 | #define FREQ_STATUS_ERROR BIT(30) | |
217 | #define FREQ_STATUS_OVERRUN BIT(29) | |
1132bb29 | 218 | #define FREQ_STATUS_MASK GENMASK(23, 0) |
2407f5d6 | 219 | |
773bda96 JL |
220 | struct ptp_ocp_flash_info { |
221 | const char *name; | |
222 | int pci_offset; | |
223 | int data_size; | |
224 | void *data; | |
225 | }; | |
226 | ||
3c3673bd VF |
227 | struct ptp_ocp_firmware_header { |
228 | char magic[4]; | |
229 | __be16 pci_vendor_id; | |
230 | __be16 pci_device_id; | |
231 | __be32 image_size; | |
232 | __be16 hw_revision; | |
233 | __be16 crc; | |
234 | }; | |
235 | ||
236 | #define OCP_FIRMWARE_MAGIC_HEADER "OCPC" | |
237 | ||
1618df6a JL |
238 | struct ptp_ocp_i2c_info { |
239 | const char *name; | |
240 | unsigned long fixed_rate; | |
241 | size_t data_size; | |
242 | void *data; | |
243 | }; | |
244 | ||
773bda96 | 245 | struct ptp_ocp_ext_info { |
773bda96 JL |
246 | int index; |
247 | irqreturn_t (*irq_fcn)(int irq, void *priv); | |
a62a56d0 | 248 | int (*enable)(void *priv, u32 req, bool enable); |
773bda96 JL |
249 | }; |
250 | ||
251 | struct ptp_ocp_ext_src { | |
252 | void __iomem *mem; | |
253 | struct ptp_ocp *bp; | |
254 | struct ptp_ocp_ext_info *info; | |
255 | int irq_vec; | |
256 | }; | |
257 | ||
a509a7c6 JL |
258 | enum ptp_ocp_sma_mode { |
259 | SMA_MODE_IN, | |
260 | SMA_MODE_OUT, | |
261 | }; | |
262 | ||
263 | struct ptp_ocp_sma_connector { | |
264 | enum ptp_ocp_sma_mode mode; | |
265 | bool fixed_fcn; | |
266 | bool fixed_dir; | |
b2c4f0ac | 267 | bool disabled; |
ee4cd725 | 268 | u8 default_fcn; |
a509a7c6 JL |
269 | }; |
270 | ||
c205d53c JL |
271 | struct ocp_attr_group { |
272 | u64 cap; | |
273 | const struct attribute_group *group; | |
274 | }; | |
275 | ||
276 | #define OCP_CAP_BASIC BIT(0) | |
b325af3c | 277 | #define OCP_CAP_SIGNAL BIT(1) |
2407f5d6 | 278 | #define OCP_CAP_FREQ BIT(2) |
b325af3c JL |
279 | |
280 | struct ptp_ocp_signal { | |
281 | ktime_t period; | |
282 | ktime_t pulse; | |
283 | ktime_t phase; | |
284 | ktime_t start; | |
285 | int duty; | |
286 | bool polarity; | |
287 | bool running; | |
288 | }; | |
c205d53c | 289 | |
895ac5a5 VF |
290 | struct ptp_ocp_serial_port { |
291 | int line; | |
292 | int baud; | |
293 | }; | |
294 | ||
0cfcdd1e JL |
295 | #define OCP_BOARD_ID_LEN 13 |
296 | #define OCP_SERIAL_LEN 6 | |
297 | ||
a7e1abad JL |
298 | struct ptp_ocp { |
299 | struct pci_dev *pdev; | |
773bda96 | 300 | struct device dev; |
a7e1abad | 301 | spinlock_t lock; |
a7e1abad JL |
302 | struct ocp_reg __iomem *reg; |
303 | struct tod_reg __iomem *tod; | |
0d43d4f2 JL |
304 | struct pps_reg __iomem *pps_to_ext; |
305 | struct pps_reg __iomem *pps_to_clk; | |
9c44a7ac | 306 | struct board_config_reg __iomem *board_config; |
f67bf662 | 307 | struct gpio_reg __iomem *pps_select; |
a509a7c6 JL |
308 | struct gpio_reg __iomem *sma_map1; |
309 | struct gpio_reg __iomem *sma_map2; | |
6baf2925 JL |
310 | struct irig_master_reg __iomem *irig_out; |
311 | struct irig_slave_reg __iomem *irig_in; | |
312 | struct dcf_master_reg __iomem *dcf_out; | |
313 | struct dcf_slave_reg __iomem *dcf_in; | |
e3516bb4 | 314 | struct tod_reg __iomem *nmea_out; |
2407f5d6 | 315 | struct frequency_reg __iomem *freq_in[4]; |
b325af3c | 316 | struct ptp_ocp_ext_src *signal_out[4]; |
773bda96 JL |
317 | struct ptp_ocp_ext_src *pps; |
318 | struct ptp_ocp_ext_src *ts0; | |
319 | struct ptp_ocp_ext_src *ts1; | |
dcf61469 | 320 | struct ptp_ocp_ext_src *ts2; |
0fa3ff7e JL |
321 | struct ptp_ocp_ext_src *ts3; |
322 | struct ptp_ocp_ext_src *ts4; | |
69dbe107 | 323 | struct ocp_art_gpio_reg __iomem *art_sma; |
773bda96 | 324 | struct img_reg __iomem *image; |
a7e1abad JL |
325 | struct ptp_clock *ptp; |
326 | struct ptp_clock_info ptp_info; | |
773bda96 JL |
327 | struct platform_device *i2c_ctrl; |
328 | struct platform_device *spi_flash; | |
329 | struct clk_hw *i2c_clk; | |
773bda96 | 330 | struct timer_list watchdog; |
c2239294 | 331 | const struct attribute_group **attr_group; |
0cfcdd1e | 332 | const struct ptp_ocp_eeprom_map *eeprom_map; |
f67bf662 | 333 | struct dentry *debug_root; |
ef0cfb34 | 334 | time64_t gnss_lost; |
773bda96 JL |
335 | int id; |
336 | int n_irqs; | |
895ac5a5 VF |
337 | struct ptp_ocp_serial_port gnss_port; |
338 | struct ptp_ocp_serial_port gnss2_port; | |
339 | struct ptp_ocp_serial_port mac_port; /* miniature atomic clock */ | |
340 | struct ptp_ocp_serial_port nmea_port; | |
5a728ac5 JL |
341 | bool fw_loader; |
342 | u8 fw_tag; | |
343 | u16 fw_version; | |
0cfcdd1e JL |
344 | u8 board_id[OCP_BOARD_ID_LEN]; |
345 | u8 serial[OCP_SERIAL_LEN]; | |
346 | bool has_eeprom_data; | |
a62a56d0 | 347 | u32 pps_req_map; |
89260d87 JL |
348 | int flash_start; |
349 | u32 utc_tai_offset; | |
1acffc6e | 350 | u32 ts_window_adjust; |
c205d53c | 351 | u64 fw_cap; |
b325af3c | 352 | struct ptp_ocp_signal signal[4]; |
a509a7c6 | 353 | struct ptp_ocp_sma_connector sma[4]; |
caab82cd | 354 | const struct ocp_sma_op *sma_op; |
773bda96 JL |
355 | }; |
356 | ||
a62a56d0 JL |
357 | #define OCP_REQ_TIMESTAMP BIT(0) |
358 | #define OCP_REQ_PPS BIT(1) | |
359 | ||
773bda96 JL |
360 | struct ocp_resource { |
361 | unsigned long offset; | |
362 | int size; | |
363 | int irq_vec; | |
364 | int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r); | |
365 | void *extra; | |
366 | unsigned long bp_offset; | |
56ec4403 | 367 | const char * const name; |
773bda96 JL |
368 | }; |
369 | ||
773bda96 JL |
370 | static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r); |
371 | static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r); | |
372 | static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r); | |
373 | static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r); | |
374 | static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r); | |
375 | static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r); | |
376 | static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv); | |
b325af3c | 377 | static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv); |
a62a56d0 | 378 | static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable); |
1aa66a3a JL |
379 | static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen, |
380 | struct ptp_perout_request *req); | |
b325af3c JL |
381 | static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable); |
382 | static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr); | |
773bda96 | 383 | |
69dbe107 VF |
384 | static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r); |
385 | ||
c205d53c JL |
386 | static const struct ocp_attr_group fb_timecard_groups[]; |
387 | ||
69dbe107 VF |
388 | static const struct ocp_attr_group art_timecard_groups[]; |
389 | ||
0cfcdd1e JL |
390 | struct ptp_ocp_eeprom_map { |
391 | u16 off; | |
392 | u16 len; | |
393 | u32 bp_offset; | |
394 | const void * const tag; | |
395 | }; | |
396 | ||
397 | #define EEPROM_ENTRY(addr, member) \ | |
398 | .off = addr, \ | |
399 | .len = sizeof_field(struct ptp_ocp, member), \ | |
400 | .bp_offset = offsetof(struct ptp_ocp, member) | |
401 | ||
402 | #define BP_MAP_ENTRY_ADDR(bp, map) ({ \ | |
403 | (void *)((uintptr_t)(bp) + (map)->bp_offset); \ | |
404 | }) | |
405 | ||
406 | static struct ptp_ocp_eeprom_map fb_eeprom_map[] = { | |
407 | { EEPROM_ENTRY(0x43, board_id) }, | |
408 | { EEPROM_ENTRY(0x00, serial), .tag = "mac" }, | |
409 | { } | |
410 | }; | |
411 | ||
69dbe107 VF |
412 | static struct ptp_ocp_eeprom_map art_eeprom_map[] = { |
413 | { EEPROM_ENTRY(0x200 + 0x43, board_id) }, | |
414 | { EEPROM_ENTRY(0x200 + 0x63, serial) }, | |
415 | { } | |
416 | }; | |
417 | ||
773bda96 JL |
418 | #define bp_assign_entry(bp, res, val) ({ \ |
419 | uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \ | |
420 | *(typeof(val) *)addr = val; \ | |
421 | }) | |
422 | ||
423 | #define OCP_RES_LOCATION(member) \ | |
56ec4403 | 424 | .name = #member, .bp_offset = offsetof(struct ptp_ocp, member) |
773bda96 JL |
425 | |
426 | #define OCP_MEM_RESOURCE(member) \ | |
427 | OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem | |
428 | ||
429 | #define OCP_SERIAL_RESOURCE(member) \ | |
430 | OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial | |
431 | ||
432 | #define OCP_I2C_RESOURCE(member) \ | |
433 | OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c | |
434 | ||
435 | #define OCP_SPI_RESOURCE(member) \ | |
436 | OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi | |
437 | ||
438 | #define OCP_EXT_RESOURCE(member) \ | |
439 | OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext | |
440 | ||
441 | /* This is the MSI vector mapping used. | |
0fa3ff7e | 442 | * 0: PPS (TS5) |
773bda96 JL |
443 | * 1: TS0 |
444 | * 2: TS1 | |
be69087c | 445 | * 3: GNSS1 |
71d7e085 | 446 | * 4: GNSS2 |
773bda96 | 447 | * 5: MAC |
dcf61469 | 448 | * 6: TS2 |
1447149d | 449 | * 7: I2C controller |
e3516bb4 | 450 | * 8: HWICAP (notused) |
773bda96 | 451 | * 9: SPI Flash |
e3516bb4 | 452 | * 10: NMEA |
b325af3c JL |
453 | * 11: Signal Generator 1 |
454 | * 12: Signal Generator 2 | |
455 | * 13: Signal Generator 3 | |
456 | * 14: Signal Generator 4 | |
0fa3ff7e JL |
457 | * 15: TS3 |
458 | * 16: TS4 | |
69dbe107 VF |
459 | -- |
460 | * 8: Orolia TS1 | |
461 | * 10: Orolia TS2 | |
462 | * 11: Orolia TS0 (GNSS) | |
463 | * 12: Orolia PPS | |
464 | * 14: Orolia TS3 | |
465 | * 15: Orolia TS4 | |
773bda96 JL |
466 | */ |
467 | ||
468 | static struct ocp_resource ocp_fb_resource[] = { | |
469 | { | |
470 | OCP_MEM_RESOURCE(reg), | |
471 | .offset = 0x01000000, .size = 0x10000, | |
472 | }, | |
473 | { | |
474 | OCP_EXT_RESOURCE(ts0), | |
475 | .offset = 0x01010000, .size = 0x10000, .irq_vec = 1, | |
476 | .extra = &(struct ptp_ocp_ext_info) { | |
56ec4403 | 477 | .index = 0, |
773bda96 JL |
478 | .irq_fcn = ptp_ocp_ts_irq, |
479 | .enable = ptp_ocp_ts_enable, | |
480 | }, | |
481 | }, | |
482 | { | |
483 | OCP_EXT_RESOURCE(ts1), | |
484 | .offset = 0x01020000, .size = 0x10000, .irq_vec = 2, | |
485 | .extra = &(struct ptp_ocp_ext_info) { | |
56ec4403 | 486 | .index = 1, |
773bda96 JL |
487 | .irq_fcn = ptp_ocp_ts_irq, |
488 | .enable = ptp_ocp_ts_enable, | |
489 | }, | |
490 | }, | |
dcf61469 JL |
491 | { |
492 | OCP_EXT_RESOURCE(ts2), | |
493 | .offset = 0x01060000, .size = 0x10000, .irq_vec = 6, | |
494 | .extra = &(struct ptp_ocp_ext_info) { | |
495 | .index = 2, | |
496 | .irq_fcn = ptp_ocp_ts_irq, | |
497 | .enable = ptp_ocp_ts_enable, | |
498 | }, | |
499 | }, | |
0fa3ff7e JL |
500 | { |
501 | OCP_EXT_RESOURCE(ts3), | |
502 | .offset = 0x01110000, .size = 0x10000, .irq_vec = 15, | |
503 | .extra = &(struct ptp_ocp_ext_info) { | |
504 | .index = 3, | |
505 | .irq_fcn = ptp_ocp_ts_irq, | |
506 | .enable = ptp_ocp_ts_enable, | |
507 | }, | |
508 | }, | |
509 | { | |
510 | OCP_EXT_RESOURCE(ts4), | |
511 | .offset = 0x01120000, .size = 0x10000, .irq_vec = 16, | |
512 | .extra = &(struct ptp_ocp_ext_info) { | |
513 | .index = 4, | |
514 | .irq_fcn = ptp_ocp_ts_irq, | |
515 | .enable = ptp_ocp_ts_enable, | |
516 | }, | |
517 | }, | |
518 | /* Timestamp for PHC and/or PPS generator */ | |
a62a56d0 JL |
519 | { |
520 | OCP_EXT_RESOURCE(pps), | |
521 | .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0, | |
522 | .extra = &(struct ptp_ocp_ext_info) { | |
0fa3ff7e | 523 | .index = 5, |
a62a56d0 JL |
524 | .irq_fcn = ptp_ocp_ts_irq, |
525 | .enable = ptp_ocp_ts_enable, | |
526 | }, | |
527 | }, | |
b325af3c JL |
528 | { |
529 | OCP_EXT_RESOURCE(signal_out[0]), | |
530 | .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11, | |
531 | .extra = &(struct ptp_ocp_ext_info) { | |
532 | .index = 1, | |
533 | .irq_fcn = ptp_ocp_signal_irq, | |
534 | .enable = ptp_ocp_signal_enable, | |
535 | }, | |
536 | }, | |
537 | { | |
538 | OCP_EXT_RESOURCE(signal_out[1]), | |
539 | .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12, | |
540 | .extra = &(struct ptp_ocp_ext_info) { | |
541 | .index = 2, | |
542 | .irq_fcn = ptp_ocp_signal_irq, | |
543 | .enable = ptp_ocp_signal_enable, | |
544 | }, | |
545 | }, | |
546 | { | |
547 | OCP_EXT_RESOURCE(signal_out[2]), | |
548 | .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13, | |
549 | .extra = &(struct ptp_ocp_ext_info) { | |
550 | .index = 3, | |
551 | .irq_fcn = ptp_ocp_signal_irq, | |
552 | .enable = ptp_ocp_signal_enable, | |
553 | }, | |
554 | }, | |
555 | { | |
556 | OCP_EXT_RESOURCE(signal_out[3]), | |
557 | .offset = 0x01100000, .size = 0x10000, .irq_vec = 14, | |
558 | .extra = &(struct ptp_ocp_ext_info) { | |
559 | .index = 4, | |
560 | .irq_fcn = ptp_ocp_signal_irq, | |
561 | .enable = ptp_ocp_signal_enable, | |
562 | }, | |
563 | }, | |
773bda96 | 564 | { |
0d43d4f2 JL |
565 | OCP_MEM_RESOURCE(pps_to_ext), |
566 | .offset = 0x01030000, .size = 0x10000, | |
567 | }, | |
568 | { | |
569 | OCP_MEM_RESOURCE(pps_to_clk), | |
773bda96 JL |
570 | .offset = 0x01040000, .size = 0x10000, |
571 | }, | |
572 | { | |
573 | OCP_MEM_RESOURCE(tod), | |
574 | .offset = 0x01050000, .size = 0x10000, | |
575 | }, | |
6baf2925 JL |
576 | { |
577 | OCP_MEM_RESOURCE(irig_in), | |
578 | .offset = 0x01070000, .size = 0x10000, | |
579 | }, | |
580 | { | |
581 | OCP_MEM_RESOURCE(irig_out), | |
582 | .offset = 0x01080000, .size = 0x10000, | |
583 | }, | |
584 | { | |
585 | OCP_MEM_RESOURCE(dcf_in), | |
586 | .offset = 0x01090000, .size = 0x10000, | |
587 | }, | |
588 | { | |
589 | OCP_MEM_RESOURCE(dcf_out), | |
590 | .offset = 0x010A0000, .size = 0x10000, | |
591 | }, | |
e3516bb4 JL |
592 | { |
593 | OCP_MEM_RESOURCE(nmea_out), | |
594 | .offset = 0x010B0000, .size = 0x10000, | |
595 | }, | |
773bda96 JL |
596 | { |
597 | OCP_MEM_RESOURCE(image), | |
598 | .offset = 0x00020000, .size = 0x1000, | |
599 | }, | |
f67bf662 JL |
600 | { |
601 | OCP_MEM_RESOURCE(pps_select), | |
602 | .offset = 0x00130000, .size = 0x1000, | |
603 | }, | |
e1daf0ec | 604 | { |
a509a7c6 | 605 | OCP_MEM_RESOURCE(sma_map1), |
e1daf0ec JL |
606 | .offset = 0x00140000, .size = 0x1000, |
607 | }, | |
a509a7c6 JL |
608 | { |
609 | OCP_MEM_RESOURCE(sma_map2), | |
610 | .offset = 0x00220000, .size = 0x1000, | |
611 | }, | |
773bda96 JL |
612 | { |
613 | OCP_I2C_RESOURCE(i2c_ctrl), | |
614 | .offset = 0x00150000, .size = 0x10000, .irq_vec = 7, | |
1618df6a JL |
615 | .extra = &(struct ptp_ocp_i2c_info) { |
616 | .name = "xiic-i2c", | |
617 | .fixed_rate = 50000000, | |
0cfcdd1e JL |
618 | .data_size = sizeof(struct xiic_i2c_platform_data), |
619 | .data = &(struct xiic_i2c_platform_data) { | |
620 | .num_devices = 2, | |
621 | .devices = (struct i2c_board_info[]) { | |
622 | { I2C_BOARD_INFO("24c02", 0x50) }, | |
623 | { I2C_BOARD_INFO("24mac402", 0x58), | |
624 | .platform_data = "mac" }, | |
625 | }, | |
626 | }, | |
1618df6a | 627 | }, |
773bda96 JL |
628 | }, |
629 | { | |
ef0cfb34 | 630 | OCP_SERIAL_RESOURCE(gnss_port), |
773bda96 | 631 | .offset = 0x00160000 + 0x1000, .irq_vec = 3, |
895ac5a5 VF |
632 | .extra = &(struct ptp_ocp_serial_port) { |
633 | .baud = 115200, | |
634 | }, | |
773bda96 | 635 | }, |
71d7e085 JL |
636 | { |
637 | OCP_SERIAL_RESOURCE(gnss2_port), | |
638 | .offset = 0x00170000 + 0x1000, .irq_vec = 4, | |
895ac5a5 VF |
639 | .extra = &(struct ptp_ocp_serial_port) { |
640 | .baud = 115200, | |
641 | }, | |
71d7e085 | 642 | }, |
773bda96 JL |
643 | { |
644 | OCP_SERIAL_RESOURCE(mac_port), | |
645 | .offset = 0x00180000 + 0x1000, .irq_vec = 5, | |
895ac5a5 VF |
646 | .extra = &(struct ptp_ocp_serial_port) { |
647 | .baud = 57600, | |
648 | }, | |
773bda96 | 649 | }, |
e3516bb4 JL |
650 | { |
651 | OCP_SERIAL_RESOURCE(nmea_port), | |
652 | .offset = 0x00190000 + 0x1000, .irq_vec = 10, | |
653 | }, | |
773bda96 JL |
654 | { |
655 | OCP_SPI_RESOURCE(spi_flash), | |
656 | .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, | |
657 | .extra = &(struct ptp_ocp_flash_info) { | |
658 | .name = "xilinx_spi", .pci_offset = 0, | |
659 | .data_size = sizeof(struct xspi_platform_data), | |
660 | .data = &(struct xspi_platform_data) { | |
661 | .num_chipselect = 1, | |
662 | .bits_per_word = 8, | |
663 | .num_devices = 1, | |
939a3f2a | 664 | .force_irq = true, |
773bda96 JL |
665 | .devices = &(struct spi_board_info) { |
666 | .modalias = "spi-nor", | |
667 | }, | |
668 | }, | |
669 | }, | |
670 | }, | |
2407f5d6 JL |
671 | { |
672 | OCP_MEM_RESOURCE(freq_in[0]), | |
673 | .offset = 0x01200000, .size = 0x10000, | |
674 | }, | |
675 | { | |
676 | OCP_MEM_RESOURCE(freq_in[1]), | |
677 | .offset = 0x01210000, .size = 0x10000, | |
678 | }, | |
679 | { | |
680 | OCP_MEM_RESOURCE(freq_in[2]), | |
681 | .offset = 0x01220000, .size = 0x10000, | |
682 | }, | |
683 | { | |
684 | OCP_MEM_RESOURCE(freq_in[3]), | |
685 | .offset = 0x01230000, .size = 0x10000, | |
686 | }, | |
773bda96 JL |
687 | { |
688 | .setup = ptp_ocp_fb_board_init, | |
689 | }, | |
690 | { } | |
691 | }; | |
692 | ||
ee6439aa VF |
693 | #define OCP_ART_CONFIG_SIZE 144 |
694 | #define OCP_ART_TEMP_TABLE_SIZE 368 | |
695 | ||
69dbe107 VF |
696 | struct ocp_art_gpio_reg { |
697 | struct { | |
698 | u32 gpio; | |
699 | u32 __pad[3]; | |
700 | } map[4]; | |
701 | }; | |
702 | ||
703 | static struct ocp_resource ocp_art_resource[] = { | |
704 | { | |
705 | OCP_MEM_RESOURCE(reg), | |
706 | .offset = 0x01000000, .size = 0x10000, | |
707 | }, | |
708 | { | |
709 | OCP_SERIAL_RESOURCE(gnss_port), | |
710 | .offset = 0x00160000 + 0x1000, .irq_vec = 3, | |
711 | .extra = &(struct ptp_ocp_serial_port) { | |
712 | .baud = 115200, | |
713 | }, | |
714 | }, | |
715 | { | |
716 | OCP_MEM_RESOURCE(art_sma), | |
717 | .offset = 0x003C0000, .size = 0x1000, | |
718 | }, | |
719 | /* Timestamp associated with GNSS1 receiver PPS */ | |
720 | { | |
721 | OCP_EXT_RESOURCE(ts0), | |
722 | .offset = 0x360000, .size = 0x20, .irq_vec = 12, | |
723 | .extra = &(struct ptp_ocp_ext_info) { | |
724 | .index = 0, | |
725 | .irq_fcn = ptp_ocp_ts_irq, | |
726 | .enable = ptp_ocp_ts_enable, | |
727 | }, | |
728 | }, | |
729 | { | |
730 | OCP_EXT_RESOURCE(ts1), | |
731 | .offset = 0x380000, .size = 0x20, .irq_vec = 8, | |
732 | .extra = &(struct ptp_ocp_ext_info) { | |
733 | .index = 1, | |
734 | .irq_fcn = ptp_ocp_ts_irq, | |
735 | .enable = ptp_ocp_ts_enable, | |
736 | }, | |
737 | }, | |
738 | { | |
739 | OCP_EXT_RESOURCE(ts2), | |
740 | .offset = 0x390000, .size = 0x20, .irq_vec = 10, | |
741 | .extra = &(struct ptp_ocp_ext_info) { | |
742 | .index = 2, | |
743 | .irq_fcn = ptp_ocp_ts_irq, | |
744 | .enable = ptp_ocp_ts_enable, | |
745 | }, | |
746 | }, | |
747 | { | |
748 | OCP_EXT_RESOURCE(ts3), | |
749 | .offset = 0x3A0000, .size = 0x20, .irq_vec = 14, | |
750 | .extra = &(struct ptp_ocp_ext_info) { | |
751 | .index = 3, | |
752 | .irq_fcn = ptp_ocp_ts_irq, | |
753 | .enable = ptp_ocp_ts_enable, | |
754 | }, | |
755 | }, | |
756 | { | |
757 | OCP_EXT_RESOURCE(ts4), | |
758 | .offset = 0x3B0000, .size = 0x20, .irq_vec = 15, | |
759 | .extra = &(struct ptp_ocp_ext_info) { | |
760 | .index = 4, | |
761 | .irq_fcn = ptp_ocp_ts_irq, | |
762 | .enable = ptp_ocp_ts_enable, | |
763 | }, | |
764 | }, | |
765 | /* Timestamp associated with Internal PPS of the card */ | |
766 | { | |
767 | OCP_EXT_RESOURCE(pps), | |
768 | .offset = 0x00330000, .size = 0x20, .irq_vec = 11, | |
769 | .extra = &(struct ptp_ocp_ext_info) { | |
770 | .index = 5, | |
771 | .irq_fcn = ptp_ocp_ts_irq, | |
772 | .enable = ptp_ocp_ts_enable, | |
773 | }, | |
774 | }, | |
775 | { | |
776 | OCP_SPI_RESOURCE(spi_flash), | |
777 | .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, | |
778 | .extra = &(struct ptp_ocp_flash_info) { | |
779 | .name = "spi_altera", .pci_offset = 0, | |
780 | .data_size = sizeof(struct altera_spi_platform_data), | |
781 | .data = &(struct altera_spi_platform_data) { | |
782 | .num_chipselect = 1, | |
783 | .num_devices = 1, | |
784 | .devices = &(struct spi_board_info) { | |
785 | .modalias = "spi-nor", | |
786 | }, | |
787 | }, | |
788 | }, | |
789 | }, | |
790 | { | |
791 | OCP_I2C_RESOURCE(i2c_ctrl), | |
792 | .offset = 0x350000, .size = 0x100, .irq_vec = 4, | |
793 | .extra = &(struct ptp_ocp_i2c_info) { | |
794 | .name = "ocores-i2c", | |
795 | .fixed_rate = 400000, | |
796 | .data_size = sizeof(struct ocores_i2c_platform_data), | |
797 | .data = &(struct ocores_i2c_platform_data) { | |
798 | .clock_khz = 125000, | |
799 | .bus_khz = 400, | |
800 | .num_devices = 1, | |
801 | .devices = &(struct i2c_board_info) { | |
802 | I2C_BOARD_INFO("24c08", 0x50), | |
803 | }, | |
804 | }, | |
805 | }, | |
806 | }, | |
9c44a7ac VF |
807 | { |
808 | OCP_SERIAL_RESOURCE(mac_port), | |
809 | .offset = 0x00190000, .irq_vec = 7, | |
810 | .extra = &(struct ptp_ocp_serial_port) { | |
811 | .baud = 9600, | |
812 | }, | |
813 | }, | |
814 | { | |
815 | OCP_MEM_RESOURCE(board_config), | |
816 | .offset = 0x210000, .size = 0x1000, | |
817 | }, | |
69dbe107 VF |
818 | { |
819 | .setup = ptp_ocp_art_board_init, | |
820 | }, | |
821 | { } | |
822 | }; | |
823 | ||
773bda96 JL |
824 | static const struct pci_device_id ptp_ocp_pcidev_id[] = { |
825 | { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) }, | |
81fa652e | 826 | { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) }, |
69dbe107 | 827 | { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) }, |
81fa652e | 828 | { } |
773bda96 JL |
829 | }; |
830 | MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id); | |
831 | ||
832 | static DEFINE_MUTEX(ptp_ocp_lock); | |
833 | static DEFINE_IDR(ptp_ocp_idr); | |
834 | ||
e1daf0ec | 835 | struct ocp_selector { |
773bda96 JL |
836 | const char *name; |
837 | int value; | |
e1daf0ec JL |
838 | }; |
839 | ||
3f3fe41c | 840 | static const struct ocp_selector ptp_ocp_clock[] = { |
773bda96 JL |
841 | { .name = "NONE", .value = 0 }, |
842 | { .name = "TOD", .value = 1 }, | |
843 | { .name = "IRIG", .value = 2 }, | |
844 | { .name = "PPS", .value = 3 }, | |
845 | { .name = "PTP", .value = 4 }, | |
846 | { .name = "RTC", .value = 5 }, | |
847 | { .name = "DCF", .value = 6 }, | |
848 | { .name = "REGS", .value = 0xfe }, | |
849 | { .name = "EXT", .value = 0xff }, | |
e1daf0ec JL |
850 | { } |
851 | }; | |
852 | ||
1132bb29 | 853 | #define SMA_DISABLE BIT(16) |
a509a7c6 | 854 | #define SMA_ENABLE BIT(15) |
1132bb29 | 855 | #define SMA_SELECT_MASK GENMASK(14, 0) |
a509a7c6 | 856 | |
3f3fe41c | 857 | static const struct ocp_selector ptp_ocp_sma_in[] = { |
2407f5d6 JL |
858 | { .name = "10Mhz", .value = 0x0000 }, |
859 | { .name = "PPS1", .value = 0x0001 }, | |
860 | { .name = "PPS2", .value = 0x0002 }, | |
861 | { .name = "TS1", .value = 0x0004 }, | |
862 | { .name = "TS2", .value = 0x0008 }, | |
863 | { .name = "IRIG", .value = 0x0010 }, | |
864 | { .name = "DCF", .value = 0x0020 }, | |
0fa3ff7e JL |
865 | { .name = "TS3", .value = 0x0040 }, |
866 | { .name = "TS4", .value = 0x0080 }, | |
2407f5d6 JL |
867 | { .name = "FREQ1", .value = 0x0100 }, |
868 | { .name = "FREQ2", .value = 0x0200 }, | |
869 | { .name = "FREQ3", .value = 0x0400 }, | |
870 | { .name = "FREQ4", .value = 0x0800 }, | |
b2c4f0ac | 871 | { .name = "None", .value = SMA_DISABLE }, |
e1daf0ec JL |
872 | { } |
873 | }; | |
874 | ||
3f3fe41c | 875 | static const struct ocp_selector ptp_ocp_sma_out[] = { |
b325af3c JL |
876 | { .name = "10Mhz", .value = 0x0000 }, |
877 | { .name = "PHC", .value = 0x0001 }, | |
878 | { .name = "MAC", .value = 0x0002 }, | |
879 | { .name = "GNSS1", .value = 0x0004 }, | |
880 | { .name = "GNSS2", .value = 0x0008 }, | |
881 | { .name = "IRIG", .value = 0x0010 }, | |
882 | { .name = "DCF", .value = 0x0020 }, | |
883 | { .name = "GEN1", .value = 0x0040 }, | |
884 | { .name = "GEN2", .value = 0x0080 }, | |
885 | { .name = "GEN3", .value = 0x0100 }, | |
886 | { .name = "GEN4", .value = 0x0200 }, | |
887 | { .name = "GND", .value = 0x2000 }, | |
888 | { .name = "VCC", .value = 0x4000 }, | |
e1daf0ec | 889 | { } |
a7e1abad JL |
890 | }; |
891 | ||
69dbe107 VF |
892 | static const struct ocp_selector ptp_ocp_art_sma_in[] = { |
893 | { .name = "PPS1", .value = 0x0001 }, | |
894 | { .name = "10Mhz", .value = 0x0008 }, | |
895 | { } | |
896 | }; | |
897 | ||
898 | static const struct ocp_selector ptp_ocp_art_sma_out[] = { | |
899 | { .name = "PHC", .value = 0x0002 }, | |
900 | { .name = "GNSS", .value = 0x0004 }, | |
901 | { .name = "10Mhz", .value = 0x0010 }, | |
902 | { } | |
903 | }; | |
904 | ||
caab82cd JL |
905 | struct ocp_sma_op { |
906 | const struct ocp_selector *tbl[2]; | |
ee4cd725 | 907 | void (*init)(struct ptp_ocp *bp); |
caab82cd JL |
908 | u32 (*get)(struct ptp_ocp *bp, int sma_nr); |
909 | int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val); | |
910 | int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val); | |
aa56a7ff JL |
911 | }; |
912 | ||
ee4cd725 JL |
913 | static void |
914 | ptp_ocp_sma_init(struct ptp_ocp *bp) | |
915 | { | |
916 | return bp->sma_op->init(bp); | |
917 | } | |
918 | ||
caab82cd JL |
919 | static u32 |
920 | ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr) | |
921 | { | |
922 | return bp->sma_op->get(bp, sma_nr); | |
923 | } | |
924 | ||
925 | static int | |
926 | ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val) | |
927 | { | |
928 | return bp->sma_op->set_inputs(bp, sma_nr, val); | |
929 | } | |
930 | ||
931 | static int | |
932 | ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val) | |
933 | { | |
934 | return bp->sma_op->set_output(bp, sma_nr, val); | |
935 | } | |
936 | ||
773bda96 | 937 | static const char * |
3f3fe41c | 938 | ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val) |
773bda96 JL |
939 | { |
940 | int i; | |
941 | ||
e1daf0ec JL |
942 | for (i = 0; tbl[i].name; i++) |
943 | if (tbl[i].value == val) | |
944 | return tbl[i].name; | |
773bda96 JL |
945 | return NULL; |
946 | } | |
947 | ||
948 | static int | |
3f3fe41c | 949 | ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name) |
773bda96 | 950 | { |
e1daf0ec | 951 | const char *select; |
773bda96 JL |
952 | int i; |
953 | ||
e1daf0ec JL |
954 | for (i = 0; tbl[i].name; i++) { |
955 | select = tbl[i].name; | |
956 | if (!strncasecmp(name, select, strlen(select))) | |
957 | return tbl[i].value; | |
773bda96 JL |
958 | } |
959 | return -EINVAL; | |
960 | } | |
961 | ||
e1daf0ec | 962 | static ssize_t |
3f3fe41c | 963 | ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf) |
e1daf0ec JL |
964 | { |
965 | ssize_t count; | |
966 | int i; | |
967 | ||
968 | count = 0; | |
969 | for (i = 0; tbl[i].name; i++) | |
970 | count += sysfs_emit_at(buf, count, "%s ", tbl[i].name); | |
971 | if (count) | |
972 | count--; | |
973 | count += sysfs_emit_at(buf, count, "\n"); | |
974 | return count; | |
975 | } | |
976 | ||
a7e1abad JL |
977 | static int |
978 | __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts, | |
979 | struct ptp_system_timestamp *sts) | |
980 | { | |
981 | u32 ctrl, time_sec, time_ns; | |
982 | int i; | |
983 | ||
a7e1abad | 984 | ptp_read_system_prets(sts); |
1acffc6e JL |
985 | |
986 | ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE; | |
a7e1abad JL |
987 | iowrite32(ctrl, &bp->reg->ctrl); |
988 | ||
989 | for (i = 0; i < 100; i++) { | |
990 | ctrl = ioread32(&bp->reg->ctrl); | |
991 | if (ctrl & OCP_CTRL_READ_TIME_DONE) | |
992 | break; | |
993 | } | |
994 | ptp_read_system_postts(sts); | |
995 | ||
1acffc6e JL |
996 | if (sts && bp->ts_window_adjust) { |
997 | s64 ns = timespec64_to_ns(&sts->post_ts); | |
998 | ||
999 | sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust); | |
1000 | } | |
1001 | ||
a7e1abad JL |
1002 | time_ns = ioread32(&bp->reg->time_ns); |
1003 | time_sec = ioread32(&bp->reg->time_sec); | |
1004 | ||
1005 | ts->tv_sec = time_sec; | |
1006 | ts->tv_nsec = time_ns; | |
1007 | ||
1008 | return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; | |
1009 | } | |
1010 | ||
1011 | static int | |
1012 | ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts, | |
1013 | struct ptp_system_timestamp *sts) | |
1014 | { | |
1015 | struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); | |
1016 | unsigned long flags; | |
1017 | int err; | |
1018 | ||
1019 | spin_lock_irqsave(&bp->lock, flags); | |
1020 | err = __ptp_ocp_gettime_locked(bp, ts, sts); | |
1021 | spin_unlock_irqrestore(&bp->lock, flags); | |
1022 | ||
1023 | return err; | |
1024 | } | |
1025 | ||
1026 | static void | |
1027 | __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts) | |
1028 | { | |
1029 | u32 ctrl, time_sec, time_ns; | |
1030 | u32 select; | |
1031 | ||
1032 | time_ns = ts->tv_nsec; | |
1033 | time_sec = ts->tv_sec; | |
1034 | ||
1035 | select = ioread32(&bp->reg->select); | |
1036 | iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); | |
1037 | ||
1038 | iowrite32(time_ns, &bp->reg->adjust_ns); | |
1039 | iowrite32(time_sec, &bp->reg->adjust_sec); | |
1040 | ||
1acffc6e | 1041 | ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE; |
a7e1abad JL |
1042 | iowrite32(ctrl, &bp->reg->ctrl); |
1043 | ||
1044 | /* restore clock selection */ | |
1045 | iowrite32(select >> 16, &bp->reg->select); | |
1046 | } | |
1047 | ||
1048 | static int | |
1049 | ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts) | |
1050 | { | |
1051 | struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); | |
1052 | unsigned long flags; | |
1053 | ||
a7e1abad JL |
1054 | spin_lock_irqsave(&bp->lock, flags); |
1055 | __ptp_ocp_settime_locked(bp, ts); | |
1056 | spin_unlock_irqrestore(&bp->lock, flags); | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
6d59d4fa | 1061 | static void |
90f8f4c0 | 1062 | __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val) |
6d59d4fa JL |
1063 | { |
1064 | u32 select, ctrl; | |
1065 | ||
1066 | select = ioread32(&bp->reg->select); | |
1067 | iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); | |
1068 | ||
1069 | iowrite32(adj_val, &bp->reg->offset_ns); | |
90f8f4c0 | 1070 | iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns); |
6d59d4fa JL |
1071 | |
1072 | ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE; | |
1073 | iowrite32(ctrl, &bp->reg->ctrl); | |
1074 | ||
1075 | /* restore clock selection */ | |
1076 | iowrite32(select >> 16, &bp->reg->select); | |
1077 | } | |
1078 | ||
90f8f4c0 | 1079 | static void |
da2172a9 | 1080 | ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns) |
90f8f4c0 JL |
1081 | { |
1082 | struct timespec64 ts; | |
1083 | unsigned long flags; | |
1084 | int err; | |
1085 | ||
1086 | spin_lock_irqsave(&bp->lock, flags); | |
1087 | err = __ptp_ocp_gettime_locked(bp, &ts, NULL); | |
1088 | if (likely(!err)) { | |
da2172a9 JL |
1089 | set_normalized_timespec64(&ts, ts.tv_sec, |
1090 | ts.tv_nsec + delta_ns); | |
90f8f4c0 JL |
1091 | __ptp_ocp_settime_locked(bp, &ts); |
1092 | } | |
1093 | spin_unlock_irqrestore(&bp->lock, flags); | |
1094 | } | |
1095 | ||
a7e1abad JL |
1096 | static int |
1097 | ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns) | |
1098 | { | |
1099 | struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); | |
a7e1abad | 1100 | unsigned long flags; |
6d59d4fa | 1101 | u32 adj_ns, sign; |
a7e1abad | 1102 | |
90f8f4c0 JL |
1103 | if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) { |
1104 | ptp_ocp_adjtime_coarse(bp, delta_ns); | |
1105 | return 0; | |
1106 | } | |
1107 | ||
6d59d4fa JL |
1108 | sign = delta_ns < 0 ? BIT(31) : 0; |
1109 | adj_ns = sign ? -delta_ns : delta_ns; | |
a7e1abad JL |
1110 | |
1111 | spin_lock_irqsave(&bp->lock, flags); | |
6d59d4fa | 1112 | __ptp_ocp_adjtime_locked(bp, sign | adj_ns); |
a7e1abad JL |
1113 | spin_unlock_irqrestore(&bp->lock, flags); |
1114 | ||
6d59d4fa | 1115 | return 0; |
a7e1abad JL |
1116 | } |
1117 | ||
1118 | static int | |
1119 | ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) | |
1120 | { | |
1121 | if (scaled_ppm == 0) | |
1122 | return 0; | |
1123 | ||
1124 | return -EOPNOTSUPP; | |
1125 | } | |
1126 | ||
d8ee5ca8 RR |
1127 | static s32 |
1128 | ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info) | |
1129 | { | |
1130 | return 0; | |
1131 | } | |
1132 | ||
773bda96 | 1133 | static int |
6d59d4fa | 1134 | ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns) |
773bda96 JL |
1135 | { |
1136 | return -EOPNOTSUPP; | |
1137 | } | |
1138 | ||
1139 | static int | |
1140 | ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq, | |
1141 | int on) | |
1142 | { | |
1143 | struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); | |
1144 | struct ptp_ocp_ext_src *ext = NULL; | |
a62a56d0 | 1145 | u32 req; |
773bda96 JL |
1146 | int err; |
1147 | ||
1148 | switch (rq->type) { | |
1149 | case PTP_CLK_REQ_EXTTS: | |
a62a56d0 | 1150 | req = OCP_REQ_TIMESTAMP; |
773bda96 JL |
1151 | switch (rq->extts.index) { |
1152 | case 0: | |
1153 | ext = bp->ts0; | |
1154 | break; | |
1155 | case 1: | |
1156 | ext = bp->ts1; | |
1157 | break; | |
dcf61469 JL |
1158 | case 2: |
1159 | ext = bp->ts2; | |
1160 | break; | |
a62a56d0 | 1161 | case 3: |
0fa3ff7e JL |
1162 | ext = bp->ts3; |
1163 | break; | |
1164 | case 4: | |
1165 | ext = bp->ts4; | |
1166 | break; | |
1167 | case 5: | |
a62a56d0 JL |
1168 | ext = bp->pps; |
1169 | break; | |
773bda96 JL |
1170 | } |
1171 | break; | |
1172 | case PTP_CLK_REQ_PPS: | |
a62a56d0 | 1173 | req = OCP_REQ_PPS; |
773bda96 JL |
1174 | ext = bp->pps; |
1175 | break; | |
a62a56d0 | 1176 | case PTP_CLK_REQ_PEROUT: |
1aa66a3a JL |
1177 | switch (rq->perout.index) { |
1178 | case 0: | |
1179 | /* This is a request for 1PPS on an output SMA. | |
1180 | * Allow, but assume manual configuration. | |
1181 | */ | |
1182 | if (on && (rq->perout.period.sec != 1 || | |
1183 | rq->perout.period.nsec != 0)) | |
1184 | return -EINVAL; | |
1185 | return 0; | |
1186 | case 1: | |
1187 | case 2: | |
1188 | case 3: | |
1189 | case 4: | |
1190 | req = rq->perout.index - 1; | |
1191 | ext = bp->signal_out[req]; | |
1192 | err = ptp_ocp_signal_from_perout(bp, req, &rq->perout); | |
1193 | if (err) | |
1194 | return err; | |
1195 | break; | |
1196 | } | |
1197 | break; | |
773bda96 JL |
1198 | default: |
1199 | return -EOPNOTSUPP; | |
1200 | } | |
1201 | ||
1202 | err = -ENXIO; | |
1203 | if (ext) | |
a62a56d0 | 1204 | err = ext->info->enable(ext, req, on); |
773bda96 JL |
1205 | |
1206 | return err; | |
1207 | } | |
1208 | ||
1aa66a3a JL |
1209 | static int |
1210 | ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin, | |
1211 | enum ptp_pin_function func, unsigned chan) | |
1212 | { | |
1213 | struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); | |
1214 | char buf[16]; | |
1215 | ||
05fc65f3 JL |
1216 | switch (func) { |
1217 | case PTP_PF_NONE: | |
d5f497b8 | 1218 | snprintf(buf, sizeof(buf), "IN: None"); |
05fc65f3 JL |
1219 | break; |
1220 | case PTP_PF_EXTTS: | |
1221 | /* Allow timestamps, but require sysfs configuration. */ | |
1222 | return 0; | |
1223 | case PTP_PF_PEROUT: | |
1224 | /* channel 0 is 1PPS from PHC. | |
1225 | * channels 1..4 are the frequency generators. | |
1226 | */ | |
1227 | if (chan) | |
d5f497b8 | 1228 | snprintf(buf, sizeof(buf), "OUT: GEN%d", chan); |
05fc65f3 | 1229 | else |
d5f497b8 | 1230 | snprintf(buf, sizeof(buf), "OUT: PHC"); |
05fc65f3 JL |
1231 | break; |
1232 | default: | |
1aa66a3a | 1233 | return -EOPNOTSUPP; |
05fc65f3 | 1234 | } |
1aa66a3a JL |
1235 | |
1236 | return ptp_ocp_sma_store(bp, buf, pin + 1); | |
1237 | } | |
1238 | ||
a7e1abad JL |
1239 | static const struct ptp_clock_info ptp_ocp_clock_info = { |
1240 | .owner = THIS_MODULE, | |
1241 | .name = KBUILD_MODNAME, | |
1242 | .max_adj = 100000000, | |
1243 | .gettimex64 = ptp_ocp_gettimex, | |
1244 | .settime64 = ptp_ocp_settime, | |
1245 | .adjtime = ptp_ocp_adjtime, | |
1246 | .adjfine = ptp_ocp_null_adjfine, | |
6d59d4fa | 1247 | .adjphase = ptp_ocp_null_adjphase, |
d8ee5ca8 | 1248 | .getmaxphase = ptp_ocp_null_getmaxphase, |
773bda96 | 1249 | .enable = ptp_ocp_enable, |
1aa66a3a | 1250 | .verify = ptp_ocp_verify, |
773bda96 | 1251 | .pps = true, |
0fa3ff7e | 1252 | .n_ext_ts = 6, |
1aa66a3a | 1253 | .n_per_out = 5, |
a7e1abad JL |
1254 | }; |
1255 | ||
773bda96 JL |
1256 | static void |
1257 | __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp) | |
1258 | { | |
1259 | u32 ctrl, select; | |
1260 | ||
1261 | select = ioread32(&bp->reg->select); | |
1262 | iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); | |
1263 | ||
1264 | iowrite32(0, &bp->reg->drift_ns); | |
1265 | ||
1acffc6e | 1266 | ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE; |
773bda96 JL |
1267 | iowrite32(ctrl, &bp->reg->ctrl); |
1268 | ||
1269 | /* restore clock selection */ | |
1270 | iowrite32(select >> 16, &bp->reg->select); | |
1271 | } | |
1272 | ||
e68462a0 VF |
1273 | static void |
1274 | ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val) | |
1275 | { | |
1276 | unsigned long flags; | |
1277 | ||
1278 | spin_lock_irqsave(&bp->lock, flags); | |
1279 | ||
1280 | bp->utc_tai_offset = val; | |
1281 | ||
1282 | if (bp->irig_out) | |
1283 | iowrite32(val, &bp->irig_out->adj_sec); | |
1284 | if (bp->dcf_out) | |
1285 | iowrite32(val, &bp->dcf_out->adj_sec); | |
1286 | if (bp->nmea_out) | |
1287 | iowrite32(val, &bp->nmea_out->adj_sec); | |
1288 | ||
1289 | spin_unlock_irqrestore(&bp->lock, flags); | |
1290 | } | |
1291 | ||
773bda96 JL |
1292 | static void |
1293 | ptp_ocp_watchdog(struct timer_list *t) | |
1294 | { | |
1295 | struct ptp_ocp *bp = from_timer(bp, t, watchdog); | |
1296 | unsigned long flags; | |
e68462a0 | 1297 | u32 status, utc_offset; |
773bda96 | 1298 | |
0d43d4f2 | 1299 | status = ioread32(&bp->pps_to_clk->status); |
773bda96 JL |
1300 | |
1301 | if (status & PPS_STATUS_SUPERV_ERR) { | |
0d43d4f2 | 1302 | iowrite32(status, &bp->pps_to_clk->status); |
ef0cfb34 | 1303 | if (!bp->gnss_lost) { |
773bda96 JL |
1304 | spin_lock_irqsave(&bp->lock, flags); |
1305 | __ptp_ocp_clear_drift_locked(bp); | |
1306 | spin_unlock_irqrestore(&bp->lock, flags); | |
ef0cfb34 | 1307 | bp->gnss_lost = ktime_get_real_seconds(); |
773bda96 JL |
1308 | } |
1309 | ||
ef0cfb34 JL |
1310 | } else if (bp->gnss_lost) { |
1311 | bp->gnss_lost = 0; | |
773bda96 JL |
1312 | } |
1313 | ||
e68462a0 VF |
1314 | /* if GNSS provides correct data we can rely on |
1315 | * it to get leap second information | |
1316 | */ | |
1317 | if (bp->tod) { | |
1318 | status = ioread32(&bp->tod->utc_status); | |
1319 | utc_offset = status & TOD_STATUS_UTC_MASK; | |
1320 | if (status & TOD_STATUS_UTC_VALID && | |
1321 | utc_offset != bp->utc_tai_offset) | |
1322 | ptp_ocp_utc_distribute(bp, utc_offset); | |
1323 | } | |
1324 | ||
773bda96 JL |
1325 | mod_timer(&bp->watchdog, jiffies + HZ); |
1326 | } | |
1327 | ||
1acffc6e JL |
1328 | static void |
1329 | ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp) | |
1330 | { | |
1331 | ktime_t start, end; | |
1332 | ktime_t delay; | |
1333 | u32 ctrl; | |
1334 | ||
1335 | ctrl = ioread32(&bp->reg->ctrl); | |
1336 | ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE; | |
1337 | ||
1338 | iowrite32(ctrl, &bp->reg->ctrl); | |
1339 | ||
1340 | start = ktime_get_ns(); | |
1341 | ||
1342 | ctrl = ioread32(&bp->reg->ctrl); | |
1343 | ||
1344 | end = ktime_get_ns(); | |
1345 | ||
1346 | delay = end - start; | |
1347 | bp->ts_window_adjust = (delay >> 5) * 3; | |
1348 | } | |
1349 | ||
a7e1abad | 1350 | static int |
773bda96 | 1351 | ptp_ocp_init_clock(struct ptp_ocp *bp) |
a7e1abad JL |
1352 | { |
1353 | struct timespec64 ts; | |
1354 | bool sync; | |
1355 | u32 ctrl; | |
1356 | ||
1acffc6e | 1357 | ctrl = OCP_CTRL_ENABLE; |
a7e1abad JL |
1358 | iowrite32(ctrl, &bp->reg->ctrl); |
1359 | ||
773bda96 JL |
1360 | /* NO DRIFT Correction */ |
1361 | /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */ | |
1362 | iowrite32(0x2000, &bp->reg->servo_offset_p); | |
1363 | iowrite32(0x1000, &bp->reg->servo_offset_i); | |
1364 | iowrite32(0, &bp->reg->servo_drift_p); | |
1365 | iowrite32(0, &bp->reg->servo_drift_i); | |
1366 | ||
1367 | /* latch servo values */ | |
1368 | ctrl |= OCP_CTRL_ADJUST_SERVO; | |
1369 | iowrite32(ctrl, &bp->reg->ctrl); | |
1370 | ||
a7e1abad JL |
1371 | if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { |
1372 | dev_err(&bp->pdev->dev, "clock not enabled\n"); | |
1373 | return -ENODEV; | |
1374 | } | |
1375 | ||
1acffc6e JL |
1376 | ptp_ocp_estimate_pci_timing(bp); |
1377 | ||
a7e1abad JL |
1378 | sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; |
1379 | if (!sync) { | |
065efcc5 | 1380 | ktime_get_clocktai_ts64(&ts); |
a7e1abad JL |
1381 | ptp_ocp_settime(&bp->ptp_info, &ts); |
1382 | } | |
a7e1abad | 1383 | |
065efcc5 JL |
1384 | /* If there is a clock supervisor, then enable the watchdog */ |
1385 | if (bp->pps_to_clk) { | |
1386 | timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); | |
1387 | mod_timer(&bp->watchdog, jiffies + HZ); | |
1388 | } | |
773bda96 | 1389 | |
a7e1abad JL |
1390 | return 0; |
1391 | } | |
1392 | ||
065efcc5 JL |
1393 | static void |
1394 | ptp_ocp_tod_init(struct ptp_ocp *bp) | |
1395 | { | |
1396 | u32 ctrl, reg; | |
1397 | ||
1398 | ctrl = ioread32(&bp->tod->ctrl); | |
1399 | ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE; | |
1400 | ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B); | |
1401 | iowrite32(ctrl, &bp->tod->ctrl); | |
1402 | ||
1403 | reg = ioread32(&bp->tod->utc_status); | |
1404 | if (reg & TOD_STATUS_UTC_VALID) | |
1405 | ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK); | |
1406 | } | |
1407 | ||
9f492c4c VF |
1408 | static const char * |
1409 | ptp_ocp_tod_proto_name(const int idx) | |
a7e1abad JL |
1410 | { |
1411 | static const char * const proto_name[] = { | |
1412 | "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none", | |
1413 | "UBX", "UBX_UTC", "UBX_LS", "UBX_none" | |
1414 | }; | |
9f492c4c VF |
1415 | return proto_name[idx]; |
1416 | } | |
1417 | ||
1418 | static const char * | |
1419 | ptp_ocp_tod_gnss_name(int idx) | |
1420 | { | |
a7e1abad JL |
1421 | static const char * const gnss_name[] = { |
1422 | "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU", | |
9f492c4c | 1423 | "Unknown" |
a7e1abad | 1424 | }; |
72f00505 | 1425 | if (idx >= ARRAY_SIZE(gnss_name)) |
9f492c4c VF |
1426 | idx = ARRAY_SIZE(gnss_name) - 1; |
1427 | return gnss_name[idx]; | |
a7e1abad JL |
1428 | } |
1429 | ||
0cfcdd1e JL |
1430 | struct ptp_ocp_nvmem_match_info { |
1431 | struct ptp_ocp *bp; | |
1432 | const void * const tag; | |
1433 | }; | |
1434 | ||
773bda96 | 1435 | static int |
0cfcdd1e | 1436 | ptp_ocp_nvmem_match(struct device *dev, const void *data) |
773bda96 | 1437 | { |
0cfcdd1e JL |
1438 | const struct ptp_ocp_nvmem_match_info *info = data; |
1439 | ||
1440 | dev = dev->parent; | |
1441 | if (!i2c_verify_client(dev) || info->tag != dev->platform_data) | |
1442 | return 0; | |
1443 | ||
1444 | while ((dev = dev->parent)) | |
1445 | if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) | |
1446 | return info->bp == dev_get_drvdata(dev); | |
1447 | return 0; | |
773bda96 JL |
1448 | } |
1449 | ||
0cfcdd1e JL |
1450 | static inline struct nvmem_device * |
1451 | ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag) | |
773bda96 | 1452 | { |
0cfcdd1e JL |
1453 | struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag }; |
1454 | ||
1455 | return nvmem_device_find(&info, ptp_ocp_nvmem_match); | |
1456 | } | |
1457 | ||
1458 | static inline void | |
1459 | ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp) | |
1460 | { | |
8f0588e8 | 1461 | if (!IS_ERR_OR_NULL(*nvmemp)) |
0cfcdd1e | 1462 | nvmem_device_put(*nvmemp); |
8f0588e8 | 1463 | *nvmemp = NULL; |
773bda96 JL |
1464 | } |
1465 | ||
1466 | static void | |
0cfcdd1e | 1467 | ptp_ocp_read_eeprom(struct ptp_ocp *bp) |
773bda96 | 1468 | { |
0cfcdd1e JL |
1469 | const struct ptp_ocp_eeprom_map *map; |
1470 | struct nvmem_device *nvmem; | |
1471 | const void *tag; | |
1472 | int ret; | |
773bda96 | 1473 | |
1447149d JL |
1474 | if (!bp->i2c_ctrl) |
1475 | return; | |
1476 | ||
0cfcdd1e JL |
1477 | tag = NULL; |
1478 | nvmem = NULL; | |
773bda96 | 1479 | |
0cfcdd1e JL |
1480 | for (map = bp->eeprom_map; map->len; map++) { |
1481 | if (map->tag != tag) { | |
1482 | tag = map->tag; | |
1483 | ptp_ocp_nvmem_device_put(&nvmem); | |
1484 | } | |
1485 | if (!nvmem) { | |
1486 | nvmem = ptp_ocp_nvmem_device_get(bp, tag); | |
8f0588e8 JL |
1487 | if (IS_ERR(nvmem)) { |
1488 | ret = PTR_ERR(nvmem); | |
1489 | goto fail; | |
1490 | } | |
0cfcdd1e JL |
1491 | } |
1492 | ret = nvmem_device_read(nvmem, map->off, map->len, | |
1493 | BP_MAP_ENTRY_ADDR(bp, map)); | |
1494 | if (ret != map->len) | |
8f0588e8 | 1495 | goto fail; |
773bda96 JL |
1496 | } |
1497 | ||
0cfcdd1e | 1498 | bp->has_eeprom_data = true; |
773bda96 JL |
1499 | |
1500 | out: | |
0cfcdd1e JL |
1501 | ptp_ocp_nvmem_device_put(&nvmem); |
1502 | return; | |
1503 | ||
8f0588e8 | 1504 | fail: |
0cfcdd1e JL |
1505 | dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret); |
1506 | goto out; | |
1507 | } | |
1508 | ||
773bda96 JL |
1509 | static struct device * |
1510 | ptp_ocp_find_flash(struct ptp_ocp *bp) | |
1511 | { | |
1512 | struct device *dev, *last; | |
1513 | ||
1514 | last = NULL; | |
1515 | dev = &bp->spi_flash->dev; | |
1516 | ||
304843c7 | 1517 | while ((dev = device_find_any_child(dev))) { |
773bda96 JL |
1518 | if (!strcmp("mtd", dev_bus_name(dev))) |
1519 | break; | |
1520 | put_device(last); | |
1521 | last = dev; | |
1522 | } | |
1523 | put_device(last); | |
1524 | ||
1525 | return dev; | |
1526 | } | |
1527 | ||
3c3673bd VF |
1528 | static int |
1529 | ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw, | |
1530 | const u8 **data, size_t *size) | |
1531 | { | |
1532 | struct ptp_ocp *bp = devlink_priv(devlink); | |
1533 | const struct ptp_ocp_firmware_header *hdr; | |
1534 | size_t offset, length; | |
1535 | u16 crc; | |
1536 | ||
1537 | hdr = (const struct ptp_ocp_firmware_header *)fw->data; | |
1538 | if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) { | |
1539 | devlink_flash_update_status_notify(devlink, | |
c1fd463d | 1540 | "No firmware header found, cancel firmware upgrade", |
3c3673bd | 1541 | NULL, 0, 0); |
c1fd463d | 1542 | return -EINVAL; |
3c3673bd VF |
1543 | } |
1544 | ||
1545 | if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor || | |
1546 | be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) { | |
1547 | devlink_flash_update_status_notify(devlink, | |
1548 | "Firmware image compatibility check failed", | |
1549 | NULL, 0, 0); | |
1550 | return -EINVAL; | |
1551 | } | |
1552 | ||
1553 | offset = sizeof(*hdr); | |
1554 | length = be32_to_cpu(hdr->image_size); | |
1555 | if (length != (fw->size - offset)) { | |
1556 | devlink_flash_update_status_notify(devlink, | |
1557 | "Firmware image size check failed", | |
1558 | NULL, 0, 0); | |
1559 | return -EINVAL; | |
1560 | } | |
1561 | ||
1562 | crc = crc16(0xffff, &fw->data[offset], length); | |
1563 | if (be16_to_cpu(hdr->crc) != crc) { | |
1564 | devlink_flash_update_status_notify(devlink, | |
1565 | "Firmware image CRC check failed", | |
1566 | NULL, 0, 0); | |
1567 | return -EINVAL; | |
1568 | } | |
1569 | ||
3c3673bd VF |
1570 | *data = &fw->data[offset]; |
1571 | *size = length; | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
773bda96 JL |
1576 | static int |
1577 | ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev, | |
1578 | const struct firmware *fw) | |
1579 | { | |
1580 | struct mtd_info *mtd = dev_get_drvdata(dev); | |
1581 | struct ptp_ocp *bp = devlink_priv(devlink); | |
3c3673bd | 1582 | size_t off, len, size, resid, wrote; |
773bda96 JL |
1583 | struct erase_info erase; |
1584 | size_t base, blksz; | |
3c3673bd VF |
1585 | const u8 *data; |
1586 | int err; | |
1587 | ||
1588 | err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size); | |
1589 | if (err) | |
1590 | goto out; | |
773bda96 JL |
1591 | |
1592 | off = 0; | |
1593 | base = bp->flash_start; | |
1594 | blksz = 4096; | |
3c3673bd | 1595 | resid = size; |
773bda96 JL |
1596 | |
1597 | while (resid) { | |
1598 | devlink_flash_update_status_notify(devlink, "Flashing", | |
3c3673bd | 1599 | NULL, off, size); |
773bda96 JL |
1600 | |
1601 | len = min_t(size_t, resid, blksz); | |
1602 | erase.addr = base + off; | |
1603 | erase.len = blksz; | |
1604 | ||
1605 | err = mtd_erase(mtd, &erase); | |
1606 | if (err) | |
1607 | goto out; | |
1608 | ||
3c3673bd | 1609 | err = mtd_write(mtd, base + off, len, &wrote, data + off); |
773bda96 JL |
1610 | if (err) |
1611 | goto out; | |
1612 | ||
1613 | off += blksz; | |
1614 | resid -= len; | |
1615 | } | |
1616 | out: | |
1617 | return err; | |
1618 | } | |
1619 | ||
1620 | static int | |
1621 | ptp_ocp_devlink_flash_update(struct devlink *devlink, | |
1622 | struct devlink_flash_update_params *params, | |
1623 | struct netlink_ext_ack *extack) | |
1624 | { | |
1625 | struct ptp_ocp *bp = devlink_priv(devlink); | |
1626 | struct device *dev; | |
1627 | const char *msg; | |
1628 | int err; | |
1629 | ||
1630 | dev = ptp_ocp_find_flash(bp); | |
1631 | if (!dev) { | |
1632 | dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n"); | |
1633 | return -ENODEV; | |
1634 | } | |
1635 | ||
1636 | devlink_flash_update_status_notify(devlink, "Preparing to flash", | |
1637 | NULL, 0, 0); | |
1638 | ||
1639 | err = ptp_ocp_devlink_flash(devlink, dev, params->fw); | |
1640 | ||
1641 | msg = err ? "Flash error" : "Flash complete"; | |
1642 | devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); | |
1643 | ||
773bda96 JL |
1644 | put_device(dev); |
1645 | return err; | |
1646 | } | |
1647 | ||
1648 | static int | |
1649 | ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, | |
1650 | struct netlink_ext_ack *extack) | |
1651 | { | |
1652 | struct ptp_ocp *bp = devlink_priv(devlink); | |
5a728ac5 | 1653 | const char *fw_image; |
773bda96 JL |
1654 | char buf[32]; |
1655 | int err; | |
1656 | ||
5a728ac5 JL |
1657 | fw_image = bp->fw_loader ? "loader" : "fw"; |
1658 | sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version); | |
1659 | err = devlink_info_version_running_put(req, fw_image, buf); | |
b0ca789a JL |
1660 | if (err) |
1661 | return err; | |
773bda96 | 1662 | |
0cfcdd1e JL |
1663 | if (!bp->has_eeprom_data) { |
1664 | ptp_ocp_read_eeprom(bp); | |
1665 | if (!bp->has_eeprom_data) | |
1666 | return 0; | |
773bda96 JL |
1667 | } |
1668 | ||
0cfcdd1e JL |
1669 | sprintf(buf, "%pM", bp->serial); |
1670 | err = devlink_info_serial_number_put(req, buf); | |
1671 | if (err) | |
1672 | return err; | |
1673 | ||
1674 | err = devlink_info_version_fixed_put(req, | |
1675 | DEVLINK_INFO_VERSION_GENERIC_BOARD_ID, | |
1676 | bp->board_id); | |
1677 | if (err) | |
1678 | return err; | |
1679 | ||
773bda96 JL |
1680 | return 0; |
1681 | } | |
1682 | ||
1683 | static const struct devlink_ops ptp_ocp_devlink_ops = { | |
1684 | .flash_update = ptp_ocp_devlink_flash_update, | |
1685 | .info_get = ptp_ocp_devlink_info_get, | |
1686 | }; | |
1687 | ||
773bda96 | 1688 | static void __iomem * |
8119c9ee | 1689 | __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size) |
773bda96 JL |
1690 | { |
1691 | struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp"); | |
1692 | ||
1693 | return devm_ioremap_resource(&bp->pdev->dev, &res); | |
1694 | } | |
1695 | ||
1696 | static void __iomem * | |
1697 | ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r) | |
1698 | { | |
8119c9ee | 1699 | resource_size_t start; |
773bda96 JL |
1700 | |
1701 | start = pci_resource_start(bp->pdev, 0) + r->offset; | |
1702 | return __ptp_ocp_get_mem(bp, start, r->size); | |
1703 | } | |
1704 | ||
1705 | static void | |
1706 | ptp_ocp_set_irq_resource(struct resource *res, int irq) | |
1707 | { | |
1708 | struct resource r = DEFINE_RES_IRQ(irq); | |
1709 | *res = r; | |
1710 | } | |
1711 | ||
1712 | static void | |
8119c9ee | 1713 | ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size) |
773bda96 JL |
1714 | { |
1715 | struct resource r = DEFINE_RES_MEM(start, size); | |
1716 | *res = r; | |
1717 | } | |
1718 | ||
1719 | static int | |
1720 | ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r) | |
1721 | { | |
1722 | struct ptp_ocp_flash_info *info; | |
1723 | struct pci_dev *pdev = bp->pdev; | |
1724 | struct platform_device *p; | |
1725 | struct resource res[2]; | |
8119c9ee | 1726 | resource_size_t start; |
773bda96 JL |
1727 | int id; |
1728 | ||
773bda96 JL |
1729 | start = pci_resource_start(pdev, 0) + r->offset; |
1730 | ptp_ocp_set_mem_resource(&res[0], start, r->size); | |
1731 | ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); | |
1732 | ||
1733 | info = r->extra; | |
1734 | id = pci_dev_id(pdev) << 1; | |
1735 | id += info->pci_offset; | |
1736 | ||
1737 | p = platform_device_register_resndata(&pdev->dev, info->name, id, | |
1738 | res, 2, info->data, | |
1739 | info->data_size); | |
1740 | if (IS_ERR(p)) | |
1741 | return PTR_ERR(p); | |
1742 | ||
1743 | bp_assign_entry(bp, r, p); | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
1748 | static struct platform_device * | |
1749 | ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id) | |
1750 | { | |
1618df6a | 1751 | struct ptp_ocp_i2c_info *info; |
773bda96 | 1752 | struct resource res[2]; |
8119c9ee | 1753 | resource_size_t start; |
773bda96 | 1754 | |
1618df6a | 1755 | info = r->extra; |
773bda96 JL |
1756 | start = pci_resource_start(pdev, 0) + r->offset; |
1757 | ptp_ocp_set_mem_resource(&res[0], start, r->size); | |
1758 | ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); | |
1759 | ||
1618df6a JL |
1760 | return platform_device_register_resndata(&pdev->dev, info->name, |
1761 | id, res, 2, | |
1762 | info->data, info->data_size); | |
773bda96 JL |
1763 | } |
1764 | ||
1765 | static int | |
1766 | ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r) | |
1767 | { | |
1768 | struct pci_dev *pdev = bp->pdev; | |
1618df6a | 1769 | struct ptp_ocp_i2c_info *info; |
773bda96 JL |
1770 | struct platform_device *p; |
1771 | struct clk_hw *clk; | |
1772 | char buf[32]; | |
1773 | int id; | |
1774 | ||
1618df6a | 1775 | info = r->extra; |
773bda96 JL |
1776 | id = pci_dev_id(bp->pdev); |
1777 | ||
1778 | sprintf(buf, "AXI.%d", id); | |
1618df6a JL |
1779 | clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, |
1780 | info->fixed_rate); | |
773bda96 JL |
1781 | if (IS_ERR(clk)) |
1782 | return PTR_ERR(clk); | |
1783 | bp->i2c_clk = clk; | |
1784 | ||
1618df6a | 1785 | sprintf(buf, "%s.%d", info->name, id); |
773bda96 JL |
1786 | devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf); |
1787 | p = ptp_ocp_i2c_bus(bp->pdev, r, id); | |
1788 | if (IS_ERR(p)) | |
1789 | return PTR_ERR(p); | |
1790 | ||
1791 | bp_assign_entry(bp, r, p); | |
1792 | ||
1793 | return 0; | |
1794 | } | |
1795 | ||
b325af3c JL |
1796 | /* The expectation is that this is triggered only on error. */ |
1797 | static irqreturn_t | |
1798 | ptp_ocp_signal_irq(int irq, void *priv) | |
1799 | { | |
1800 | struct ptp_ocp_ext_src *ext = priv; | |
1801 | struct signal_reg __iomem *reg = ext->mem; | |
1802 | struct ptp_ocp *bp = ext->bp; | |
1803 | u32 enable, status; | |
1804 | int gen; | |
1805 | ||
1806 | gen = ext->info->index - 1; | |
1807 | ||
1808 | enable = ioread32(®->enable); | |
1809 | status = ioread32(®->status); | |
1810 | ||
1811 | /* disable generator on error */ | |
1812 | if (status || !enable) { | |
1813 | iowrite32(0, ®->intr_mask); | |
1814 | iowrite32(0, ®->enable); | |
1815 | bp->signal[gen].running = false; | |
1816 | } | |
1817 | ||
1818 | iowrite32(0, ®->intr); /* ack interrupt */ | |
1819 | ||
1820 | return IRQ_HANDLED; | |
1821 | } | |
1822 | ||
1823 | static int | |
1824 | ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s) | |
1825 | { | |
1826 | struct ptp_system_timestamp sts; | |
1827 | struct timespec64 ts; | |
1828 | ktime_t start_ns; | |
1829 | int err; | |
1830 | ||
1831 | if (!s->period) | |
1832 | return 0; | |
1833 | ||
1834 | if (!s->pulse) | |
1835 | s->pulse = ktime_divns(s->period * s->duty, 100); | |
1836 | ||
1837 | err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts); | |
1838 | if (err) | |
1839 | return err; | |
1840 | ||
1841 | start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC; | |
1842 | if (!s->start) { | |
1843 | /* roundup() does not work on 32-bit systems */ | |
4bd46bb0 | 1844 | s->start = DIV64_U64_ROUND_UP(start_ns, s->period); |
b325af3c JL |
1845 | s->start = ktime_add(s->start, s->phase); |
1846 | } | |
1847 | ||
1848 | if (s->duty < 1 || s->duty > 99) | |
1849 | return -EINVAL; | |
1850 | ||
1851 | if (s->pulse < 1 || s->pulse > s->period) | |
1852 | return -EINVAL; | |
1853 | ||
1854 | if (s->start < start_ns) | |
1855 | return -EINVAL; | |
1856 | ||
1857 | bp->signal[gen] = *s; | |
1858 | ||
1859 | return 0; | |
1860 | } | |
1861 | ||
1aa66a3a JL |
1862 | static int |
1863 | ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen, | |
1864 | struct ptp_perout_request *req) | |
1865 | { | |
1866 | struct ptp_ocp_signal s = { }; | |
1867 | ||
1868 | s.polarity = bp->signal[gen].polarity; | |
1869 | s.period = ktime_set(req->period.sec, req->period.nsec); | |
1870 | if (!s.period) | |
1871 | return 0; | |
1872 | ||
1873 | if (req->flags & PTP_PEROUT_DUTY_CYCLE) { | |
1874 | s.pulse = ktime_set(req->on.sec, req->on.nsec); | |
1875 | s.duty = ktime_divns(s.pulse * 100, s.period); | |
1876 | } | |
1877 | ||
1878 | if (req->flags & PTP_PEROUT_PHASE) | |
1879 | s.phase = ktime_set(req->phase.sec, req->phase.nsec); | |
1880 | else | |
1881 | s.start = ktime_set(req->start.sec, req->start.nsec); | |
1882 | ||
1883 | return ptp_ocp_signal_set(bp, gen, &s); | |
1884 | } | |
1885 | ||
b325af3c JL |
1886 | static int |
1887 | ptp_ocp_signal_enable(void *priv, u32 req, bool enable) | |
1888 | { | |
1889 | struct ptp_ocp_ext_src *ext = priv; | |
1890 | struct signal_reg __iomem *reg = ext->mem; | |
1891 | struct ptp_ocp *bp = ext->bp; | |
1892 | struct timespec64 ts; | |
1893 | int gen; | |
1894 | ||
1895 | gen = ext->info->index - 1; | |
1896 | ||
1897 | iowrite32(0, ®->intr_mask); | |
1898 | iowrite32(0, ®->enable); | |
1899 | bp->signal[gen].running = false; | |
1900 | if (!enable) | |
1901 | return 0; | |
1902 | ||
1903 | ts = ktime_to_timespec64(bp->signal[gen].start); | |
1904 | iowrite32(ts.tv_sec, ®->start_sec); | |
1905 | iowrite32(ts.tv_nsec, ®->start_ns); | |
1906 | ||
1907 | ts = ktime_to_timespec64(bp->signal[gen].period); | |
1908 | iowrite32(ts.tv_sec, ®->period_sec); | |
1909 | iowrite32(ts.tv_nsec, ®->period_ns); | |
1910 | ||
1911 | ts = ktime_to_timespec64(bp->signal[gen].pulse); | |
1912 | iowrite32(ts.tv_sec, ®->pulse_sec); | |
1913 | iowrite32(ts.tv_nsec, ®->pulse_ns); | |
1914 | ||
1915 | iowrite32(bp->signal[gen].polarity, ®->polarity); | |
1916 | iowrite32(0, ®->repeat_count); | |
1917 | ||
1918 | iowrite32(0, ®->intr); /* clear interrupt state */ | |
1919 | iowrite32(1, ®->intr_mask); /* enable interrupt */ | |
1920 | iowrite32(3, ®->enable); /* valid & enable */ | |
1921 | ||
1922 | bp->signal[gen].running = true; | |
1923 | ||
1924 | return 0; | |
1925 | } | |
1926 | ||
773bda96 JL |
1927 | static irqreturn_t |
1928 | ptp_ocp_ts_irq(int irq, void *priv) | |
1929 | { | |
1930 | struct ptp_ocp_ext_src *ext = priv; | |
1931 | struct ts_reg __iomem *reg = ext->mem; | |
1932 | struct ptp_clock_event ev; | |
1933 | u32 sec, nsec; | |
1934 | ||
a62a56d0 JL |
1935 | if (ext == ext->bp->pps) { |
1936 | if (ext->bp->pps_req_map & OCP_REQ_PPS) { | |
1937 | ev.type = PTP_CLOCK_PPS; | |
1938 | ptp_clock_event(ext->bp->ptp, &ev); | |
1939 | } | |
1940 | ||
1941 | if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) | |
1942 | goto out; | |
1943 | } | |
1944 | ||
773bda96 JL |
1945 | /* XXX should fix API - this converts s/ns -> ts -> s/ns */ |
1946 | sec = ioread32(®->time_sec); | |
1947 | nsec = ioread32(®->time_ns); | |
1948 | ||
1949 | ev.type = PTP_CLOCK_EXTTS; | |
1950 | ev.index = ext->info->index; | |
1acffc6e | 1951 | ev.timestamp = sec * NSEC_PER_SEC + nsec; |
773bda96 JL |
1952 | |
1953 | ptp_clock_event(ext->bp->ptp, &ev); | |
1954 | ||
a62a56d0 | 1955 | out: |
773bda96 JL |
1956 | iowrite32(1, ®->intr); /* write 1 to ack */ |
1957 | ||
1958 | return IRQ_HANDLED; | |
1959 | } | |
1960 | ||
1961 | static int | |
a62a56d0 | 1962 | ptp_ocp_ts_enable(void *priv, u32 req, bool enable) |
773bda96 JL |
1963 | { |
1964 | struct ptp_ocp_ext_src *ext = priv; | |
1965 | struct ts_reg __iomem *reg = ext->mem; | |
a62a56d0 JL |
1966 | struct ptp_ocp *bp = ext->bp; |
1967 | ||
1968 | if (ext == bp->pps) { | |
1969 | u32 old_map = bp->pps_req_map; | |
1970 | ||
1971 | if (enable) | |
1972 | bp->pps_req_map |= req; | |
1973 | else | |
1974 | bp->pps_req_map &= ~req; | |
1975 | ||
1976 | /* if no state change, just return */ | |
1977 | if ((!!old_map ^ !!bp->pps_req_map) == 0) | |
1978 | return 0; | |
1979 | } | |
773bda96 JL |
1980 | |
1981 | if (enable) { | |
1982 | iowrite32(1, ®->enable); | |
1983 | iowrite32(1, ®->intr_mask); | |
1984 | iowrite32(1, ®->intr); | |
1985 | } else { | |
1986 | iowrite32(0, ®->intr_mask); | |
1987 | iowrite32(0, ®->enable); | |
1988 | } | |
1989 | ||
1990 | return 0; | |
1991 | } | |
1992 | ||
1993 | static void | |
1994 | ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext) | |
1995 | { | |
a62a56d0 | 1996 | ext->info->enable(ext, ~0, false); |
773bda96 JL |
1997 | pci_free_irq(ext->bp->pdev, ext->irq_vec, ext); |
1998 | kfree(ext); | |
1999 | } | |
2000 | ||
2001 | static int | |
2002 | ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r) | |
2003 | { | |
2004 | struct pci_dev *pdev = bp->pdev; | |
2005 | struct ptp_ocp_ext_src *ext; | |
2006 | int err; | |
2007 | ||
2008 | ext = kzalloc(sizeof(*ext), GFP_KERNEL); | |
2009 | if (!ext) | |
a7e1abad | 2010 | return -ENOMEM; |
a7e1abad | 2011 | |
773bda96 | 2012 | ext->mem = ptp_ocp_get_mem(bp, r); |
c7521d3a DC |
2013 | if (IS_ERR(ext->mem)) { |
2014 | err = PTR_ERR(ext->mem); | |
773bda96 | 2015 | goto out; |
c7521d3a | 2016 | } |
773bda96 JL |
2017 | |
2018 | ext->bp = bp; | |
2019 | ext->info = r->extra; | |
2020 | ext->irq_vec = r->irq_vec; | |
2021 | ||
2022 | err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL, | |
56ec4403 | 2023 | ext, "ocp%d.%s", bp->id, r->name); |
a7e1abad | 2024 | if (err) { |
773bda96 JL |
2025 | dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec); |
2026 | goto out; | |
a7e1abad JL |
2027 | } |
2028 | ||
773bda96 JL |
2029 | bp_assign_entry(bp, r, ext); |
2030 | ||
2031 | return 0; | |
2032 | ||
2033 | out: | |
2034 | kfree(ext); | |
2035 | return err; | |
2036 | } | |
2037 | ||
2038 | static int | |
2039 | ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r) | |
2040 | { | |
2041 | struct pci_dev *pdev = bp->pdev; | |
2042 | struct uart_8250_port uart; | |
2043 | ||
2044 | /* Setting UPF_IOREMAP and leaving port.membase unspecified lets | |
2045 | * the serial port device claim and release the pci resource. | |
2046 | */ | |
2047 | memset(&uart, 0, sizeof(uart)); | |
2048 | uart.port.dev = &pdev->dev; | |
2049 | uart.port.iotype = UPIO_MEM; | |
2050 | uart.port.regshift = 2; | |
2051 | uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; | |
2052 | uart.port.irq = pci_irq_vector(pdev, r->irq_vec); | |
2053 | uart.port.uartclk = 50000000; | |
c17c4059 | 2054 | uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST; |
773bda96 JL |
2055 | uart.port.type = PORT_16550A; |
2056 | ||
2057 | return serial8250_register_8250_port(&uart); | |
2058 | } | |
2059 | ||
2060 | static int | |
2061 | ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r) | |
2062 | { | |
895ac5a5 VF |
2063 | struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra; |
2064 | struct ptp_ocp_serial_port port = {}; | |
2065 | ||
2066 | port.line = ptp_ocp_serial_line(bp, r); | |
2067 | if (port.line < 0) | |
2068 | return port.line; | |
773bda96 | 2069 | |
895ac5a5 VF |
2070 | if (p) |
2071 | port.baud = p->baud; | |
773bda96 JL |
2072 | |
2073 | bp_assign_entry(bp, r, port); | |
2074 | ||
2075 | return 0; | |
2076 | } | |
2077 | ||
2078 | static int | |
2079 | ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r) | |
2080 | { | |
2081 | void __iomem *mem; | |
2082 | ||
2083 | mem = ptp_ocp_get_mem(bp, r); | |
c7521d3a DC |
2084 | if (IS_ERR(mem)) |
2085 | return PTR_ERR(mem); | |
773bda96 JL |
2086 | |
2087 | bp_assign_entry(bp, r, mem); | |
2088 | ||
2089 | return 0; | |
2090 | } | |
2091 | ||
e3516bb4 JL |
2092 | static void |
2093 | ptp_ocp_nmea_out_init(struct ptp_ocp *bp) | |
2094 | { | |
2095 | if (!bp->nmea_out) | |
2096 | return; | |
2097 | ||
2098 | iowrite32(0, &bp->nmea_out->ctrl); /* disable */ | |
2099 | iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */ | |
2100 | iowrite32(1, &bp->nmea_out->ctrl); /* enable */ | |
2101 | } | |
2102 | ||
b325af3c JL |
2103 | static void |
2104 | _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg) | |
2105 | { | |
2106 | u32 val; | |
2107 | ||
2108 | iowrite32(0, ®->enable); /* disable */ | |
2109 | ||
2110 | val = ioread32(®->polarity); | |
2111 | s->polarity = val ? true : false; | |
2112 | s->duty = 50; | |
2113 | } | |
2114 | ||
2115 | static void | |
2116 | ptp_ocp_signal_init(struct ptp_ocp *bp) | |
2117 | { | |
2118 | int i; | |
2119 | ||
2120 | for (i = 0; i < 4; i++) | |
2121 | if (bp->signal_out[i]) | |
2122 | _ptp_ocp_signal_init(&bp->signal[i], | |
2123 | bp->signal_out[i]->mem); | |
2124 | } | |
2125 | ||
c2239294 JL |
2126 | static void |
2127 | ptp_ocp_attr_group_del(struct ptp_ocp *bp) | |
2128 | { | |
2129 | sysfs_remove_groups(&bp->dev.kobj, bp->attr_group); | |
2130 | kfree(bp->attr_group); | |
2131 | } | |
2132 | ||
2133 | static int | |
2134 | ptp_ocp_attr_group_add(struct ptp_ocp *bp, | |
2135 | const struct ocp_attr_group *attr_tbl) | |
2136 | { | |
2137 | int count, i; | |
2138 | int err; | |
2139 | ||
2140 | count = 0; | |
2141 | for (i = 0; attr_tbl[i].cap; i++) | |
2142 | if (attr_tbl[i].cap & bp->fw_cap) | |
2143 | count++; | |
2144 | ||
2145 | bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *), | |
2146 | GFP_KERNEL); | |
2147 | if (!bp->attr_group) | |
2148 | return -ENOMEM; | |
2149 | ||
2150 | count = 0; | |
2151 | for (i = 0; attr_tbl[i].cap; i++) | |
2152 | if (attr_tbl[i].cap & bp->fw_cap) | |
2153 | bp->attr_group[count++] = attr_tbl[i].group; | |
2154 | ||
2155 | err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group); | |
2156 | if (err) | |
2157 | bp->attr_group[0] = NULL; | |
2158 | ||
2159 | return err; | |
2160 | } | |
2161 | ||
caab82cd JL |
2162 | static void |
2163 | ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable) | |
2164 | { | |
2165 | u32 ctrl; | |
2166 | bool on; | |
2167 | ||
2168 | ctrl = ioread32(reg); | |
2169 | on = ctrl & bit; | |
2170 | if (on ^ enable) { | |
2171 | ctrl &= ~bit; | |
2172 | ctrl |= enable ? bit : 0; | |
2173 | iowrite32(ctrl, reg); | |
2174 | } | |
2175 | } | |
2176 | ||
2177 | static void | |
2178 | ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable) | |
2179 | { | |
2180 | return ptp_ocp_enable_fpga(&bp->irig_out->ctrl, | |
2181 | IRIG_M_CTRL_ENABLE, enable); | |
2182 | } | |
2183 | ||
2184 | static void | |
2185 | ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable) | |
2186 | { | |
2187 | return ptp_ocp_enable_fpga(&bp->irig_in->ctrl, | |
2188 | IRIG_S_CTRL_ENABLE, enable); | |
2189 | } | |
2190 | ||
2191 | static void | |
2192 | ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable) | |
2193 | { | |
2194 | return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl, | |
2195 | DCF_M_CTRL_ENABLE, enable); | |
2196 | } | |
2197 | ||
2198 | static void | |
2199 | ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable) | |
2200 | { | |
2201 | return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl, | |
2202 | DCF_S_CTRL_ENABLE, enable); | |
2203 | } | |
2204 | ||
2205 | static void | |
2206 | __handle_signal_outputs(struct ptp_ocp *bp, u32 val) | |
2207 | { | |
2208 | ptp_ocp_irig_out(bp, val & 0x00100010); | |
2209 | ptp_ocp_dcf_out(bp, val & 0x00200020); | |
2210 | } | |
2211 | ||
2212 | static void | |
2213 | __handle_signal_inputs(struct ptp_ocp *bp, u32 val) | |
2214 | { | |
2215 | ptp_ocp_irig_in(bp, val & 0x00100010); | |
2216 | ptp_ocp_dcf_in(bp, val & 0x00200020); | |
2217 | } | |
2218 | ||
2219 | static u32 | |
2220 | ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr) | |
2221 | { | |
2222 | u32 __iomem *gpio; | |
2223 | u32 shift; | |
2224 | ||
2225 | if (bp->sma[sma_nr - 1].fixed_fcn) | |
2226 | return (sma_nr - 1) & 1; | |
2227 | ||
2228 | if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN) | |
2229 | gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1; | |
2230 | else | |
2231 | gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2; | |
2232 | shift = sma_nr & 1 ? 0 : 16; | |
2233 | ||
2234 | return (ioread32(gpio) >> shift) & 0xffff; | |
2235 | } | |
2236 | ||
2237 | static int | |
2238 | ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val) | |
2239 | { | |
2240 | u32 reg, mask, shift; | |
2241 | unsigned long flags; | |
2242 | u32 __iomem *gpio; | |
2243 | ||
2244 | gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2; | |
2245 | shift = sma_nr & 1 ? 0 : 16; | |
2246 | ||
2247 | mask = 0xffff << (16 - shift); | |
2248 | ||
2249 | spin_lock_irqsave(&bp->lock, flags); | |
2250 | ||
2251 | reg = ioread32(gpio); | |
2252 | reg = (reg & mask) | (val << shift); | |
2253 | ||
2254 | __handle_signal_outputs(bp, reg); | |
2255 | ||
2256 | iowrite32(reg, gpio); | |
2257 | ||
2258 | spin_unlock_irqrestore(&bp->lock, flags); | |
2259 | ||
2260 | return 0; | |
2261 | } | |
2262 | ||
2263 | static int | |
2264 | ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val) | |
2265 | { | |
2266 | u32 reg, mask, shift; | |
2267 | unsigned long flags; | |
2268 | u32 __iomem *gpio; | |
2269 | ||
2270 | gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1; | |
2271 | shift = sma_nr & 1 ? 0 : 16; | |
2272 | ||
2273 | mask = 0xffff << (16 - shift); | |
2274 | ||
2275 | spin_lock_irqsave(&bp->lock, flags); | |
2276 | ||
2277 | reg = ioread32(gpio); | |
2278 | reg = (reg & mask) | (val << shift); | |
2279 | ||
2280 | __handle_signal_inputs(bp, reg); | |
2281 | ||
2282 | iowrite32(reg, gpio); | |
2283 | ||
2284 | spin_unlock_irqrestore(&bp->lock, flags); | |
2285 | ||
2286 | return 0; | |
2287 | } | |
2288 | ||
a509a7c6 | 2289 | static void |
ee4cd725 | 2290 | ptp_ocp_sma_fb_init(struct ptp_ocp *bp) |
a509a7c6 JL |
2291 | { |
2292 | u32 reg; | |
2293 | int i; | |
2294 | ||
2295 | /* defaults */ | |
2296 | bp->sma[0].mode = SMA_MODE_IN; | |
2297 | bp->sma[1].mode = SMA_MODE_IN; | |
2298 | bp->sma[2].mode = SMA_MODE_OUT; | |
2299 | bp->sma[3].mode = SMA_MODE_OUT; | |
ee4cd725 JL |
2300 | for (i = 0; i < 4; i++) |
2301 | bp->sma[i].default_fcn = i & 1; | |
a509a7c6 JL |
2302 | |
2303 | /* If no SMA1 map, the pin functions and directions are fixed. */ | |
2304 | if (!bp->sma_map1) { | |
2305 | for (i = 0; i < 4; i++) { | |
2306 | bp->sma[i].fixed_fcn = true; | |
2307 | bp->sma[i].fixed_dir = true; | |
2308 | } | |
2309 | return; | |
2310 | } | |
2311 | ||
2312 | /* If SMA2 GPIO output map is all 1, it is not present. | |
2313 | * This indicates the firmware has fixed direction SMA pins. | |
2314 | */ | |
2315 | reg = ioread32(&bp->sma_map2->gpio2); | |
2316 | if (reg == 0xffffffff) { | |
2317 | for (i = 0; i < 4; i++) | |
2318 | bp->sma[i].fixed_dir = true; | |
2319 | } else { | |
2320 | reg = ioread32(&bp->sma_map1->gpio1); | |
2321 | bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT; | |
2322 | bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT; | |
2323 | ||
2324 | reg = ioread32(&bp->sma_map1->gpio2); | |
2325 | bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN; | |
2326 | bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN; | |
2327 | } | |
2328 | } | |
2329 | ||
ee4cd725 JL |
2330 | static const struct ocp_sma_op ocp_fb_sma_op = { |
2331 | .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out }, | |
2332 | .init = ptp_ocp_sma_fb_init, | |
2333 | .get = ptp_ocp_sma_fb_get, | |
2334 | .set_inputs = ptp_ocp_sma_fb_set_inputs, | |
2335 | .set_output = ptp_ocp_sma_fb_set_output, | |
2336 | }; | |
2337 | ||
1aa66a3a JL |
2338 | static int |
2339 | ptp_ocp_fb_set_pins(struct ptp_ocp *bp) | |
2340 | { | |
2341 | struct ptp_pin_desc *config; | |
2342 | int i; | |
2343 | ||
9a7a1be6 | 2344 | config = kcalloc(4, sizeof(*config), GFP_KERNEL); |
1aa66a3a JL |
2345 | if (!config) |
2346 | return -ENOMEM; | |
2347 | ||
2348 | for (i = 0; i < 4; i++) { | |
2349 | sprintf(config[i].name, "sma%d", i + 1); | |
2350 | config[i].index = i; | |
2351 | } | |
2352 | ||
2353 | bp->ptp_info.n_pins = 4; | |
2354 | bp->ptp_info.pin_config = config; | |
2355 | ||
2356 | return 0; | |
2357 | } | |
2358 | ||
5a728ac5 JL |
2359 | static void |
2360 | ptp_ocp_fb_set_version(struct ptp_ocp *bp) | |
2361 | { | |
2362 | u64 cap = OCP_CAP_BASIC; | |
2363 | u32 version; | |
2364 | ||
2365 | version = ioread32(&bp->image->version); | |
2366 | ||
2367 | /* if lower 16 bits are empty, this is the fw loader. */ | |
2368 | if ((version & 0xffff) == 0) { | |
2369 | version = version >> 16; | |
2370 | bp->fw_loader = true; | |
2371 | } | |
2372 | ||
2373 | bp->fw_tag = version >> 15; | |
2374 | bp->fw_version = version & 0x7fff; | |
2375 | ||
2376 | if (bp->fw_tag) { | |
2377 | /* FPGA firmware */ | |
2378 | if (version >= 5) | |
2379 | cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ; | |
2380 | } else { | |
2381 | /* SOM firmware */ | |
2382 | if (version >= 19) | |
2383 | cap |= OCP_CAP_SIGNAL; | |
2384 | if (version >= 20) | |
2385 | cap |= OCP_CAP_FREQ; | |
2386 | } | |
2387 | ||
2388 | bp->fw_cap = cap; | |
2389 | } | |
2390 | ||
773bda96 JL |
2391 | /* FB specific board initializers; last "resource" registered. */ |
2392 | static int | |
2393 | ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r) | |
2394 | { | |
5a728ac5 | 2395 | int err; |
b325af3c | 2396 | |
773bda96 | 2397 | bp->flash_start = 1024 * 4096; |
0cfcdd1e | 2398 | bp->eeprom_map = fb_eeprom_map; |
b0ca789a | 2399 | bp->fw_version = ioread32(&bp->image->version); |
caab82cd | 2400 | bp->sma_op = &ocp_fb_sma_op; |
773bda96 | 2401 | |
5a728ac5 | 2402 | ptp_ocp_fb_set_version(bp); |
b325af3c | 2403 | |
065efcc5 | 2404 | ptp_ocp_tod_init(bp); |
e3516bb4 | 2405 | ptp_ocp_nmea_out_init(bp); |
a509a7c6 | 2406 | ptp_ocp_sma_init(bp); |
b325af3c | 2407 | ptp_ocp_signal_init(bp); |
065efcc5 | 2408 | |
c2239294 JL |
2409 | err = ptp_ocp_attr_group_add(bp, fb_timecard_groups); |
2410 | if (err) | |
2411 | return err; | |
2412 | ||
1aa66a3a JL |
2413 | err = ptp_ocp_fb_set_pins(bp); |
2414 | if (err) | |
2415 | return err; | |
2416 | ||
773bda96 JL |
2417 | return ptp_ocp_init_clock(bp); |
2418 | } | |
2419 | ||
56ec4403 JL |
2420 | static bool |
2421 | ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r) | |
2422 | { | |
2423 | bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs; | |
2424 | ||
2425 | if (!allow) | |
2426 | dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n", | |
2427 | r->irq_vec, r->name); | |
2428 | return allow; | |
2429 | } | |
2430 | ||
773bda96 JL |
2431 | static int |
2432 | ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data) | |
2433 | { | |
2434 | struct ocp_resource *r, *table; | |
2435 | int err = 0; | |
2436 | ||
2437 | table = (struct ocp_resource *)driver_data; | |
2438 | for (r = table; r->setup; r++) { | |
56ec4403 JL |
2439 | if (!ptp_ocp_allow_irq(bp, r)) |
2440 | continue; | |
773bda96 | 2441 | err = r->setup(bp, r); |
bceff290 JL |
2442 | if (err) { |
2443 | dev_err(&bp->pdev->dev, | |
2444 | "Could not register %s: err %d\n", | |
2445 | r->name, err); | |
773bda96 | 2446 | break; |
bceff290 | 2447 | } |
a7e1abad | 2448 | } |
773bda96 JL |
2449 | return err; |
2450 | } | |
2451 | ||
69dbe107 VF |
2452 | static void |
2453 | ptp_ocp_art_sma_init(struct ptp_ocp *bp) | |
2454 | { | |
2455 | u32 reg; | |
2456 | int i; | |
2457 | ||
2458 | /* defaults */ | |
2459 | bp->sma[0].mode = SMA_MODE_IN; | |
2460 | bp->sma[1].mode = SMA_MODE_IN; | |
2461 | bp->sma[2].mode = SMA_MODE_OUT; | |
2462 | bp->sma[3].mode = SMA_MODE_OUT; | |
2463 | ||
2464 | bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */ | |
2465 | bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */ | |
2466 | bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */ | |
2467 | bp->sma[3].default_fcn = 0x02; /* OUT: PHC */ | |
2468 | ||
2469 | /* If no SMA map, the pin functions and directions are fixed. */ | |
2470 | if (!bp->art_sma) { | |
2471 | for (i = 0; i < 4; i++) { | |
2472 | bp->sma[i].fixed_fcn = true; | |
2473 | bp->sma[i].fixed_dir = true; | |
2474 | } | |
2475 | return; | |
2476 | } | |
2477 | ||
2478 | for (i = 0; i < 4; i++) { | |
2479 | reg = ioread32(&bp->art_sma->map[i].gpio); | |
2480 | ||
2481 | switch (reg & 0xff) { | |
2482 | case 0: | |
2483 | bp->sma[i].fixed_fcn = true; | |
2484 | bp->sma[i].fixed_dir = true; | |
2485 | break; | |
2486 | case 1: | |
2487 | case 8: | |
2488 | bp->sma[i].mode = SMA_MODE_IN; | |
2489 | break; | |
2490 | default: | |
2491 | bp->sma[i].mode = SMA_MODE_OUT; | |
2492 | break; | |
2493 | } | |
2494 | } | |
2495 | } | |
2496 | ||
2497 | static u32 | |
2498 | ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr) | |
2499 | { | |
2500 | if (bp->sma[sma_nr - 1].fixed_fcn) | |
2501 | return bp->sma[sma_nr - 1].default_fcn; | |
2502 | ||
2503 | return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff; | |
2504 | } | |
2505 | ||
2506 | /* note: store 0 is considered invalid. */ | |
2507 | static int | |
2508 | ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val) | |
2509 | { | |
2510 | unsigned long flags; | |
2511 | u32 __iomem *gpio; | |
2512 | int err = 0; | |
2513 | u32 reg; | |
2514 | ||
2515 | val &= SMA_SELECT_MASK; | |
2516 | if (hweight32(val) > 1) | |
2517 | return -EINVAL; | |
2518 | ||
2519 | gpio = &bp->art_sma->map[sma_nr - 1].gpio; | |
2520 | ||
2521 | spin_lock_irqsave(&bp->lock, flags); | |
2522 | reg = ioread32(gpio); | |
2523 | if (((reg >> 16) & val) == 0) { | |
2524 | err = -EOPNOTSUPP; | |
2525 | } else { | |
2526 | reg = (reg & 0xff00) | (val & 0xff); | |
2527 | iowrite32(reg, gpio); | |
2528 | } | |
2529 | spin_unlock_irqrestore(&bp->lock, flags); | |
2530 | ||
2531 | return err; | |
2532 | } | |
2533 | ||
2534 | static const struct ocp_sma_op ocp_art_sma_op = { | |
2535 | .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out }, | |
2536 | .init = ptp_ocp_art_sma_init, | |
2537 | .get = ptp_ocp_art_sma_get, | |
2538 | .set_inputs = ptp_ocp_art_sma_set, | |
2539 | .set_output = ptp_ocp_art_sma_set, | |
2540 | }; | |
2541 | ||
2542 | /* ART specific board initializers; last "resource" registered. */ | |
2543 | static int | |
2544 | ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r) | |
2545 | { | |
2546 | int err; | |
2547 | ||
2548 | bp->flash_start = 0x1000000; | |
2549 | bp->eeprom_map = art_eeprom_map; | |
2550 | bp->fw_cap = OCP_CAP_BASIC; | |
2551 | bp->fw_version = ioread32(&bp->reg->version); | |
2552 | bp->fw_tag = 2; | |
2553 | bp->sma_op = &ocp_art_sma_op; | |
2554 | ||
9c44a7ac VF |
2555 | /* Enable MAC serial port during initialisation */ |
2556 | iowrite32(1, &bp->board_config->mro50_serial_activate); | |
2557 | ||
69dbe107 VF |
2558 | ptp_ocp_sma_init(bp); |
2559 | ||
2560 | err = ptp_ocp_attr_group_add(bp, art_timecard_groups); | |
2561 | if (err) | |
2562 | return err; | |
2563 | ||
2564 | return ptp_ocp_init_clock(bp); | |
2565 | } | |
2566 | ||
e1daf0ec | 2567 | static ssize_t |
3f3fe41c JL |
2568 | ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf, |
2569 | int def_val) | |
e1daf0ec JL |
2570 | { |
2571 | const char *name; | |
2572 | ssize_t count; | |
2573 | ||
2574 | count = sysfs_emit(buf, "OUT: "); | |
aa56a7ff | 2575 | name = ptp_ocp_select_name_from_val(tbl, val); |
e1daf0ec | 2576 | if (!name) |
aa56a7ff | 2577 | name = ptp_ocp_select_name_from_val(tbl, def_val); |
e1daf0ec JL |
2578 | count += sysfs_emit_at(buf, count, "%s\n", name); |
2579 | return count; | |
2580 | } | |
2581 | ||
2582 | static ssize_t | |
3f3fe41c JL |
2583 | ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf, |
2584 | int def_val) | |
e1daf0ec JL |
2585 | { |
2586 | const char *name; | |
2587 | ssize_t count; | |
2588 | int i; | |
2589 | ||
2590 | count = sysfs_emit(buf, "IN: "); | |
aa56a7ff JL |
2591 | for (i = 0; tbl[i].name; i++) { |
2592 | if (val & tbl[i].value) { | |
2593 | name = tbl[i].name; | |
e1daf0ec JL |
2594 | count += sysfs_emit_at(buf, count, "%s ", name); |
2595 | } | |
2596 | } | |
b2c4f0ac | 2597 | if (!val && def_val >= 0) { |
aa56a7ff | 2598 | name = ptp_ocp_select_name_from_val(tbl, def_val); |
b2c4f0ac JL |
2599 | count += sysfs_emit_at(buf, count, "%s ", name); |
2600 | } | |
e1daf0ec JL |
2601 | if (count) |
2602 | count--; | |
2603 | count += sysfs_emit_at(buf, count, "\n"); | |
2604 | return count; | |
2605 | } | |
2606 | ||
2607 | static int | |
3f3fe41c | 2608 | sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf, |
aa56a7ff | 2609 | enum ptp_ocp_sma_mode *mode) |
e1daf0ec | 2610 | { |
e1daf0ec JL |
2611 | int idx, count, dir; |
2612 | char **argv; | |
2613 | int ret; | |
2614 | ||
2615 | argv = argv_split(GFP_KERNEL, buf, &count); | |
2616 | if (!argv) | |
2617 | return -ENOMEM; | |
2618 | ||
2619 | ret = -EINVAL; | |
2620 | if (!count) | |
2621 | goto out; | |
2622 | ||
2623 | idx = 0; | |
2624 | dir = *mode == SMA_MODE_IN ? 0 : 1; | |
a509a7c6 | 2625 | if (!strcasecmp("IN:", argv[0])) { |
e1daf0ec JL |
2626 | dir = 0; |
2627 | idx++; | |
2628 | } | |
2629 | if (!strcasecmp("OUT:", argv[0])) { | |
2630 | dir = 1; | |
2631 | idx++; | |
2632 | } | |
2633 | *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; | |
2634 | ||
2635 | ret = 0; | |
2636 | for (; idx < count; idx++) | |
2637 | ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]); | |
2638 | if (ret < 0) | |
2639 | ret = -EINVAL; | |
2640 | ||
2641 | out: | |
2642 | argv_free(argv); | |
2643 | return ret; | |
2644 | } | |
2645 | ||
2646 | static ssize_t | |
a509a7c6 | 2647 | ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf, |
b2c4f0ac | 2648 | int default_in_val, int default_out_val) |
e1daf0ec | 2649 | { |
a509a7c6 | 2650 | struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1]; |
3f3fe41c | 2651 | const struct ocp_selector * const *tbl; |
a509a7c6 JL |
2652 | u32 val; |
2653 | ||
caab82cd JL |
2654 | tbl = bp->sma_op->tbl; |
2655 | val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK; | |
e1daf0ec | 2656 | |
b2c4f0ac JL |
2657 | if (sma->mode == SMA_MODE_IN) { |
2658 | if (sma->disabled) | |
2659 | val = SMA_DISABLE; | |
aa56a7ff | 2660 | return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val); |
b2c4f0ac | 2661 | } |
e1daf0ec | 2662 | |
aa56a7ff | 2663 | return ptp_ocp_show_output(tbl[1], val, buf, default_out_val); |
e1daf0ec JL |
2664 | } |
2665 | ||
2666 | static ssize_t | |
2667 | sma1_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2668 | { | |
2669 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
e1daf0ec | 2670 | |
a509a7c6 | 2671 | return ptp_ocp_sma_show(bp, 1, buf, 0, 1); |
e1daf0ec JL |
2672 | } |
2673 | ||
2674 | static ssize_t | |
2675 | sma2_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2676 | { | |
2677 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
e1daf0ec | 2678 | |
a509a7c6 | 2679 | return ptp_ocp_sma_show(bp, 2, buf, -1, 1); |
e1daf0ec JL |
2680 | } |
2681 | ||
2682 | static ssize_t | |
2683 | sma3_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2684 | { | |
2685 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
e1daf0ec | 2686 | |
a509a7c6 | 2687 | return ptp_ocp_sma_show(bp, 3, buf, -1, 0); |
e1daf0ec JL |
2688 | } |
2689 | ||
2690 | static ssize_t | |
2691 | sma4_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2692 | { | |
2693 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
e1daf0ec | 2694 | |
a509a7c6 | 2695 | return ptp_ocp_sma_show(bp, 4, buf, -1, 1); |
e1daf0ec JL |
2696 | } |
2697 | ||
a509a7c6 JL |
2698 | static int |
2699 | ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr) | |
e1daf0ec | 2700 | { |
a509a7c6 | 2701 | struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1]; |
e1daf0ec JL |
2702 | enum ptp_ocp_sma_mode mode; |
2703 | int val; | |
2704 | ||
2705 | mode = sma->mode; | |
caab82cd | 2706 | val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode); |
e1daf0ec JL |
2707 | if (val < 0) |
2708 | return val; | |
2709 | ||
b2c4f0ac | 2710 | if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE)) |
e1daf0ec JL |
2711 | return -EOPNOTSUPP; |
2712 | ||
a509a7c6 | 2713 | if (sma->fixed_fcn) { |
ee4cd725 | 2714 | if (val != sma->default_fcn) |
a509a7c6 JL |
2715 | return -EOPNOTSUPP; |
2716 | return 0; | |
2717 | } | |
2718 | ||
b2c4f0ac JL |
2719 | sma->disabled = !!(val & SMA_DISABLE); |
2720 | ||
e1daf0ec | 2721 | if (mode != sma->mode) { |
a509a7c6 | 2722 | if (mode == SMA_MODE_IN) |
caab82cd | 2723 | ptp_ocp_sma_set_output(bp, sma_nr, 0); |
a509a7c6 | 2724 | else |
caab82cd | 2725 | ptp_ocp_sma_set_inputs(bp, sma_nr, 0); |
a509a7c6 | 2726 | sma->mode = mode; |
e1daf0ec JL |
2727 | } |
2728 | ||
a509a7c6 JL |
2729 | if (!sma->fixed_dir) |
2730 | val |= SMA_ENABLE; /* add enable bit */ | |
2731 | ||
b2c4f0ac JL |
2732 | if (sma->disabled) |
2733 | val = 0; | |
2734 | ||
a509a7c6 | 2735 | if (mode == SMA_MODE_IN) |
caab82cd | 2736 | val = ptp_ocp_sma_set_inputs(bp, sma_nr, val); |
e1daf0ec | 2737 | else |
caab82cd | 2738 | val = ptp_ocp_sma_set_output(bp, sma_nr, val); |
e1daf0ec | 2739 | |
caab82cd | 2740 | return val; |
e1daf0ec JL |
2741 | } |
2742 | ||
2743 | static ssize_t | |
2744 | sma1_store(struct device *dev, struct device_attribute *attr, | |
2745 | const char *buf, size_t count) | |
2746 | { | |
2747 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2748 | int err; | |
2749 | ||
a509a7c6 | 2750 | err = ptp_ocp_sma_store(bp, buf, 1); |
e1daf0ec JL |
2751 | return err ? err : count; |
2752 | } | |
2753 | ||
2754 | static ssize_t | |
2755 | sma2_store(struct device *dev, struct device_attribute *attr, | |
2756 | const char *buf, size_t count) | |
2757 | { | |
2758 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2759 | int err; | |
2760 | ||
a509a7c6 | 2761 | err = ptp_ocp_sma_store(bp, buf, 2); |
e1daf0ec JL |
2762 | return err ? err : count; |
2763 | } | |
2764 | ||
2765 | static ssize_t | |
2766 | sma3_store(struct device *dev, struct device_attribute *attr, | |
2767 | const char *buf, size_t count) | |
2768 | { | |
2769 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2770 | int err; | |
2771 | ||
a509a7c6 | 2772 | err = ptp_ocp_sma_store(bp, buf, 3); |
e1daf0ec JL |
2773 | return err ? err : count; |
2774 | } | |
2775 | ||
2776 | static ssize_t | |
2777 | sma4_store(struct device *dev, struct device_attribute *attr, | |
2778 | const char *buf, size_t count) | |
2779 | { | |
2780 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2781 | int err; | |
2782 | ||
a509a7c6 | 2783 | err = ptp_ocp_sma_store(bp, buf, 4); |
e1daf0ec JL |
2784 | return err ? err : count; |
2785 | } | |
2786 | static DEVICE_ATTR_RW(sma1); | |
2787 | static DEVICE_ATTR_RW(sma2); | |
2788 | static DEVICE_ATTR_RW(sma3); | |
2789 | static DEVICE_ATTR_RW(sma4); | |
2790 | ||
2791 | static ssize_t | |
2792 | available_sma_inputs_show(struct device *dev, | |
2793 | struct device_attribute *attr, char *buf) | |
2794 | { | |
aa56a7ff JL |
2795 | struct ptp_ocp *bp = dev_get_drvdata(dev); |
2796 | ||
caab82cd | 2797 | return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf); |
e1daf0ec JL |
2798 | } |
2799 | static DEVICE_ATTR_RO(available_sma_inputs); | |
2800 | ||
2801 | static ssize_t | |
2802 | available_sma_outputs_show(struct device *dev, | |
2803 | struct device_attribute *attr, char *buf) | |
2804 | { | |
aa56a7ff JL |
2805 | struct ptp_ocp *bp = dev_get_drvdata(dev); |
2806 | ||
caab82cd | 2807 | return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf); |
e1daf0ec JL |
2808 | } |
2809 | static DEVICE_ATTR_RO(available_sma_outputs); | |
2810 | ||
b325af3c JL |
2811 | #define EXT_ATTR_RO(_group, _name, _val) \ |
2812 | struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \ | |
2813 | { __ATTR_RO(_name), (void *)_val } | |
2814 | #define EXT_ATTR_RW(_group, _name, _val) \ | |
2815 | struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \ | |
2816 | { __ATTR_RW(_name), (void *)_val } | |
2817 | #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr) | |
2818 | ||
2819 | /* period [duty [phase [polarity]]] */ | |
2820 | static ssize_t | |
2821 | signal_store(struct device *dev, struct device_attribute *attr, | |
2822 | const char *buf, size_t count) | |
2823 | { | |
2824 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2825 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2826 | struct ptp_ocp_signal s = { }; | |
2827 | int gen = (uintptr_t)ea->var; | |
2828 | int argc, err; | |
2829 | char **argv; | |
2830 | ||
2831 | argv = argv_split(GFP_KERNEL, buf, &argc); | |
2832 | if (!argv) | |
2833 | return -ENOMEM; | |
2834 | ||
2835 | err = -EINVAL; | |
2836 | s.duty = bp->signal[gen].duty; | |
2837 | s.phase = bp->signal[gen].phase; | |
2838 | s.period = bp->signal[gen].period; | |
2839 | s.polarity = bp->signal[gen].polarity; | |
2840 | ||
2841 | switch (argc) { | |
2842 | case 4: | |
2843 | argc--; | |
2844 | err = kstrtobool(argv[argc], &s.polarity); | |
2845 | if (err) | |
2846 | goto out; | |
2847 | fallthrough; | |
2848 | case 3: | |
2849 | argc--; | |
2850 | err = kstrtou64(argv[argc], 0, &s.phase); | |
2851 | if (err) | |
2852 | goto out; | |
2853 | fallthrough; | |
2854 | case 2: | |
2855 | argc--; | |
2856 | err = kstrtoint(argv[argc], 0, &s.duty); | |
2857 | if (err) | |
2858 | goto out; | |
2859 | fallthrough; | |
2860 | case 1: | |
2861 | argc--; | |
2862 | err = kstrtou64(argv[argc], 0, &s.period); | |
2863 | if (err) | |
2864 | goto out; | |
2865 | break; | |
2866 | default: | |
2867 | goto out; | |
2868 | } | |
2869 | ||
2870 | err = ptp_ocp_signal_set(bp, gen, &s); | |
2871 | if (err) | |
2872 | goto out; | |
2873 | ||
2874 | err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0); | |
2875 | ||
2876 | out: | |
2877 | argv_free(argv); | |
2878 | return err ? err : count; | |
2879 | } | |
2880 | ||
2881 | static ssize_t | |
2882 | signal_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2883 | { | |
2884 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2885 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2886 | struct ptp_ocp_signal *signal; | |
2887 | struct timespec64 ts; | |
2888 | ssize_t count; | |
2889 | int i; | |
2890 | ||
2891 | i = (uintptr_t)ea->var; | |
2892 | signal = &bp->signal[i]; | |
2893 | ||
2894 | count = sysfs_emit(buf, "%llu %d %llu %d", signal->period, | |
2895 | signal->duty, signal->phase, signal->polarity); | |
2896 | ||
2897 | ts = ktime_to_timespec64(signal->start); | |
2898 | count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts); | |
2899 | ||
2900 | return count; | |
2901 | } | |
2902 | static EXT_ATTR_RW(signal, signal, 0); | |
2903 | static EXT_ATTR_RW(signal, signal, 1); | |
2904 | static EXT_ATTR_RW(signal, signal, 2); | |
2905 | static EXT_ATTR_RW(signal, signal, 3); | |
2906 | ||
2907 | static ssize_t | |
2908 | duty_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2909 | { | |
2910 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2911 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2912 | int i = (uintptr_t)ea->var; | |
2913 | ||
2914 | return sysfs_emit(buf, "%d\n", bp->signal[i].duty); | |
2915 | } | |
2916 | static EXT_ATTR_RO(signal, duty, 0); | |
2917 | static EXT_ATTR_RO(signal, duty, 1); | |
2918 | static EXT_ATTR_RO(signal, duty, 2); | |
2919 | static EXT_ATTR_RO(signal, duty, 3); | |
2920 | ||
2921 | static ssize_t | |
2922 | period_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2923 | { | |
2924 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2925 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2926 | int i = (uintptr_t)ea->var; | |
2927 | ||
2928 | return sysfs_emit(buf, "%llu\n", bp->signal[i].period); | |
2929 | } | |
2930 | static EXT_ATTR_RO(signal, period, 0); | |
2931 | static EXT_ATTR_RO(signal, period, 1); | |
2932 | static EXT_ATTR_RO(signal, period, 2); | |
2933 | static EXT_ATTR_RO(signal, period, 3); | |
2934 | ||
2935 | static ssize_t | |
2936 | phase_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2937 | { | |
2938 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2939 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2940 | int i = (uintptr_t)ea->var; | |
2941 | ||
2942 | return sysfs_emit(buf, "%llu\n", bp->signal[i].phase); | |
2943 | } | |
2944 | static EXT_ATTR_RO(signal, phase, 0); | |
2945 | static EXT_ATTR_RO(signal, phase, 1); | |
2946 | static EXT_ATTR_RO(signal, phase, 2); | |
2947 | static EXT_ATTR_RO(signal, phase, 3); | |
2948 | ||
2949 | static ssize_t | |
2950 | polarity_show(struct device *dev, struct device_attribute *attr, | |
2951 | char *buf) | |
2952 | { | |
2953 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2954 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2955 | int i = (uintptr_t)ea->var; | |
2956 | ||
2957 | return sysfs_emit(buf, "%d\n", bp->signal[i].polarity); | |
2958 | } | |
2959 | static EXT_ATTR_RO(signal, polarity, 0); | |
2960 | static EXT_ATTR_RO(signal, polarity, 1); | |
2961 | static EXT_ATTR_RO(signal, polarity, 2); | |
2962 | static EXT_ATTR_RO(signal, polarity, 3); | |
2963 | ||
2964 | static ssize_t | |
2965 | running_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2966 | { | |
2967 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2968 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2969 | int i = (uintptr_t)ea->var; | |
2970 | ||
2971 | return sysfs_emit(buf, "%d\n", bp->signal[i].running); | |
2972 | } | |
2973 | static EXT_ATTR_RO(signal, running, 0); | |
2974 | static EXT_ATTR_RO(signal, running, 1); | |
2975 | static EXT_ATTR_RO(signal, running, 2); | |
2976 | static EXT_ATTR_RO(signal, running, 3); | |
2977 | ||
2978 | static ssize_t | |
2979 | start_show(struct device *dev, struct device_attribute *attr, char *buf) | |
2980 | { | |
2981 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2982 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
2983 | int i = (uintptr_t)ea->var; | |
2984 | struct timespec64 ts; | |
2985 | ||
2986 | ts = ktime_to_timespec64(bp->signal[i].start); | |
2987 | return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec); | |
2988 | } | |
2989 | static EXT_ATTR_RO(signal, start, 0); | |
2990 | static EXT_ATTR_RO(signal, start, 1); | |
2991 | static EXT_ATTR_RO(signal, start, 2); | |
2992 | static EXT_ATTR_RO(signal, start, 3); | |
2993 | ||
2407f5d6 JL |
2994 | static ssize_t |
2995 | seconds_store(struct device *dev, struct device_attribute *attr, | |
2996 | const char *buf, size_t count) | |
2997 | { | |
2998 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
2999 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3000 | int idx = (uintptr_t)ea->var; | |
3001 | u32 val; | |
3002 | int err; | |
3003 | ||
3004 | err = kstrtou32(buf, 0, &val); | |
3005 | if (err) | |
3006 | return err; | |
3007 | if (val > 0xff) | |
3008 | return -EINVAL; | |
3009 | ||
3010 | if (val) | |
3011 | val = (val << 8) | 0x1; | |
3012 | ||
3013 | iowrite32(val, &bp->freq_in[idx]->ctrl); | |
3014 | ||
3015 | return count; | |
3016 | } | |
3017 | ||
3018 | static ssize_t | |
3019 | seconds_show(struct device *dev, struct device_attribute *attr, char *buf) | |
3020 | { | |
3021 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
3022 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3023 | int idx = (uintptr_t)ea->var; | |
3024 | u32 val; | |
3025 | ||
3026 | val = ioread32(&bp->freq_in[idx]->ctrl); | |
3027 | if (val & 1) | |
3028 | val = (val >> 8) & 0xff; | |
3029 | else | |
3030 | val = 0; | |
3031 | ||
3032 | return sysfs_emit(buf, "%u\n", val); | |
3033 | } | |
3034 | static EXT_ATTR_RW(freq, seconds, 0); | |
3035 | static EXT_ATTR_RW(freq, seconds, 1); | |
3036 | static EXT_ATTR_RW(freq, seconds, 2); | |
3037 | static EXT_ATTR_RW(freq, seconds, 3); | |
3038 | ||
3039 | static ssize_t | |
3040 | frequency_show(struct device *dev, struct device_attribute *attr, char *buf) | |
3041 | { | |
3042 | struct dev_ext_attribute *ea = to_ext_attr(attr); | |
3043 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3044 | int idx = (uintptr_t)ea->var; | |
3045 | u32 val; | |
3046 | ||
3047 | val = ioread32(&bp->freq_in[idx]->status); | |
3048 | if (val & FREQ_STATUS_ERROR) | |
3049 | return sysfs_emit(buf, "error\n"); | |
3050 | if (val & FREQ_STATUS_OVERRUN) | |
3051 | return sysfs_emit(buf, "overrun\n"); | |
3052 | if (val & FREQ_STATUS_VALID) | |
3053 | return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK); | |
3054 | return 0; | |
3055 | } | |
3056 | static EXT_ATTR_RO(freq, frequency, 0); | |
3057 | static EXT_ATTR_RO(freq, frequency, 1); | |
3058 | static EXT_ATTR_RO(freq, frequency, 2); | |
3059 | static EXT_ATTR_RO(freq, frequency, 3); | |
3060 | ||
773bda96 JL |
3061 | static ssize_t |
3062 | serialnum_show(struct device *dev, struct device_attribute *attr, char *buf) | |
3063 | { | |
3064 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3065 | ||
0cfcdd1e JL |
3066 | if (!bp->has_eeprom_data) |
3067 | ptp_ocp_read_eeprom(bp); | |
773bda96 JL |
3068 | |
3069 | return sysfs_emit(buf, "%pM\n", bp->serial); | |
3070 | } | |
3071 | static DEVICE_ATTR_RO(serialnum); | |
3072 | ||
3073 | static ssize_t | |
ef0cfb34 | 3074 | gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf) |
773bda96 JL |
3075 | { |
3076 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3077 | ssize_t ret; | |
3078 | ||
ef0cfb34 JL |
3079 | if (bp->gnss_lost) |
3080 | ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost); | |
773bda96 JL |
3081 | else |
3082 | ret = sysfs_emit(buf, "SYNC\n"); | |
3083 | ||
3084 | return ret; | |
3085 | } | |
ef0cfb34 | 3086 | static DEVICE_ATTR_RO(gnss_sync); |
773bda96 | 3087 | |
89260d87 JL |
3088 | static ssize_t |
3089 | utc_tai_offset_show(struct device *dev, | |
3090 | struct device_attribute *attr, char *buf) | |
3091 | { | |
3092 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3093 | ||
3094 | return sysfs_emit(buf, "%d\n", bp->utc_tai_offset); | |
3095 | } | |
3096 | ||
3097 | static ssize_t | |
3098 | utc_tai_offset_store(struct device *dev, | |
3099 | struct device_attribute *attr, | |
3100 | const char *buf, size_t count) | |
3101 | { | |
3102 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3103 | int err; | |
3104 | u32 val; | |
3105 | ||
3106 | err = kstrtou32(buf, 0, &val); | |
3107 | if (err) | |
3108 | return err; | |
3109 | ||
3110 | ptp_ocp_utc_distribute(bp, val); | |
3111 | ||
3112 | return count; | |
3113 | } | |
3114 | static DEVICE_ATTR_RW(utc_tai_offset); | |
3115 | ||
1acffc6e JL |
3116 | static ssize_t |
3117 | ts_window_adjust_show(struct device *dev, | |
3118 | struct device_attribute *attr, char *buf) | |
3119 | { | |
3120 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3121 | ||
3122 | return sysfs_emit(buf, "%d\n", bp->ts_window_adjust); | |
3123 | } | |
3124 | ||
3125 | static ssize_t | |
3126 | ts_window_adjust_store(struct device *dev, | |
3127 | struct device_attribute *attr, | |
3128 | const char *buf, size_t count) | |
3129 | { | |
3130 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3131 | int err; | |
3132 | u32 val; | |
3133 | ||
3134 | err = kstrtou32(buf, 0, &val); | |
3135 | if (err) | |
3136 | return err; | |
3137 | ||
3138 | bp->ts_window_adjust = val; | |
3139 | ||
3140 | return count; | |
3141 | } | |
3142 | static DEVICE_ATTR_RW(ts_window_adjust); | |
3143 | ||
d14ee252 JL |
3144 | static ssize_t |
3145 | irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
3146 | { | |
3147 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3148 | u32 val; | |
3149 | ||
3150 | val = ioread32(&bp->irig_out->ctrl); | |
3151 | val = (val >> 16) & 0x07; | |
3152 | return sysfs_emit(buf, "%d\n", val); | |
3153 | } | |
3154 | ||
3155 | static ssize_t | |
3156 | irig_b_mode_store(struct device *dev, | |
3157 | struct device_attribute *attr, | |
3158 | const char *buf, size_t count) | |
3159 | { | |
3160 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3161 | unsigned long flags; | |
3162 | int err; | |
3163 | u32 reg; | |
3164 | u8 val; | |
3165 | ||
3166 | err = kstrtou8(buf, 0, &val); | |
3167 | if (err) | |
3168 | return err; | |
3169 | if (val > 7) | |
3170 | return -EINVAL; | |
3171 | ||
3172 | reg = ((val & 0x7) << 16); | |
3173 | ||
3174 | spin_lock_irqsave(&bp->lock, flags); | |
3175 | iowrite32(0, &bp->irig_out->ctrl); /* disable */ | |
3176 | iowrite32(reg, &bp->irig_out->ctrl); /* change mode */ | |
3177 | iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl); | |
3178 | spin_unlock_irqrestore(&bp->lock, flags); | |
3179 | ||
3180 | return count; | |
3181 | } | |
3182 | static DEVICE_ATTR_RW(irig_b_mode); | |
3183 | ||
773bda96 JL |
3184 | static ssize_t |
3185 | clock_source_show(struct device *dev, struct device_attribute *attr, char *buf) | |
3186 | { | |
3187 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3188 | const char *p; | |
3189 | u32 select; | |
3190 | ||
3191 | select = ioread32(&bp->reg->select); | |
e1daf0ec | 3192 | p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16); |
773bda96 JL |
3193 | |
3194 | return sysfs_emit(buf, "%s\n", p); | |
3195 | } | |
3196 | ||
3197 | static ssize_t | |
3198 | clock_source_store(struct device *dev, struct device_attribute *attr, | |
3199 | const char *buf, size_t count) | |
3200 | { | |
3201 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3202 | unsigned long flags; | |
3203 | int val; | |
3204 | ||
e1daf0ec | 3205 | val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf); |
773bda96 JL |
3206 | if (val < 0) |
3207 | return val; | |
3208 | ||
3209 | spin_lock_irqsave(&bp->lock, flags); | |
3210 | iowrite32(val, &bp->reg->select); | |
3211 | spin_unlock_irqrestore(&bp->lock, flags); | |
3212 | ||
3213 | return count; | |
3214 | } | |
3215 | static DEVICE_ATTR_RW(clock_source); | |
3216 | ||
3217 | static ssize_t | |
3218 | available_clock_sources_show(struct device *dev, | |
3219 | struct device_attribute *attr, char *buf) | |
3220 | { | |
e1daf0ec | 3221 | return ptp_ocp_select_table_show(ptp_ocp_clock, buf); |
773bda96 JL |
3222 | } |
3223 | static DEVICE_ATTR_RO(available_clock_sources); | |
3224 | ||
2f23f486 VF |
3225 | static ssize_t |
3226 | clock_status_drift_show(struct device *dev, | |
3227 | struct device_attribute *attr, char *buf) | |
3228 | { | |
3229 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3230 | u32 val; | |
3231 | int res; | |
3232 | ||
3233 | val = ioread32(&bp->reg->status_drift); | |
3234 | res = (val & ~INT_MAX) ? -1 : 1; | |
3235 | res *= (val & INT_MAX); | |
3236 | return sysfs_emit(buf, "%d\n", res); | |
3237 | } | |
3238 | static DEVICE_ATTR_RO(clock_status_drift); | |
3239 | ||
3240 | static ssize_t | |
3241 | clock_status_offset_show(struct device *dev, | |
3242 | struct device_attribute *attr, char *buf) | |
3243 | { | |
3244 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3245 | u32 val; | |
3246 | int res; | |
3247 | ||
3248 | val = ioread32(&bp->reg->status_offset); | |
3249 | res = (val & ~INT_MAX) ? -1 : 1; | |
3250 | res *= (val & INT_MAX); | |
3251 | return sysfs_emit(buf, "%d\n", res); | |
3252 | } | |
3253 | static DEVICE_ATTR_RO(clock_status_offset); | |
3254 | ||
44a412d1 VF |
3255 | static ssize_t |
3256 | tod_correction_show(struct device *dev, | |
3257 | struct device_attribute *attr, char *buf) | |
3258 | { | |
3259 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3260 | u32 val; | |
3261 | int res; | |
3262 | ||
3263 | val = ioread32(&bp->tod->adj_sec); | |
3264 | res = (val & ~INT_MAX) ? -1 : 1; | |
3265 | res *= (val & INT_MAX); | |
3266 | return sysfs_emit(buf, "%d\n", res); | |
3267 | } | |
3268 | ||
3269 | static ssize_t | |
3270 | tod_correction_store(struct device *dev, struct device_attribute *attr, | |
3271 | const char *buf, size_t count) | |
3272 | { | |
3273 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3274 | unsigned long flags; | |
3275 | int err, res; | |
3276 | u32 val = 0; | |
3277 | ||
3278 | err = kstrtos32(buf, 0, &res); | |
3279 | if (err) | |
3280 | return err; | |
3281 | if (res < 0) { | |
3282 | res *= -1; | |
3283 | val |= BIT(31); | |
3284 | } | |
3285 | val |= res; | |
3286 | ||
3287 | spin_lock_irqsave(&bp->lock, flags); | |
3288 | iowrite32(val, &bp->tod->adj_sec); | |
3289 | spin_unlock_irqrestore(&bp->lock, flags); | |
3290 | ||
3291 | return count; | |
3292 | } | |
3293 | static DEVICE_ATTR_RW(tod_correction); | |
3294 | ||
b325af3c JL |
3295 | #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \ |
3296 | static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \ | |
3297 | &dev_attr_signal##_nr##_signal.attr.attr, \ | |
3298 | &dev_attr_signal##_nr##_duty.attr.attr, \ | |
3299 | &dev_attr_signal##_nr##_phase.attr.attr, \ | |
3300 | &dev_attr_signal##_nr##_period.attr.attr, \ | |
3301 | &dev_attr_signal##_nr##_polarity.attr.attr, \ | |
3302 | &dev_attr_signal##_nr##_running.attr.attr, \ | |
3303 | &dev_attr_signal##_nr##_start.attr.attr, \ | |
3304 | NULL, \ | |
3305 | } | |
3306 | ||
3307 | #define DEVICE_SIGNAL_GROUP(_name, _nr) \ | |
3308 | _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \ | |
3309 | static const struct attribute_group \ | |
3310 | fb_timecard_signal##_nr##_group = { \ | |
3311 | .name = #_name, \ | |
3312 | .attrs = fb_timecard_signal##_nr##_attrs, \ | |
3313 | } | |
3314 | ||
3315 | DEVICE_SIGNAL_GROUP(gen1, 0); | |
3316 | DEVICE_SIGNAL_GROUP(gen2, 1); | |
3317 | DEVICE_SIGNAL_GROUP(gen3, 2); | |
3318 | DEVICE_SIGNAL_GROUP(gen4, 3); | |
3319 | ||
2407f5d6 JL |
3320 | #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \ |
3321 | static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \ | |
3322 | &dev_attr_freq##_nr##_seconds.attr.attr, \ | |
3323 | &dev_attr_freq##_nr##_frequency.attr.attr, \ | |
3324 | NULL, \ | |
3325 | } | |
3326 | ||
3327 | #define DEVICE_FREQ_GROUP(_name, _nr) \ | |
3328 | _DEVICE_FREQ_GROUP_ATTRS(_nr); \ | |
3329 | static const struct attribute_group \ | |
3330 | fb_timecard_freq##_nr##_group = { \ | |
3331 | .name = #_name, \ | |
3332 | .attrs = fb_timecard_freq##_nr##_attrs, \ | |
3333 | } | |
3334 | ||
3335 | DEVICE_FREQ_GROUP(freq1, 0); | |
3336 | DEVICE_FREQ_GROUP(freq2, 1); | |
3337 | DEVICE_FREQ_GROUP(freq3, 2); | |
3338 | DEVICE_FREQ_GROUP(freq4, 3); | |
3339 | ||
ee6439aa VF |
3340 | static ssize_t |
3341 | disciplining_config_read(struct file *filp, struct kobject *kobj, | |
3342 | struct bin_attribute *bin_attr, char *buf, | |
3343 | loff_t off, size_t count) | |
3344 | { | |
3345 | struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); | |
3346 | size_t size = OCP_ART_CONFIG_SIZE; | |
3347 | struct nvmem_device *nvmem; | |
3348 | ssize_t err; | |
3349 | ||
3350 | nvmem = ptp_ocp_nvmem_device_get(bp, NULL); | |
3351 | if (IS_ERR(nvmem)) | |
3352 | return PTR_ERR(nvmem); | |
3353 | ||
3354 | if (off > size) { | |
3355 | err = 0; | |
3356 | goto out; | |
3357 | } | |
3358 | ||
3359 | if (off + count > size) | |
3360 | count = size - off; | |
3361 | ||
3362 | // the configuration is in the very beginning of the EEPROM | |
3363 | err = nvmem_device_read(nvmem, off, count, buf); | |
3364 | if (err != count) { | |
3365 | err = -EFAULT; | |
3366 | goto out; | |
3367 | } | |
3368 | ||
3369 | out: | |
3370 | ptp_ocp_nvmem_device_put(&nvmem); | |
3371 | ||
3372 | return err; | |
3373 | } | |
3374 | ||
3375 | static ssize_t | |
3376 | disciplining_config_write(struct file *filp, struct kobject *kobj, | |
3377 | struct bin_attribute *bin_attr, char *buf, | |
3378 | loff_t off, size_t count) | |
3379 | { | |
3380 | struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); | |
3381 | struct nvmem_device *nvmem; | |
3382 | ssize_t err; | |
3383 | ||
3384 | /* Allow write of the whole area only */ | |
3385 | if (off || count != OCP_ART_CONFIG_SIZE) | |
3386 | return -EFAULT; | |
3387 | ||
3388 | nvmem = ptp_ocp_nvmem_device_get(bp, NULL); | |
3389 | if (IS_ERR(nvmem)) | |
3390 | return PTR_ERR(nvmem); | |
3391 | ||
3392 | err = nvmem_device_write(nvmem, 0x00, count, buf); | |
3393 | if (err != count) | |
3394 | err = -EFAULT; | |
3395 | ||
3396 | ptp_ocp_nvmem_device_put(&nvmem); | |
3397 | ||
3398 | return err; | |
3399 | } | |
3400 | static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE); | |
3401 | ||
3402 | static ssize_t | |
3403 | temperature_table_read(struct file *filp, struct kobject *kobj, | |
3404 | struct bin_attribute *bin_attr, char *buf, | |
3405 | loff_t off, size_t count) | |
3406 | { | |
3407 | struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); | |
3408 | size_t size = OCP_ART_TEMP_TABLE_SIZE; | |
3409 | struct nvmem_device *nvmem; | |
3410 | ssize_t err; | |
3411 | ||
3412 | nvmem = ptp_ocp_nvmem_device_get(bp, NULL); | |
3413 | if (IS_ERR(nvmem)) | |
3414 | return PTR_ERR(nvmem); | |
3415 | ||
3416 | if (off > size) { | |
3417 | err = 0; | |
3418 | goto out; | |
3419 | } | |
3420 | ||
3421 | if (off + count > size) | |
3422 | count = size - off; | |
3423 | ||
3424 | // the configuration is in the very beginning of the EEPROM | |
3425 | err = nvmem_device_read(nvmem, 0x90 + off, count, buf); | |
3426 | if (err != count) { | |
3427 | err = -EFAULT; | |
3428 | goto out; | |
3429 | } | |
3430 | ||
3431 | out: | |
3432 | ptp_ocp_nvmem_device_put(&nvmem); | |
3433 | ||
3434 | return err; | |
3435 | } | |
3436 | ||
3437 | static ssize_t | |
3438 | temperature_table_write(struct file *filp, struct kobject *kobj, | |
3439 | struct bin_attribute *bin_attr, char *buf, | |
3440 | loff_t off, size_t count) | |
3441 | { | |
3442 | struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); | |
3443 | struct nvmem_device *nvmem; | |
3444 | ssize_t err; | |
3445 | ||
3446 | /* Allow write of the whole area only */ | |
3447 | if (off || count != OCP_ART_TEMP_TABLE_SIZE) | |
3448 | return -EFAULT; | |
3449 | ||
3450 | nvmem = ptp_ocp_nvmem_device_get(bp, NULL); | |
3451 | if (IS_ERR(nvmem)) | |
3452 | return PTR_ERR(nvmem); | |
3453 | ||
3454 | err = nvmem_device_write(nvmem, 0x90, count, buf); | |
3455 | if (err != count) | |
3456 | err = -EFAULT; | |
3457 | ||
3458 | ptp_ocp_nvmem_device_put(&nvmem); | |
3459 | ||
3460 | return err; | |
3461 | } | |
3462 | static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE); | |
3463 | ||
c205d53c | 3464 | static struct attribute *fb_timecard_attrs[] = { |
773bda96 | 3465 | &dev_attr_serialnum.attr, |
ef0cfb34 | 3466 | &dev_attr_gnss_sync.attr, |
773bda96 JL |
3467 | &dev_attr_clock_source.attr, |
3468 | &dev_attr_available_clock_sources.attr, | |
e1daf0ec JL |
3469 | &dev_attr_sma1.attr, |
3470 | &dev_attr_sma2.attr, | |
3471 | &dev_attr_sma3.attr, | |
3472 | &dev_attr_sma4.attr, | |
3473 | &dev_attr_available_sma_inputs.attr, | |
3474 | &dev_attr_available_sma_outputs.attr, | |
2f23f486 VF |
3475 | &dev_attr_clock_status_drift.attr, |
3476 | &dev_attr_clock_status_offset.attr, | |
d14ee252 | 3477 | &dev_attr_irig_b_mode.attr, |
89260d87 | 3478 | &dev_attr_utc_tai_offset.attr, |
1acffc6e | 3479 | &dev_attr_ts_window_adjust.attr, |
44a412d1 | 3480 | &dev_attr_tod_correction.attr, |
773bda96 JL |
3481 | NULL, |
3482 | }; | |
ee6439aa | 3483 | |
c205d53c JL |
3484 | static const struct attribute_group fb_timecard_group = { |
3485 | .attrs = fb_timecard_attrs, | |
3486 | }; | |
ee6439aa | 3487 | |
c205d53c JL |
3488 | static const struct ocp_attr_group fb_timecard_groups[] = { |
3489 | { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group }, | |
b325af3c JL |
3490 | { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group }, |
3491 | { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group }, | |
3492 | { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group }, | |
3493 | { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group }, | |
2407f5d6 JL |
3494 | { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group }, |
3495 | { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group }, | |
3496 | { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group }, | |
3497 | { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group }, | |
c205d53c JL |
3498 | { }, |
3499 | }; | |
773bda96 | 3500 | |
69dbe107 VF |
3501 | static struct attribute *art_timecard_attrs[] = { |
3502 | &dev_attr_serialnum.attr, | |
3503 | &dev_attr_clock_source.attr, | |
3504 | &dev_attr_available_clock_sources.attr, | |
3505 | &dev_attr_utc_tai_offset.attr, | |
3506 | &dev_attr_ts_window_adjust.attr, | |
3507 | &dev_attr_sma1.attr, | |
3508 | &dev_attr_sma2.attr, | |
3509 | &dev_attr_sma3.attr, | |
3510 | &dev_attr_sma4.attr, | |
3511 | &dev_attr_available_sma_inputs.attr, | |
3512 | &dev_attr_available_sma_outputs.attr, | |
3513 | NULL, | |
3514 | }; | |
3515 | ||
ee6439aa VF |
3516 | static struct bin_attribute *bin_art_timecard_attrs[] = { |
3517 | &bin_attr_disciplining_config, | |
3518 | &bin_attr_temperature_table, | |
3519 | NULL, | |
3520 | }; | |
3521 | ||
69dbe107 VF |
3522 | static const struct attribute_group art_timecard_group = { |
3523 | .attrs = art_timecard_attrs, | |
ee6439aa | 3524 | .bin_attrs = bin_art_timecard_attrs, |
69dbe107 VF |
3525 | }; |
3526 | ||
3527 | static const struct ocp_attr_group art_timecard_groups[] = { | |
3528 | { .cap = OCP_CAP_BASIC, .group = &art_timecard_group }, | |
3529 | { }, | |
3530 | }; | |
3531 | ||
a509a7c6 JL |
3532 | static void |
3533 | gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit, | |
3534 | const char *def) | |
f67bf662 | 3535 | { |
a509a7c6 | 3536 | int i; |
f67bf662 | 3537 | |
a509a7c6 JL |
3538 | for (i = 0; i < 4; i++) { |
3539 | if (bp->sma[i].mode != SMA_MODE_IN) | |
3540 | continue; | |
3541 | if (map[i][0] & (1 << bit)) { | |
3542 | sprintf(buf, "sma%d", i + 1); | |
3543 | return; | |
3544 | } | |
3545 | } | |
3546 | if (!def) | |
3547 | def = "----"; | |
3548 | strcpy(buf, def); | |
f67bf662 JL |
3549 | } |
3550 | ||
3551 | static void | |
a509a7c6 | 3552 | gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit) |
f67bf662 JL |
3553 | { |
3554 | char *ans = buf; | |
a509a7c6 | 3555 | int i; |
f67bf662 | 3556 | |
a509a7c6 JL |
3557 | strcpy(ans, "----"); |
3558 | for (i = 0; i < 4; i++) { | |
3559 | if (bp->sma[i].mode != SMA_MODE_OUT) | |
3560 | continue; | |
3561 | if (map[i][1] & (1 << bit)) | |
3562 | ans += sprintf(ans, "sma%d ", i + 1); | |
3563 | } | |
f67bf662 JL |
3564 | } |
3565 | ||
b325af3c JL |
3566 | static void |
3567 | _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr) | |
3568 | { | |
3569 | struct signal_reg __iomem *reg = bp->signal_out[nr]->mem; | |
3570 | struct ptp_ocp_signal *signal = &bp->signal[nr]; | |
3571 | char label[8]; | |
3572 | bool on; | |
3573 | u32 val; | |
3574 | ||
3575 | if (!signal) | |
3576 | return; | |
3577 | ||
3578 | on = signal->running; | |
05fc65f3 | 3579 | sprintf(label, "GEN%d", nr + 1); |
b325af3c JL |
3580 | seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d", |
3581 | label, on ? " ON" : "OFF", | |
3582 | signal->period, signal->duty, signal->phase, | |
3583 | signal->polarity); | |
3584 | ||
3585 | val = ioread32(®->enable); | |
3586 | seq_printf(s, " [%x", val); | |
3587 | val = ioread32(®->status); | |
3588 | seq_printf(s, " %x]", val); | |
3589 | ||
3590 | seq_printf(s, " start:%llu\n", signal->start); | |
3591 | } | |
3592 | ||
2407f5d6 JL |
3593 | static void |
3594 | _frequency_summary_show(struct seq_file *s, int nr, | |
3595 | struct frequency_reg __iomem *reg) | |
3596 | { | |
3597 | char label[8]; | |
3598 | bool on; | |
3599 | u32 val; | |
3600 | ||
3601 | if (!reg) | |
3602 | return; | |
3603 | ||
05fc65f3 | 3604 | sprintf(label, "FREQ%d", nr + 1); |
2407f5d6 JL |
3605 | val = ioread32(®->ctrl); |
3606 | on = val & 1; | |
3607 | val = (val >> 8) & 0xff; | |
3608 | seq_printf(s, "%7s: %s, sec:%u", | |
3609 | label, | |
3610 | on ? " ON" : "OFF", | |
3611 | val); | |
3612 | ||
3613 | val = ioread32(®->status); | |
3614 | if (val & FREQ_STATUS_ERROR) | |
3615 | seq_printf(s, ", error"); | |
3616 | if (val & FREQ_STATUS_OVERRUN) | |
3617 | seq_printf(s, ", overrun"); | |
3618 | if (val & FREQ_STATUS_VALID) | |
3619 | seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK); | |
3620 | seq_printf(s, " reg:%x\n", val); | |
3621 | } | |
3622 | ||
f67bf662 JL |
3623 | static int |
3624 | ptp_ocp_summary_show(struct seq_file *s, void *data) | |
3625 | { | |
3626 | struct device *dev = s->private; | |
3627 | struct ptp_system_timestamp sts; | |
f67bf662 | 3628 | struct ts_reg __iomem *ts_reg; |
b88fdbba | 3629 | char *buf, *src, *mac_src; |
f67bf662 JL |
3630 | struct timespec64 ts; |
3631 | struct ptp_ocp *bp; | |
2b341f75 | 3632 | u16 sma_val[4][2]; |
2b341f75 | 3633 | u32 ctrl, val; |
a62a56d0 | 3634 | bool on, map; |
b325af3c | 3635 | int i; |
f67bf662 JL |
3636 | |
3637 | buf = (char *)__get_free_page(GFP_KERNEL); | |
3638 | if (!buf) | |
3639 | return -ENOMEM; | |
3640 | ||
3641 | bp = dev_get_drvdata(dev); | |
f67bf662 JL |
3642 | |
3643 | seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp)); | |
895ac5a5 VF |
3644 | if (bp->gnss_port.line != -1) |
3645 | seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1", | |
3646 | bp->gnss_port.line); | |
3647 | if (bp->gnss2_port.line != -1) | |
3648 | seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2", | |
3649 | bp->gnss2_port.line); | |
3650 | if (bp->mac_port.line != -1) | |
3651 | seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line); | |
3652 | if (bp->nmea_port.line != -1) | |
3653 | seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line); | |
f67bf662 | 3654 | |
a509a7c6 JL |
3655 | memset(sma_val, 0xff, sizeof(sma_val)); |
3656 | if (bp->sma_map1) { | |
3657 | u32 reg; | |
3658 | ||
3659 | reg = ioread32(&bp->sma_map1->gpio1); | |
3660 | sma_val[0][0] = reg & 0xffff; | |
3661 | sma_val[1][0] = reg >> 16; | |
3662 | ||
3663 | reg = ioread32(&bp->sma_map1->gpio2); | |
3664 | sma_val[2][1] = reg & 0xffff; | |
3665 | sma_val[3][1] = reg >> 16; | |
3666 | ||
3667 | reg = ioread32(&bp->sma_map2->gpio1); | |
3668 | sma_val[2][0] = reg & 0xffff; | |
3669 | sma_val[3][0] = reg >> 16; | |
3670 | ||
3671 | reg = ioread32(&bp->sma_map2->gpio2); | |
3672 | sma_val[0][1] = reg & 0xffff; | |
3673 | sma_val[1][1] = reg >> 16; | |
3674 | } | |
3675 | ||
f67bf662 | 3676 | sma1_show(dev, NULL, buf); |
a509a7c6 JL |
3677 | seq_printf(s, " sma1: %04x,%04x %s", |
3678 | sma_val[0][0], sma_val[0][1], buf); | |
f67bf662 JL |
3679 | |
3680 | sma2_show(dev, NULL, buf); | |
a509a7c6 JL |
3681 | seq_printf(s, " sma2: %04x,%04x %s", |
3682 | sma_val[1][0], sma_val[1][1], buf); | |
f67bf662 JL |
3683 | |
3684 | sma3_show(dev, NULL, buf); | |
a509a7c6 JL |
3685 | seq_printf(s, " sma3: %04x,%04x %s", |
3686 | sma_val[2][0], sma_val[2][1], buf); | |
f67bf662 JL |
3687 | |
3688 | sma4_show(dev, NULL, buf); | |
a509a7c6 JL |
3689 | seq_printf(s, " sma4: %04x,%04x %s", |
3690 | sma_val[3][0], sma_val[3][1], buf); | |
f67bf662 JL |
3691 | |
3692 | if (bp->ts0) { | |
3693 | ts_reg = bp->ts0->mem; | |
3694 | on = ioread32(&ts_reg->enable); | |
be69087c | 3695 | src = "GNSS1"; |
f67bf662 JL |
3696 | seq_printf(s, "%7s: %s, src: %s\n", "TS0", |
3697 | on ? " ON" : "OFF", src); | |
3698 | } | |
3699 | ||
3700 | if (bp->ts1) { | |
3701 | ts_reg = bp->ts1->mem; | |
3702 | on = ioread32(&ts_reg->enable); | |
a509a7c6 | 3703 | gpio_input_map(buf, bp, sma_val, 2, NULL); |
f67bf662 | 3704 | seq_printf(s, "%7s: %s, src: %s\n", "TS1", |
a509a7c6 | 3705 | on ? " ON" : "OFF", buf); |
f67bf662 JL |
3706 | } |
3707 | ||
3708 | if (bp->ts2) { | |
3709 | ts_reg = bp->ts2->mem; | |
3710 | on = ioread32(&ts_reg->enable); | |
a509a7c6 | 3711 | gpio_input_map(buf, bp, sma_val, 3, NULL); |
f67bf662 | 3712 | seq_printf(s, "%7s: %s, src: %s\n", "TS2", |
a509a7c6 | 3713 | on ? " ON" : "OFF", buf); |
f67bf662 JL |
3714 | } |
3715 | ||
0fa3ff7e JL |
3716 | if (bp->ts3) { |
3717 | ts_reg = bp->ts3->mem; | |
3718 | on = ioread32(&ts_reg->enable); | |
3719 | gpio_input_map(buf, bp, sma_val, 6, NULL); | |
3720 | seq_printf(s, "%7s: %s, src: %s\n", "TS3", | |
3721 | on ? " ON" : "OFF", buf); | |
3722 | } | |
3723 | ||
3724 | if (bp->ts4) { | |
3725 | ts_reg = bp->ts4->mem; | |
3726 | on = ioread32(&ts_reg->enable); | |
3727 | gpio_input_map(buf, bp, sma_val, 7, NULL); | |
3728 | seq_printf(s, "%7s: %s, src: %s\n", "TS4", | |
3729 | on ? " ON" : "OFF", buf); | |
3730 | } | |
3731 | ||
a62a56d0 JL |
3732 | if (bp->pps) { |
3733 | ts_reg = bp->pps->mem; | |
3734 | src = "PHC"; | |
3735 | on = ioread32(&ts_reg->enable); | |
3736 | map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP); | |
0fa3ff7e | 3737 | seq_printf(s, "%7s: %s, src: %s\n", "TS5", |
1a575cde | 3738 | on && map ? " ON" : "OFF", src); |
a62a56d0 JL |
3739 | |
3740 | map = !!(bp->pps_req_map & OCP_REQ_PPS); | |
3741 | seq_printf(s, "%7s: %s, src: %s\n", "PPS", | |
1a575cde | 3742 | on && map ? " ON" : "OFF", src); |
a62a56d0 JL |
3743 | } |
3744 | ||
b325af3c JL |
3745 | if (bp->fw_cap & OCP_CAP_SIGNAL) |
3746 | for (i = 0; i < 4; i++) | |
3747 | _signal_summary_show(s, bp, i); | |
3748 | ||
2407f5d6 JL |
3749 | if (bp->fw_cap & OCP_CAP_FREQ) |
3750 | for (i = 0; i < 4; i++) | |
3751 | _frequency_summary_show(s, i, bp->freq_in[i]); | |
3752 | ||
f67bf662 JL |
3753 | if (bp->irig_out) { |
3754 | ctrl = ioread32(&bp->irig_out->ctrl); | |
3755 | on = ctrl & IRIG_M_CTRL_ENABLE; | |
3756 | val = ioread32(&bp->irig_out->status); | |
a509a7c6 | 3757 | gpio_output_map(buf, bp, sma_val, 4); |
f67bf662 JL |
3758 | seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG", |
3759 | on ? " ON" : "OFF", val, (ctrl >> 16), buf); | |
3760 | } | |
3761 | ||
3762 | if (bp->irig_in) { | |
3763 | on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE; | |
3764 | val = ioread32(&bp->irig_in->status); | |
a509a7c6 | 3765 | gpio_input_map(buf, bp, sma_val, 4, NULL); |
f67bf662 | 3766 | seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in", |
a509a7c6 | 3767 | on ? " ON" : "OFF", val, buf); |
f67bf662 JL |
3768 | } |
3769 | ||
3770 | if (bp->dcf_out) { | |
3771 | on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE; | |
3772 | val = ioread32(&bp->dcf_out->status); | |
a509a7c6 | 3773 | gpio_output_map(buf, bp, sma_val, 5); |
f67bf662 JL |
3774 | seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF", |
3775 | on ? " ON" : "OFF", val, buf); | |
3776 | } | |
3777 | ||
3778 | if (bp->dcf_in) { | |
3779 | on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE; | |
3780 | val = ioread32(&bp->dcf_in->status); | |
a509a7c6 | 3781 | gpio_input_map(buf, bp, sma_val, 5, NULL); |
f67bf662 | 3782 | seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in", |
a509a7c6 | 3783 | on ? " ON" : "OFF", val, buf); |
f67bf662 JL |
3784 | } |
3785 | ||
e3516bb4 JL |
3786 | if (bp->nmea_out) { |
3787 | on = ioread32(&bp->nmea_out->ctrl) & 1; | |
3788 | val = ioread32(&bp->nmea_out->status); | |
3789 | seq_printf(s, "%7s: %s, error: %d\n", "NMEA", | |
3790 | on ? " ON" : "OFF", val); | |
3791 | } | |
3792 | ||
f67bf662 JL |
3793 | /* compute src for PPS1, used below. */ |
3794 | if (bp->pps_select) { | |
3795 | val = ioread32(&bp->pps_select->gpio1); | |
a509a7c6 | 3796 | src = &buf[80]; |
b88fdbba JL |
3797 | mac_src = "GNSS1"; |
3798 | if (val & 0x01) { | |
a509a7c6 | 3799 | gpio_input_map(src, bp, sma_val, 0, NULL); |
b88fdbba JL |
3800 | mac_src = src; |
3801 | } else if (val & 0x02) { | |
f67bf662 | 3802 | src = "MAC"; |
b88fdbba | 3803 | } else if (val & 0x04) { |
be69087c | 3804 | src = "GNSS1"; |
b88fdbba | 3805 | } else { |
f67bf662 | 3806 | src = "----"; |
b88fdbba JL |
3807 | mac_src = src; |
3808 | } | |
f67bf662 JL |
3809 | } else { |
3810 | src = "?"; | |
b88fdbba | 3811 | mac_src = src; |
f67bf662 | 3812 | } |
b88fdbba JL |
3813 | seq_printf(s, "MAC PPS1 src: %s\n", mac_src); |
3814 | ||
3815 | gpio_input_map(buf, bp, sma_val, 1, "GNSS2"); | |
3816 | seq_printf(s, "MAC PPS2 src: %s\n", buf); | |
f67bf662 JL |
3817 | |
3818 | /* assumes automatic switchover/selection */ | |
3819 | val = ioread32(&bp->reg->select); | |
3820 | switch (val >> 16) { | |
3821 | case 0: | |
3822 | sprintf(buf, "----"); | |
3823 | break; | |
3824 | case 2: | |
3825 | sprintf(buf, "IRIG"); | |
3826 | break; | |
3827 | case 3: | |
3828 | sprintf(buf, "%s via PPS1", src); | |
3829 | break; | |
3830 | case 6: | |
3831 | sprintf(buf, "DCF"); | |
3832 | break; | |
3833 | default: | |
3834 | strcpy(buf, "unknown"); | |
3835 | break; | |
3836 | } | |
3837 | val = ioread32(&bp->reg->status); | |
3838 | seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf, | |
3839 | val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced"); | |
3840 | ||
f67bf662 JL |
3841 | if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) { |
3842 | struct timespec64 sys_ts; | |
3843 | s64 pre_ns, post_ns, ns; | |
3844 | ||
3845 | pre_ns = timespec64_to_ns(&sts.pre_ts); | |
3846 | post_ns = timespec64_to_ns(&sts.post_ts); | |
3847 | ns = (pre_ns + post_ns) / 2; | |
3848 | ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC; | |
3849 | sys_ts = ns_to_timespec64(ns); | |
3850 | ||
3851 | seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC", | |
3852 | ts.tv_sec, ts.tv_nsec, &ts); | |
3853 | seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS", | |
3854 | sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts, | |
3855 | bp->utc_tai_offset); | |
3856 | seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "", | |
3857 | timespec64_to_ns(&ts) - ns, | |
3858 | post_ns - pre_ns); | |
3859 | } | |
3860 | ||
3861 | free_page((unsigned long)buf); | |
3862 | return 0; | |
3863 | } | |
3864 | DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary); | |
3865 | ||
9f492c4c VF |
3866 | static int |
3867 | ptp_ocp_tod_status_show(struct seq_file *s, void *data) | |
3868 | { | |
3869 | struct device *dev = s->private; | |
3870 | struct ptp_ocp *bp; | |
3871 | u32 val; | |
3872 | int idx; | |
3873 | ||
3874 | bp = dev_get_drvdata(dev); | |
3875 | ||
3876 | val = ioread32(&bp->tod->ctrl); | |
3877 | if (!(val & TOD_CTRL_ENABLE)) { | |
3878 | seq_printf(s, "TOD Slave disabled\n"); | |
3879 | return 0; | |
3880 | } | |
3881 | seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val); | |
3882 | ||
3883 | idx = val & TOD_CTRL_PROTOCOL ? 4 : 0; | |
3884 | idx += (val >> 16) & 3; | |
3885 | seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx)); | |
3886 | ||
3887 | idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK; | |
3888 | seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx)); | |
3889 | ||
3890 | val = ioread32(&bp->tod->version); | |
3891 | seq_printf(s, "TOD Version %d.%d.%d\n", | |
3892 | val >> 24, (val >> 16) & 0xff, val & 0xffff); | |
3893 | ||
3894 | val = ioread32(&bp->tod->status); | |
3895 | seq_printf(s, "Status register: 0x%08X\n", val); | |
3896 | ||
3897 | val = ioread32(&bp->tod->adj_sec); | |
3898 | idx = (val & ~INT_MAX) ? -1 : 1; | |
3899 | idx *= (val & INT_MAX); | |
3900 | seq_printf(s, "Correction seconds: %d\n", idx); | |
3901 | ||
3902 | val = ioread32(&bp->tod->utc_status); | |
3903 | seq_printf(s, "UTC status register: 0x%08X\n", val); | |
1132bb29 | 3904 | seq_printf(s, "UTC offset: %ld valid:%d\n", |
9f492c4c VF |
3905 | val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0); |
3906 | seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n", | |
3907 | val & TOD_STATUS_LEAP_VALID ? 1 : 0, | |
3908 | val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0); | |
3909 | ||
3910 | val = ioread32(&bp->tod->leap); | |
3911 | seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val); | |
3912 | ||
3913 | return 0; | |
3914 | } | |
3915 | DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status); | |
3916 | ||
f67bf662 JL |
3917 | static struct dentry *ptp_ocp_debugfs_root; |
3918 | ||
3919 | static void | |
3920 | ptp_ocp_debugfs_add_device(struct ptp_ocp *bp) | |
3921 | { | |
3922 | struct dentry *d; | |
3923 | ||
3924 | d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root); | |
3925 | bp->debug_root = d; | |
3926 | debugfs_create_file("summary", 0444, bp->debug_root, | |
3927 | &bp->dev, &ptp_ocp_summary_fops); | |
9f492c4c VF |
3928 | if (bp->tod) |
3929 | debugfs_create_file("tod_status", 0444, bp->debug_root, | |
3930 | &bp->dev, &ptp_ocp_tod_status_fops); | |
f67bf662 JL |
3931 | } |
3932 | ||
3933 | static void | |
3934 | ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp) | |
3935 | { | |
3936 | debugfs_remove_recursive(bp->debug_root); | |
3937 | } | |
3938 | ||
3939 | static void | |
3940 | ptp_ocp_debugfs_init(void) | |
3941 | { | |
3942 | ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL); | |
3943 | } | |
3944 | ||
3945 | static void | |
3946 | ptp_ocp_debugfs_fini(void) | |
3947 | { | |
3948 | debugfs_remove_recursive(ptp_ocp_debugfs_root); | |
3949 | } | |
3950 | ||
773bda96 JL |
3951 | static void |
3952 | ptp_ocp_dev_release(struct device *dev) | |
3953 | { | |
3954 | struct ptp_ocp *bp = dev_get_drvdata(dev); | |
3955 | ||
3956 | mutex_lock(&ptp_ocp_lock); | |
3957 | idr_remove(&ptp_ocp_idr, bp->id); | |
3958 | mutex_unlock(&ptp_ocp_lock); | |
3959 | } | |
3960 | ||
3961 | static int | |
3962 | ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev) | |
3963 | { | |
3964 | int err; | |
3965 | ||
3966 | mutex_lock(&ptp_ocp_lock); | |
3967 | err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); | |
3968 | mutex_unlock(&ptp_ocp_lock); | |
3969 | if (err < 0) { | |
3970 | dev_err(&pdev->dev, "idr_alloc failed: %d\n", err); | |
3971 | return err; | |
3972 | } | |
3973 | bp->id = err; | |
3974 | ||
a7e1abad JL |
3975 | bp->ptp_info = ptp_ocp_clock_info; |
3976 | spin_lock_init(&bp->lock); | |
895ac5a5 VF |
3977 | bp->gnss_port.line = -1; |
3978 | bp->gnss2_port.line = -1; | |
3979 | bp->mac_port.line = -1; | |
3980 | bp->nmea_port.line = -1; | |
773bda96 JL |
3981 | bp->pdev = pdev; |
3982 | ||
3983 | device_initialize(&bp->dev); | |
3984 | dev_set_name(&bp->dev, "ocp%d", bp->id); | |
3985 | bp->dev.class = &timecard_class; | |
3986 | bp->dev.parent = &pdev->dev; | |
3987 | bp->dev.release = ptp_ocp_dev_release; | |
3988 | dev_set_drvdata(&bp->dev, bp); | |
3989 | ||
3990 | err = device_add(&bp->dev); | |
3991 | if (err) { | |
3992 | dev_err(&bp->dev, "device add failed: %d\n", err); | |
773bda96 JL |
3993 | goto out; |
3994 | } | |
3995 | ||
3996 | pci_set_drvdata(pdev, bp); | |
3997 | ||
3998 | return 0; | |
3999 | ||
4000 | out: | |
d12f23fa | 4001 | put_device(&bp->dev); |
773bda96 JL |
4002 | return err; |
4003 | } | |
4004 | ||
4005 | static void | |
4006 | ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link) | |
4007 | { | |
4008 | struct device *dev = &bp->dev; | |
4009 | ||
4010 | if (sysfs_create_link(&dev->kobj, &child->kobj, link)) | |
4011 | dev_err(dev, "%s symlink failed\n", link); | |
4012 | } | |
4013 | ||
4014 | static void | |
4015 | ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link) | |
4016 | { | |
4017 | struct device *dev, *child; | |
4018 | ||
4019 | dev = &bp->pdev->dev; | |
4020 | ||
4021 | child = device_find_child_by_name(dev, name); | |
4022 | if (!child) { | |
4023 | dev_err(dev, "Could not find device %s\n", name); | |
4024 | return; | |
4025 | } | |
4026 | ||
4027 | ptp_ocp_symlink(bp, child, link); | |
4028 | put_device(child); | |
4029 | } | |
4030 | ||
4031 | static int | |
4032 | ptp_ocp_complete(struct ptp_ocp *bp) | |
4033 | { | |
4034 | struct pps_device *pps; | |
4035 | char buf[32]; | |
4036 | ||
895ac5a5 VF |
4037 | if (bp->gnss_port.line != -1) { |
4038 | sprintf(buf, "ttyS%d", bp->gnss_port.line); | |
ef0cfb34 | 4039 | ptp_ocp_link_child(bp, buf, "ttyGNSS"); |
773bda96 | 4040 | } |
895ac5a5 VF |
4041 | if (bp->gnss2_port.line != -1) { |
4042 | sprintf(buf, "ttyS%d", bp->gnss2_port.line); | |
71d7e085 JL |
4043 | ptp_ocp_link_child(bp, buf, "ttyGNSS2"); |
4044 | } | |
895ac5a5 VF |
4045 | if (bp->mac_port.line != -1) { |
4046 | sprintf(buf, "ttyS%d", bp->mac_port.line); | |
773bda96 JL |
4047 | ptp_ocp_link_child(bp, buf, "ttyMAC"); |
4048 | } | |
895ac5a5 VF |
4049 | if (bp->nmea_port.line != -1) { |
4050 | sprintf(buf, "ttyS%d", bp->nmea_port.line); | |
e3516bb4 JL |
4051 | ptp_ocp_link_child(bp, buf, "ttyNMEA"); |
4052 | } | |
773bda96 JL |
4053 | sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp)); |
4054 | ptp_ocp_link_child(bp, buf, "ptp"); | |
4055 | ||
4056 | pps = pps_lookup_dev(bp->ptp); | |
4057 | if (pps) | |
4058 | ptp_ocp_symlink(bp, pps->dev, "pps"); | |
4059 | ||
f67bf662 JL |
4060 | ptp_ocp_debugfs_add_device(bp); |
4061 | ||
773bda96 JL |
4062 | return 0; |
4063 | } | |
4064 | ||
4065 | static void | |
065efcc5 JL |
4066 | ptp_ocp_phc_info(struct ptp_ocp *bp) |
4067 | { | |
4068 | struct timespec64 ts; | |
4069 | u32 version, select; | |
4070 | bool sync; | |
4071 | ||
4072 | version = ioread32(&bp->reg->version); | |
4073 | select = ioread32(&bp->reg->select); | |
4074 | dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n", | |
4075 | version >> 24, (version >> 16) & 0xff, version & 0xffff, | |
4076 | ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16), | |
4077 | ptp_clock_index(bp->ptp)); | |
4078 | ||
4079 | sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; | |
4080 | if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL)) | |
4081 | dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n", | |
4082 | ts.tv_sec, ts.tv_nsec, | |
4083 | sync ? "in-sync" : "UNSYNCED"); | |
4084 | } | |
4085 | ||
4086 | static void | |
4087 | ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud) | |
4088 | { | |
4089 | if (port != -1) | |
4090 | dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud); | |
4091 | } | |
4092 | ||
4093 | static void | |
4094 | ptp_ocp_info(struct ptp_ocp *bp) | |
773bda96 | 4095 | { |
e3516bb4 JL |
4096 | static int nmea_baud[] = { |
4097 | 1200, 2400, 4800, 9600, 19200, 38400, | |
4098 | 57600, 115200, 230400, 460800, 921600, | |
4099 | 1000000, 2000000 | |
4100 | }; | |
773bda96 | 4101 | struct device *dev = &bp->pdev->dev; |
e3516bb4 | 4102 | u32 reg; |
773bda96 | 4103 | |
065efcc5 | 4104 | ptp_ocp_phc_info(bp); |
065efcc5 | 4105 | |
895ac5a5 VF |
4106 | ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line, |
4107 | bp->gnss_port.baud); | |
4108 | ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line, | |
4109 | bp->gnss2_port.baud); | |
4110 | ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud); | |
4111 | if (bp->nmea_out && bp->nmea_port.line != -1) { | |
4112 | bp->nmea_port.baud = -1; | |
e3516bb4 JL |
4113 | |
4114 | reg = ioread32(&bp->nmea_out->uart_baud); | |
4115 | if (reg < ARRAY_SIZE(nmea_baud)) | |
895ac5a5 VF |
4116 | bp->nmea_port.baud = nmea_baud[reg]; |
4117 | ||
4118 | ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line, | |
4119 | bp->nmea_port.baud); | |
e3516bb4 | 4120 | } |
773bda96 | 4121 | } |
a7e1abad | 4122 | |
773bda96 JL |
4123 | static void |
4124 | ptp_ocp_detach_sysfs(struct ptp_ocp *bp) | |
4125 | { | |
4126 | struct device *dev = &bp->dev; | |
4127 | ||
ef0cfb34 | 4128 | sysfs_remove_link(&dev->kobj, "ttyGNSS"); |
84cdf5bc | 4129 | sysfs_remove_link(&dev->kobj, "ttyGNSS2"); |
773bda96 JL |
4130 | sysfs_remove_link(&dev->kobj, "ttyMAC"); |
4131 | sysfs_remove_link(&dev->kobj, "ptp"); | |
4132 | sysfs_remove_link(&dev->kobj, "pps"); | |
773bda96 JL |
4133 | } |
4134 | ||
4135 | static void | |
4136 | ptp_ocp_detach(struct ptp_ocp *bp) | |
4137 | { | |
b325af3c JL |
4138 | int i; |
4139 | ||
f67bf662 | 4140 | ptp_ocp_debugfs_remove_device(bp); |
773bda96 | 4141 | ptp_ocp_detach_sysfs(bp); |
c2239294 | 4142 | ptp_ocp_attr_group_del(bp); |
773bda96 JL |
4143 | if (timer_pending(&bp->watchdog)) |
4144 | del_timer_sync(&bp->watchdog); | |
4145 | if (bp->ts0) | |
4146 | ptp_ocp_unregister_ext(bp->ts0); | |
4147 | if (bp->ts1) | |
4148 | ptp_ocp_unregister_ext(bp->ts1); | |
dcf61469 JL |
4149 | if (bp->ts2) |
4150 | ptp_ocp_unregister_ext(bp->ts2); | |
0fa3ff7e JL |
4151 | if (bp->ts3) |
4152 | ptp_ocp_unregister_ext(bp->ts3); | |
4153 | if (bp->ts4) | |
4154 | ptp_ocp_unregister_ext(bp->ts4); | |
773bda96 JL |
4155 | if (bp->pps) |
4156 | ptp_ocp_unregister_ext(bp->pps); | |
b325af3c JL |
4157 | for (i = 0; i < 4; i++) |
4158 | if (bp->signal_out[i]) | |
4159 | ptp_ocp_unregister_ext(bp->signal_out[i]); | |
895ac5a5 VF |
4160 | if (bp->gnss_port.line != -1) |
4161 | serial8250_unregister_port(bp->gnss_port.line); | |
4162 | if (bp->gnss2_port.line != -1) | |
4163 | serial8250_unregister_port(bp->gnss2_port.line); | |
4164 | if (bp->mac_port.line != -1) | |
4165 | serial8250_unregister_port(bp->mac_port.line); | |
4166 | if (bp->nmea_port.line != -1) | |
4167 | serial8250_unregister_port(bp->nmea_port.line); | |
3a544ebf AS |
4168 | platform_device_unregister(bp->spi_flash); |
4169 | platform_device_unregister(bp->i2c_ctrl); | |
773bda96 JL |
4170 | if (bp->i2c_clk) |
4171 | clk_hw_unregister_fixed_rate(bp->i2c_clk); | |
4172 | if (bp->n_irqs) | |
4173 | pci_free_irq_vectors(bp->pdev); | |
4174 | if (bp->ptp) | |
4175 | ptp_clock_unregister(bp->ptp); | |
1aa66a3a | 4176 | kfree(bp->ptp_info.pin_config); |
773bda96 JL |
4177 | device_unregister(&bp->dev); |
4178 | } | |
4179 | ||
4180 | static int | |
4181 | ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
4182 | { | |
4183 | struct devlink *devlink; | |
4184 | struct ptp_ocp *bp; | |
4185 | int err; | |
4186 | ||
919d13a7 | 4187 | devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev); |
773bda96 JL |
4188 | if (!devlink) { |
4189 | dev_err(&pdev->dev, "devlink_alloc failed\n"); | |
4190 | return -ENOMEM; | |
4191 | } | |
4192 | ||
773bda96 JL |
4193 | err = pci_enable_device(pdev); |
4194 | if (err) { | |
4195 | dev_err(&pdev->dev, "pci_enable_device\n"); | |
4587369b | 4196 | goto out_free; |
773bda96 JL |
4197 | } |
4198 | ||
4199 | bp = devlink_priv(devlink); | |
4200 | err = ptp_ocp_device_init(bp, pdev); | |
4201 | if (err) | |
d9fdbf13 | 4202 | goto out_disable; |
773bda96 JL |
4203 | |
4204 | /* compat mode. | |
4205 | * Older FPGA firmware only returns 2 irq's. | |
4206 | * allow this - if not all of the IRQ's are returned, skip the | |
4207 | * extra devices and just register the clock. | |
4208 | */ | |
0fa3ff7e | 4209 | err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX); |
773bda96 JL |
4210 | if (err < 0) { |
4211 | dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err); | |
4212 | goto out; | |
4213 | } | |
4214 | bp->n_irqs = err; | |
4215 | pci_set_master(pdev); | |
4216 | ||
4217 | err = ptp_ocp_register_resources(bp, id->driver_data); | |
a7e1abad JL |
4218 | if (err) |
4219 | goto out; | |
4220 | ||
4221 | bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev); | |
4222 | if (IS_ERR(bp->ptp)) { | |
a7e1abad | 4223 | err = PTR_ERR(bp->ptp); |
773bda96 JL |
4224 | dev_err(&pdev->dev, "ptp_clock_register: %d\n", err); |
4225 | bp->ptp = NULL; | |
a7e1abad JL |
4226 | goto out; |
4227 | } | |
4228 | ||
773bda96 JL |
4229 | err = ptp_ocp_complete(bp); |
4230 | if (err) | |
4231 | goto out; | |
4232 | ||
a7e1abad | 4233 | ptp_ocp_info(bp); |
c89f78e9 | 4234 | devlink_register(devlink); |
a7e1abad JL |
4235 | return 0; |
4236 | ||
4237 | out: | |
773bda96 | 4238 | ptp_ocp_detach(bp); |
d9fdbf13 JL |
4239 | out_disable: |
4240 | pci_disable_device(pdev); | |
4587369b | 4241 | out_free: |
773bda96 | 4242 | devlink_free(devlink); |
a7e1abad JL |
4243 | return err; |
4244 | } | |
4245 | ||
4246 | static void | |
4247 | ptp_ocp_remove(struct pci_dev *pdev) | |
4248 | { | |
4249 | struct ptp_ocp *bp = pci_get_drvdata(pdev); | |
773bda96 | 4250 | struct devlink *devlink = priv_to_devlink(bp); |
a7e1abad | 4251 | |
c89f78e9 | 4252 | devlink_unregister(devlink); |
773bda96 | 4253 | ptp_ocp_detach(bp); |
d9fdbf13 | 4254 | pci_disable_device(pdev); |
773bda96 | 4255 | |
773bda96 | 4256 | devlink_free(devlink); |
a7e1abad JL |
4257 | } |
4258 | ||
4259 | static struct pci_driver ptp_ocp_driver = { | |
4260 | .name = KBUILD_MODNAME, | |
4261 | .id_table = ptp_ocp_pcidev_id, | |
4262 | .probe = ptp_ocp_probe, | |
4263 | .remove = ptp_ocp_remove, | |
4264 | }; | |
4265 | ||
773bda96 JL |
4266 | static int |
4267 | ptp_ocp_i2c_notifier_call(struct notifier_block *nb, | |
4268 | unsigned long action, void *data) | |
4269 | { | |
4270 | struct device *dev, *child = data; | |
4271 | struct ptp_ocp *bp; | |
4272 | bool add; | |
4273 | ||
4274 | switch (action) { | |
4275 | case BUS_NOTIFY_ADD_DEVICE: | |
4276 | case BUS_NOTIFY_DEL_DEVICE: | |
4277 | add = action == BUS_NOTIFY_ADD_DEVICE; | |
4278 | break; | |
4279 | default: | |
4280 | return 0; | |
4281 | } | |
4282 | ||
4283 | if (!i2c_verify_adapter(child)) | |
4284 | return 0; | |
4285 | ||
4286 | dev = child; | |
4287 | while ((dev = dev->parent)) | |
4288 | if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) | |
4289 | goto found; | |
4290 | return 0; | |
4291 | ||
4292 | found: | |
4293 | bp = dev_get_drvdata(dev); | |
4294 | if (add) | |
4295 | ptp_ocp_symlink(bp, child, "i2c"); | |
4296 | else | |
4297 | sysfs_remove_link(&bp->dev.kobj, "i2c"); | |
4298 | ||
4299 | return 0; | |
4300 | } | |
4301 | ||
4302 | static struct notifier_block ptp_ocp_i2c_notifier = { | |
4303 | .notifier_call = ptp_ocp_i2c_notifier_call, | |
4304 | }; | |
4305 | ||
a7e1abad JL |
4306 | static int __init |
4307 | ptp_ocp_init(void) | |
4308 | { | |
773bda96 | 4309 | const char *what; |
a7e1abad JL |
4310 | int err; |
4311 | ||
f67bf662 JL |
4312 | ptp_ocp_debugfs_init(); |
4313 | ||
773bda96 JL |
4314 | what = "timecard class"; |
4315 | err = class_register(&timecard_class); | |
4316 | if (err) | |
4317 | goto out; | |
4318 | ||
4319 | what = "i2c notifier"; | |
4320 | err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); | |
4321 | if (err) | |
4322 | goto out_notifier; | |
4323 | ||
4324 | what = "ptp_ocp driver"; | |
a7e1abad | 4325 | err = pci_register_driver(&ptp_ocp_driver); |
773bda96 JL |
4326 | if (err) |
4327 | goto out_register; | |
4328 | ||
4329 | return 0; | |
4330 | ||
4331 | out_register: | |
4332 | bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); | |
4333 | out_notifier: | |
4334 | class_unregister(&timecard_class); | |
4335 | out: | |
f67bf662 | 4336 | ptp_ocp_debugfs_fini(); |
773bda96 | 4337 | pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err); |
a7e1abad JL |
4338 | return err; |
4339 | } | |
4340 | ||
4341 | static void __exit | |
4342 | ptp_ocp_fini(void) | |
4343 | { | |
773bda96 | 4344 | bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); |
a7e1abad | 4345 | pci_unregister_driver(&ptp_ocp_driver); |
773bda96 | 4346 | class_unregister(&timecard_class); |
f67bf662 | 4347 | ptp_ocp_debugfs_fini(); |
a7e1abad JL |
4348 | } |
4349 | ||
4350 | module_init(ptp_ocp_init); | |
4351 | module_exit(ptp_ocp_fini); | |
4352 | ||
4353 | MODULE_DESCRIPTION("OpenCompute TimeCard driver"); | |
4354 | MODULE_LICENSE("GPL v2"); |