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3a6ba7dc VC |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and | |
4 | * synchronization devices. | |
5 | * | |
6 | * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company. | |
7 | */ | |
8 | #include <linux/firmware.h> | |
9 | #include <linux/i2c.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/ptp_clock_kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/timekeeping.h> | |
15 | ||
16 | #include "ptp_private.h" | |
17 | #include "ptp_clockmatrix.h" | |
18 | ||
19 | MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family"); | |
20 | MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); | |
21 | MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>"); | |
22 | MODULE_VERSION("1.0"); | |
23 | MODULE_LICENSE("GPL"); | |
24 | ||
25 | #define SETTIME_CORRECTION (0) | |
26 | ||
27 | static int char_array_to_timespec(u8 *buf, | |
28 | u8 count, | |
29 | struct timespec64 *ts) | |
30 | { | |
31 | u8 i; | |
32 | u64 nsec; | |
33 | time64_t sec; | |
34 | ||
35 | if (count < TOD_BYTE_COUNT) | |
36 | return 1; | |
37 | ||
38 | /* Sub-nanoseconds are in buf[0]. */ | |
39 | nsec = buf[4]; | |
40 | for (i = 0; i < 3; i++) { | |
41 | nsec <<= 8; | |
42 | nsec |= buf[3 - i]; | |
43 | } | |
44 | ||
45 | sec = buf[10]; | |
46 | for (i = 0; i < 5; i++) { | |
47 | sec <<= 8; | |
48 | sec |= buf[9 - i]; | |
49 | } | |
50 | ||
51 | ts->tv_sec = sec; | |
52 | ts->tv_nsec = nsec; | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | static int timespec_to_char_array(struct timespec64 const *ts, | |
58 | u8 *buf, | |
59 | u8 count) | |
60 | { | |
61 | u8 i; | |
62 | s32 nsec; | |
63 | time64_t sec; | |
64 | ||
65 | if (count < TOD_BYTE_COUNT) | |
66 | return 1; | |
67 | ||
68 | nsec = ts->tv_nsec; | |
69 | sec = ts->tv_sec; | |
70 | ||
71 | /* Sub-nanoseconds are in buf[0]. */ | |
72 | buf[0] = 0; | |
73 | for (i = 1; i < 5; i++) { | |
74 | buf[i] = nsec & 0xff; | |
75 | nsec >>= 8; | |
76 | } | |
77 | ||
78 | for (i = 5; i < TOD_BYTE_COUNT; i++) { | |
79 | ||
80 | buf[i] = sec & 0xff; | |
81 | sec >>= 8; | |
82 | } | |
83 | ||
84 | return 0; | |
85 | } | |
86 | ||
87 | static int idtcm_xfer(struct idtcm *idtcm, | |
88 | u8 regaddr, | |
89 | u8 *buf, | |
90 | u16 count, | |
91 | bool write) | |
92 | { | |
93 | struct i2c_client *client = idtcm->client; | |
94 | struct i2c_msg msg[2]; | |
95 | int cnt; | |
96 | ||
97 | msg[0].addr = client->addr; | |
98 | msg[0].flags = 0; | |
99 | msg[0].len = 1; | |
100 | msg[0].buf = ®addr; | |
101 | ||
102 | msg[1].addr = client->addr; | |
103 | msg[1].flags = write ? 0 : I2C_M_RD; | |
104 | msg[1].len = count; | |
105 | msg[1].buf = buf; | |
106 | ||
107 | cnt = i2c_transfer(client->adapter, msg, 2); | |
108 | ||
109 | if (cnt < 0) { | |
110 | dev_err(&client->dev, "i2c_transfer returned %d\n", cnt); | |
111 | return cnt; | |
112 | } else if (cnt != 2) { | |
113 | dev_err(&client->dev, | |
114 | "i2c_transfer sent only %d of %d messages\n", cnt, 2); | |
115 | return -EIO; | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | static int idtcm_page_offset(struct idtcm *idtcm, u8 val) | |
122 | { | |
123 | u8 buf[4]; | |
124 | int err; | |
125 | ||
126 | if (idtcm->page_offset == val) | |
127 | return 0; | |
128 | ||
129 | buf[0] = 0x0; | |
130 | buf[1] = val; | |
131 | buf[2] = 0x10; | |
132 | buf[3] = 0x20; | |
133 | ||
134 | err = idtcm_xfer(idtcm, PAGE_ADDR, buf, sizeof(buf), 1); | |
135 | ||
136 | if (err) | |
137 | dev_err(&idtcm->client->dev, "failed to set page offset\n"); | |
138 | else | |
139 | idtcm->page_offset = val; | |
140 | ||
141 | return err; | |
142 | } | |
143 | ||
144 | static int _idtcm_rdwr(struct idtcm *idtcm, | |
145 | u16 regaddr, | |
146 | u8 *buf, | |
147 | u16 count, | |
148 | bool write) | |
149 | { | |
150 | u8 hi; | |
151 | u8 lo; | |
152 | int err; | |
153 | ||
154 | hi = (regaddr >> 8) & 0xff; | |
155 | lo = regaddr & 0xff; | |
156 | ||
157 | err = idtcm_page_offset(idtcm, hi); | |
158 | ||
159 | if (err) | |
160 | goto out; | |
161 | ||
162 | err = idtcm_xfer(idtcm, lo, buf, count, write); | |
163 | out: | |
164 | return err; | |
165 | } | |
166 | ||
167 | static int idtcm_read(struct idtcm *idtcm, | |
168 | u16 module, | |
169 | u16 regaddr, | |
170 | u8 *buf, | |
171 | u16 count) | |
172 | { | |
173 | return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false); | |
174 | } | |
175 | ||
176 | static int idtcm_write(struct idtcm *idtcm, | |
177 | u16 module, | |
178 | u16 regaddr, | |
179 | u8 *buf, | |
180 | u16 count) | |
181 | { | |
182 | return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true); | |
183 | } | |
184 | ||
185 | static int _idtcm_gettime(struct idtcm_channel *channel, | |
186 | struct timespec64 *ts) | |
187 | { | |
188 | struct idtcm *idtcm = channel->idtcm; | |
189 | u8 buf[TOD_BYTE_COUNT]; | |
190 | u8 trigger; | |
191 | int err; | |
192 | ||
193 | err = idtcm_read(idtcm, channel->tod_read_primary, | |
194 | TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger)); | |
195 | if (err) | |
196 | return err; | |
197 | ||
198 | trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT); | |
199 | trigger |= (1 << TOD_READ_TRIGGER_SHIFT); | |
200 | trigger |= TOD_READ_TRIGGER_MODE; | |
201 | ||
202 | err = idtcm_write(idtcm, channel->tod_read_primary, | |
203 | TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger)); | |
204 | ||
205 | if (err) | |
206 | return err; | |
207 | ||
208 | if (idtcm->calculate_overhead_flag) | |
209 | idtcm->start_time = ktime_get_raw(); | |
210 | ||
211 | err = idtcm_read(idtcm, channel->tod_read_primary, | |
212 | TOD_READ_PRIMARY, buf, sizeof(buf)); | |
213 | ||
214 | if (err) | |
215 | return err; | |
216 | ||
217 | err = char_array_to_timespec(buf, sizeof(buf), ts); | |
218 | ||
219 | return err; | |
220 | } | |
221 | ||
222 | static int _sync_pll_output(struct idtcm *idtcm, | |
223 | u8 pll, | |
224 | u8 sync_src, | |
225 | u8 qn, | |
226 | u8 qn_plus_1) | |
227 | { | |
228 | int err; | |
229 | u8 val; | |
230 | u16 sync_ctrl0; | |
231 | u16 sync_ctrl1; | |
232 | ||
233 | if ((qn == 0) && (qn_plus_1 == 0)) | |
234 | return 0; | |
235 | ||
236 | switch (pll) { | |
237 | case 0: | |
238 | sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0; | |
239 | sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1; | |
240 | break; | |
241 | case 1: | |
242 | sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0; | |
243 | sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1; | |
244 | break; | |
245 | case 2: | |
246 | sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0; | |
247 | sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1; | |
248 | break; | |
249 | case 3: | |
250 | sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0; | |
251 | sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1; | |
252 | break; | |
253 | case 4: | |
254 | sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0; | |
255 | sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1; | |
256 | break; | |
257 | case 5: | |
258 | sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0; | |
259 | sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1; | |
260 | break; | |
261 | case 6: | |
262 | sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0; | |
263 | sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1; | |
264 | break; | |
265 | case 7: | |
266 | sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0; | |
267 | sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1; | |
268 | break; | |
269 | default: | |
270 | return -EINVAL; | |
271 | } | |
272 | ||
273 | val = SYNCTRL1_MASTER_SYNC_RST; | |
274 | ||
275 | /* Place master sync in reset */ | |
276 | err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); | |
277 | if (err) | |
278 | return err; | |
279 | ||
280 | err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src)); | |
281 | if (err) | |
282 | return err; | |
283 | ||
284 | /* Set sync trigger mask */ | |
285 | val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG; | |
286 | ||
287 | if (qn) | |
288 | val |= SYNCTRL1_Q0_DIV_SYNC_TRIG; | |
289 | ||
290 | if (qn_plus_1) | |
291 | val |= SYNCTRL1_Q1_DIV_SYNC_TRIG; | |
292 | ||
293 | err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); | |
294 | if (err) | |
295 | return err; | |
296 | ||
297 | /* Place master sync out of reset */ | |
298 | val &= ~(SYNCTRL1_MASTER_SYNC_RST); | |
299 | err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val)); | |
300 | ||
301 | return err; | |
302 | } | |
303 | ||
304 | static int idtcm_sync_pps_output(struct idtcm_channel *channel) | |
305 | { | |
306 | struct idtcm *idtcm = channel->idtcm; | |
307 | ||
308 | u8 pll; | |
309 | u8 sync_src; | |
310 | u8 qn; | |
311 | u8 qn_plus_1; | |
312 | int err = 0; | |
313 | ||
314 | u16 output_mask = channel->output_mask; | |
315 | ||
316 | switch (channel->dpll_n) { | |
317 | case DPLL_0: | |
318 | sync_src = SYNC_SOURCE_DPLL0_TOD_PPS; | |
319 | break; | |
320 | case DPLL_1: | |
321 | sync_src = SYNC_SOURCE_DPLL1_TOD_PPS; | |
322 | break; | |
323 | case DPLL_2: | |
324 | sync_src = SYNC_SOURCE_DPLL2_TOD_PPS; | |
325 | break; | |
326 | case DPLL_3: | |
327 | sync_src = SYNC_SOURCE_DPLL3_TOD_PPS; | |
328 | break; | |
329 | default: | |
330 | return -EINVAL; | |
331 | } | |
332 | ||
333 | for (pll = 0; pll < 8; pll++) { | |
334 | ||
335 | qn = output_mask & 0x1; | |
336 | output_mask = output_mask >> 1; | |
337 | ||
338 | if (pll < 4) { | |
339 | /* First 4 pll has 2 outputs */ | |
340 | qn_plus_1 = output_mask & 0x1; | |
341 | output_mask = output_mask >> 1; | |
342 | } else { | |
343 | qn_plus_1 = 0; | |
344 | } | |
345 | ||
346 | if ((qn != 0) || (qn_plus_1 != 0)) | |
347 | err = _sync_pll_output(idtcm, pll, sync_src, qn, | |
348 | qn_plus_1); | |
349 | ||
350 | if (err) | |
351 | return err; | |
352 | } | |
353 | ||
354 | return err; | |
355 | } | |
356 | ||
357 | static int _idtcm_set_dpll_tod(struct idtcm_channel *channel, | |
358 | struct timespec64 const *ts, | |
359 | enum hw_tod_write_trig_sel wr_trig) | |
360 | { | |
361 | struct idtcm *idtcm = channel->idtcm; | |
362 | ||
363 | u8 buf[TOD_BYTE_COUNT]; | |
364 | u8 cmd; | |
365 | int err; | |
366 | struct timespec64 local_ts = *ts; | |
367 | s64 total_overhead_ns; | |
368 | ||
369 | /* Configure HW TOD write trigger. */ | |
370 | err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, | |
371 | &cmd, sizeof(cmd)); | |
372 | ||
373 | if (err) | |
374 | return err; | |
375 | ||
376 | cmd &= ~(0x0f); | |
377 | cmd |= wr_trig | 0x08; | |
378 | ||
379 | err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, | |
380 | &cmd, sizeof(cmd)); | |
381 | ||
382 | if (err) | |
383 | return err; | |
384 | ||
385 | if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) { | |
386 | ||
387 | err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); | |
388 | ||
389 | if (err) | |
390 | return err; | |
391 | ||
392 | err = idtcm_write(idtcm, channel->hw_dpll_n, | |
393 | HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); | |
394 | ||
395 | if (err) | |
396 | return err; | |
397 | } | |
398 | ||
399 | /* ARM HW TOD write trigger. */ | |
400 | cmd &= ~(0x08); | |
401 | ||
402 | err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, | |
403 | &cmd, sizeof(cmd)); | |
404 | ||
405 | if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) { | |
406 | ||
407 | if (idtcm->calculate_overhead_flag) { | |
1ece2fbe | 408 | /* Assumption: I2C @ 400KHz */ |
3a6ba7dc VC |
409 | total_overhead_ns = ktime_to_ns(ktime_get_raw() |
410 | - idtcm->start_time) | |
411 | + idtcm->tod_write_overhead_ns | |
412 | + SETTIME_CORRECTION; | |
413 | ||
414 | timespec64_add_ns(&local_ts, total_overhead_ns); | |
415 | ||
416 | idtcm->calculate_overhead_flag = 0; | |
417 | } | |
418 | ||
419 | err = timespec_to_char_array(&local_ts, buf, sizeof(buf)); | |
420 | ||
421 | if (err) | |
422 | return err; | |
423 | ||
424 | err = idtcm_write(idtcm, channel->hw_dpll_n, | |
425 | HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); | |
426 | } | |
427 | ||
428 | return err; | |
429 | } | |
430 | ||
431 | static int _idtcm_settime(struct idtcm_channel *channel, | |
432 | struct timespec64 const *ts, | |
433 | enum hw_tod_write_trig_sel wr_trig) | |
434 | { | |
435 | struct idtcm *idtcm = channel->idtcm; | |
436 | s32 retval; | |
437 | int err; | |
438 | int i; | |
439 | u8 trig_sel; | |
440 | ||
441 | err = _idtcm_set_dpll_tod(channel, ts, wr_trig); | |
442 | ||
443 | if (err) | |
444 | return err; | |
445 | ||
446 | /* Wait for the operation to complete. */ | |
447 | for (i = 0; i < 10000; i++) { | |
448 | err = idtcm_read(idtcm, channel->hw_dpll_n, | |
449 | HW_DPLL_TOD_CTRL_1, &trig_sel, | |
450 | sizeof(trig_sel)); | |
451 | ||
452 | if (err) | |
453 | return err; | |
454 | ||
455 | if (trig_sel == 0x4a) | |
456 | break; | |
457 | ||
458 | err = 1; | |
459 | } | |
460 | ||
461 | if (err) | |
462 | return err; | |
463 | ||
464 | retval = idtcm_sync_pps_output(channel); | |
465 | ||
466 | return retval; | |
467 | } | |
468 | ||
469 | static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel, | |
470 | s32 offset_ns) | |
471 | { | |
472 | int err; | |
473 | int i; | |
474 | struct idtcm *idtcm = channel->idtcm; | |
475 | ||
476 | u8 buf[4]; | |
477 | ||
478 | for (i = 0; i < 4; i++) { | |
479 | buf[i] = 0xff & (offset_ns); | |
480 | offset_ns >>= 8; | |
481 | } | |
482 | ||
483 | err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET, | |
484 | buf, sizeof(buf)); | |
485 | ||
486 | return err; | |
487 | } | |
488 | ||
489 | static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel, | |
490 | u32 max_ffo_ppb) | |
491 | { | |
492 | int err; | |
493 | u8 i; | |
494 | struct idtcm *idtcm = channel->idtcm; | |
495 | ||
496 | u8 buf[3]; | |
497 | ||
498 | if (max_ffo_ppb & 0xff000000) | |
499 | max_ffo_ppb = 0; | |
500 | ||
501 | for (i = 0; i < 3; i++) { | |
502 | buf[i] = 0xff & (max_ffo_ppb); | |
503 | max_ffo_ppb >>= 8; | |
504 | } | |
505 | ||
506 | err = idtcm_write(idtcm, channel->dpll_phase_pull_in, | |
507 | PULL_IN_SLOPE_LIMIT, buf, sizeof(buf)); | |
508 | ||
509 | return err; | |
510 | } | |
511 | ||
512 | static int idtcm_start_phase_pull_in(struct idtcm_channel *channel) | |
513 | { | |
514 | int err; | |
515 | struct idtcm *idtcm = channel->idtcm; | |
516 | ||
517 | u8 buf; | |
518 | ||
519 | err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL, | |
520 | &buf, sizeof(buf)); | |
521 | ||
522 | if (err) | |
523 | return err; | |
524 | ||
525 | if (buf == 0) { | |
526 | buf = 0x01; | |
527 | err = idtcm_write(idtcm, channel->dpll_phase_pull_in, | |
528 | PULL_IN_CTRL, &buf, sizeof(buf)); | |
529 | } else { | |
530 | err = -EBUSY; | |
531 | } | |
532 | ||
533 | return err; | |
534 | } | |
535 | ||
536 | static int idtcm_do_phase_pull_in(struct idtcm_channel *channel, | |
537 | s32 offset_ns, | |
538 | u32 max_ffo_ppb) | |
539 | { | |
540 | int err; | |
541 | ||
542 | err = idtcm_set_phase_pull_in_offset(channel, -offset_ns); | |
543 | ||
544 | if (err) | |
545 | return err; | |
546 | ||
547 | err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb); | |
548 | ||
549 | if (err) | |
550 | return err; | |
551 | ||
552 | err = idtcm_start_phase_pull_in(channel); | |
553 | ||
554 | return err; | |
555 | } | |
556 | ||
557 | static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta) | |
558 | { | |
559 | int err; | |
560 | struct idtcm *idtcm = channel->idtcm; | |
561 | struct timespec64 ts; | |
562 | s64 now; | |
563 | ||
564 | if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { | |
565 | err = idtcm_do_phase_pull_in(channel, delta, 0); | |
566 | } else { | |
567 | idtcm->calculate_overhead_flag = 1; | |
568 | ||
569 | err = _idtcm_gettime(channel, &ts); | |
570 | ||
571 | if (err) | |
572 | return err; | |
573 | ||
574 | now = timespec64_to_ns(&ts); | |
575 | now += delta; | |
576 | ||
577 | ts = ns_to_timespec64(now); | |
578 | ||
579 | err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB); | |
580 | } | |
581 | ||
582 | return err; | |
583 | } | |
584 | ||
585 | static int idtcm_state_machine_reset(struct idtcm *idtcm) | |
586 | { | |
587 | int err; | |
588 | u8 byte = SM_RESET_CMD; | |
589 | ||
590 | err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte)); | |
591 | ||
592 | if (!err) | |
593 | msleep_interruptible(POST_SM_RESET_DELAY_MS); | |
594 | ||
595 | return err; | |
596 | } | |
597 | ||
598 | static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id) | |
599 | { | |
1ece2fbe | 600 | return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8)); |
3a6ba7dc VC |
601 | } |
602 | ||
603 | static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id) | |
604 | { | |
605 | int err; | |
606 | u8 buf[2] = {0}; | |
607 | ||
608 | err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf)); | |
609 | ||
610 | *product_id = (buf[1] << 8) | buf[0]; | |
611 | ||
612 | return err; | |
613 | } | |
614 | ||
615 | static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major) | |
616 | { | |
617 | int err; | |
618 | u8 buf = 0; | |
619 | ||
620 | err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf)); | |
621 | ||
622 | *major = buf >> 1; | |
623 | ||
624 | return err; | |
625 | } | |
626 | ||
627 | static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor) | |
628 | { | |
629 | return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8)); | |
630 | } | |
631 | ||
632 | static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix) | |
633 | { | |
634 | return idtcm_read(idtcm, | |
635 | GENERAL_STATUS, | |
636 | HOTFIX_REL, | |
637 | hotfix, | |
638 | sizeof(u8)); | |
639 | } | |
640 | ||
1ece2fbe VC |
641 | static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm, |
642 | u8 *config_select) | |
3a6ba7dc | 643 | { |
1ece2fbe VC |
644 | return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT, |
645 | config_select, sizeof(u8)); | |
3a6ba7dc VC |
646 | } |
647 | ||
648 | static int process_pll_mask(struct idtcm *idtcm, u32 addr, u8 val, u8 *mask) | |
649 | { | |
650 | int err = 0; | |
651 | ||
652 | if (addr == PLL_MASK_ADDR) { | |
653 | if ((val & 0xf0) || !(val & 0xf)) { | |
654 | dev_err(&idtcm->client->dev, | |
655 | "Invalid PLL mask 0x%hhx\n", val); | |
656 | err = -EINVAL; | |
657 | } | |
658 | *mask = val; | |
659 | } | |
660 | ||
661 | return err; | |
662 | } | |
663 | ||
664 | static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val) | |
665 | { | |
666 | int err = 0; | |
667 | ||
668 | switch (addr) { | |
669 | case OUTPUT_MASK_PLL0_ADDR: | |
670 | SET_U16_LSB(idtcm->channel[0].output_mask, val); | |
671 | break; | |
672 | case OUTPUT_MASK_PLL0_ADDR + 1: | |
673 | SET_U16_MSB(idtcm->channel[0].output_mask, val); | |
674 | break; | |
675 | case OUTPUT_MASK_PLL1_ADDR: | |
676 | SET_U16_LSB(idtcm->channel[1].output_mask, val); | |
677 | break; | |
678 | case OUTPUT_MASK_PLL1_ADDR + 1: | |
679 | SET_U16_MSB(idtcm->channel[1].output_mask, val); | |
680 | break; | |
681 | case OUTPUT_MASK_PLL2_ADDR: | |
682 | SET_U16_LSB(idtcm->channel[2].output_mask, val); | |
683 | break; | |
684 | case OUTPUT_MASK_PLL2_ADDR + 1: | |
685 | SET_U16_MSB(idtcm->channel[2].output_mask, val); | |
686 | break; | |
687 | case OUTPUT_MASK_PLL3_ADDR: | |
688 | SET_U16_LSB(idtcm->channel[3].output_mask, val); | |
689 | break; | |
690 | case OUTPUT_MASK_PLL3_ADDR + 1: | |
691 | SET_U16_MSB(idtcm->channel[3].output_mask, val); | |
692 | break; | |
693 | default: | |
694 | err = -EINVAL; | |
695 | break; | |
696 | } | |
697 | ||
698 | return err; | |
699 | } | |
700 | ||
701 | static int check_and_set_masks(struct idtcm *idtcm, | |
702 | u16 regaddr, | |
703 | u8 val) | |
704 | { | |
705 | int err = 0; | |
706 | ||
707 | if (set_pll_output_mask(idtcm, regaddr, val)) { | |
708 | /* Not an output mask, check for pll mask */ | |
709 | err = process_pll_mask(idtcm, regaddr, val, &idtcm->pll_mask); | |
710 | } | |
711 | ||
712 | return err; | |
713 | } | |
714 | ||
715 | static void display_pll_and_output_masks(struct idtcm *idtcm) | |
716 | { | |
717 | u8 i; | |
718 | u8 mask; | |
719 | ||
720 | dev_dbg(&idtcm->client->dev, "pllmask = 0x%02x\n", idtcm->pll_mask); | |
721 | ||
722 | for (i = 0; i < MAX_PHC_PLL; i++) { | |
723 | mask = 1 << i; | |
724 | ||
725 | if (mask & idtcm->pll_mask) | |
726 | dev_dbg(&idtcm->client->dev, | |
727 | "PLL%d output_mask = 0x%04x\n", | |
728 | i, idtcm->channel[i].output_mask); | |
729 | } | |
730 | } | |
731 | ||
732 | static int idtcm_load_firmware(struct idtcm *idtcm, | |
733 | struct device *dev) | |
734 | { | |
735 | const struct firmware *fw; | |
736 | struct idtcm_fwrc *rec; | |
737 | u32 regaddr; | |
738 | int err; | |
739 | s32 len; | |
740 | u8 val; | |
741 | u8 loaddr; | |
742 | ||
743 | dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", FW_FILENAME); | |
744 | ||
745 | err = request_firmware(&fw, FW_FILENAME, dev); | |
746 | ||
747 | if (err) | |
748 | return err; | |
749 | ||
750 | dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size); | |
751 | ||
752 | rec = (struct idtcm_fwrc *) fw->data; | |
753 | ||
754 | if (fw->size > 0) | |
755 | idtcm_state_machine_reset(idtcm); | |
756 | ||
757 | for (len = fw->size; len > 0; len -= sizeof(*rec)) { | |
758 | ||
759 | if (rec->reserved) { | |
760 | dev_err(&idtcm->client->dev, | |
761 | "bad firmware, reserved field non-zero\n"); | |
762 | err = -EINVAL; | |
763 | } else { | |
764 | regaddr = rec->hiaddr << 8; | |
765 | regaddr |= rec->loaddr; | |
766 | ||
767 | val = rec->value; | |
768 | loaddr = rec->loaddr; | |
769 | ||
770 | rec++; | |
771 | ||
772 | err = check_and_set_masks(idtcm, regaddr, val); | |
773 | } | |
774 | ||
775 | if (err == 0) { | |
776 | /* Top (status registers) and bottom are read-only */ | |
777 | if ((regaddr < GPIO_USER_CONTROL) | |
778 | || (regaddr >= SCRATCH)) | |
779 | continue; | |
780 | ||
781 | /* Page size 128, last 4 bytes of page skipped */ | |
782 | if (((loaddr > 0x7b) && (loaddr <= 0x7f)) | |
3e14462f | 783 | || loaddr > 0xfb) |
3a6ba7dc VC |
784 | continue; |
785 | ||
786 | err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val)); | |
787 | } | |
788 | ||
789 | if (err) | |
790 | goto out; | |
791 | } | |
792 | ||
793 | display_pll_and_output_masks(idtcm); | |
794 | ||
795 | out: | |
796 | release_firmware(fw); | |
797 | return err; | |
798 | } | |
799 | ||
800 | static int idtcm_pps_enable(struct idtcm_channel *channel, bool enable) | |
801 | { | |
802 | struct idtcm *idtcm = channel->idtcm; | |
803 | u32 module; | |
804 | u8 val; | |
805 | int err; | |
806 | ||
807 | /* | |
808 | * This assumes that the 1-PPS is on the second of the two | |
809 | * output. But is this always true? | |
810 | */ | |
811 | switch (channel->dpll_n) { | |
812 | case DPLL_0: | |
813 | module = OUTPUT_1; | |
814 | break; | |
815 | case DPLL_1: | |
816 | module = OUTPUT_3; | |
817 | break; | |
818 | case DPLL_2: | |
819 | module = OUTPUT_5; | |
820 | break; | |
821 | case DPLL_3: | |
822 | module = OUTPUT_7; | |
823 | break; | |
824 | default: | |
825 | return -EINVAL; | |
826 | } | |
827 | ||
828 | err = idtcm_read(idtcm, module, OUT_CTRL_1, &val, sizeof(val)); | |
829 | ||
830 | if (err) | |
831 | return err; | |
832 | ||
833 | if (enable) | |
834 | val |= SQUELCH_DISABLE; | |
835 | else | |
836 | val &= ~SQUELCH_DISABLE; | |
837 | ||
838 | err = idtcm_write(idtcm, module, OUT_CTRL_1, &val, sizeof(val)); | |
839 | ||
840 | if (err) | |
841 | return err; | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | static int idtcm_set_pll_mode(struct idtcm_channel *channel, | |
847 | enum pll_mode pll_mode) | |
848 | { | |
849 | struct idtcm *idtcm = channel->idtcm; | |
850 | int err; | |
851 | u8 dpll_mode; | |
852 | ||
853 | err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE, | |
854 | &dpll_mode, sizeof(dpll_mode)); | |
855 | if (err) | |
856 | return err; | |
857 | ||
858 | dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); | |
859 | ||
860 | dpll_mode |= (pll_mode << PLL_MODE_SHIFT); | |
861 | ||
862 | channel->pll_mode = pll_mode; | |
863 | ||
864 | err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE, | |
865 | &dpll_mode, sizeof(dpll_mode)); | |
866 | if (err) | |
867 | return err; | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | /* PTP Hardware Clock interface */ | |
873 | ||
874 | static int idtcm_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
875 | { | |
876 | struct idtcm_channel *channel = | |
877 | container_of(ptp, struct idtcm_channel, caps); | |
878 | struct idtcm *idtcm = channel->idtcm; | |
879 | u8 i; | |
880 | bool neg_adj = 0; | |
881 | int err; | |
882 | u8 buf[6] = {0}; | |
883 | s64 fcw; | |
884 | ||
885 | if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) { | |
886 | err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); | |
887 | if (err) | |
888 | return err; | |
889 | } | |
890 | ||
891 | /* | |
892 | * Frequency Control Word unit is: 1.11 * 10^-10 ppm | |
893 | * | |
894 | * adjfreq: | |
895 | * ppb * 10^9 | |
896 | * FCW = ---------- | |
897 | * 111 | |
898 | * | |
899 | * adjfine: | |
900 | * ppm_16 * 5^12 | |
901 | * FCW = ------------- | |
902 | * 111 * 2^4 | |
903 | */ | |
904 | if (ppb < 0) { | |
905 | neg_adj = 1; | |
906 | ppb = -ppb; | |
907 | } | |
908 | ||
909 | /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */ | |
910 | fcw = ppb * 1000000000000ULL; | |
911 | ||
912 | fcw = div_u64(fcw, 111022); | |
913 | ||
914 | if (neg_adj) | |
915 | fcw = -fcw; | |
916 | ||
917 | for (i = 0; i < 6; i++) { | |
918 | buf[i] = fcw & 0xff; | |
919 | fcw >>= 8; | |
920 | } | |
921 | ||
922 | mutex_lock(&idtcm->reg_lock); | |
923 | ||
924 | err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ, | |
925 | buf, sizeof(buf)); | |
926 | ||
927 | mutex_unlock(&idtcm->reg_lock); | |
928 | return err; | |
929 | } | |
930 | ||
931 | static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) | |
932 | { | |
933 | struct idtcm_channel *channel = | |
934 | container_of(ptp, struct idtcm_channel, caps); | |
935 | struct idtcm *idtcm = channel->idtcm; | |
936 | int err; | |
937 | ||
938 | mutex_lock(&idtcm->reg_lock); | |
939 | ||
940 | err = _idtcm_gettime(channel, ts); | |
941 | ||
942 | mutex_unlock(&idtcm->reg_lock); | |
943 | ||
944 | return err; | |
945 | } | |
946 | ||
947 | static int idtcm_settime(struct ptp_clock_info *ptp, | |
948 | const struct timespec64 *ts) | |
949 | { | |
950 | struct idtcm_channel *channel = | |
951 | container_of(ptp, struct idtcm_channel, caps); | |
952 | struct idtcm *idtcm = channel->idtcm; | |
953 | int err; | |
954 | ||
955 | mutex_lock(&idtcm->reg_lock); | |
956 | ||
957 | err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB); | |
958 | ||
959 | mutex_unlock(&idtcm->reg_lock); | |
960 | ||
961 | return err; | |
962 | } | |
963 | ||
964 | static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
965 | { | |
966 | struct idtcm_channel *channel = | |
967 | container_of(ptp, struct idtcm_channel, caps); | |
968 | struct idtcm *idtcm = channel->idtcm; | |
969 | int err; | |
970 | ||
971 | mutex_lock(&idtcm->reg_lock); | |
972 | ||
973 | err = _idtcm_adjtime(channel, delta); | |
974 | ||
975 | mutex_unlock(&idtcm->reg_lock); | |
976 | ||
977 | return err; | |
978 | } | |
979 | ||
980 | static int idtcm_enable(struct ptp_clock_info *ptp, | |
981 | struct ptp_clock_request *rq, int on) | |
982 | { | |
983 | struct idtcm_channel *channel = | |
984 | container_of(ptp, struct idtcm_channel, caps); | |
985 | ||
986 | switch (rq->type) { | |
987 | case PTP_CLK_REQ_PEROUT: | |
988 | if (!on) | |
989 | return idtcm_pps_enable(channel, false); | |
990 | ||
991 | /* Only accept a 1-PPS aligned to the second. */ | |
992 | if (rq->perout.start.nsec || rq->perout.period.sec != 1 || | |
993 | rq->perout.period.nsec) | |
994 | return -ERANGE; | |
995 | ||
996 | return idtcm_pps_enable(channel, true); | |
997 | default: | |
998 | break; | |
999 | } | |
1000 | ||
1001 | return -EOPNOTSUPP; | |
1002 | } | |
1003 | ||
1004 | static int idtcm_enable_tod(struct idtcm_channel *channel) | |
1005 | { | |
1006 | struct idtcm *idtcm = channel->idtcm; | |
1007 | struct timespec64 ts = {0, 0}; | |
1008 | u8 cfg; | |
1009 | int err; | |
1010 | ||
1011 | err = idtcm_pps_enable(channel, false); | |
1012 | if (err) | |
1013 | return err; | |
1014 | ||
1015 | /* | |
1016 | * Start the TOD clock ticking. | |
1017 | */ | |
1018 | err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); | |
1019 | if (err) | |
1020 | return err; | |
1021 | ||
1022 | cfg |= TOD_ENABLE; | |
1023 | ||
1024 | err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg)); | |
1025 | if (err) | |
1026 | return err; | |
1027 | ||
1028 | return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB); | |
1029 | } | |
1030 | ||
1031 | static void idtcm_display_version_info(struct idtcm *idtcm) | |
1032 | { | |
1033 | u8 major; | |
1034 | u8 minor; | |
1035 | u8 hotfix; | |
3a6ba7dc | 1036 | u16 product_id; |
3a6ba7dc | 1037 | u8 hw_rev_id; |
1ece2fbe VC |
1038 | u8 config_select; |
1039 | char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n"; | |
3a6ba7dc VC |
1040 | |
1041 | idtcm_read_major_release(idtcm, &major); | |
1042 | idtcm_read_minor_release(idtcm, &minor); | |
1043 | idtcm_read_hotfix_release(idtcm, &hotfix); | |
3a6ba7dc VC |
1044 | |
1045 | idtcm_read_product_id(idtcm, &product_id); | |
1046 | idtcm_read_hw_rev_id(idtcm, &hw_rev_id); | |
1ece2fbe VC |
1047 | |
1048 | idtcm_read_otp_scsr_config_select(idtcm, &config_select); | |
1049 | ||
1050 | dev_info(&idtcm->client->dev, fmt, major, minor, hotfix, | |
1051 | product_id, hw_rev_id, config_select); | |
3a6ba7dc VC |
1052 | } |
1053 | ||
6485f9ae | 1054 | static const struct ptp_clock_info idtcm_caps = { |
3a6ba7dc VC |
1055 | .owner = THIS_MODULE, |
1056 | .max_adj = 244000, | |
1057 | .n_per_out = 1, | |
1058 | .adjfreq = &idtcm_adjfreq, | |
1059 | .adjtime = &idtcm_adjtime, | |
1060 | .gettime64 = &idtcm_gettime, | |
1061 | .settime64 = &idtcm_settime, | |
1062 | .enable = &idtcm_enable, | |
1063 | }; | |
1064 | ||
1065 | static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) | |
1066 | { | |
1067 | struct idtcm_channel *channel; | |
1068 | int err; | |
1069 | ||
1070 | if (!(index < MAX_PHC_PLL)) | |
1071 | return -EINVAL; | |
1072 | ||
1073 | channel = &idtcm->channel[index]; | |
1074 | ||
1075 | switch (index) { | |
1076 | case 0: | |
1077 | channel->dpll_freq = DPLL_FREQ_0; | |
1078 | channel->dpll_n = DPLL_0; | |
1079 | channel->tod_read_primary = TOD_READ_PRIMARY_0; | |
1080 | channel->tod_write = TOD_WRITE_0; | |
1081 | channel->tod_n = TOD_0; | |
1082 | channel->hw_dpll_n = HW_DPLL_0; | |
1083 | channel->dpll_phase = DPLL_PHASE_0; | |
1084 | channel->dpll_ctrl_n = DPLL_CTRL_0; | |
1085 | channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0; | |
1086 | break; | |
1087 | case 1: | |
1088 | channel->dpll_freq = DPLL_FREQ_1; | |
1089 | channel->dpll_n = DPLL_1; | |
1090 | channel->tod_read_primary = TOD_READ_PRIMARY_1; | |
1091 | channel->tod_write = TOD_WRITE_1; | |
1092 | channel->tod_n = TOD_1; | |
1093 | channel->hw_dpll_n = HW_DPLL_1; | |
1094 | channel->dpll_phase = DPLL_PHASE_1; | |
1095 | channel->dpll_ctrl_n = DPLL_CTRL_1; | |
1096 | channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1; | |
1097 | break; | |
1098 | case 2: | |
1099 | channel->dpll_freq = DPLL_FREQ_2; | |
1100 | channel->dpll_n = DPLL_2; | |
1101 | channel->tod_read_primary = TOD_READ_PRIMARY_2; | |
1102 | channel->tod_write = TOD_WRITE_2; | |
1103 | channel->tod_n = TOD_2; | |
1104 | channel->hw_dpll_n = HW_DPLL_2; | |
1105 | channel->dpll_phase = DPLL_PHASE_2; | |
1106 | channel->dpll_ctrl_n = DPLL_CTRL_2; | |
1107 | channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2; | |
1108 | break; | |
1109 | case 3: | |
1110 | channel->dpll_freq = DPLL_FREQ_3; | |
1111 | channel->dpll_n = DPLL_3; | |
1112 | channel->tod_read_primary = TOD_READ_PRIMARY_3; | |
1113 | channel->tod_write = TOD_WRITE_3; | |
1114 | channel->tod_n = TOD_3; | |
1115 | channel->hw_dpll_n = HW_DPLL_3; | |
1116 | channel->dpll_phase = DPLL_PHASE_3; | |
1117 | channel->dpll_ctrl_n = DPLL_CTRL_3; | |
1118 | channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3; | |
1119 | break; | |
1120 | default: | |
1121 | return -EINVAL; | |
1122 | } | |
1123 | ||
1124 | channel->idtcm = idtcm; | |
1125 | ||
1126 | channel->caps = idtcm_caps; | |
1127 | snprintf(channel->caps.name, sizeof(channel->caps.name), | |
1128 | "IDT CM PLL%u", index); | |
1129 | ||
1130 | err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY); | |
1131 | if (err) | |
1132 | return err; | |
1133 | ||
1134 | err = idtcm_enable_tod(channel); | |
1135 | if (err) | |
1136 | return err; | |
1137 | ||
1138 | channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); | |
1139 | ||
1140 | if (IS_ERR(channel->ptp_clock)) { | |
1141 | err = PTR_ERR(channel->ptp_clock); | |
1142 | channel->ptp_clock = NULL; | |
1143 | return err; | |
1144 | } | |
1145 | ||
1146 | if (!channel->ptp_clock) | |
1147 | return -ENOTSUPP; | |
1148 | ||
1149 | dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n", | |
1150 | index, channel->ptp_clock->index); | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | static void ptp_clock_unregister_all(struct idtcm *idtcm) | |
1156 | { | |
1157 | u8 i; | |
1158 | struct idtcm_channel *channel; | |
1159 | ||
1160 | for (i = 0; i < MAX_PHC_PLL; i++) { | |
1161 | ||
1162 | channel = &idtcm->channel[i]; | |
1163 | ||
1164 | if (channel->ptp_clock) | |
1165 | ptp_clock_unregister(channel->ptp_clock); | |
1166 | } | |
1167 | } | |
1168 | ||
1169 | static void set_default_masks(struct idtcm *idtcm) | |
1170 | { | |
1171 | idtcm->pll_mask = DEFAULT_PLL_MASK; | |
1172 | ||
1173 | idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; | |
1174 | idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; | |
1175 | idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2; | |
1176 | idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3; | |
1177 | } | |
1178 | ||
1179 | static int set_tod_write_overhead(struct idtcm *idtcm) | |
1180 | { | |
1181 | int err; | |
1182 | u8 i; | |
1183 | ||
1184 | s64 total_ns = 0; | |
1185 | ||
1186 | ktime_t start; | |
1187 | ktime_t stop; | |
1188 | ||
1189 | char buf[TOD_BYTE_COUNT]; | |
1190 | ||
1191 | struct idtcm_channel *channel = &idtcm->channel[2]; | |
1192 | ||
1193 | /* Set page offset */ | |
1194 | idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0, | |
1195 | buf, sizeof(buf)); | |
1196 | ||
1197 | for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) { | |
1198 | ||
1199 | start = ktime_get_raw(); | |
1200 | ||
1201 | err = idtcm_write(idtcm, channel->hw_dpll_n, | |
1202 | HW_DPLL_TOD_OVR__0, buf, sizeof(buf)); | |
1203 | ||
1204 | if (err) | |
1205 | return err; | |
1206 | ||
1207 | stop = ktime_get_raw(); | |
1208 | ||
1209 | total_ns += ktime_to_ns(stop - start); | |
1210 | } | |
1211 | ||
1212 | idtcm->tod_write_overhead_ns = div_s64(total_ns, | |
1213 | TOD_WRITE_OVERHEAD_COUNT_MAX); | |
1214 | ||
1215 | return err; | |
1216 | } | |
1217 | ||
1218 | static int idtcm_probe(struct i2c_client *client, | |
1219 | const struct i2c_device_id *id) | |
1220 | { | |
1221 | struct idtcm *idtcm; | |
1222 | int err; | |
1223 | u8 i; | |
1224 | ||
1225 | /* Unused for now */ | |
1226 | (void)id; | |
1227 | ||
1228 | idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL); | |
1229 | ||
1230 | if (!idtcm) | |
1231 | return -ENOMEM; | |
1232 | ||
1233 | idtcm->client = client; | |
1234 | idtcm->page_offset = 0xff; | |
1235 | idtcm->calculate_overhead_flag = 0; | |
1236 | ||
1237 | set_default_masks(idtcm); | |
1238 | ||
1239 | mutex_init(&idtcm->reg_lock); | |
1240 | mutex_lock(&idtcm->reg_lock); | |
1241 | ||
1242 | idtcm_display_version_info(idtcm); | |
1243 | ||
1244 | err = set_tod_write_overhead(idtcm); | |
1245 | ||
b97fa0b5 WY |
1246 | if (err) { |
1247 | mutex_unlock(&idtcm->reg_lock); | |
3a6ba7dc | 1248 | return err; |
b97fa0b5 | 1249 | } |
3a6ba7dc VC |
1250 | |
1251 | err = idtcm_load_firmware(idtcm, &client->dev); | |
1252 | ||
1253 | if (err) | |
1254 | dev_warn(&idtcm->client->dev, | |
1255 | "loading firmware failed with %d\n", err); | |
1256 | ||
1257 | if (idtcm->pll_mask) { | |
1258 | for (i = 0; i < MAX_PHC_PLL; i++) { | |
1259 | if (idtcm->pll_mask & (1 << i)) { | |
1260 | err = idtcm_enable_channel(idtcm, i); | |
1261 | if (err) | |
1262 | break; | |
1263 | } | |
1264 | } | |
1265 | } else { | |
1266 | dev_err(&idtcm->client->dev, | |
1267 | "no PLLs flagged as PHCs, nothing to do\n"); | |
1268 | err = -ENODEV; | |
1269 | } | |
1270 | ||
1271 | mutex_unlock(&idtcm->reg_lock); | |
1272 | ||
1273 | if (err) { | |
1274 | ptp_clock_unregister_all(idtcm); | |
1275 | return err; | |
1276 | } | |
1277 | ||
1278 | i2c_set_clientdata(client, idtcm); | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | static int idtcm_remove(struct i2c_client *client) | |
1284 | { | |
1285 | struct idtcm *idtcm = i2c_get_clientdata(client); | |
1286 | ||
1287 | ptp_clock_unregister_all(idtcm); | |
1288 | ||
1289 | mutex_destroy(&idtcm->reg_lock); | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | #ifdef CONFIG_OF | |
1295 | static const struct of_device_id idtcm_dt_id[] = { | |
1296 | { .compatible = "idt,8a34000" }, | |
1297 | { .compatible = "idt,8a34001" }, | |
1298 | { .compatible = "idt,8a34002" }, | |
1299 | { .compatible = "idt,8a34003" }, | |
1300 | { .compatible = "idt,8a34004" }, | |
1301 | { .compatible = "idt,8a34005" }, | |
1302 | { .compatible = "idt,8a34006" }, | |
1303 | { .compatible = "idt,8a34007" }, | |
1304 | { .compatible = "idt,8a34008" }, | |
1305 | { .compatible = "idt,8a34009" }, | |
1306 | { .compatible = "idt,8a34010" }, | |
1307 | { .compatible = "idt,8a34011" }, | |
1308 | { .compatible = "idt,8a34012" }, | |
1309 | { .compatible = "idt,8a34013" }, | |
1310 | { .compatible = "idt,8a34014" }, | |
1311 | { .compatible = "idt,8a34015" }, | |
1312 | { .compatible = "idt,8a34016" }, | |
1313 | { .compatible = "idt,8a34017" }, | |
1314 | { .compatible = "idt,8a34018" }, | |
1315 | { .compatible = "idt,8a34019" }, | |
1316 | { .compatible = "idt,8a34040" }, | |
1317 | { .compatible = "idt,8a34041" }, | |
1318 | { .compatible = "idt,8a34042" }, | |
1319 | { .compatible = "idt,8a34043" }, | |
1320 | { .compatible = "idt,8a34044" }, | |
1321 | { .compatible = "idt,8a34045" }, | |
1322 | { .compatible = "idt,8a34046" }, | |
1323 | { .compatible = "idt,8a34047" }, | |
1324 | { .compatible = "idt,8a34048" }, | |
1325 | { .compatible = "idt,8a34049" }, | |
1326 | {}, | |
1327 | }; | |
1328 | MODULE_DEVICE_TABLE(of, idtcm_dt_id); | |
1329 | #endif | |
1330 | ||
1331 | static const struct i2c_device_id idtcm_i2c_id[] = { | |
1332 | { "8a34000" }, | |
1333 | { "8a34001" }, | |
1334 | { "8a34002" }, | |
1335 | { "8a34003" }, | |
1336 | { "8a34004" }, | |
1337 | { "8a34005" }, | |
1338 | { "8a34006" }, | |
1339 | { "8a34007" }, | |
1340 | { "8a34008" }, | |
1341 | { "8a34009" }, | |
1342 | { "8a34010" }, | |
1343 | { "8a34011" }, | |
1344 | { "8a34012" }, | |
1345 | { "8a34013" }, | |
1346 | { "8a34014" }, | |
1347 | { "8a34015" }, | |
1348 | { "8a34016" }, | |
1349 | { "8a34017" }, | |
1350 | { "8a34018" }, | |
1351 | { "8a34019" }, | |
1352 | { "8a34040" }, | |
1353 | { "8a34041" }, | |
1354 | { "8a34042" }, | |
1355 | { "8a34043" }, | |
1356 | { "8a34044" }, | |
1357 | { "8a34045" }, | |
1358 | { "8a34046" }, | |
1359 | { "8a34047" }, | |
1360 | { "8a34048" }, | |
1361 | { "8a34049" }, | |
1362 | {}, | |
1363 | }; | |
1364 | MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id); | |
1365 | ||
1366 | static struct i2c_driver idtcm_driver = { | |
1367 | .driver = { | |
1368 | .of_match_table = of_match_ptr(idtcm_dt_id), | |
1369 | .name = "idtcm", | |
1370 | }, | |
1371 | .probe = idtcm_probe, | |
1372 | .remove = idtcm_remove, | |
1373 | .id_table = idtcm_i2c_id, | |
1374 | }; | |
1375 | ||
1376 | module_i2c_driver(idtcm_driver); |