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ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.
[linux-block.git] / drivers / ptp / ptp_clockmatrix.c
CommitLineData
3a6ba7dc
VC		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
5 *
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
7 */
8#include <linux/firmware.h>
9#include <linux/i2c.h>
10#include <linux/module.h>
11#include <linux/ptp_clock_kernel.h>
12#include <linux/delay.h>
425d2b1c 13#include <linux/jiffies.h>
3a6ba7dc
VC		 14#include <linux/kernel.h>
15#include <linux/timekeeping.h>
7ea5fda2 16#include <linux/string.h>
3a6ba7dc
VC		 17
18#include "ptp_private.h"
19#include "ptp_clockmatrix.h"
20
21MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
22MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
23MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
24MODULE_VERSION("1.0");
25MODULE_LICENSE("GPL");
26
7ea5fda2
ML		 27/*
28 * The name of the firmware file to be loaded
29 * over-rides any automatic selection
30 */
31static char *firmware;
32module_param(firmware, charp, 0);
33
3a6ba7dc
VC		 34#define SETTIME_CORRECTION (0)
35
251f4fe2
ML		 36static int contains_full_configuration(const struct firmware *fw)
37{
38 s32 full_count = FULL_FW_CFG_BYTES - FULL_FW_CFG_SKIPPED_BYTES;
39 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
40 s32 count = 0;
41 u16 regaddr;
42 u8 loaddr;
43 s32 len;
44
45 /* If the firmware contains 'full configuration' SM_RESET can be used
46 * to ensure proper configuration.
47 *
48 * Full configuration is defined as the number of programmable
49 * bytes within the configuration range minus page offset addr range.
50 */
51 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
52 regaddr = rec->hiaddr << 8;
53 regaddr |= rec->loaddr;
54
55 loaddr = rec->loaddr;
56
57 rec++;
58
59 /* Top (status registers) and bottom are read-only */
60 if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
61 continue;
62
63 /* Page size 128, last 4 bytes of page skipped */
64 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
65 continue;
66
67 count++;
68 }
69
70 return (count >= full_count);
71}
72
3a6ba7dc
VC		 73static int char_array_to_timespec(u8 *buf,
74 u8 count,
75 struct timespec64 *ts)
76{
77 u8 i;
78 u64 nsec;
79 time64_t sec;
80
81 if (count < TOD_BYTE_COUNT)
82 return 1;
83
84 /* Sub-nanoseconds are in buf[0]. */
85 nsec = buf[4];
86 for (i = 0; i < 3; i++) {
87 nsec <<= 8;
88 nsec |= buf[3 - i];
89 }
90
91 sec = buf[10];
92 for (i = 0; i < 5; i++) {
93 sec <<= 8;
94 sec |= buf[9 - i];
95 }
96
97 ts->tv_sec = sec;
98 ts->tv_nsec = nsec;
99
100 return 0;
101}
102
103static int timespec_to_char_array(struct timespec64 const *ts,
104 u8 *buf,
105 u8 count)
106{
107 u8 i;
108 s32 nsec;
109 time64_t sec;
110
111 if (count < TOD_BYTE_COUNT)
112 return 1;
113
114 nsec = ts->tv_nsec;
115 sec = ts->tv_sec;
116
117 /* Sub-nanoseconds are in buf[0]. */
118 buf[0] = 0;
119 for (i = 1; i < 5; i++) {
120 buf[i] = nsec & 0xff;
121 nsec >>= 8;
122 }
123
124 for (i = 5; i < TOD_BYTE_COUNT; i++) {
125
126 buf[i] = sec & 0xff;
127 sec >>= 8;
128 }
129
130 return 0;
131}
132
3cb2e6d9 133static int idtcm_strverscmp(const char *version1, const char *version2)
7ea5fda2 134{
3cb2e6d9
ML		 135 u8 ver1[3], ver2[3];
136 int i;
7ea5fda2 137
3cb2e6d9
ML		 138 if (sscanf(version1, "%hhu.%hhu.%hhu",
139 &ver1[0], &ver1[1], &ver1[2]) != 3)
140 return -1;
141 if (sscanf(version2, "%hhu.%hhu.%hhu",
142 &ver2[0], &ver2[1], &ver2[2]) != 3)
143 return -1;
7ea5fda2 144
3cb2e6d9
ML		 145 for (i = 0; i < 3; i++) {
146 if (ver1[i] > ver2[i])
147 return 1;
148 if (ver1[i] < ver2[i])
149 return -1;
7ea5fda2 150 }
3cb2e6d9
ML		 151
152 return 0;
7ea5fda2
ML		 153}
154
957ff427
ML		 155static int idtcm_xfer_read(struct idtcm *idtcm,
156 u8 regaddr,
157 u8 *buf,
158 u16 count)
3a6ba7dc
VC		 159{
160 struct i2c_client *client = idtcm->client;
161 struct i2c_msg msg[2];
162 int cnt;
957ff427 163 char *fmt = "i2c_transfer failed at %d in %s, at addr: %04X!\n";
3a6ba7dc
VC		 164
165 msg[0].addr = client->addr;
166 msg[0].flags = 0;
167 msg[0].len = 1;
168 msg[0].buf = &regaddr;
169
170 msg[1].addr = client->addr;
957ff427 171 msg[1].flags = I2C_M_RD;
3a6ba7dc
VC		 172 msg[1].len = count;
173 msg[1].buf = buf;
174
175 cnt = i2c_transfer(client->adapter, msg, 2);
176
177 if (cnt < 0) {
7ea5fda2
ML		 178 dev_err(&client->dev,
179 fmt,
180 __LINE__,
181 __func__,
7ea5fda2 182 regaddr);
3a6ba7dc
VC		 183 return cnt;
184 } else if (cnt != 2) {
185 dev_err(&client->dev,
186 "i2c_transfer sent only %d of %d messages\n", cnt, 2);
187 return -EIO;
188 }
189
190 return 0;
191}
192
957ff427
ML		 193static int idtcm_xfer_write(struct idtcm *idtcm,
194 u8 regaddr,
195 u8 *buf,
196 u16 count)
197{
198 struct i2c_client *client = idtcm->client;
199 /* we add 1 byte for device register */
200 u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
201 int cnt;
202 char *fmt = "i2c_master_send failed at %d in %s, at addr: %04X!\n";
203
204 if (count > IDTCM_MAX_WRITE_COUNT)
205 return -EINVAL;
206
207 msg[0] = regaddr;
208 memcpy(&msg[1], buf, count);
209
210 cnt = i2c_master_send(client, msg, count + 1);
211
212 if (cnt < 0) {
213 dev_err(&client->dev,
214 fmt,
215 __LINE__,
216 __func__,
217 regaddr);
218 return cnt;
219 }
220
221 return 0;
222}
223
3a6ba7dc
VC		 224static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
225{
226 u8 buf[4];
227 int err;
228
229 if (idtcm->page_offset == val)
230 return 0;
231
232 buf[0] = 0x0;
233 buf[1] = val;
234 buf[2] = 0x10;
235 buf[3] = 0x20;
236
957ff427 237 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
3a6ba7dc 238
7ea5fda2
ML		 239 if (err) {
240 idtcm->page_offset = 0xff;
3a6ba7dc 241 dev_err(&idtcm->client->dev, "failed to set page offset\n");
7ea5fda2 242 } else {
3a6ba7dc 243 idtcm->page_offset = val;
7ea5fda2 244 }
3a6ba7dc
VC		 245
246 return err;
247}
248
249static int _idtcm_rdwr(struct idtcm *idtcm,
250 u16 regaddr,
251 u8 *buf,
252 u16 count,
253 bool write)
254{
255 u8 hi;
256 u8 lo;
257 int err;
258
259 hi = (regaddr >> 8) & 0xff;
260 lo = regaddr & 0xff;
261
262 err = idtcm_page_offset(idtcm, hi);
263
264 if (err)
957ff427 265 return err;
3a6ba7dc 266
957ff427
ML		 267 if (write)
268 return idtcm_xfer_write(idtcm, lo, buf, count);
269
270 return idtcm_xfer_read(idtcm, lo, buf, count);
3a6ba7dc
VC		 271}
272
273static int idtcm_read(struct idtcm *idtcm,
274 u16 module,
275 u16 regaddr,
276 u8 *buf,
277 u16 count)
278{
279 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
280}
281
282static int idtcm_write(struct idtcm *idtcm,
283 u16 module,
284 u16 regaddr,
285 u8 *buf,
286 u16 count)
287{
288 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
289}
290
251f4fe2
ML		 291static int clear_boot_status(struct idtcm *idtcm)
292{
293 int err;
294 u8 buf[4] = {0};
295
296 err = idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
297
298 return err;
299}
300
301static int read_boot_status(struct idtcm *idtcm, u32 *status)
302{
303 int err;
304 u8 buf[4] = {0};
305
306 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
307
308 *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
309
310 return err;
311}
312
313static int wait_for_boot_status_ready(struct idtcm *idtcm)
314{
315 u32 status = 0;
316 u8 i = 30; /* 30 * 100ms = 3s */
317 int err;
318
319 do {
320 err = read_boot_status(idtcm, &status);
321
322 if (err)
323 return err;
324
325 if (status == 0xA0)
326 return 0;
327
328 msleep(100);
329 i--;
330
331 } while (i);
332
333 dev_warn(&idtcm->client->dev, "%s timed out\n", __func__);
334
335 return -EBUSY;
336}
337
797d3186
VC		 338static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
339{
340 return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
341 sizeof(u8));
342}
343
344static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
345{
346 return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
347}
348
349static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
350{
351 unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
352 u8 apll = 0;
353 u8 dpll = 0;
354 int err;
355
356 do {
357 err = read_sys_apll_status(idtcm, &apll);
358 if (err)
359 return err;
360
361 err = read_sys_dpll_status(idtcm, &dpll);
362 if (err)
363 return err;
364
365 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
366 dpll &= DPLL_SYS_STATE_MASK;
367
368 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
369 dpll == DPLL_STATE_LOCKED) {
370 return 0;
371 } else if (dpll == DPLL_STATE_FREERUN ||
372 dpll == DPLL_STATE_HOLDOVER ||
373 dpll == DPLL_STATE_OPEN_LOOP) {
374 dev_warn(&idtcm->client->dev,
375 "No wait state: DPLL_SYS_STATE %d", dpll);
376 return -EPERM;
377 }
378
379 msleep(LOCK_POLL_INTERVAL_MS);
380 } while (time_is_after_jiffies(timeout));
381
382 dev_warn(&idtcm->client->dev,
383 "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d",
384 LOCK_TIMEOUT_MS, apll, dpll);
385
386 return -ETIME;
387}
388
389static void wait_for_chip_ready(struct idtcm *idtcm)
390{
391 if (wait_for_boot_status_ready(idtcm))
392 dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0");
393
394 if (wait_for_sys_apll_dpll_lock(idtcm))
395 dev_warn(&idtcm->client->dev,
396 "Continuing while SYS APLL/DPLL is not locked");
397}
398
3a6ba7dc
VC		 399static int _idtcm_gettime(struct idtcm_channel *channel,
400 struct timespec64 *ts)
401{
402 struct idtcm *idtcm = channel->idtcm;
403 u8 buf[TOD_BYTE_COUNT];
7ea5fda2 404 u8 timeout = 10;
3a6ba7dc
VC		 405 u8 trigger;
406 int err;
407
408 err = idtcm_read(idtcm, channel->tod_read_primary,
409 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
410 if (err)
411 return err;
412
413 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
414 trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
7ea5fda2 415 trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
3a6ba7dc
VC		 416
417 err = idtcm_write(idtcm, channel->tod_read_primary,
418 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
3a6ba7dc
VC		 419 if (err)
420 return err;
421
7ea5fda2
ML		 422 /* wait trigger to be 0 */
423 while (trigger & TOD_READ_TRIGGER_MASK) {
424
425 if (idtcm->calculate_overhead_flag)
426 idtcm->start_time = ktime_get_raw();
427
428 err = idtcm_read(idtcm, channel->tod_read_primary,
429 TOD_READ_PRIMARY_CMD, &trigger,
430 sizeof(trigger));
431
432 if (err)
433 return err;
434
435 if (--timeout == 0)
436 return -EIO;
437 }
3a6ba7dc
VC		 438
439 err = idtcm_read(idtcm, channel->tod_read_primary,
440 TOD_READ_PRIMARY, buf, sizeof(buf));
441
442 if (err)
443 return err;
444
445 err = char_array_to_timespec(buf, sizeof(buf), ts);
446
447 return err;
448}
449
450static int _sync_pll_output(struct idtcm *idtcm,
451 u8 pll,
452 u8 sync_src,
453 u8 qn,
454 u8 qn_plus_1)
455{
456 int err;
457 u8 val;
458 u16 sync_ctrl0;
459 u16 sync_ctrl1;
7ea5fda2 460 u8 temp;
3a6ba7dc
VC		 461
462 if ((qn == 0) && (qn_plus_1 == 0))
463 return 0;
464
465 switch (pll) {
466 case 0:
467 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
468 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
469 break;
470 case 1:
471 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
472 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
473 break;
474 case 2:
475 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
476 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
477 break;
478 case 3:
479 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
480 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
481 break;
482 case 4:
483 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
484 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
485 break;
486 case 5:
487 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
488 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
489 break;
490 case 6:
491 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
492 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
493 break;
494 case 7:
495 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
496 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
497 break;
498 default:
499 return -EINVAL;
500 }
501
502 val = SYNCTRL1_MASTER_SYNC_RST;
503
504 /* Place master sync in reset */
505 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
506 if (err)
507 return err;
508
509 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
510 if (err)
511 return err;
512
513 /* Set sync trigger mask */
514 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
515
516 if (qn)
517 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
518
519 if (qn_plus_1)
520 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
521
522 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
523 if (err)
524 return err;
525
7ea5fda2
ML		 526 /* PLL5 can have OUT8 as second additional output. */
527 if ((pll == 5) && (qn_plus_1 != 0)) {
528 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
529 &temp, sizeof(temp));
530 if (err)
531 return err;
532
533 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
534
535 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
536 &temp, sizeof(temp));
537 if (err)
538 return err;
539
540 temp |= Q9_TO_Q8_SYNC_TRIG;
541
542 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
543 &temp, sizeof(temp));
544 if (err)
545 return err;
546 }
547
548 /* PLL6 can have OUT11 as second additional output. */
549 if ((pll == 6) && (qn_plus_1 != 0)) {
550 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
551 &temp, sizeof(temp));
552 if (err)
553 return err;
554
555 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
556
557 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
558 &temp, sizeof(temp));
559 if (err)
560 return err;
561
562 temp |= Q10_TO_Q11_SYNC_TRIG;
563
564 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
565 &temp, sizeof(temp));
566 if (err)
567 return err;
568 }
569
3a6ba7dc
VC		 570 /* Place master sync out of reset */
571 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
572 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
573
574 return err;
575}
576
7ea5fda2
ML		 577static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
578{
579 int err = 0;
580
581 switch (tod_addr) {
582 case TOD_0:
583 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
584 break;
585 case TOD_1:
586 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
587 break;
588 case TOD_2:
589 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
590 break;
591 case TOD_3:
592 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
593 break;
594 default:
595 err = -EINVAL;
596 }
597
598 return err;
599}
600
3a6ba7dc
VC		 601static int idtcm_sync_pps_output(struct idtcm_channel *channel)
602{
603 struct idtcm *idtcm = channel->idtcm;
604
605 u8 pll;
606 u8 sync_src;
607 u8 qn;
608 u8 qn_plus_1;
609 int err = 0;
7ea5fda2
ML		 610 u8 out8_mux = 0;
611 u8 out11_mux = 0;
612 u8 temp;
3a6ba7dc
VC		 613
614 u16 output_mask = channel->output_mask;
615
7ea5fda2
ML		 616 err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
617 if (err)
618 return err;
3a6ba7dc 619
7ea5fda2
ML		 620 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
621 &temp, sizeof(temp));
622 if (err)
623 return err;
624
625 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
626 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
627 out8_mux = 1;
628
629 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
630 &temp, sizeof(temp));
631 if (err)
632 return err;
633
634 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
635 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
636 out11_mux = 1;
3a6ba7dc 637
7ea5fda2
ML		 638 for (pll = 0; pll < 8; pll++) {
639 qn = 0;
640 qn_plus_1 = 0;
3a6ba7dc
VC		 641
642 if (pll < 4) {
643 /* First 4 pll has 2 outputs */
7ea5fda2
ML		 644 qn = output_mask & 0x1;
645 output_mask = output_mask >> 1;
3a6ba7dc
VC		 646 qn_plus_1 = output_mask & 0x1;
647 output_mask = output_mask >> 1;
7ea5fda2
ML		 648 } else if (pll == 4) {
649 if (out8_mux == 0) {
650 qn = output_mask & 0x1;
651 output_mask = output_mask >> 1;
652 }
653 } else if (pll == 5) {
654 if (out8_mux) {
655 qn_plus_1 = output_mask & 0x1;
656 output_mask = output_mask >> 1;
657 }
658 qn = output_mask & 0x1;
659 output_mask = output_mask >> 1;
660 } else if (pll == 6) {
661 qn = output_mask & 0x1;
662 output_mask = output_mask >> 1;
663 if (out11_mux) {
664 qn_plus_1 = output_mask & 0x1;
665 output_mask = output_mask >> 1;
666 }
667 } else if (pll == 7) {
668 if (out11_mux == 0) {
669 qn = output_mask & 0x1;
670 output_mask = output_mask >> 1;
671 }
3a6ba7dc
VC		 672 }
673
674 if ((qn != 0) || (qn_plus_1 != 0))
675 err = _sync_pll_output(idtcm, pll, sync_src, qn,
676 qn_plus_1);
677
678 if (err)
679 return err;
680 }
681
682 return err;
683}
684
7ea5fda2 685static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
3a6ba7dc
VC		 686 struct timespec64 const *ts,
687 enum hw_tod_write_trig_sel wr_trig)
688{
689 struct idtcm *idtcm = channel->idtcm;
690
691 u8 buf[TOD_BYTE_COUNT];
692 u8 cmd;
693 int err;
694 struct timespec64 local_ts = *ts;
695 s64 total_overhead_ns;
696
697 /* Configure HW TOD write trigger. */
698 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
699 &cmd, sizeof(cmd));
700
701 if (err)
702 return err;
703
704 cmd &= ~(0x0f);
705 cmd |= wr_trig | 0x08;
706
707 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
708 &cmd, sizeof(cmd));
709
710 if (err)
711 return err;
712
713 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
714
715 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
716
717 if (err)
718 return err;
719
720 err = idtcm_write(idtcm, channel->hw_dpll_n,
721 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
722
723 if (err)
724 return err;
725 }
726
727 /* ARM HW TOD write trigger. */
728 cmd &= ~(0x08);
729
730 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
731 &cmd, sizeof(cmd));
732
733 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
734
735 if (idtcm->calculate_overhead_flag) {
1ece2fbe 736 /* Assumption: I2C @ 400KHz */
7260d1c8
ML		 737 ktime_t diff = ktime_sub(ktime_get_raw(),
738 idtcm->start_time);
739 total_overhead_ns = ktime_to_ns(diff)
3a6ba7dc
VC		 740 + idtcm->tod_write_overhead_ns
741 + SETTIME_CORRECTION;
742
743 timespec64_add_ns(&local_ts, total_overhead_ns);
744
745 idtcm->calculate_overhead_flag = 0;
746 }
747
748 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
749
750 if (err)
751 return err;
752
753 err = idtcm_write(idtcm, channel->hw_dpll_n,
754 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
755 }
756
757 return err;
758}
759
7ea5fda2
ML		 760static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
761 struct timespec64 const *ts,
762 enum scsr_tod_write_trig_sel wr_trig,
763 enum scsr_tod_write_type_sel wr_type)
764{
765 struct idtcm *idtcm = channel->idtcm;
766 unsigned char buf[TOD_BYTE_COUNT], cmd;
767 struct timespec64 local_ts = *ts;
768 int err, count = 0;
769
770 timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
771
772 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
773
774 if (err)
775 return err;
776
777 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
778 buf, sizeof(buf));
779 if (err)
780 return err;
781
782 /* Trigger the write operation. */
783 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
784 &cmd, sizeof(cmd));
785 if (err)
786 return err;
787
788 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
789 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
790 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
791 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
792
793 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
794 &cmd, sizeof(cmd));
795 if (err)
796 return err;
797
798 /* Wait for the operation to complete. */
799 while (1) {
800 /* pps trigger takes up to 1 sec to complete */
801 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
802 msleep(50);
803
804 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
805 &cmd, sizeof(cmd));
806 if (err)
807 return err;
808
251f4fe2 809 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
7ea5fda2
ML		 810 break;
811
812 if (++count > 20) {
813 dev_err(&idtcm->client->dev,
814 "Timed out waiting for the write counter\n");
815 return -EIO;
816 }
817 }
818
819 return 0;
820}
821
7260d1c8
ML		 822static int get_output_base_addr(u8 outn)
823{
824 int base;
825
826 switch (outn) {
827 case 0:
828 base = OUTPUT_0;
829 break;
830 case 1:
831 base = OUTPUT_1;
832 break;
833 case 2:
834 base = OUTPUT_2;
835 break;
836 case 3:
837 base = OUTPUT_3;
838 break;
839 case 4:
840 base = OUTPUT_4;
841 break;
842 case 5:
843 base = OUTPUT_5;
844 break;
845 case 6:
846 base = OUTPUT_6;
847 break;
848 case 7:
849 base = OUTPUT_7;
850 break;
851 case 8:
852 base = OUTPUT_8;
853 break;
854 case 9:
855 base = OUTPUT_9;
856 break;
857 case 10:
858 base = OUTPUT_10;
859 break;
860 case 11:
861 base = OUTPUT_11;
862 break;
863 default:
864 base = -EINVAL;
865 }
866
867 return base;
868}
869
da948233
ML		 870static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
871 struct timespec64 const *ts)
3a6ba7dc
VC		 872{
873 struct idtcm *idtcm = channel->idtcm;
3a6ba7dc 874 int err;
3a6ba7dc 875
251f4fe2 876 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
3a6ba7dc 877
7ea5fda2
ML		 878 if (err) {
879 dev_err(&idtcm->client->dev,
251f4fe2 880 "%s: Set HW ToD failed\n", __func__);
3a6ba7dc 881 return err;
7ea5fda2 882 }
3a6ba7dc 883
7ea5fda2
ML		 884 return idtcm_sync_pps_output(channel);
885}
3a6ba7dc 886
da948233
ML		 887static int _idtcm_settime(struct idtcm_channel *channel,
888 struct timespec64 const *ts,
889 enum scsr_tod_write_type_sel wr_type)
7ea5fda2
ML		 890{
891 return _idtcm_set_dpll_scsr_tod(channel, ts,
892 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
893 wr_type);
3a6ba7dc
VC		 894}
895
896static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
897 s32 offset_ns)
898{
899 int err;
900 int i;
901 struct idtcm *idtcm = channel->idtcm;
902
903 u8 buf[4];
904
905 for (i = 0; i < 4; i++) {
906 buf[i] = 0xff & (offset_ns);
907 offset_ns >>= 8;
908 }
909
910 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
911 buf, sizeof(buf));
912
913 return err;
914}
915
916static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
917 u32 max_ffo_ppb)
918{
919 int err;
920 u8 i;
921 struct idtcm *idtcm = channel->idtcm;
922
923 u8 buf[3];
924
925 if (max_ffo_ppb & 0xff000000)
926 max_ffo_ppb = 0;
927
928 for (i = 0; i < 3; i++) {
929 buf[i] = 0xff & (max_ffo_ppb);
930 max_ffo_ppb >>= 8;
931 }
932
933 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
934 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
935
936 return err;
937}
938
939static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
940{
941 int err;
942 struct idtcm *idtcm = channel->idtcm;
943
944 u8 buf;
945
946 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
947 &buf, sizeof(buf));
948
949 if (err)
950 return err;
951
952 if (buf == 0) {
953 buf = 0x01;
954 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
955 PULL_IN_CTRL, &buf, sizeof(buf));
956 } else {
957 err = -EBUSY;
958 }
959
960 return err;
961}
962
963static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
964 s32 offset_ns,
965 u32 max_ffo_ppb)
966{
967 int err;
968
969 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
970
971 if (err)
972 return err;
973
974 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
975
976 if (err)
977 return err;
978
979 err = idtcm_start_phase_pull_in(channel);
980
981 return err;
982}
983
7ea5fda2
ML		 984static int set_tod_write_overhead(struct idtcm_channel *channel)
985{
986 struct idtcm *idtcm = channel->idtcm;
987 s64 current_ns = 0;
988 s64 lowest_ns = 0;
989 int err;
990 u8 i;
991
992 ktime_t start;
993 ktime_t stop;
7260d1c8 994 ktime_t diff;
7ea5fda2
ML		 995
996 char buf[TOD_BYTE_COUNT] = {0};
997
998 /* Set page offset */
999 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
1000 buf, sizeof(buf));
1001
1002 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
1003
1004 start = ktime_get_raw();
1005
1006 err = idtcm_write(idtcm, channel->hw_dpll_n,
1007 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
1008
1009 if (err)
1010 return err;
1011
1012 stop = ktime_get_raw();
1013
7260d1c8
ML		 1014 diff = ktime_sub(stop, start);
1015
1016 current_ns = ktime_to_ns(diff);
7ea5fda2
ML		 1017
1018 if (i == 0) {
1019 lowest_ns = current_ns;
1020 } else {
1021 if (current_ns < lowest_ns)
1022 lowest_ns = current_ns;
1023 }
1024 }
1025
1026 idtcm->tod_write_overhead_ns = lowest_ns;
1027
1028 return err;
1029}
1030
da948233 1031static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
3a6ba7dc
VC		 1032{
1033 int err;
1034 struct idtcm *idtcm = channel->idtcm;
1035 struct timespec64 ts;
1036 s64 now;
1037
da948233 1038 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
3a6ba7dc
VC		 1039 err = idtcm_do_phase_pull_in(channel, delta, 0);
1040 } else {
1041 idtcm->calculate_overhead_flag = 1;
1042
7ea5fda2
ML		 1043 err = set_tod_write_overhead(channel);
1044
1045 if (err)
1046 return err;
1047
3a6ba7dc
VC		 1048 err = _idtcm_gettime(channel, &ts);
1049
1050 if (err)
1051 return err;
1052
1053 now = timespec64_to_ns(&ts);
1054 now += delta;
1055
1056 ts = ns_to_timespec64(now);
1057
da948233 1058 err = _idtcm_settime_deprecated(channel, &ts);
3a6ba7dc
VC		 1059 }
1060
1061 return err;
1062}
1063
1064static int idtcm_state_machine_reset(struct idtcm *idtcm)
1065{
3a6ba7dc 1066 u8 byte = SM_RESET_CMD;
251f4fe2
ML		 1067 u32 status = 0;
1068 int err;
1069 u8 i;
1070
1071 clear_boot_status(idtcm);
3a6ba7dc
VC		 1072
1073 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
1074
251f4fe2
ML		 1075 if (!err) {
1076 for (i = 0; i < 30; i++) {
1077 msleep_interruptible(100);
1078 read_boot_status(idtcm, &status);
1079
1080 if (status == 0xA0) {
1081 dev_dbg(&idtcm->client->dev,
1082 "SM_RESET completed in %d ms\n",
1083 i * 100);
1084 break;
1085 }
1086 }
1087
1088 if (!status)
1089 dev_err(&idtcm->client->dev, "Timed out waiting for CM_RESET to complete\n");
1090 }
3a6ba7dc
VC		 1091
1092 return err;
1093}
1094
1095static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1096{
1ece2fbe 1097 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
3a6ba7dc
VC		 1098}
1099
1100static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1101{
1102 int err;
1103 u8 buf[2] = {0};
1104
1105 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1106
1107 *product_id = (buf[1] << 8) | buf[0];
1108
1109 return err;
1110}
1111
1112static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1113{
1114 int err;
1115 u8 buf = 0;
1116
1117 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1118
1119 *major = buf >> 1;
1120
1121 return err;
1122}
1123
1124static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1125{
1126 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1127}
1128
1129static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1130{
1131 return idtcm_read(idtcm,
1132 GENERAL_STATUS,
1133 HOTFIX_REL,
1134 hotfix,
1135 sizeof(u8));
1136}
1137
1ece2fbe
VC		 1138static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1139 u8 *config_select)
3a6ba7dc 1140{
1ece2fbe
VC		 1141 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1142 config_select, sizeof(u8));
3a6ba7dc
VC		 1143}
1144
3a6ba7dc
VC		 1145static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1146{
1147 int err = 0;
1148
1149 switch (addr) {
7ea5fda2 1150 case TOD0_OUT_ALIGN_MASK_ADDR:
3a6ba7dc
VC		 1151 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1152 break;
7ea5fda2 1153 case TOD0_OUT_ALIGN_MASK_ADDR + 1:
3a6ba7dc
VC		 1154 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1155 break;
7ea5fda2 1156 case TOD1_OUT_ALIGN_MASK_ADDR:
3a6ba7dc
VC		 1157 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1158 break;
7ea5fda2 1159 case TOD1_OUT_ALIGN_MASK_ADDR + 1:
3a6ba7dc
VC		 1160 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1161 break;
7ea5fda2 1162 case TOD2_OUT_ALIGN_MASK_ADDR:
3a6ba7dc
VC		 1163 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1164 break;
7ea5fda2 1165 case TOD2_OUT_ALIGN_MASK_ADDR + 1:
3a6ba7dc
VC		 1166 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1167 break;
7ea5fda2 1168 case TOD3_OUT_ALIGN_MASK_ADDR:
3a6ba7dc
VC		 1169 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1170 break;
7ea5fda2 1171 case TOD3_OUT_ALIGN_MASK_ADDR + 1:
3a6ba7dc
VC		 1172 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1173 break;
1174 default:
7ea5fda2 1175 err = -EFAULT; /* Bad address */;
3a6ba7dc
VC		 1176 break;
1177 }
1178
1179 return err;
1180}
1181
7ea5fda2
ML		 1182static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1183{
1184 if (index >= MAX_TOD) {
1185 dev_err(&idtcm->client->dev, "ToD%d not supported\n", index);
1186 return -EINVAL;
1187 }
1188
1189 if (pll >= MAX_PLL) {
1190 dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll);
1191 return -EINVAL;
1192 }
1193
1194 idtcm->channel[index].pll = pll;
1195
1196 return 0;
1197}
1198
3a6ba7dc
VC		 1199static int check_and_set_masks(struct idtcm *idtcm,
1200 u16 regaddr,
1201 u8 val)
1202{
1203 int err = 0;
1204
7ea5fda2
ML		 1205 switch (regaddr) {
1206 case TOD_MASK_ADDR:
1207 if ((val & 0xf0) || !(val & 0x0f)) {
1208 dev_err(&idtcm->client->dev,
1209 "Invalid TOD mask 0x%hhx\n", val);
1210 err = -EINVAL;
1211 } else {
1212 idtcm->tod_mask = val;
1213 }
1214 break;
1215 case TOD0_PTP_PLL_ADDR:
1216 err = set_tod_ptp_pll(idtcm, 0, val);
1217 break;
1218 case TOD1_PTP_PLL_ADDR:
1219 err = set_tod_ptp_pll(idtcm, 1, val);
1220 break;
1221 case TOD2_PTP_PLL_ADDR:
1222 err = set_tod_ptp_pll(idtcm, 2, val);
1223 break;
1224 case TOD3_PTP_PLL_ADDR:
1225 err = set_tod_ptp_pll(idtcm, 3, val);
1226 break;
1227 default:
1228 err = set_pll_output_mask(idtcm, regaddr, val);
1229 break;
3a6ba7dc
VC		 1230 }
1231
1232 return err;
1233}
1234
7ea5fda2 1235static void display_pll_and_masks(struct idtcm *idtcm)
3a6ba7dc
VC		 1236{
1237 u8 i;
1238 u8 mask;
1239
7ea5fda2 1240 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask);
3a6ba7dc 1241
7ea5fda2 1242 for (i = 0; i < MAX_TOD; i++) {
3a6ba7dc
VC		 1243 mask = 1 << i;
1244
7ea5fda2 1245 if (mask & idtcm->tod_mask)
3a6ba7dc 1246 dev_dbg(&idtcm->client->dev,
7ea5fda2
ML		 1247 "TOD%d pll = %d output_mask = 0x%04x\n",
1248 i, idtcm->channel[i].pll,
1249 idtcm->channel[i].output_mask);
3a6ba7dc
VC		 1250 }
1251}
1252
1253static int idtcm_load_firmware(struct idtcm *idtcm,
1254 struct device *dev)
1255{
7ea5fda2 1256 char fname[128] = FW_FILENAME;
3a6ba7dc
VC		 1257 const struct firmware *fw;
1258 struct idtcm_fwrc *rec;
1259 u32 regaddr;
1260 int err;
1261 s32 len;
1262 u8 val;
1263 u8 loaddr;
1264
7ea5fda2
ML		 1265 if (firmware) /* module parameter */
1266 snprintf(fname, sizeof(fname), "%s", firmware);
3a6ba7dc 1267
7ea5fda2 1268 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname);
3a6ba7dc 1269
7ea5fda2
ML		 1270 err = request_firmware(&fw, fname, dev);
1271
1272 if (err) {
1273 dev_err(&idtcm->client->dev,
1274 "Failed at line %d in func %s!\n",
1275 __LINE__,
1276 __func__);
3a6ba7dc 1277 return err;
7ea5fda2 1278 }
3a6ba7dc
VC		 1279
1280 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
1281
1282 rec = (struct idtcm_fwrc *) fw->data;
1283
251f4fe2 1284 if (contains_full_configuration(fw))
3a6ba7dc
VC		 1285 idtcm_state_machine_reset(idtcm);
1286
1287 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1288
1289 if (rec->reserved) {
1290 dev_err(&idtcm->client->dev,
1291 "bad firmware, reserved field non-zero\n");
1292 err = -EINVAL;
1293 } else {
1294 regaddr = rec->hiaddr << 8;
1295 regaddr |= rec->loaddr;
1296
1297 val = rec->value;
1298 loaddr = rec->loaddr;
1299
1300 rec++;
1301
1302 err = check_and_set_masks(idtcm, regaddr, val);
1303 }
1304
7ea5fda2
ML		 1305 if (err != -EINVAL) {
1306 err = 0;
1307
3a6ba7dc
VC		 1308 /* Top (status registers) and bottom are read-only */
1309 if ((regaddr < GPIO_USER_CONTROL)
1310 || (regaddr >= SCRATCH))
1311 continue;
1312
1313 /* Page size 128, last 4 bytes of page skipped */
1314 if (((loaddr > 0x7b) && (loaddr <= 0x7f))
3e14462f 1315 || loaddr > 0xfb)
3a6ba7dc
VC		 1316 continue;
1317
1318 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1319 }
1320
1321 if (err)
1322 goto out;
1323 }
1324
7ea5fda2 1325 display_pll_and_masks(idtcm);
3a6ba7dc
VC		 1326
1327out:
1328 release_firmware(fw);
1329 return err;
1330}
1331
7ea5fda2
ML		 1332static int idtcm_output_enable(struct idtcm_channel *channel,
1333 bool enable, unsigned int outn)
3a6ba7dc
VC		 1334{
1335 struct idtcm *idtcm = channel->idtcm;
7260d1c8 1336 int base;
3a6ba7dc 1337 int err;
7ea5fda2 1338 u8 val;
3a6ba7dc 1339
7260d1c8
ML		 1340 base = get_output_base_addr(outn);
1341
1342 if (!(base > 0)) {
1343 dev_err(&idtcm->client->dev,
1344 "%s - Unsupported out%d", __func__, outn);
1345 return base;
1346 }
1347
1348 err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
3a6ba7dc
VC		 1349
1350 if (err)
1351 return err;
1352
1353 if (enable)
1354 val |= SQUELCH_DISABLE;
1355 else
1356 val &= ~SQUELCH_DISABLE;
1357
7260d1c8 1358 return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
7ea5fda2 1359}
3a6ba7dc 1360
7ea5fda2
ML		 1361static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1362 bool enable)
1363{
1364 u16 mask;
1365 int err;
1366 u8 outn;
1367
1368 mask = channel->output_mask;
1369 outn = 0;
1370
1371 while (mask) {
1372
1373 if (mask & 0x1) {
1374
1375 err = idtcm_output_enable(channel, enable, outn);
1376
1377 if (err)
1378 return err;
1379 }
1380
1381 mask >>= 0x1;
1382 outn++;
1383 }
3a6ba7dc
VC		 1384
1385 return 0;
1386}
1387
7ea5fda2
ML		 1388static int idtcm_perout_enable(struct idtcm_channel *channel,
1389 bool enable,
1390 struct ptp_perout_request *perout)
1391{
1392 unsigned int flags = perout->flags;
1393
1394 if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1395 return idtcm_output_mask_enable(channel, enable);
1396
1397 /* Enable/disable individual output instead */
1398 return idtcm_output_enable(channel, enable, perout->index);
1399}
1400
7260d1c8
ML		 1401static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1402 enum pll_mode *pll_mode)
1403{
1404 struct idtcm *idtcm = channel->idtcm;
1405 int err;
1406 u8 dpll_mode;
1407
1408 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1409 &dpll_mode, sizeof(dpll_mode));
1410 if (err)
1411 return err;
1412
1413 *pll_mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1414
1415 return 0;
1416}
1417
3a6ba7dc
VC		 1418static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1419 enum pll_mode pll_mode)
1420{
1421 struct idtcm *idtcm = channel->idtcm;
1422 int err;
1423 u8 dpll_mode;
1424
1425 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1426 &dpll_mode, sizeof(dpll_mode));
1427 if (err)
1428 return err;
1429
1430 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1431
1432 dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1433
1434 channel->pll_mode = pll_mode;
1435
1436 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1437 &dpll_mode, sizeof(dpll_mode));
1438 if (err)
1439 return err;
1440
1441 return 0;
1442}
1443
1444/* PTP Hardware Clock interface */
1445
425d2b1c
VC		 1446/**
1447 * @brief Maximum absolute value for write phase offset in picoseconds
1448 *
1449 * Destination signed register is 32-bit register in resolution of 50ps
1450 *
1451 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1452 */
1453static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1454{
1455 struct idtcm *idtcm = channel->idtcm;
1456
1457 int err;
1458 u8 i;
1459 u8 buf[4] = {0};
1460 s32 phase_50ps;
1461 s64 offset_ps;
1462
1463 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1464
1465 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1466
1467 if (err)
1468 return err;
425d2b1c
VC		 1469 }
1470
425d2b1c
VC		 1471 offset_ps = (s64)delta_ns * 1000;
1472
1473 /*
1474 * Check for 32-bit signed max * 50:
1475 *
1476 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1477 */
1478 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1479 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1480 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1481 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1482
7260d1c8 1483 phase_50ps = div_s64(offset_ps, 50);
425d2b1c
VC		 1484
1485 for (i = 0; i < 4; i++) {
1486 buf[i] = phase_50ps & 0xff;
1487 phase_50ps >>= 8;
1488 }
1489
1490 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1491 buf, sizeof(buf));
1492
1493 return err;
1494}
1495
7ea5fda2 1496static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
3a6ba7dc 1497{
3a6ba7dc
VC		 1498 struct idtcm *idtcm = channel->idtcm;
1499 u8 i;
3a6ba7dc
VC		 1500 int err;
1501 u8 buf[6] = {0};
1502 s64 fcw;
1503
1504 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
1505 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1506 if (err)
1507 return err;
1508 }
1509
1510 /*
1511 * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1512 *
1513 * adjfreq:
1514 * ppb * 10^9
1515 * FCW = ----------
1516 * 111
1517 *
1518 * adjfine:
1519 * ppm_16 * 5^12
1520 * FCW = -------------
1521 * 111 * 2^4
1522 */
3a6ba7dc
VC		 1523
1524 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
7ea5fda2 1525 fcw = scaled_ppm * 244140625ULL;
3a6ba7dc 1526
7260d1c8 1527 fcw = div_s64(fcw, 1776);
3a6ba7dc
VC		 1528
1529 for (i = 0; i < 6; i++) {
1530 buf[i] = fcw & 0xff;
1531 fcw >>= 8;
1532 }
1533
3a6ba7dc
VC		 1534 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1535 buf, sizeof(buf));
1536
3a6ba7dc
VC		 1537 return err;
1538}
1539
1540static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1541{
1542 struct idtcm_channel *channel =
1543 container_of(ptp, struct idtcm_channel, caps);
1544 struct idtcm *idtcm = channel->idtcm;
1545 int err;
1546
1547 mutex_lock(&idtcm->reg_lock);
1548
1549 err = _idtcm_gettime(channel, ts);
1550
7ea5fda2
ML		 1551 if (err)
1552 dev_err(&idtcm->client->dev,
1553 "Failed at line %d in func %s!\n",
1554 __LINE__,
1555 __func__);
1556
3a6ba7dc
VC		 1557 mutex_unlock(&idtcm->reg_lock);
1558
1559 return err;
1560}
1561
da948233
ML		 1562static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1563 const struct timespec64 *ts)
3a6ba7dc
VC		 1564{
1565 struct idtcm_channel *channel =
1566 container_of(ptp, struct idtcm_channel, caps);
1567 struct idtcm *idtcm = channel->idtcm;
1568 int err;
1569
1570 mutex_lock(&idtcm->reg_lock);
1571
da948233 1572 err = _idtcm_settime_deprecated(channel, ts);
3a6ba7dc 1573
7ea5fda2
ML		 1574 if (err)
1575 dev_err(&idtcm->client->dev,
1576 "Failed at line %d in func %s!\n",
1577 __LINE__,
1578 __func__);
1579
3a6ba7dc
VC		 1580 mutex_unlock(&idtcm->reg_lock);
1581
1582 return err;
1583}
1584
da948233 1585static int idtcm_settime(struct ptp_clock_info *ptp,
7ea5fda2 1586 const struct timespec64 *ts)
3a6ba7dc
VC		 1587{
1588 struct idtcm_channel *channel =
1589 container_of(ptp, struct idtcm_channel, caps);
1590 struct idtcm *idtcm = channel->idtcm;
1591 int err;
1592
1593 mutex_lock(&idtcm->reg_lock);
1594
da948233 1595 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
7ea5fda2
ML		 1596
1597 if (err)
1598 dev_err(&idtcm->client->dev,
1599 "Failed at line %d in func %s!\n",
1600 __LINE__,
1601 __func__);
3a6ba7dc
VC		 1602
1603 mutex_unlock(&idtcm->reg_lock);
1604
1605 return err;
1606}
1607
da948233 1608static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
7ea5fda2
ML		 1609{
1610 struct idtcm_channel *channel =
1611 container_of(ptp, struct idtcm_channel, caps);
1612 struct idtcm *idtcm = channel->idtcm;
1613 int err;
1614
1615 mutex_lock(&idtcm->reg_lock);
1616
da948233 1617 err = _idtcm_adjtime_deprecated(channel, delta);
7ea5fda2
ML		 1618
1619 if (err)
1620 dev_err(&idtcm->client->dev,
1621 "Failed at line %d in func %s!\n",
1622 __LINE__,
1623 __func__);
1624
1625 mutex_unlock(&idtcm->reg_lock);
1626
1627 return err;
1628}
1629
da948233 1630static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
7ea5fda2
ML		 1631{
1632 struct idtcm_channel *channel =
1633 container_of(ptp, struct idtcm_channel, caps);
1634 struct idtcm *idtcm = channel->idtcm;
1635 struct timespec64 ts;
1636 enum scsr_tod_write_type_sel type;
1637 int err;
1638
da948233 1639 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
7ea5fda2
ML		 1640 err = idtcm_do_phase_pull_in(channel, delta, 0);
1641 if (err)
1642 dev_err(&idtcm->client->dev,
1643 "Failed at line %d in func %s!\n",
1644 __LINE__,
1645 __func__);
1646 return err;
1647 }
1648
1649 if (delta >= 0) {
1650 ts = ns_to_timespec64(delta);
1651 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1652 } else {
1653 ts = ns_to_timespec64(-delta);
1654 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1655 }
1656
1657 mutex_lock(&idtcm->reg_lock);
1658
da948233 1659 err = _idtcm_settime(channel, &ts, type);
7ea5fda2
ML		 1660
1661 if (err)
1662 dev_err(&idtcm->client->dev,
1663 "Failed at line %d in func %s!\n",
1664 __LINE__,
1665 __func__);
1666
1667 mutex_unlock(&idtcm->reg_lock);
1668
1669 return err;
1670}
1671
1672static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
425d2b1c
VC		 1673{
1674 struct idtcm_channel *channel =
1675 container_of(ptp, struct idtcm_channel, caps);
1676
1677 struct idtcm *idtcm = channel->idtcm;
1678
1679 int err;
1680
1681 mutex_lock(&idtcm->reg_lock);
1682
1683 err = _idtcm_adjphase(channel, delta);
1684
7ea5fda2
ML		 1685 if (err)
1686 dev_err(&idtcm->client->dev,
1687 "Failed at line %d in func %s!\n",
1688 __LINE__,
1689 __func__);
1690
1691 mutex_unlock(&idtcm->reg_lock);
1692
1693 return err;
1694}
1695
1696static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1697{
1698 struct idtcm_channel *channel =
1699 container_of(ptp, struct idtcm_channel, caps);
1700
1701 struct idtcm *idtcm = channel->idtcm;
1702
1703 int err;
1704
1705 mutex_lock(&idtcm->reg_lock);
1706
1707 err = _idtcm_adjfine(channel, scaled_ppm);
1708
1709 if (err)
1710 dev_err(&idtcm->client->dev,
1711 "Failed at line %d in func %s!\n",
1712 __LINE__,
1713 __func__);
1714
425d2b1c
VC		 1715 mutex_unlock(&idtcm->reg_lock);
1716
1717 return err;
1718}
1719
3a6ba7dc
VC		 1720static int idtcm_enable(struct ptp_clock_info *ptp,
1721 struct ptp_clock_request *rq, int on)
1722{
7ea5fda2
ML		 1723 int err;
1724
3a6ba7dc
VC		 1725 struct idtcm_channel *channel =
1726 container_of(ptp, struct idtcm_channel, caps);
1727
1728 switch (rq->type) {
1729 case PTP_CLK_REQ_PEROUT:
7ea5fda2
ML		 1730 if (!on) {
1731 err = idtcm_perout_enable(channel, false, &rq->perout);
1732 if (err)
1733 dev_err(&channel->idtcm->client->dev,
1734 "Failed at line %d in func %s!\n",
1735 __LINE__,
1736 __func__);
1737 return err;
1738 }
3a6ba7dc
VC		 1739
1740 /* Only accept a 1-PPS aligned to the second. */
1741 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1742 rq->perout.period.nsec)
1743 return -ERANGE;
1744
7ea5fda2
ML		 1745 err = idtcm_perout_enable(channel, true, &rq->perout);
1746 if (err)
1747 dev_err(&channel->idtcm->client->dev,
1748 "Failed at line %d in func %s!\n",
1749 __LINE__,
1750 __func__);
1751 return err;
3a6ba7dc
VC		 1752 default:
1753 break;
1754 }
1755
1756 return -EOPNOTSUPP;
1757}
1758
7ea5fda2
ML		 1759static int _enable_pll_tod_sync(struct idtcm *idtcm,
1760 u8 pll,
1761 u8 sync_src,
1762 u8 qn,
1763 u8 qn_plus_1)
1764{
1765 int err;
1766 u8 val;
1767 u16 dpll;
1768 u16 out0 = 0, out1 = 0;
1769
1770 if ((qn == 0) && (qn_plus_1 == 0))
1771 return 0;
1772
1773 switch (pll) {
1774 case 0:
1775 dpll = DPLL_0;
1776 if (qn)
1777 out0 = OUTPUT_0;
1778 if (qn_plus_1)
1779 out1 = OUTPUT_1;
1780 break;
1781 case 1:
1782 dpll = DPLL_1;
1783 if (qn)
1784 out0 = OUTPUT_2;
1785 if (qn_plus_1)
1786 out1 = OUTPUT_3;
1787 break;
1788 case 2:
1789 dpll = DPLL_2;
1790 if (qn)
1791 out0 = OUTPUT_4;
1792 if (qn_plus_1)
1793 out1 = OUTPUT_5;
1794 break;
1795 case 3:
1796 dpll = DPLL_3;
1797 if (qn)
1798 out0 = OUTPUT_6;
1799 if (qn_plus_1)
1800 out1 = OUTPUT_7;
1801 break;
1802 case 4:
1803 dpll = DPLL_4;
1804 if (qn)
1805 out0 = OUTPUT_8;
1806 break;
1807 case 5:
1808 dpll = DPLL_5;
1809 if (qn)
1810 out0 = OUTPUT_9;
1811 if (qn_plus_1)
1812 out1 = OUTPUT_8;
1813 break;
1814 case 6:
1815 dpll = DPLL_6;
1816 if (qn)
1817 out0 = OUTPUT_10;
1818 if (qn_plus_1)
1819 out1 = OUTPUT_11;
1820 break;
1821 case 7:
1822 dpll = DPLL_7;
1823 if (qn)
1824 out0 = OUTPUT_11;
1825 break;
1826 default:
1827 return -EINVAL;
1828 }
1829
1830 /*
1831 * Enable OUTPUT OUT_SYNC.
1832 */
1833 if (out0) {
1834 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1835
1836 if (err)
1837 return err;
1838
1839 val &= ~OUT_SYNC_DISABLE;
1840
1841 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1842
1843 if (err)
1844 return err;
1845 }
1846
1847 if (out1) {
1848 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1849
1850 if (err)
1851 return err;
1852
1853 val &= ~OUT_SYNC_DISABLE;
1854
1855 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1856
1857 if (err)
1858 return err;
1859 }
1860
1861 /* enable dpll sync tod pps, must be set before dpll_mode */
1862 err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1863 if (err)
1864 return err;
1865
1866 val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1867 val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1868 val |= TOD_SYNC_EN;
1869
1870 return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1871}
1872
1873static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
3a6ba7dc
VC		 1874{
1875 struct idtcm *idtcm = channel->idtcm;
7ea5fda2
ML		 1876
1877 u8 pll;
1878 u8 sync_src;
1879 u8 qn;
1880 u8 qn_plus_1;
3a6ba7dc 1881 u8 cfg;
7ea5fda2
ML		 1882 int err = 0;
1883 u16 output_mask = channel->output_mask;
1884 u8 out8_mux = 0;
1885 u8 out11_mux = 0;
1886 u8 temp;
3a6ba7dc 1887
7ea5fda2
ML		 1888 /*
1889 * set tod_out_sync_enable to 0.
1890 */
1891 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
3a6ba7dc
VC		 1892 if (err)
1893 return err;
1894
7ea5fda2
ML		 1895 cfg &= ~TOD_OUT_SYNC_ENABLE;
1896
1897 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1898 if (err)
1899 return err;
1900
1901 switch (channel->tod_n) {
1902 case TOD_0:
1903 sync_src = 0;
1904 break;
1905 case TOD_1:
1906 sync_src = 1;
1907 break;
1908 case TOD_2:
1909 sync_src = 2;
1910 break;
1911 case TOD_3:
1912 sync_src = 3;
1913 break;
1914 default:
1915 return -EINVAL;
1916 }
1917
1918 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
1919 &temp, sizeof(temp));
1920 if (err)
1921 return err;
1922
1923 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1924 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1925 out8_mux = 1;
1926
1927 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
1928 &temp, sizeof(temp));
1929 if (err)
1930 return err;
1931
1932 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1933 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1934 out11_mux = 1;
1935
1936 for (pll = 0; pll < 8; pll++) {
1937 qn = 0;
1938 qn_plus_1 = 0;
1939
1940 if (pll < 4) {
1941 /* First 4 pll has 2 outputs */
1942 qn = output_mask & 0x1;
1943 output_mask = output_mask >> 1;
1944 qn_plus_1 = output_mask & 0x1;
1945 output_mask = output_mask >> 1;
1946 } else if (pll == 4) {
1947 if (out8_mux == 0) {
1948 qn = output_mask & 0x1;
1949 output_mask = output_mask >> 1;
1950 }
1951 } else if (pll == 5) {
1952 if (out8_mux) {
1953 qn_plus_1 = output_mask & 0x1;
1954 output_mask = output_mask >> 1;
1955 }
1956 qn = output_mask & 0x1;
1957 output_mask = output_mask >> 1;
1958 } else if (pll == 6) {
1959 qn = output_mask & 0x1;
1960 output_mask = output_mask >> 1;
1961 if (out11_mux) {
1962 qn_plus_1 = output_mask & 0x1;
1963 output_mask = output_mask >> 1;
1964 }
1965 } else if (pll == 7) {
1966 if (out11_mux == 0) {
1967 qn = output_mask & 0x1;
1968 output_mask = output_mask >> 1;
1969 }
1970 }
1971
1972 if ((qn != 0) || (qn_plus_1 != 0))
1973 err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1974 qn_plus_1);
1975
1976 if (err)
1977 return err;
1978 }
1979
1980 return err;
1981}
1982
1983static int idtcm_enable_tod(struct idtcm_channel *channel)
1984{
1985 struct idtcm *idtcm = channel->idtcm;
1986 struct timespec64 ts = {0, 0};
1987 u8 cfg;
1988 int err;
1989
3a6ba7dc
VC		 1990 /*
1991 * Start the TOD clock ticking.
1992 */
1993 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1994 if (err)
1995 return err;
1996
1997 cfg |= TOD_ENABLE;
1998
1999 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
2000 if (err)
2001 return err;
2002
da948233
ML		 2003 if (idtcm->deprecated)
2004 return _idtcm_settime_deprecated(channel, &ts);
2005 else
2006 return _idtcm_settime(channel, &ts,
2007 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
3a6ba7dc
VC		 2008}
2009
da948233 2010static void idtcm_set_version_info(struct idtcm *idtcm)
3a6ba7dc
VC		 2011{
2012 u8 major;
2013 u8 minor;
2014 u8 hotfix;
3a6ba7dc 2015 u16 product_id;
3a6ba7dc 2016 u8 hw_rev_id;
1ece2fbe
VC		 2017 u8 config_select;
2018 char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n";
3a6ba7dc
VC		 2019
2020 idtcm_read_major_release(idtcm, &major);
2021 idtcm_read_minor_release(idtcm, &minor);
2022 idtcm_read_hotfix_release(idtcm, &hotfix);
3a6ba7dc
VC		 2023
2024 idtcm_read_product_id(idtcm, &product_id);
2025 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1ece2fbe
VC		 2026
2027 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
2028
7ea5fda2
ML		 2029 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
2030 major, minor, hotfix);
2031
da948233
ML		 2032 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
2033 idtcm->deprecated = 0;
2034 else
2035 idtcm->deprecated = 1;
2036
1ece2fbe
VC		 2037 dev_info(&idtcm->client->dev, fmt, major, minor, hotfix,
2038 product_id, hw_rev_id, config_select);
3a6ba7dc
VC		 2039}
2040
da948233 2041static const struct ptp_clock_info idtcm_caps = {
7ea5fda2
ML		 2042 .owner = THIS_MODULE,
2043 .max_adj = 244000,
2044 .n_per_out = 12,
2045 .adjphase = &idtcm_adjphase,
2046 .adjfine = &idtcm_adjfine,
da948233 2047 .adjtime = &idtcm_adjtime,
7ea5fda2 2048 .gettime64 = &idtcm_gettime,
da948233 2049 .settime64 = &idtcm_settime,
7ea5fda2 2050 .enable = &idtcm_enable,
7ea5fda2
ML		 2051};
2052
da948233 2053static const struct ptp_clock_info idtcm_caps_deprecated = {
3a6ba7dc
VC		 2054 .owner = THIS_MODULE,
2055 .max_adj = 244000,
7ea5fda2 2056 .n_per_out = 12,
425d2b1c 2057 .adjphase = &idtcm_adjphase,
7ea5fda2 2058 .adjfine = &idtcm_adjfine,
da948233 2059 .adjtime = &idtcm_adjtime_deprecated,
3a6ba7dc 2060 .gettime64 = &idtcm_gettime,
da948233 2061 .settime64 = &idtcm_settime_deprecated,
3a6ba7dc
VC		 2062 .enable = &idtcm_enable,
2063};
2064
7ea5fda2 2065static int configure_channel_pll(struct idtcm_channel *channel)
3a6ba7dc 2066{
7ea5fda2 2067 int err = 0;
3a6ba7dc 2068
7ea5fda2 2069 switch (channel->pll) {
3a6ba7dc
VC		 2070 case 0:
2071 channel->dpll_freq = DPLL_FREQ_0;
2072 channel->dpll_n = DPLL_0;
3a6ba7dc
VC		 2073 channel->hw_dpll_n = HW_DPLL_0;
2074 channel->dpll_phase = DPLL_PHASE_0;
2075 channel->dpll_ctrl_n = DPLL_CTRL_0;
2076 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
2077 break;
2078 case 1:
2079 channel->dpll_freq = DPLL_FREQ_1;
2080 channel->dpll_n = DPLL_1;
3a6ba7dc
VC		 2081 channel->hw_dpll_n = HW_DPLL_1;
2082 channel->dpll_phase = DPLL_PHASE_1;
2083 channel->dpll_ctrl_n = DPLL_CTRL_1;
2084 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
2085 break;
2086 case 2:
2087 channel->dpll_freq = DPLL_FREQ_2;
2088 channel->dpll_n = DPLL_2;
3a6ba7dc
VC		 2089 channel->hw_dpll_n = HW_DPLL_2;
2090 channel->dpll_phase = DPLL_PHASE_2;
2091 channel->dpll_ctrl_n = DPLL_CTRL_2;
2092 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2093 break;
2094 case 3:
2095 channel->dpll_freq = DPLL_FREQ_3;
2096 channel->dpll_n = DPLL_3;
3a6ba7dc
VC		 2097 channel->hw_dpll_n = HW_DPLL_3;
2098 channel->dpll_phase = DPLL_PHASE_3;
2099 channel->dpll_ctrl_n = DPLL_CTRL_3;
2100 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2101 break;
7ea5fda2
ML		 2102 case 4:
2103 channel->dpll_freq = DPLL_FREQ_4;
2104 channel->dpll_n = DPLL_4;
2105 channel->hw_dpll_n = HW_DPLL_4;
2106 channel->dpll_phase = DPLL_PHASE_4;
2107 channel->dpll_ctrl_n = DPLL_CTRL_4;
2108 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2109 break;
2110 case 5:
2111 channel->dpll_freq = DPLL_FREQ_5;
2112 channel->dpll_n = DPLL_5;
2113 channel->hw_dpll_n = HW_DPLL_5;
2114 channel->dpll_phase = DPLL_PHASE_5;
2115 channel->dpll_ctrl_n = DPLL_CTRL_5;
2116 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2117 break;
2118 case 6:
2119 channel->dpll_freq = DPLL_FREQ_6;
2120 channel->dpll_n = DPLL_6;
2121 channel->hw_dpll_n = HW_DPLL_6;
2122 channel->dpll_phase = DPLL_PHASE_6;
2123 channel->dpll_ctrl_n = DPLL_CTRL_6;
2124 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2125 break;
2126 case 7:
2127 channel->dpll_freq = DPLL_FREQ_7;
2128 channel->dpll_n = DPLL_7;
2129 channel->hw_dpll_n = HW_DPLL_7;
2130 channel->dpll_phase = DPLL_PHASE_7;
2131 channel->dpll_ctrl_n = DPLL_CTRL_7;
2132 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2133 break;
2134 default:
2135 err = -EINVAL;
2136 }
2137
2138 return err;
2139}
2140
2141static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2142{
2143 struct idtcm_channel *channel;
2144 int err;
2145
2146 if (!(index < MAX_TOD))
2147 return -EINVAL;
2148
2149 channel = &idtcm->channel[index];
2150
2151 /* Set pll addresses */
2152 err = configure_channel_pll(channel);
2153 if (err)
2154 return err;
2155
2156 /* Set tod addresses */
2157 switch (index) {
2158 case 0:
2159 channel->tod_read_primary = TOD_READ_PRIMARY_0;
2160 channel->tod_write = TOD_WRITE_0;
2161 channel->tod_n = TOD_0;
2162 break;
2163 case 1:
2164 channel->tod_read_primary = TOD_READ_PRIMARY_1;
2165 channel->tod_write = TOD_WRITE_1;
2166 channel->tod_n = TOD_1;
2167 break;
2168 case 2:
2169 channel->tod_read_primary = TOD_READ_PRIMARY_2;
2170 channel->tod_write = TOD_WRITE_2;
2171 channel->tod_n = TOD_2;
2172 break;
2173 case 3:
2174 channel->tod_read_primary = TOD_READ_PRIMARY_3;
2175 channel->tod_write = TOD_WRITE_3;
2176 channel->tod_n = TOD_3;
2177 break;
3a6ba7dc
VC		 2178 default:
2179 return -EINVAL;
2180 }
2181
2182 channel->idtcm = idtcm;
2183
da948233
ML		 2184 if (idtcm->deprecated)
2185 channel->caps = idtcm_caps_deprecated;
7ea5fda2
ML		 2186 else
2187 channel->caps = idtcm_caps;
2188
3a6ba7dc 2189 snprintf(channel->caps.name, sizeof(channel->caps.name),
7ea5fda2
ML		 2190 "IDT CM TOD%u", index);
2191
da948233 2192 if (!idtcm->deprecated) {
7ea5fda2
ML		 2193 err = idtcm_enable_tod_sync(channel);
2194 if (err) {
2195 dev_err(&idtcm->client->dev,
2196 "Failed at line %d in func %s!\n",
2197 __LINE__,
2198 __func__);
2199 return err;
2200 }
2201 }
3a6ba7dc 2202
7260d1c8
ML		 2203 /* Sync pll mode with hardware */
2204 err = idtcm_get_pll_mode(channel, &channel->pll_mode);
7ea5fda2
ML		 2205 if (err) {
2206 dev_err(&idtcm->client->dev,
7260d1c8 2207 "Error: %s - Unable to read pll mode\n", __func__);
3a6ba7dc 2208 return err;
7ea5fda2 2209 }
3a6ba7dc
VC		 2210
2211 err = idtcm_enable_tod(channel);
7ea5fda2
ML		 2212 if (err) {
2213 dev_err(&idtcm->client->dev,
2214 "Failed at line %d in func %s!\n",
2215 __LINE__,
2216 __func__);
3a6ba7dc 2217 return err;
7ea5fda2 2218 }
3a6ba7dc
VC		 2219
2220 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2221
2222 if (IS_ERR(channel->ptp_clock)) {
2223 err = PTR_ERR(channel->ptp_clock);
2224 channel->ptp_clock = NULL;
2225 return err;
2226 }
2227
2228 if (!channel->ptp_clock)
2229 return -ENOTSUPP;
2230
2231 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
2232 index, channel->ptp_clock->index);
2233
2234 return 0;
2235}
2236
2237static void ptp_clock_unregister_all(struct idtcm *idtcm)
2238{
2239 u8 i;
2240 struct idtcm_channel *channel;
2241
7ea5fda2 2242 for (i = 0; i < MAX_TOD; i++) {
3a6ba7dc
VC		 2243
2244 channel = &idtcm->channel[i];
2245
2246 if (channel->ptp_clock)
2247 ptp_clock_unregister(channel->ptp_clock);
2248 }
2249}
2250
2251static void set_default_masks(struct idtcm *idtcm)
2252{
7ea5fda2
ML		 2253 idtcm->tod_mask = DEFAULT_TOD_MASK;
2254
2255 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2256 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2257 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2258 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
3a6ba7dc
VC		 2259
2260 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2261 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2262 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2263 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2264}
2265
3a6ba7dc
VC		 2266static int idtcm_probe(struct i2c_client *client,
2267 const struct i2c_device_id *id)
2268{
2269 struct idtcm *idtcm;
2270 int err;
2271 u8 i;
7ea5fda2 2272 char *fmt = "Failed at %d in line %s with channel output %d!\n";
3a6ba7dc
VC		 2273
2274 /* Unused for now */
2275 (void)id;
2276
2277 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2278
2279 if (!idtcm)
2280 return -ENOMEM;
2281
2282 idtcm->client = client;
2283 idtcm->page_offset = 0xff;
2284 idtcm->calculate_overhead_flag = 0;
2285
2286 set_default_masks(idtcm);
2287
2288 mutex_init(&idtcm->reg_lock);
2289 mutex_lock(&idtcm->reg_lock);
2290
da948233 2291 idtcm_set_version_info(idtcm);
3a6ba7dc 2292
3a6ba7dc
VC		 2293 err = idtcm_load_firmware(idtcm, &client->dev);
2294
2295 if (err)
2296 dev_warn(&idtcm->client->dev,
2297 "loading firmware failed with %d\n", err);
2298
797d3186 2299 wait_for_chip_ready(idtcm);
251f4fe2 2300
7ea5fda2
ML		 2301 if (idtcm->tod_mask) {
2302 for (i = 0; i < MAX_TOD; i++) {
2303 if (idtcm->tod_mask & (1 << i)) {
3a6ba7dc 2304 err = idtcm_enable_channel(idtcm, i);
7ea5fda2
ML		 2305 if (err) {
2306 dev_err(&idtcm->client->dev,
2307 fmt,
2308 __LINE__,
2309 __func__,
2310 i);
3a6ba7dc 2311 break;
7ea5fda2 2312 }
3a6ba7dc
VC		 2313 }
2314 }
2315 } else {
2316 dev_err(&idtcm->client->dev,
2317 "no PLLs flagged as PHCs, nothing to do\n");
2318 err = -ENODEV;
2319 }
2320
2321 mutex_unlock(&idtcm->reg_lock);
2322
2323 if (err) {
2324 ptp_clock_unregister_all(idtcm);
2325 return err;
2326 }
2327
2328 i2c_set_clientdata(client, idtcm);
2329
2330 return 0;
2331}
2332
2333static int idtcm_remove(struct i2c_client *client)
2334{
2335 struct idtcm *idtcm = i2c_get_clientdata(client);
2336
2337 ptp_clock_unregister_all(idtcm);
2338
2339 mutex_destroy(&idtcm->reg_lock);
2340
2341 return 0;
2342}
2343
2344#ifdef CONFIG_OF
2345static const struct of_device_id idtcm_dt_id[] = {
2346 { .compatible = "idt,8a34000" },
2347 { .compatible = "idt,8a34001" },
2348 { .compatible = "idt,8a34002" },
2349 { .compatible = "idt,8a34003" },
2350 { .compatible = "idt,8a34004" },
2351 { .compatible = "idt,8a34005" },
2352 { .compatible = "idt,8a34006" },
2353 { .compatible = "idt,8a34007" },
2354 { .compatible = "idt,8a34008" },
2355 { .compatible = "idt,8a34009" },
2356 { .compatible = "idt,8a34010" },
2357 { .compatible = "idt,8a34011" },
2358 { .compatible = "idt,8a34012" },
2359 { .compatible = "idt,8a34013" },
2360 { .compatible = "idt,8a34014" },
2361 { .compatible = "idt,8a34015" },
2362 { .compatible = "idt,8a34016" },
2363 { .compatible = "idt,8a34017" },
2364 { .compatible = "idt,8a34018" },
2365 { .compatible = "idt,8a34019" },
2366 { .compatible = "idt,8a34040" },
2367 { .compatible = "idt,8a34041" },
2368 { .compatible = "idt,8a34042" },
2369 { .compatible = "idt,8a34043" },
2370 { .compatible = "idt,8a34044" },
2371 { .compatible = "idt,8a34045" },
2372 { .compatible = "idt,8a34046" },
2373 { .compatible = "idt,8a34047" },
2374 { .compatible = "idt,8a34048" },
2375 { .compatible = "idt,8a34049" },
2376 {},
2377};
2378MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2379#endif
2380
2381static const struct i2c_device_id idtcm_i2c_id[] = {
2382 { "8a34000" },
2383 { "8a34001" },
2384 { "8a34002" },
2385 { "8a34003" },
2386 { "8a34004" },
2387 { "8a34005" },
2388 { "8a34006" },
2389 { "8a34007" },
2390 { "8a34008" },
2391 { "8a34009" },
2392 { "8a34010" },
2393 { "8a34011" },
2394 { "8a34012" },
2395 { "8a34013" },
2396 { "8a34014" },
2397 { "8a34015" },
2398 { "8a34016" },
2399 { "8a34017" },
2400 { "8a34018" },
2401 { "8a34019" },
2402 { "8a34040" },
2403 { "8a34041" },
2404 { "8a34042" },
2405 { "8a34043" },
2406 { "8a34044" },
2407 { "8a34045" },
2408 { "8a34046" },
2409 { "8a34047" },
2410 { "8a34048" },
2411 { "8a34049" },
2412 {},
2413};
2414MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2415
2416static struct i2c_driver idtcm_driver = {
2417 .driver = {
2418 .of_match_table = of_match_ptr(idtcm_dt_id),
2419 .name = "idtcm",
2420 },
2421 .probe = idtcm_probe,
2422 .remove = idtcm_remove,
2423 .id_table = idtcm_i2c_id,
2424};
2425
2426module_i2c_driver(idtcm_driver);
Linux 6.x block layer and io_uring tree(s)