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[linux-block.git] / drivers / ptp / ptp_clockmatrix.c
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3a6ba7dc
VC		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
5 *
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
7 */
8#include <linux/firmware.h>
930dfa56 9#include <linux/platform_device.h>
3a6ba7dc
VC		 10#include <linux/module.h>
11#include <linux/ptp_clock_kernel.h>
12#include <linux/delay.h>
425d2b1c 13#include <linux/jiffies.h>
3a6ba7dc
VC		 14#include <linux/kernel.h>
15#include <linux/timekeeping.h>
7ea5fda2 16#include <linux/string.h>
930dfa56
ML		 17#include <linux/of.h>
18#include <linux/mfd/rsmu.h>
19#include <linux/mfd/idt8a340_reg.h>
20#include <asm/unaligned.h>
3a6ba7dc
VC		 21
22#include "ptp_private.h"
23#include "ptp_clockmatrix.h"
24
25MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
26MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
27MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
28MODULE_VERSION("1.0");
29MODULE_LICENSE("GPL");
30
7ea5fda2
ML		 31/*
32 * The name of the firmware file to be loaded
33 * over-rides any automatic selection
34 */
35static char *firmware;
36module_param(firmware, charp, 0);
37
3a6ba7dc 38#define SETTIME_CORRECTION (0)
930dfa56 39#define EXTTS_PERIOD_MS (95)
3a6ba7dc 40
da9facf1
ML		 41static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
42
930dfa56
ML		 43static inline int idtcm_read(struct idtcm *idtcm,
44 u16 module,
45 u16 regaddr,
46 u8 *buf,
47 u16 count)
48{
49 return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count);
50}
51
52static inline int idtcm_write(struct idtcm *idtcm,
53 u16 module,
54 u16 regaddr,
55 u8 *buf,
56 u16 count)
57{
58 return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count);
59}
60
794c3dff
ML		 61static int contains_full_configuration(struct idtcm *idtcm,
62 const struct firmware *fw)
251f4fe2 63{
251f4fe2 64 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
794c3dff
ML		 65 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
66 s32 full_count;
251f4fe2
ML		 67 s32 count = 0;
68 u16 regaddr;
69 u8 loaddr;
70 s32 len;
71
794c3dff
ML		 72 /* 4 bytes skipped every 0x80 */
73 full_count = (scratch - GPIO_USER_CONTROL) -
74 ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4;
75
251f4fe2
ML		 76 /* If the firmware contains 'full configuration' SM_RESET can be used
77 * to ensure proper configuration.
78 *
79 * Full configuration is defined as the number of programmable
80 * bytes within the configuration range minus page offset addr range.
81 */
82 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
83 regaddr = rec->hiaddr << 8;
84 regaddr |= rec->loaddr;
85
86 loaddr = rec->loaddr;
87
88 rec++;
89
90 /* Top (status registers) and bottom are read-only */
794c3dff 91 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
251f4fe2
ML		 92 continue;
93
94 /* Page size 128, last 4 bytes of page skipped */
95 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
96 continue;
97
98 count++;
99 }
100
101 return (count >= full_count);
102}
103
3a6ba7dc
VC		 104static int char_array_to_timespec(u8 *buf,
105 u8 count,
106 struct timespec64 *ts)
107{
108 u8 i;
109 u64 nsec;
110 time64_t sec;
111
112 if (count < TOD_BYTE_COUNT)
113 return 1;
114
115 /* Sub-nanoseconds are in buf[0]. */
116 nsec = buf[4];
117 for (i = 0; i < 3; i++) {
118 nsec <<= 8;
119 nsec |= buf[3 - i];
120 }
121
122 sec = buf[10];
123 for (i = 0; i < 5; i++) {
124 sec <<= 8;
125 sec |= buf[9 - i];
126 }
127
128 ts->tv_sec = sec;
129 ts->tv_nsec = nsec;
130
131 return 0;
132}
133
134static int timespec_to_char_array(struct timespec64 const *ts,
135 u8 *buf,
136 u8 count)
137{
138 u8 i;
139 s32 nsec;
140 time64_t sec;
141
142 if (count < TOD_BYTE_COUNT)
143 return 1;
144
145 nsec = ts->tv_nsec;
146 sec = ts->tv_sec;
147
148 /* Sub-nanoseconds are in buf[0]. */
149 buf[0] = 0;
150 for (i = 1; i < 5; i++) {
151 buf[i] = nsec & 0xff;
152 nsec >>= 8;
153 }
154
155 for (i = 5; i < TOD_BYTE_COUNT; i++) {
156
157 buf[i] = sec & 0xff;
158 sec >>= 8;
159 }
160
161 return 0;
162}
163
3cb2e6d9 164static int idtcm_strverscmp(const char *version1, const char *version2)
7ea5fda2 165{
3cb2e6d9
ML		 166 u8 ver1[3], ver2[3];
167 int i;
7ea5fda2 168
3cb2e6d9
ML		 169 if (sscanf(version1, "%hhu.%hhu.%hhu",
170 &ver1[0], &ver1[1], &ver1[2]) != 3)
171 return -1;
172 if (sscanf(version2, "%hhu.%hhu.%hhu",
173 &ver2[0], &ver2[1], &ver2[2]) != 3)
174 return -1;
7ea5fda2 175
3cb2e6d9
ML		 176 for (i = 0; i < 3; i++) {
177 if (ver1[i] > ver2[i])
178 return 1;
179 if (ver1[i] < ver2[i])
180 return -1;
7ea5fda2 181 }
3cb2e6d9
ML		 182
183 return 0;
7ea5fda2
ML		 184}
185
794c3dff
ML		 186static enum fw_version idtcm_fw_version(const char *version)
187{
188 enum fw_version ver = V_DEFAULT;
189
190 if (idtcm_strverscmp(version, "4.8.7") >= 0)
191 ver = V487;
192
193 if (idtcm_strverscmp(version, "5.2.0") >= 0)
194 ver = V520;
195
196 return ver;
197}
198
251f4fe2
ML		 199static int clear_boot_status(struct idtcm *idtcm)
200{
251f4fe2
ML		 201 u8 buf[4] = {0};
202
fde3b3a7 203 return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
251f4fe2
ML		 204}
205
206static int read_boot_status(struct idtcm *idtcm, u32 *status)
207{
208 int err;
209 u8 buf[4] = {0};
210
211 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
212
213 *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
214
215 return err;
216}
217
218static int wait_for_boot_status_ready(struct idtcm *idtcm)
219{
220 u32 status = 0;
221 u8 i = 30; /* 30 * 100ms = 3s */
222 int err;
223
224 do {
225 err = read_boot_status(idtcm, &status);
251f4fe2
ML		 226 if (err)
227 return err;
228
229 if (status == 0xA0)
230 return 0;
231
232 msleep(100);
233 i--;
234
235 } while (i);
236
930dfa56 237 dev_warn(idtcm->dev, "%s timed out", __func__);
251f4fe2
ML		 238
239 return -EBUSY;
240}
241
bec67592 242static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)
930dfa56
ML		 243{
244 struct idtcm *idtcm = channel->idtcm;
bec67592
ML		 245 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
246 u8 val = 0;
930dfa56
ML		 247 int err;
248
bec67592
ML		 249 val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
250 val |= (ref << WR_REF_INDEX_SHIFT);
930dfa56 251
bec67592
ML		 252 err = idtcm_write(idtcm, channel->tod_read_secondary,
253 TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val));
930dfa56
ML		 254 if (err)
255 return err;
256
bec67592
ML		 257 val = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT);
258
259 err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
260 &val, sizeof(val));
261 if (err)
262 dev_err(idtcm->dev, "%s: err = %d", __func__, err);
930dfa56 263
930dfa56
ML		 264 return err;
265}
266
bec67592 267static bool is_single_shot(u8 mask)
930dfa56 268{
bec67592 269 /* Treat single bit ToD masks as continuous trigger */
d0bbe032 270 return !(mask <= 8 && is_power_of_2(mask));
bec67592
ML		 271}
272
273static int idtcm_extts_enable(struct idtcm_channel *channel,
274 struct ptp_clock_request *rq, int on)
275{
276 u8 index = rq->extts.index;
277 struct idtcm *idtcm;
278 u8 mask = 1 << index;
930dfa56 279 int err = 0;
bec67592
ML		 280 u8 old_mask;
281 int ref;
282
283 idtcm = channel->idtcm;
284 old_mask = idtcm->extts_mask;
930dfa56 285
bec67592
ML		 286 /* Reject requests with unsupported flags */
287 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
288 PTP_RISING_EDGE |
289 PTP_FALLING_EDGE |
290 PTP_STRICT_FLAGS))
291 return -EOPNOTSUPP;
292
293 /* Reject requests to enable time stamping on falling edge */
294 if ((rq->extts.flags & PTP_ENABLE_FEATURE) &&
295 (rq->extts.flags & PTP_FALLING_EDGE))
296 return -EOPNOTSUPP;
297
298 if (index >= MAX_TOD)
930dfa56
ML		 299 return -EINVAL;
300
bec67592
ML		 301 if (on) {
302 /* Support triggering more than one TOD_0/1/2/3 by same pin */
303 /* Use the pin configured for the channel */
304 ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod);
305
306 if (ref < 0) {
307 dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n",
308 __func__, channel->tod);
309 return -EBUSY;
310 }
311
312 err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
313
930dfa56
ML		 314 if (err == 0) {
315 idtcm->extts_mask |= mask;
bec67592
ML		 316 idtcm->event_channel[index] = channel;
317 idtcm->channel[index].refn = ref;
318 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
319
320 if (old_mask)
321 return 0;
322
323 schedule_delayed_work(&idtcm->extts_work,
324 msecs_to_jiffies(EXTTS_PERIOD_MS));
930dfa56 325 }
bec67592 326 } else {
930dfa56 327 idtcm->extts_mask &= ~mask;
bec67592 328 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
930dfa56 329
bec67592
ML		 330 if (idtcm->extts_mask == 0)
331 cancel_delayed_work(&idtcm->extts_work);
332 }
930dfa56
ML		 333
334 return err;
335}
336
797d3186
VC		 337static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
338{
339 return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
340 sizeof(u8));
341}
342
343static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
344{
345 return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
346}
347
348static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
349{
350 unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
351 u8 apll = 0;
352 u8 dpll = 0;
353 int err;
354
355 do {
356 err = read_sys_apll_status(idtcm, &apll);
357 if (err)
358 return err;
359
360 err = read_sys_dpll_status(idtcm, &dpll);
361 if (err)
362 return err;
363
364 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
365 dpll &= DPLL_SYS_STATE_MASK;
366
794c3dff
ML		 367 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
368 dpll == DPLL_STATE_LOCKED) {
797d3186
VC		 369 return 0;
370 } else if (dpll == DPLL_STATE_FREERUN ||
371 dpll == DPLL_STATE_HOLDOVER ||
372 dpll == DPLL_STATE_OPEN_LOOP) {
930dfa56 373 dev_warn(idtcm->dev,
797d3186
VC		 374 "No wait state: DPLL_SYS_STATE %d", dpll);
375 return -EPERM;
376 }
377
378 msleep(LOCK_POLL_INTERVAL_MS);
379 } while (time_is_after_jiffies(timeout));
380
930dfa56 381 dev_warn(idtcm->dev,
797d3186
VC		 382 "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d",
383 LOCK_TIMEOUT_MS, apll, dpll);
384
385 return -ETIME;
386}
387
388static void wait_for_chip_ready(struct idtcm *idtcm)
389{
390 if (wait_for_boot_status_ready(idtcm))
930dfa56 391 dev_warn(idtcm->dev, "BOOT_STATUS != 0xA0");
797d3186
VC		 392
393 if (wait_for_sys_apll_dpll_lock(idtcm))
930dfa56 394 dev_warn(idtcm->dev,
797d3186
VC		 395 "Continuing while SYS APLL/DPLL is not locked");
396}
397
bec67592
ML		 398static int _idtcm_gettime_triggered(struct idtcm_channel *channel,
399 struct timespec64 *ts)
400{
401 struct idtcm *idtcm = channel->idtcm;
402 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
403 u8 buf[TOD_BYTE_COUNT];
404 u8 trigger;
405 int err;
406
407 err = idtcm_read(idtcm, channel->tod_read_secondary,
408 tod_read_cmd, &trigger, sizeof(trigger));
409 if (err)
410 return err;
411
412 if (trigger & TOD_READ_TRIGGER_MASK)
413 return -EBUSY;
414
415 err = idtcm_read(idtcm, channel->tod_read_secondary,
416 TOD_READ_SECONDARY_BASE, buf, sizeof(buf));
417 if (err)
418 return err;
419
420 return char_array_to_timespec(buf, sizeof(buf), ts);
421}
422
3a6ba7dc 423static int _idtcm_gettime(struct idtcm_channel *channel,
930dfa56 424 struct timespec64 *ts, u8 timeout)
3a6ba7dc
VC		 425{
426 struct idtcm *idtcm = channel->idtcm;
794c3dff 427 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
3a6ba7dc
VC		 428 u8 buf[TOD_BYTE_COUNT];
429 u8 trigger;
430 int err;
431
7ea5fda2 432 /* wait trigger to be 0 */
930dfa56
ML		 433 do {
434 if (timeout-- == 0)
435 return -EIO;
436
7ea5fda2
ML		 437 if (idtcm->calculate_overhead_flag)
438 idtcm->start_time = ktime_get_raw();
439
440 err = idtcm_read(idtcm, channel->tod_read_primary,
794c3dff 441 tod_read_cmd, &trigger,
7ea5fda2 442 sizeof(trigger));
7ea5fda2
ML		 443 if (err)
444 return err;
930dfa56 445 } while (trigger & TOD_READ_TRIGGER_MASK);
3a6ba7dc
VC		 446
447 err = idtcm_read(idtcm, channel->tod_read_primary,
bec67592 448 TOD_READ_PRIMARY_BASE, buf, sizeof(buf));
3a6ba7dc
VC		 449 if (err)
450 return err;
451
452 err = char_array_to_timespec(buf, sizeof(buf), ts);
453
454 return err;
455}
456
930dfa56
ML		 457static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn)
458{
459 struct idtcm_channel *ptp_channel, *extts_channel;
460 struct ptp_clock_event event;
461 struct timespec64 ts;
462 u32 dco_delay = 0;
463 int err;
464
465 extts_channel = &idtcm->channel[todn];
466 ptp_channel = idtcm->event_channel[todn];
bec67592 467
930dfa56
ML		 468 if (extts_channel == ptp_channel)
469 dco_delay = ptp_channel->dco_delay;
470
bec67592
ML		 471 err = _idtcm_gettime_triggered(extts_channel, &ts);
472 if (err)
473 return err;
930dfa56 474
bec67592
ML		 475 /* Triggered - save timestamp */
476 event.type = PTP_CLOCK_EXTTS;
477 event.index = todn;
478 event.timestamp = timespec64_to_ns(&ts) - dco_delay;
479 ptp_clock_event(ptp_channel->ptp_clock, &event);
930dfa56 480
bec67592 481 return err;
930dfa56
ML		 482}
483
484static int _idtcm_gettime_immediate(struct idtcm_channel *channel,
485 struct timespec64 *ts)
486{
487 struct idtcm *idtcm = channel->idtcm;
930dfa56 488
bec67592
ML		 489 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
490 u8 val = (SCSR_TOD_READ_TRIG_SEL_IMMEDIATE << TOD_READ_TRIGGER_SHIFT);
491 int err;
930dfa56 492
bec67592
ML		 493 err = idtcm_write(idtcm, channel->tod_read_primary,
494 tod_read_cmd, &val, sizeof(val));
495 if (err)
496 return err;
930dfa56 497
bec67592 498 return _idtcm_gettime(channel, ts, 10);
930dfa56
ML		 499}
500
3a6ba7dc
VC		 501static int _sync_pll_output(struct idtcm *idtcm,
502 u8 pll,
503 u8 sync_src,
504 u8 qn,
505 u8 qn_plus_1)
506{
507 int err;
508 u8 val;
509 u16 sync_ctrl0;
510 u16 sync_ctrl1;
7ea5fda2 511 u8 temp;
3a6ba7dc 512
77fdb168 513 if (qn == 0 && qn_plus_1 == 0)
3a6ba7dc
VC		 514 return 0;
515
516 switch (pll) {
517 case 0:
518 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
519 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
520 break;
521 case 1:
522 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
523 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
524 break;
525 case 2:
526 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
527 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
528 break;
529 case 3:
530 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
531 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
532 break;
533 case 4:
534 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
535 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
536 break;
537 case 5:
538 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
539 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
540 break;
541 case 6:
542 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
543 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
544 break;
545 case 7:
546 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
547 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
548 break;
549 default:
550 return -EINVAL;
551 }
552
553 val = SYNCTRL1_MASTER_SYNC_RST;
554
555 /* Place master sync in reset */
556 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
557 if (err)
558 return err;
559
560 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
561 if (err)
562 return err;
563
564 /* Set sync trigger mask */
565 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
566
567 if (qn)
568 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
569
570 if (qn_plus_1)
571 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
572
573 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
574 if (err)
575 return err;
576
7ea5fda2 577 /* PLL5 can have OUT8 as second additional output. */
77fdb168 578 if (pll == 5 && qn_plus_1 != 0) {
7ea5fda2
ML		 579 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
580 &temp, sizeof(temp));
581 if (err)
582 return err;
583
584 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
585
586 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
587 &temp, sizeof(temp));
588 if (err)
589 return err;
590
591 temp |= Q9_TO_Q8_SYNC_TRIG;
592
593 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
594 &temp, sizeof(temp));
595 if (err)
596 return err;
597 }
598
599 /* PLL6 can have OUT11 as second additional output. */
77fdb168 600 if (pll == 6 && qn_plus_1 != 0) {
7ea5fda2
ML		 601 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
602 &temp, sizeof(temp));
603 if (err)
604 return err;
605
606 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
607
608 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
609 &temp, sizeof(temp));
610 if (err)
611 return err;
612
613 temp |= Q10_TO_Q11_SYNC_TRIG;
614
615 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
616 &temp, sizeof(temp));
617 if (err)
618 return err;
619 }
620
3a6ba7dc
VC		 621 /* Place master sync out of reset */
622 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
623 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
624
625 return err;
626}
627
628static int idtcm_sync_pps_output(struct idtcm_channel *channel)
629{
630 struct idtcm *idtcm = channel->idtcm;
3a6ba7dc 631 u8 pll;
3a6ba7dc
VC		 632 u8 qn;
633 u8 qn_plus_1;
634 int err = 0;
7ea5fda2
ML		 635 u8 out8_mux = 0;
636 u8 out11_mux = 0;
637 u8 temp;
3a6ba7dc
VC		 638 u16 output_mask = channel->output_mask;
639
7ea5fda2
ML		 640 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
641 &temp, sizeof(temp));
642 if (err)
643 return err;
644
645 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
646 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
647 out8_mux = 1;
648
649 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
650 &temp, sizeof(temp));
651 if (err)
652 return err;
653
654 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
655 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
656 out11_mux = 1;
3a6ba7dc 657
7ea5fda2
ML		 658 for (pll = 0; pll < 8; pll++) {
659 qn = 0;
660 qn_plus_1 = 0;
3a6ba7dc
VC		 661
662 if (pll < 4) {
663 /* First 4 pll has 2 outputs */
7ea5fda2
ML		 664 qn = output_mask & 0x1;
665 output_mask = output_mask >> 1;
3a6ba7dc
VC		 666 qn_plus_1 = output_mask & 0x1;
667 output_mask = output_mask >> 1;
7ea5fda2
ML		 668 } else if (pll == 4) {
669 if (out8_mux == 0) {
670 qn = output_mask & 0x1;
671 output_mask = output_mask >> 1;
672 }
673 } else if (pll == 5) {
674 if (out8_mux) {
675 qn_plus_1 = output_mask & 0x1;
676 output_mask = output_mask >> 1;
677 }
678 qn = output_mask & 0x1;
679 output_mask = output_mask >> 1;
680 } else if (pll == 6) {
681 qn = output_mask & 0x1;
682 output_mask = output_mask >> 1;
683 if (out11_mux) {
684 qn_plus_1 = output_mask & 0x1;
685 output_mask = output_mask >> 1;
686 }
687 } else if (pll == 7) {
688 if (out11_mux == 0) {
689 qn = output_mask & 0x1;
690 output_mask = output_mask >> 1;
691 }
3a6ba7dc
VC		 692 }
693
77fdb168 694 if (qn != 0 || qn_plus_1 != 0)
794c3dff
ML		 695 err = _sync_pll_output(idtcm, pll, channel->sync_src,
696 qn, qn_plus_1);
3a6ba7dc
VC		 697
698 if (err)
699 return err;
700 }
701
702 return err;
703}
704
7ea5fda2 705static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
da9facf1
ML		 706 struct timespec64 const *ts,
707 enum hw_tod_write_trig_sel wr_trig)
3a6ba7dc
VC		 708{
709 struct idtcm *idtcm = channel->idtcm;
3a6ba7dc
VC		 710 u8 buf[TOD_BYTE_COUNT];
711 u8 cmd;
712 int err;
713 struct timespec64 local_ts = *ts;
714 s64 total_overhead_ns;
715
716 /* Configure HW TOD write trigger. */
717 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
718 &cmd, sizeof(cmd));
3a6ba7dc
VC		 719 if (err)
720 return err;
721
722 cmd &= ~(0x0f);
723 cmd |= wr_trig | 0x08;
724
725 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
726 &cmd, sizeof(cmd));
3a6ba7dc
VC		 727 if (err)
728 return err;
729
730 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
3a6ba7dc 731 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
3a6ba7dc
VC		 732 if (err)
733 return err;
734
735 err = idtcm_write(idtcm, channel->hw_dpll_n,
736 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
3a6ba7dc
VC		 737 if (err)
738 return err;
739 }
740
741 /* ARM HW TOD write trigger. */
742 cmd &= ~(0x08);
743
744 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
745 &cmd, sizeof(cmd));
746
747 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
3a6ba7dc 748 if (idtcm->calculate_overhead_flag) {
1ece2fbe 749 /* Assumption: I2C @ 400KHz */
7260d1c8
ML		 750 ktime_t diff = ktime_sub(ktime_get_raw(),
751 idtcm->start_time);
752 total_overhead_ns = ktime_to_ns(diff)
3a6ba7dc
VC		 753 + idtcm->tod_write_overhead_ns
754 + SETTIME_CORRECTION;
755
756 timespec64_add_ns(&local_ts, total_overhead_ns);
757
758 idtcm->calculate_overhead_flag = 0;
759 }
760
761 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
3a6ba7dc
VC		 762 if (err)
763 return err;
764
765 err = idtcm_write(idtcm, channel->hw_dpll_n,
766 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
767 }
768
769 return err;
770}
771
7ea5fda2
ML		 772static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
773 struct timespec64 const *ts,
774 enum scsr_tod_write_trig_sel wr_trig,
775 enum scsr_tod_write_type_sel wr_type)
776{
777 struct idtcm *idtcm = channel->idtcm;
778 unsigned char buf[TOD_BYTE_COUNT], cmd;
779 struct timespec64 local_ts = *ts;
780 int err, count = 0;
781
782 timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
783
784 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
7ea5fda2
ML		 785 if (err)
786 return err;
787
788 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
789 buf, sizeof(buf));
790 if (err)
791 return err;
792
793 /* Trigger the write operation. */
794 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
795 &cmd, sizeof(cmd));
796 if (err)
797 return err;
798
799 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
800 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
801 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
802 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
803
804 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
805 &cmd, sizeof(cmd));
806 if (err)
807 return err;
808
809 /* Wait for the operation to complete. */
810 while (1) {
811 /* pps trigger takes up to 1 sec to complete */
812 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
813 msleep(50);
814
815 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
816 &cmd, sizeof(cmd));
817 if (err)
818 return err;
819
251f4fe2 820 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
7ea5fda2
ML		 821 break;
822
823 if (++count > 20) {
930dfa56 824 dev_err(idtcm->dev,
1c49d3e9 825 "Timed out waiting for the write counter");
7ea5fda2
ML		 826 return -EIO;
827 }
828 }
829
830 return 0;
831}
832
794c3dff 833static int get_output_base_addr(enum fw_version ver, u8 outn)
7260d1c8
ML		 834{
835 int base;
836
837 switch (outn) {
838 case 0:
794c3dff 839 base = IDTCM_FW_REG(ver, V520, OUTPUT_0);
7260d1c8
ML		 840 break;
841 case 1:
794c3dff 842 base = IDTCM_FW_REG(ver, V520, OUTPUT_1);
7260d1c8
ML		 843 break;
844 case 2:
794c3dff 845 base = IDTCM_FW_REG(ver, V520, OUTPUT_2);
7260d1c8
ML		 846 break;
847 case 3:
794c3dff 848 base = IDTCM_FW_REG(ver, V520, OUTPUT_3);
7260d1c8
ML		 849 break;
850 case 4:
794c3dff 851 base = IDTCM_FW_REG(ver, V520, OUTPUT_4);
7260d1c8
ML		 852 break;
853 case 5:
794c3dff 854 base = IDTCM_FW_REG(ver, V520, OUTPUT_5);
7260d1c8
ML		 855 break;
856 case 6:
794c3dff 857 base = IDTCM_FW_REG(ver, V520, OUTPUT_6);
7260d1c8
ML		 858 break;
859 case 7:
794c3dff 860 base = IDTCM_FW_REG(ver, V520, OUTPUT_7);
7260d1c8
ML		 861 break;
862 case 8:
794c3dff 863 base = IDTCM_FW_REG(ver, V520, OUTPUT_8);
7260d1c8
ML		 864 break;
865 case 9:
794c3dff 866 base = IDTCM_FW_REG(ver, V520, OUTPUT_9);
7260d1c8
ML		 867 break;
868 case 10:
794c3dff 869 base = IDTCM_FW_REG(ver, V520, OUTPUT_10);
7260d1c8
ML		 870 break;
871 case 11:
794c3dff 872 base = IDTCM_FW_REG(ver, V520, OUTPUT_11);
7260d1c8
ML		 873 break;
874 default:
875 base = -EINVAL;
876 }
877
878 return base;
879}
880
da948233
ML		 881static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
882 struct timespec64 const *ts)
3a6ba7dc
VC		 883{
884 struct idtcm *idtcm = channel->idtcm;
3a6ba7dc 885 int err;
3a6ba7dc 886
251f4fe2 887 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
7ea5fda2 888 if (err) {
930dfa56 889 dev_err(idtcm->dev,
1c49d3e9 890 "%s: Set HW ToD failed", __func__);
3a6ba7dc 891 return err;
7ea5fda2 892 }
3a6ba7dc 893
7ea5fda2
ML		 894 return idtcm_sync_pps_output(channel);
895}
3a6ba7dc 896
da948233
ML		 897static int _idtcm_settime(struct idtcm_channel *channel,
898 struct timespec64 const *ts,
899 enum scsr_tod_write_type_sel wr_type)
7ea5fda2
ML		 900{
901 return _idtcm_set_dpll_scsr_tod(channel, ts,
902 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
903 wr_type);
3a6ba7dc
VC		 904}
905
906static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
907 s32 offset_ns)
908{
909 int err;
910 int i;
911 struct idtcm *idtcm = channel->idtcm;
3a6ba7dc
VC		 912 u8 buf[4];
913
914 for (i = 0; i < 4; i++) {
915 buf[i] = 0xff & (offset_ns);
916 offset_ns >>= 8;
917 }
918
919 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
920 buf, sizeof(buf));
921
922 return err;
923}
924
925static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
926 u32 max_ffo_ppb)
927{
928 int err;
929 u8 i;
930 struct idtcm *idtcm = channel->idtcm;
3a6ba7dc
VC		 931 u8 buf[3];
932
933 if (max_ffo_ppb & 0xff000000)
934 max_ffo_ppb = 0;
935
936 for (i = 0; i < 3; i++) {
937 buf[i] = 0xff & (max_ffo_ppb);
938 max_ffo_ppb >>= 8;
939 }
940
941 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
942 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
943
944 return err;
945}
946
947static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
948{
949 int err;
950 struct idtcm *idtcm = channel->idtcm;
3a6ba7dc
VC		 951 u8 buf;
952
953 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
954 &buf, sizeof(buf));
3a6ba7dc
VC		 955 if (err)
956 return err;
957
958 if (buf == 0) {
959 buf = 0x01;
960 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
961 PULL_IN_CTRL, &buf, sizeof(buf));
962 } else {
963 err = -EBUSY;
964 }
965
966 return err;
967}
968
da9facf1
ML		 969static int do_phase_pull_in_fw(struct idtcm_channel *channel,
970 s32 offset_ns,
971 u32 max_ffo_ppb)
3a6ba7dc
VC		 972{
973 int err;
974
975 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
3a6ba7dc
VC		 976 if (err)
977 return err;
978
979 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
3a6ba7dc
VC		 980 if (err)
981 return err;
982
983 err = idtcm_start_phase_pull_in(channel);
984
985 return err;
986}
987
7ea5fda2
ML		 988static int set_tod_write_overhead(struct idtcm_channel *channel)
989{
990 struct idtcm *idtcm = channel->idtcm;
991 s64 current_ns = 0;
992 s64 lowest_ns = 0;
993 int err;
994 u8 i;
7ea5fda2
ML		 995 ktime_t start;
996 ktime_t stop;
7260d1c8 997 ktime_t diff;
7ea5fda2
ML		 998
999 char buf[TOD_BYTE_COUNT] = {0};
1000
1001 /* Set page offset */
1002 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
1003 buf, sizeof(buf));
1004
1005 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
7ea5fda2
ML		 1006 start = ktime_get_raw();
1007
1008 err = idtcm_write(idtcm, channel->hw_dpll_n,
1009 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
7ea5fda2
ML		 1010 if (err)
1011 return err;
1012
1013 stop = ktime_get_raw();
1014
7260d1c8
ML		 1015 diff = ktime_sub(stop, start);
1016
1017 current_ns = ktime_to_ns(diff);
7ea5fda2
ML		 1018
1019 if (i == 0) {
1020 lowest_ns = current_ns;
1021 } else {
1022 if (current_ns < lowest_ns)
1023 lowest_ns = current_ns;
1024 }
1025 }
1026
1027 idtcm->tod_write_overhead_ns = lowest_ns;
1028
1029 return err;
1030}
1031
da948233 1032static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
3a6ba7dc
VC		 1033{
1034 int err;
1035 struct idtcm *idtcm = channel->idtcm;
1036 struct timespec64 ts;
1037 s64 now;
1038
da948233 1039 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
da9facf1 1040 err = channel->do_phase_pull_in(channel, delta, 0);
3a6ba7dc
VC		 1041 } else {
1042 idtcm->calculate_overhead_flag = 1;
1043
7ea5fda2 1044 err = set_tod_write_overhead(channel);
7ea5fda2
ML		 1045 if (err)
1046 return err;
1047
930dfa56 1048 err = _idtcm_gettime_immediate(channel, &ts);
3a6ba7dc
VC		 1049 if (err)
1050 return err;
1051
1052 now = timespec64_to_ns(&ts);
1053 now += delta;
1054
1055 ts = ns_to_timespec64(now);
1056
da948233 1057 err = _idtcm_settime_deprecated(channel, &ts);
3a6ba7dc
VC		 1058 }
1059
1060 return err;
1061}
1062
1063static int idtcm_state_machine_reset(struct idtcm *idtcm)
1064{
3a6ba7dc 1065 u8 byte = SM_RESET_CMD;
251f4fe2
ML		 1066 u32 status = 0;
1067 int err;
1068 u8 i;
1069
1070 clear_boot_status(idtcm);
3a6ba7dc 1071
794c3dff
ML		 1072 err = idtcm_write(idtcm, RESET_CTRL,
1073 IDTCM_FW_REG(idtcm->fw_ver, V520, SM_RESET),
1074 &byte, sizeof(byte));
3a6ba7dc 1075
251f4fe2
ML		 1076 if (!err) {
1077 for (i = 0; i < 30; i++) {
1078 msleep_interruptible(100);
1079 read_boot_status(idtcm, &status);
1080
1081 if (status == 0xA0) {
930dfa56 1082 dev_dbg(idtcm->dev,
1c49d3e9 1083 "SM_RESET completed in %d ms", i * 100);
251f4fe2
ML		 1084 break;
1085 }
1086 }
1087
1088 if (!status)
930dfa56 1089 dev_err(idtcm->dev,
1c49d3e9 1090 "Timed out waiting for CM_RESET to complete");
251f4fe2 1091 }
3a6ba7dc
VC		 1092
1093 return err;
1094}
1095
1096static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1097{
1ece2fbe 1098 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
3a6ba7dc
VC		 1099}
1100
1101static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1102{
1103 int err;
1104 u8 buf[2] = {0};
1105
1106 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1107
1108 *product_id = (buf[1] << 8) | buf[0];
1109
1110 return err;
1111}
1112
1113static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1114{
1115 int err;
1116 u8 buf = 0;
1117
1118 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1119
1120 *major = buf >> 1;
1121
1122 return err;
1123}
1124
1125static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1126{
1127 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1128}
1129
1130static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1131{
1132 return idtcm_read(idtcm,
1133 GENERAL_STATUS,
1134 HOTFIX_REL,
1135 hotfix,
1136 sizeof(u8));
1137}
1138
1ece2fbe
VC		 1139static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1140 u8 *config_select)
3a6ba7dc 1141{
1ece2fbe
VC		 1142 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1143 config_select, sizeof(u8));
3a6ba7dc
VC		 1144}
1145
3a6ba7dc
VC		 1146static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1147{
1148 int err = 0;
1149
1150 switch (addr) {
7ea5fda2 1151 case TOD0_OUT_ALIGN_MASK_ADDR:
3a6ba7dc
VC		 1152 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1153 break;
7ea5fda2 1154 case TOD0_OUT_ALIGN_MASK_ADDR + 1:
3a6ba7dc
VC		 1155 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1156 break;
7ea5fda2 1157 case TOD1_OUT_ALIGN_MASK_ADDR:
3a6ba7dc
VC		 1158 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1159 break;
7ea5fda2 1160 case TOD1_OUT_ALIGN_MASK_ADDR + 1:
3a6ba7dc
VC		 1161 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1162 break;
7ea5fda2 1163 case TOD2_OUT_ALIGN_MASK_ADDR:
3a6ba7dc
VC		 1164 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1165 break;
7ea5fda2 1166 case TOD2_OUT_ALIGN_MASK_ADDR + 1:
3a6ba7dc
VC		 1167 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1168 break;
7ea5fda2 1169 case TOD3_OUT_ALIGN_MASK_ADDR:
3a6ba7dc
VC		 1170 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1171 break;
7ea5fda2 1172 case TOD3_OUT_ALIGN_MASK_ADDR + 1:
3a6ba7dc
VC		 1173 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1174 break;
1175 default:
7ea5fda2 1176 err = -EFAULT; /* Bad address */;
3a6ba7dc
VC		 1177 break;
1178 }
1179
1180 return err;
1181}
1182
7ea5fda2
ML		 1183static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1184{
1185 if (index >= MAX_TOD) {
930dfa56 1186 dev_err(idtcm->dev, "ToD%d not supported", index);
7ea5fda2
ML		 1187 return -EINVAL;
1188 }
1189
1190 if (pll >= MAX_PLL) {
930dfa56 1191 dev_err(idtcm->dev, "Pll%d not supported", pll);
7ea5fda2
ML		 1192 return -EINVAL;
1193 }
1194
1195 idtcm->channel[index].pll = pll;
1196
1197 return 0;
1198}
1199
3a6ba7dc
VC		 1200static int check_and_set_masks(struct idtcm *idtcm,
1201 u16 regaddr,
1202 u8 val)
1203{
1204 int err = 0;
1205
7ea5fda2
ML		 1206 switch (regaddr) {
1207 case TOD_MASK_ADDR:
1208 if ((val & 0xf0) || !(val & 0x0f)) {
930dfa56 1209 dev_err(idtcm->dev, "Invalid TOD mask 0x%02x", val);
7ea5fda2
ML		 1210 err = -EINVAL;
1211 } else {
1212 idtcm->tod_mask = val;
1213 }
1214 break;
1215 case TOD0_PTP_PLL_ADDR:
1216 err = set_tod_ptp_pll(idtcm, 0, val);
1217 break;
1218 case TOD1_PTP_PLL_ADDR:
1219 err = set_tod_ptp_pll(idtcm, 1, val);
1220 break;
1221 case TOD2_PTP_PLL_ADDR:
1222 err = set_tod_ptp_pll(idtcm, 2, val);
1223 break;
1224 case TOD3_PTP_PLL_ADDR:
1225 err = set_tod_ptp_pll(idtcm, 3, val);
1226 break;
1227 default:
1228 err = set_pll_output_mask(idtcm, regaddr, val);
1229 break;
3a6ba7dc
VC		 1230 }
1231
1232 return err;
1233}
1234
7ea5fda2 1235static void display_pll_and_masks(struct idtcm *idtcm)
3a6ba7dc
VC		 1236{
1237 u8 i;
1238 u8 mask;
1239
930dfa56 1240 dev_dbg(idtcm->dev, "tod_mask = 0x%02x", idtcm->tod_mask);
3a6ba7dc 1241
7ea5fda2 1242 for (i = 0; i < MAX_TOD; i++) {
3a6ba7dc
VC		 1243 mask = 1 << i;
1244
7ea5fda2 1245 if (mask & idtcm->tod_mask)
930dfa56 1246 dev_dbg(idtcm->dev,
1c49d3e9 1247 "TOD%d pll = %d output_mask = 0x%04x",
7ea5fda2
ML		 1248 i, idtcm->channel[i].pll,
1249 idtcm->channel[i].output_mask);
3a6ba7dc
VC		 1250 }
1251}
1252
1253static int idtcm_load_firmware(struct idtcm *idtcm,
1254 struct device *dev)
1255{
794c3dff 1256 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
7ea5fda2 1257 char fname[128] = FW_FILENAME;
3a6ba7dc
VC		 1258 const struct firmware *fw;
1259 struct idtcm_fwrc *rec;
1260 u32 regaddr;
1261 int err;
1262 s32 len;
1263 u8 val;
1264 u8 loaddr;
1265
7ea5fda2
ML		 1266 if (firmware) /* module parameter */
1267 snprintf(fname, sizeof(fname), "%s", firmware);
3a6ba7dc 1268
930dfa56 1269 dev_info(idtcm->dev, "requesting firmware '%s'", fname);
3a6ba7dc 1270
7ea5fda2 1271 err = request_firmware(&fw, fname, dev);
7ea5fda2 1272 if (err) {
930dfa56 1273 dev_err(idtcm->dev,
1c49d3e9 1274 "Failed at line %d in %s!", __LINE__, __func__);
3a6ba7dc 1275 return err;
7ea5fda2 1276 }
3a6ba7dc 1277
930dfa56 1278 dev_dbg(idtcm->dev, "firmware size %zu bytes", fw->size);
3a6ba7dc
VC		 1279
1280 rec = (struct idtcm_fwrc *) fw->data;
1281
794c3dff 1282 if (contains_full_configuration(idtcm, fw))
3a6ba7dc
VC		 1283 idtcm_state_machine_reset(idtcm);
1284
1285 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
3a6ba7dc 1286 if (rec->reserved) {
930dfa56 1287 dev_err(idtcm->dev,
1c49d3e9 1288 "bad firmware, reserved field non-zero");
3a6ba7dc
VC		 1289 err = -EINVAL;
1290 } else {
1291 regaddr = rec->hiaddr << 8;
1292 regaddr |= rec->loaddr;
1293
1294 val = rec->value;
1295 loaddr = rec->loaddr;
1296
1297 rec++;
1298
1299 err = check_and_set_masks(idtcm, regaddr, val);
1300 }
1301
7ea5fda2
ML		 1302 if (err != -EINVAL) {
1303 err = 0;
1304
3a6ba7dc 1305 /* Top (status registers) and bottom are read-only */
794c3dff 1306 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
3a6ba7dc
VC		 1307 continue;
1308
1309 /* Page size 128, last 4 bytes of page skipped */
77fdb168 1310 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
3a6ba7dc
VC		 1311 continue;
1312
1313 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1314 }
1315
1316 if (err)
1317 goto out;
1318 }
1319
7ea5fda2 1320 display_pll_and_masks(idtcm);
3a6ba7dc
VC		 1321
1322out:
1323 release_firmware(fw);
1324 return err;
1325}
1326
7ea5fda2
ML		 1327static int idtcm_output_enable(struct idtcm_channel *channel,
1328 bool enable, unsigned int outn)
3a6ba7dc
VC		 1329{
1330 struct idtcm *idtcm = channel->idtcm;
7260d1c8 1331 int base;
3a6ba7dc 1332 int err;
7ea5fda2 1333 u8 val;
3a6ba7dc 1334
794c3dff 1335 base = get_output_base_addr(idtcm->fw_ver, outn);
7260d1c8
ML		 1336
1337 if (!(base > 0)) {
930dfa56 1338 dev_err(idtcm->dev,
7260d1c8
ML		 1339 "%s - Unsupported out%d", __func__, outn);
1340 return base;
1341 }
1342
1343 err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
3a6ba7dc
VC		 1344 if (err)
1345 return err;
1346
1347 if (enable)
1348 val |= SQUELCH_DISABLE;
1349 else
1350 val &= ~SQUELCH_DISABLE;
1351
7260d1c8 1352 return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
7ea5fda2 1353}
3a6ba7dc 1354
7ea5fda2 1355static int idtcm_perout_enable(struct idtcm_channel *channel,
930dfa56
ML		 1356 struct ptp_perout_request *perout,
1357 bool enable)
7ea5fda2 1358{
e8b4d8b5 1359 struct idtcm *idtcm = channel->idtcm;
e8b4d8b5
VC		 1360 struct timespec64 ts = {0, 0};
1361 int err;
7ea5fda2 1362
7c7dcd66 1363 err = idtcm_output_enable(channel, enable, perout->index);
e8b4d8b5
VC		 1364
1365 if (err) {
930dfa56 1366 dev_err(idtcm->dev, "Unable to set output enable");
e8b4d8b5
VC		 1367 return err;
1368 }
7ea5fda2 1369
e8b4d8b5
VC		 1370 /* Align output to internal 1 PPS */
1371 return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS);
7ea5fda2
ML		 1372}
1373
7260d1c8 1374static int idtcm_get_pll_mode(struct idtcm_channel *channel,
da9facf1 1375 enum pll_mode *mode)
7260d1c8
ML		 1376{
1377 struct idtcm *idtcm = channel->idtcm;
1378 int err;
1379 u8 dpll_mode;
1380
794c3dff
ML		 1381 err = idtcm_read(idtcm, channel->dpll_n,
1382 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
7260d1c8
ML		 1383 &dpll_mode, sizeof(dpll_mode));
1384 if (err)
1385 return err;
1386
da9facf1 1387 *mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
7260d1c8
ML		 1388
1389 return 0;
1390}
1391
3a6ba7dc 1392static int idtcm_set_pll_mode(struct idtcm_channel *channel,
da9facf1 1393 enum pll_mode mode)
3a6ba7dc
VC		 1394{
1395 struct idtcm *idtcm = channel->idtcm;
1396 int err;
1397 u8 dpll_mode;
1398
794c3dff
ML		 1399 err = idtcm_read(idtcm, channel->dpll_n,
1400 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
3a6ba7dc
VC		 1401 &dpll_mode, sizeof(dpll_mode));
1402 if (err)
1403 return err;
1404
1405 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1406
da9facf1 1407 dpll_mode |= (mode << PLL_MODE_SHIFT);
3a6ba7dc 1408
794c3dff
ML		 1409 err = idtcm_write(idtcm, channel->dpll_n,
1410 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
3a6ba7dc 1411 &dpll_mode, sizeof(dpll_mode));
da9facf1
ML		 1412 return err;
1413}
1414
1415static int idtcm_get_manual_reference(struct idtcm_channel *channel,
1416 enum manual_reference *ref)
1417{
1418 struct idtcm *idtcm = channel->idtcm;
1419 u8 dpll_manu_ref_cfg;
1420 int err;
1421
1422 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1423 DPLL_CTRL_DPLL_MANU_REF_CFG,
1424 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1425 if (err)
1426 return err;
1427
1428 dpll_manu_ref_cfg &= (MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
1429
1430 *ref = dpll_manu_ref_cfg >> MANUAL_REFERENCE_SHIFT;
1431
1432 return 0;
1433}
1434
1435static int idtcm_set_manual_reference(struct idtcm_channel *channel,
1436 enum manual_reference ref)
1437{
1438 struct idtcm *idtcm = channel->idtcm;
1439 u8 dpll_manu_ref_cfg;
1440 int err;
1441
1442 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1443 DPLL_CTRL_DPLL_MANU_REF_CFG,
1444 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1445 if (err)
1446 return err;
1447
1448 dpll_manu_ref_cfg &= ~(MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
1449
1450 dpll_manu_ref_cfg |= (ref << MANUAL_REFERENCE_SHIFT);
1451
1452 err = idtcm_write(idtcm, channel->dpll_ctrl_n,
1453 DPLL_CTRL_DPLL_MANU_REF_CFG,
1454 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1455
1456 return err;
1457}
1458
1459static int configure_dpll_mode_write_frequency(struct idtcm_channel *channel)
1460{
1461 struct idtcm *idtcm = channel->idtcm;
1462 int err;
1463
1464 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1465
1466 if (err)
930dfa56 1467 dev_err(idtcm->dev, "Failed to set pll mode to write frequency");
da9facf1
ML		 1468 else
1469 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1470
1471 return err;
1472}
1473
1474static int configure_dpll_mode_write_phase(struct idtcm_channel *channel)
1475{
1476 struct idtcm *idtcm = channel->idtcm;
1477 int err;
1478
1479 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1480
1481 if (err)
930dfa56 1482 dev_err(idtcm->dev, "Failed to set pll mode to write phase");
da9facf1
ML		 1483 else
1484 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1485
1486 return err;
1487}
1488
1489static int configure_manual_reference_write_frequency(struct idtcm_channel *channel)
1490{
1491 struct idtcm *idtcm = channel->idtcm;
1492 int err;
1493
1494 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_FREQUENCY);
1495
1496 if (err)
930dfa56 1497 dev_err(idtcm->dev, "Failed to set manual reference to write frequency");
da9facf1
ML		 1498 else
1499 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1500
1501 return err;
1502}
1503
1504static int configure_manual_reference_write_phase(struct idtcm_channel *channel)
1505{
1506 struct idtcm *idtcm = channel->idtcm;
1507 int err;
1508
1509 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_PHASE);
1510
1511 if (err)
930dfa56 1512 dev_err(idtcm->dev, "Failed to set manual reference to write phase");
da9facf1
ML		 1513 else
1514 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1515
1516 return err;
1517}
1518
1519static int idtcm_stop_phase_pull_in(struct idtcm_channel *channel)
1520{
1521 int err;
1522
1523 err = _idtcm_adjfine(channel, channel->current_freq_scaled_ppm);
3a6ba7dc
VC		 1524 if (err)
1525 return err;
1526
da9facf1
ML		 1527 channel->phase_pull_in = false;
1528
3a6ba7dc
VC		 1529 return 0;
1530}
1531
da9facf1
ML		 1532static long idtcm_work_handler(struct ptp_clock_info *ptp)
1533{
1534 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1535 struct idtcm *idtcm = channel->idtcm;
1536
930dfa56 1537 mutex_lock(idtcm->lock);
da9facf1
ML		 1538
1539 (void)idtcm_stop_phase_pull_in(channel);
1540
930dfa56 1541 mutex_unlock(idtcm->lock);
da9facf1
ML		 1542
1543 /* Return a negative value here to not reschedule */
1544 return -1;
1545}
1546
1547static s32 phase_pull_in_scaled_ppm(s32 current_ppm, s32 phase_pull_in_ppb)
1548{
1549 /* ppb = scaled_ppm * 125 / 2^13 */
1550 /* scaled_ppm = ppb * 2^13 / 125 */
1551
930dfa56
ML		 1552 s64 max_scaled_ppm = div_s64((s64)PHASE_PULL_IN_MAX_PPB << 13, 125);
1553 s64 scaled_ppm = div_s64((s64)phase_pull_in_ppb << 13, 125);
da9facf1
ML		 1554
1555 current_ppm += scaled_ppm;
1556
1557 if (current_ppm > max_scaled_ppm)
1558 current_ppm = max_scaled_ppm;
1559 else if (current_ppm < -max_scaled_ppm)
1560 current_ppm = -max_scaled_ppm;
1561
1562 return current_ppm;
1563}
1564
1565static int do_phase_pull_in_sw(struct idtcm_channel *channel,
1566 s32 delta_ns,
1567 u32 max_ffo_ppb)
1568{
1569 s32 current_ppm = channel->current_freq_scaled_ppm;
1570 u32 duration_ms = MSEC_PER_SEC;
1571 s32 delta_ppm;
1572 s32 ppb;
1573 int err;
1574
1575 /* If the ToD correction is less than PHASE_PULL_IN_MIN_THRESHOLD_NS,
1576 * skip. The error introduced by the ToD adjustment procedure would
1577 * be bigger than the required ToD correction
1578 */
1579 if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS)
1580 return 0;
1581
1582 if (max_ffo_ppb == 0)
1583 max_ffo_ppb = PHASE_PULL_IN_MAX_PPB;
1584
1585 /* For most cases, keep phase pull-in duration 1 second */
1586 ppb = delta_ns;
1587 while (abs(ppb) > max_ffo_ppb) {
1588 duration_ms *= 2;
1589 ppb /= 2;
1590 }
1591
1592 delta_ppm = phase_pull_in_scaled_ppm(current_ppm, ppb);
1593
1594 err = _idtcm_adjfine(channel, delta_ppm);
1595
1596 if (err)
1597 return err;
1598
1599 /* schedule the worker to cancel phase pull-in */
1600 ptp_schedule_worker(channel->ptp_clock,
1601 msecs_to_jiffies(duration_ms) - 1);
1602
1603 channel->phase_pull_in = true;
1604
1605 return 0;
1606}
1607
1608static int initialize_operating_mode_with_manual_reference(struct idtcm_channel *channel,
1609 enum manual_reference ref)
1610{
1611 struct idtcm *idtcm = channel->idtcm;
1612
1613 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1614 channel->configure_write_frequency = configure_manual_reference_write_frequency;
1615 channel->configure_write_phase = configure_manual_reference_write_phase;
1616 channel->do_phase_pull_in = do_phase_pull_in_sw;
1617
1618 switch (ref) {
1619 case MANU_REF_WRITE_PHASE:
1620 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1621 break;
1622 case MANU_REF_WRITE_FREQUENCY:
1623 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1624 break;
1625 default:
930dfa56 1626 dev_warn(idtcm->dev,
da9facf1
ML		 1627 "Unsupported MANUAL_REFERENCE: 0x%02x", ref);
1628 }
1629
1630 return 0;
1631}
1632
1633static int initialize_operating_mode_with_pll_mode(struct idtcm_channel *channel,
1634 enum pll_mode mode)
1635{
1636 struct idtcm *idtcm = channel->idtcm;
1637 int err = 0;
1638
1639 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1640 channel->configure_write_frequency = configure_dpll_mode_write_frequency;
1641 channel->configure_write_phase = configure_dpll_mode_write_phase;
1642 channel->do_phase_pull_in = do_phase_pull_in_fw;
1643
1644 switch (mode) {
1645 case PLL_MODE_WRITE_PHASE:
1646 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1647 break;
1648 case PLL_MODE_WRITE_FREQUENCY:
1649 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1650 break;
1651 default:
930dfa56 1652 dev_err(idtcm->dev,
da9facf1
ML		 1653 "Unsupported PLL_MODE: 0x%02x", mode);
1654 err = -EINVAL;
1655 }
1656
1657 return err;
1658}
1659
1660static int initialize_dco_operating_mode(struct idtcm_channel *channel)
1661{
1662 enum manual_reference ref = MANU_REF_XO_DPLL;
1663 enum pll_mode mode = PLL_MODE_DISABLED;
1664 struct idtcm *idtcm = channel->idtcm;
1665 int err;
1666
1667 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1668
1669 err = idtcm_get_pll_mode(channel, &mode);
1670 if (err) {
930dfa56 1671 dev_err(idtcm->dev, "Unable to read pll mode!");
da9facf1
ML		 1672 return err;
1673 }
1674
1675 if (mode == PLL_MODE_PLL) {
1676 err = idtcm_get_manual_reference(channel, &ref);
1677 if (err) {
930dfa56 1678 dev_err(idtcm->dev, "Unable to read manual reference!");
da9facf1
ML		 1679 return err;
1680 }
1681 err = initialize_operating_mode_with_manual_reference(channel, ref);
1682 } else {
1683 err = initialize_operating_mode_with_pll_mode(channel, mode);
1684 }
1685
1686 if (channel->mode == PTP_PLL_MODE_WRITE_PHASE)
1687 channel->configure_write_frequency(channel);
1688
1689 return err;
1690}
1691
3a6ba7dc
VC		 1692/* PTP Hardware Clock interface */
1693
87530779 1694/*
da9facf1
ML		 1695 * Maximum absolute value for write phase offset in picoseconds
1696 *
bec67592
ML		 1697 * @channel: channel
1698 * @delta_ns: delta in nanoseconds
1699 *
425d2b1c
VC		 1700 * Destination signed register is 32-bit register in resolution of 50ps
1701 *
1702 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1703 */
1704static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1705{
1706 struct idtcm *idtcm = channel->idtcm;
425d2b1c
VC		 1707 int err;
1708 u8 i;
1709 u8 buf[4] = {0};
1710 s32 phase_50ps;
1711 s64 offset_ps;
1712
da9facf1
ML		 1713 if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
1714 err = channel->configure_write_phase(channel);
425d2b1c
VC		 1715 if (err)
1716 return err;
425d2b1c
VC		 1717 }
1718
425d2b1c
VC		 1719 offset_ps = (s64)delta_ns * 1000;
1720
1721 /*
1722 * Check for 32-bit signed max * 50:
1723 *
1724 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1725 */
1726 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1727 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1728 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1729 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1730
7260d1c8 1731 phase_50ps = div_s64(offset_ps, 50);
425d2b1c
VC		 1732
1733 for (i = 0; i < 4; i++) {
1734 buf[i] = phase_50ps & 0xff;
1735 phase_50ps >>= 8;
1736 }
1737
1738 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1739 buf, sizeof(buf));
1740
1741 return err;
1742}
1743
7ea5fda2 1744static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
3a6ba7dc 1745{
3a6ba7dc
VC		 1746 struct idtcm *idtcm = channel->idtcm;
1747 u8 i;
3a6ba7dc
VC		 1748 int err;
1749 u8 buf[6] = {0};
1750 s64 fcw;
1751
da9facf1
ML		 1752 if (channel->mode != PTP_PLL_MODE_WRITE_FREQUENCY) {
1753 err = channel->configure_write_frequency(channel);
3a6ba7dc
VC		 1754 if (err)
1755 return err;
1756 }
1757
1758 /*
1759 * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1760 *
1761 * adjfreq:
1762 * ppb * 10^9
1763 * FCW = ----------
1764 * 111
1765 *
1766 * adjfine:
1767 * ppm_16 * 5^12
1768 * FCW = -------------
1769 * 111 * 2^4
1770 */
3a6ba7dc
VC		 1771
1772 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
7ea5fda2 1773 fcw = scaled_ppm * 244140625ULL;
3a6ba7dc 1774
7260d1c8 1775 fcw = div_s64(fcw, 1776);
3a6ba7dc
VC		 1776
1777 for (i = 0; i < 6; i++) {
1778 buf[i] = fcw & 0xff;
1779 fcw >>= 8;
1780 }
1781
3a6ba7dc
VC		 1782 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1783 buf, sizeof(buf));
1784
3a6ba7dc
VC		 1785 return err;
1786}
1787
1788static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1789{
fcfd3757 1790 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
3a6ba7dc
VC		 1791 struct idtcm *idtcm = channel->idtcm;
1792 int err;
1793
930dfa56
ML		 1794 mutex_lock(idtcm->lock);
1795 err = _idtcm_gettime_immediate(channel, ts);
1796 mutex_unlock(idtcm->lock);
3a6ba7dc 1797
7ea5fda2 1798 if (err)
930dfa56 1799 dev_err(idtcm->dev, "Failed at line %d in %s!",
1c49d3e9 1800 __LINE__, __func__);
7ea5fda2 1801
3a6ba7dc
VC		 1802 return err;
1803}
1804
da948233
ML		 1805static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1806 const struct timespec64 *ts)
3a6ba7dc 1807{
fcfd3757 1808 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
3a6ba7dc
VC		 1809 struct idtcm *idtcm = channel->idtcm;
1810 int err;
1811
930dfa56 1812 mutex_lock(idtcm->lock);
da948233 1813 err = _idtcm_settime_deprecated(channel, ts);
930dfa56
ML		 1814 mutex_unlock(idtcm->lock);
1815
7ea5fda2 1816 if (err)
930dfa56 1817 dev_err(idtcm->dev,
1c49d3e9 1818 "Failed at line %d in %s!", __LINE__, __func__);
7ea5fda2 1819
3a6ba7dc
VC		 1820 return err;
1821}
1822
da948233 1823static int idtcm_settime(struct ptp_clock_info *ptp,
7ea5fda2 1824 const struct timespec64 *ts)
3a6ba7dc 1825{
fcfd3757 1826 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
3a6ba7dc
VC		 1827 struct idtcm *idtcm = channel->idtcm;
1828 int err;
1829
930dfa56 1830 mutex_lock(idtcm->lock);
da948233 1831 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
930dfa56
ML		 1832 mutex_unlock(idtcm->lock);
1833
7ea5fda2 1834 if (err)
930dfa56 1835 dev_err(idtcm->dev,
1c49d3e9 1836 "Failed at line %d in %s!", __LINE__, __func__);
3a6ba7dc 1837
3a6ba7dc
VC		 1838 return err;
1839}
1840
da948233 1841static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
7ea5fda2 1842{
fcfd3757 1843 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
7ea5fda2
ML		 1844 struct idtcm *idtcm = channel->idtcm;
1845 int err;
1846
930dfa56 1847 mutex_lock(idtcm->lock);
da948233 1848 err = _idtcm_adjtime_deprecated(channel, delta);
930dfa56
ML		 1849 mutex_unlock(idtcm->lock);
1850
7ea5fda2 1851 if (err)
930dfa56 1852 dev_err(idtcm->dev,
1c49d3e9 1853 "Failed at line %d in %s!", __LINE__, __func__);
7ea5fda2 1854
7ea5fda2
ML		 1855 return err;
1856}
1857
da948233 1858static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
7ea5fda2 1859{
fcfd3757 1860 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
7ea5fda2
ML		 1861 struct idtcm *idtcm = channel->idtcm;
1862 struct timespec64 ts;
1863 enum scsr_tod_write_type_sel type;
1864 int err;
1865
da9facf1 1866 if (channel->phase_pull_in == true)
7c7dcd66 1867 return -EBUSY;
da9facf1 1868
930dfa56 1869 mutex_lock(idtcm->lock);
da9facf1 1870
da948233 1871 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
da9facf1 1872 err = channel->do_phase_pull_in(channel, delta, 0);
7ea5fda2 1873 } else {
da9facf1
ML		 1874 if (delta >= 0) {
1875 ts = ns_to_timespec64(delta);
1876 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1877 } else {
1878 ts = ns_to_timespec64(-delta);
1879 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1880 }
1881 err = _idtcm_settime(channel, &ts, type);
7ea5fda2 1882 }
930dfa56
ML		 1883
1884 mutex_unlock(idtcm->lock);
1885
1886 if (err)
1887 dev_err(idtcm->dev,
1888 "Failed at line %d in %s!", __LINE__, __func__);
7ea5fda2
ML		 1889
1890 return err;
1891}
1892
1893static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
425d2b1c 1894{
fcfd3757 1895 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
425d2b1c 1896 struct idtcm *idtcm = channel->idtcm;
425d2b1c
VC		 1897 int err;
1898
930dfa56 1899 mutex_lock(idtcm->lock);
425d2b1c 1900 err = _idtcm_adjphase(channel, delta);
930dfa56
ML		 1901 mutex_unlock(idtcm->lock);
1902
7ea5fda2 1903 if (err)
930dfa56 1904 dev_err(idtcm->dev,
1c49d3e9 1905 "Failed at line %d in %s!", __LINE__, __func__);
7ea5fda2 1906
7ea5fda2
ML		 1907 return err;
1908}
1909
1910static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1911{
fcfd3757 1912 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
7ea5fda2 1913 struct idtcm *idtcm = channel->idtcm;
7ea5fda2
ML		 1914 int err;
1915
da9facf1
ML		 1916 if (channel->phase_pull_in == true)
1917 return 0;
1918
1919 if (scaled_ppm == channel->current_freq_scaled_ppm)
1920 return 0;
1921
930dfa56 1922 mutex_lock(idtcm->lock);
7ea5fda2 1923 err = _idtcm_adjfine(channel, scaled_ppm);
930dfa56 1924 mutex_unlock(idtcm->lock);
7ea5fda2 1925
930dfa56
ML		 1926 if (err)
1927 dev_err(idtcm->dev,
1928 "Failed at line %d in %s!", __LINE__, __func__);
1929 else
da9facf1
ML		 1930 channel->current_freq_scaled_ppm = scaled_ppm;
1931
425d2b1c
VC		 1932 return err;
1933}
1934
3a6ba7dc
VC		 1935static int idtcm_enable(struct ptp_clock_info *ptp,
1936 struct ptp_clock_request *rq, int on)
1937{
fcfd3757 1938 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
930dfa56
ML		 1939 struct idtcm *idtcm = channel->idtcm;
1940 int err = -EOPNOTSUPP;
1941
1942 mutex_lock(idtcm->lock);
3a6ba7dc
VC		 1943
1944 switch (rq->type) {
1945 case PTP_CLK_REQ_PEROUT:
930dfa56
ML		 1946 if (!on)
1947 err = idtcm_perout_enable(channel, &rq->perout, false);
3a6ba7dc 1948 /* Only accept a 1-PPS aligned to the second. */
930dfa56
ML		 1949 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1950 rq->perout.period.nsec)
1951 err = -ERANGE;
1952 else
1953 err = idtcm_perout_enable(channel, &rq->perout, true);
1954 break;
1955 case PTP_CLK_REQ_EXTTS:
bec67592 1956 err = idtcm_extts_enable(channel, rq, on);
930dfa56 1957 break;
3a6ba7dc
VC		 1958 default:
1959 break;
1960 }
1961
930dfa56
ML		 1962 mutex_unlock(idtcm->lock);
1963
1964 if (err)
1965 dev_err(channel->idtcm->dev,
1966 "Failed in %s with err %d!", __func__, err);
1967
1968 return err;
3a6ba7dc
VC		 1969}
1970
7ea5fda2
ML		 1971static int idtcm_enable_tod(struct idtcm_channel *channel)
1972{
1973 struct idtcm *idtcm = channel->idtcm;
1974 struct timespec64 ts = {0, 0};
794c3dff 1975 u16 tod_cfg = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_CFG);
7ea5fda2
ML		 1976 u8 cfg;
1977 int err;
1978
3a6ba7dc
VC		 1979 /*
1980 * Start the TOD clock ticking.
1981 */
794c3dff 1982 err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
3a6ba7dc
VC		 1983 if (err)
1984 return err;
1985
1986 cfg |= TOD_ENABLE;
1987
794c3dff 1988 err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
3a6ba7dc
VC		 1989 if (err)
1990 return err;
1991
794c3dff 1992 if (idtcm->fw_ver < V487)
da948233
ML		 1993 return _idtcm_settime_deprecated(channel, &ts);
1994 else
1995 return _idtcm_settime(channel, &ts,
1996 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
3a6ba7dc
VC		 1997}
1998
da948233 1999static void idtcm_set_version_info(struct idtcm *idtcm)
3a6ba7dc
VC		 2000{
2001 u8 major;
2002 u8 minor;
2003 u8 hotfix;
3a6ba7dc 2004 u16 product_id;
3a6ba7dc 2005 u8 hw_rev_id;
1ece2fbe 2006 u8 config_select;
3a6ba7dc
VC		 2007
2008 idtcm_read_major_release(idtcm, &major);
2009 idtcm_read_minor_release(idtcm, &minor);
2010 idtcm_read_hotfix_release(idtcm, &hotfix);
3a6ba7dc
VC		 2011
2012 idtcm_read_product_id(idtcm, &product_id);
2013 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1ece2fbe
VC		 2014
2015 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
2016
7ea5fda2
ML		 2017 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
2018 major, minor, hotfix);
2019
794c3dff 2020 idtcm->fw_ver = idtcm_fw_version(idtcm->version);
da948233 2021
930dfa56 2022 dev_info(idtcm->dev,
1c49d3e9
VC		 2023 "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d",
2024 major, minor, hotfix,
1ece2fbe 2025 product_id, hw_rev_id, config_select);
3a6ba7dc
VC		 2026}
2027
bec67592
ML		 2028static int idtcm_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
2029 enum ptp_pin_function func, unsigned int chan)
2030{
2031 switch (func) {
2032 case PTP_PF_NONE:
2033 case PTP_PF_EXTTS:
2034 break;
2035 case PTP_PF_PEROUT:
2036 case PTP_PF_PHYSYNC:
2037 return -1;
2038 }
2039 return 0;
2040}
2041
2042static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK];
2043
da948233 2044static const struct ptp_clock_info idtcm_caps = {
7ea5fda2
ML		 2045 .owner = THIS_MODULE,
2046 .max_adj = 244000,
2047 .n_per_out = 12,
930dfa56 2048 .n_ext_ts = MAX_TOD,
bec67592 2049 .n_pins = MAX_REF_CLK,
7ea5fda2
ML		 2050 .adjphase = &idtcm_adjphase,
2051 .adjfine = &idtcm_adjfine,
da948233 2052 .adjtime = &idtcm_adjtime,
7ea5fda2 2053 .gettime64 = &idtcm_gettime,
da948233 2054 .settime64 = &idtcm_settime,
7ea5fda2 2055 .enable = &idtcm_enable,
bec67592 2056 .verify = &idtcm_verify_pin,
da9facf1 2057 .do_aux_work = &idtcm_work_handler,
7ea5fda2
ML		 2058};
2059
da948233 2060static const struct ptp_clock_info idtcm_caps_deprecated = {
3a6ba7dc
VC		 2061 .owner = THIS_MODULE,
2062 .max_adj = 244000,
7ea5fda2 2063 .n_per_out = 12,
930dfa56 2064 .n_ext_ts = MAX_TOD,
bec67592 2065 .n_pins = MAX_REF_CLK,
425d2b1c 2066 .adjphase = &idtcm_adjphase,
7ea5fda2 2067 .adjfine = &idtcm_adjfine,
da948233 2068 .adjtime = &idtcm_adjtime_deprecated,
3a6ba7dc 2069 .gettime64 = &idtcm_gettime,
da948233 2070 .settime64 = &idtcm_settime_deprecated,
3a6ba7dc 2071 .enable = &idtcm_enable,
bec67592 2072 .verify = &idtcm_verify_pin,
da9facf1 2073 .do_aux_work = &idtcm_work_handler,
3a6ba7dc
VC		 2074};
2075
7ea5fda2 2076static int configure_channel_pll(struct idtcm_channel *channel)
3a6ba7dc 2077{
794c3dff 2078 struct idtcm *idtcm = channel->idtcm;
7ea5fda2 2079 int err = 0;
3a6ba7dc 2080
7ea5fda2 2081 switch (channel->pll) {
3a6ba7dc
VC		 2082 case 0:
2083 channel->dpll_freq = DPLL_FREQ_0;
2084 channel->dpll_n = DPLL_0;
3a6ba7dc
VC		 2085 channel->hw_dpll_n = HW_DPLL_0;
2086 channel->dpll_phase = DPLL_PHASE_0;
2087 channel->dpll_ctrl_n = DPLL_CTRL_0;
2088 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
2089 break;
2090 case 1:
2091 channel->dpll_freq = DPLL_FREQ_1;
2092 channel->dpll_n = DPLL_1;
3a6ba7dc
VC		 2093 channel->hw_dpll_n = HW_DPLL_1;
2094 channel->dpll_phase = DPLL_PHASE_1;
2095 channel->dpll_ctrl_n = DPLL_CTRL_1;
2096 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
2097 break;
2098 case 2:
2099 channel->dpll_freq = DPLL_FREQ_2;
794c3dff 2100 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2);
3a6ba7dc
VC		 2101 channel->hw_dpll_n = HW_DPLL_2;
2102 channel->dpll_phase = DPLL_PHASE_2;
2103 channel->dpll_ctrl_n = DPLL_CTRL_2;
2104 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2105 break;
2106 case 3:
2107 channel->dpll_freq = DPLL_FREQ_3;
2108 channel->dpll_n = DPLL_3;
3a6ba7dc
VC		 2109 channel->hw_dpll_n = HW_DPLL_3;
2110 channel->dpll_phase = DPLL_PHASE_3;
2111 channel->dpll_ctrl_n = DPLL_CTRL_3;
2112 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2113 break;
7ea5fda2
ML		 2114 case 4:
2115 channel->dpll_freq = DPLL_FREQ_4;
794c3dff 2116 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4);
7ea5fda2
ML		 2117 channel->hw_dpll_n = HW_DPLL_4;
2118 channel->dpll_phase = DPLL_PHASE_4;
2119 channel->dpll_ctrl_n = DPLL_CTRL_4;
2120 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2121 break;
2122 case 5:
2123 channel->dpll_freq = DPLL_FREQ_5;
2124 channel->dpll_n = DPLL_5;
2125 channel->hw_dpll_n = HW_DPLL_5;
2126 channel->dpll_phase = DPLL_PHASE_5;
2127 channel->dpll_ctrl_n = DPLL_CTRL_5;
2128 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2129 break;
2130 case 6:
2131 channel->dpll_freq = DPLL_FREQ_6;
794c3dff 2132 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6);
7ea5fda2
ML		 2133 channel->hw_dpll_n = HW_DPLL_6;
2134 channel->dpll_phase = DPLL_PHASE_6;
2135 channel->dpll_ctrl_n = DPLL_CTRL_6;
2136 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2137 break;
2138 case 7:
2139 channel->dpll_freq = DPLL_FREQ_7;
2140 channel->dpll_n = DPLL_7;
2141 channel->hw_dpll_n = HW_DPLL_7;
2142 channel->dpll_phase = DPLL_PHASE_7;
2143 channel->dpll_ctrl_n = DPLL_CTRL_7;
2144 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2145 break;
2146 default:
2147 err = -EINVAL;
2148 }
2149
2150 return err;
2151}
2152
930dfa56
ML		 2153/*
2154 * Compensate for the PTP DCO input-to-output delay.
2155 * This delay is 18 FOD cycles.
2156 */
2157static u32 idtcm_get_dco_delay(struct idtcm_channel *channel)
7ea5fda2 2158{
930dfa56
ML		 2159 struct idtcm *idtcm = channel->idtcm;
2160 u8 mbuf[8] = {0};
2161 u8 nbuf[2] = {0};
2162 u32 fodFreq;
7ea5fda2 2163 int err;
930dfa56
ML		 2164 u64 m;
2165 u16 n;
7ea5fda2 2166
930dfa56
ML		 2167 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2168 DPLL_CTRL_DPLL_FOD_FREQ, mbuf, 6);
2169 if (err)
2170 return 0;
7ea5fda2 2171
930dfa56
ML		 2172 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2173 DPLL_CTRL_DPLL_FOD_FREQ + 6, nbuf, 2);
2174 if (err)
2175 return 0;
da9facf1 2176
930dfa56
ML		 2177 m = get_unaligned_le64(mbuf);
2178 n = get_unaligned_le16(nbuf);
7ea5fda2 2179
930dfa56
ML		 2180 if (n == 0)
2181 n = 1;
2182
2183 fodFreq = (u32)div_u64(m, n);
bec67592 2184
930dfa56 2185 if (fodFreq >= 500000000)
bec67592 2186 return (u32)div_u64(18 * (u64)NSEC_PER_SEC, fodFreq);
930dfa56
ML		 2187
2188 return 0;
2189}
2190
2191static int configure_channel_tod(struct idtcm_channel *channel, u32 index)
2192{
2193 enum fw_version fw_ver = channel->idtcm->fw_ver;
7ea5fda2
ML		 2194
2195 /* Set tod addresses */
2196 switch (index) {
2197 case 0:
794c3dff 2198 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0);
bec67592 2199 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_0);
794c3dff
ML		 2200 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0);
2201 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0);
2202 channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
7ea5fda2
ML		 2203 break;
2204 case 1:
794c3dff 2205 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1);
bec67592 2206 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_1);
794c3dff
ML		 2207 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1);
2208 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1);
2209 channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
7ea5fda2
ML		 2210 break;
2211 case 2:
794c3dff 2212 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2);
bec67592 2213 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_2);
794c3dff
ML		 2214 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2);
2215 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2);
2216 channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
7ea5fda2
ML		 2217 break;
2218 case 3:
794c3dff 2219 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3);
bec67592 2220 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_3);
794c3dff
ML		 2221 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3);
2222 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3);
2223 channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
7ea5fda2 2224 break;
3a6ba7dc
VC		 2225 default:
2226 return -EINVAL;
2227 }
2228
930dfa56
ML		 2229 return 0;
2230}
2231
2232static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2233{
2234 struct idtcm_channel *channel;
2235 int err;
bec67592 2236 int i;
930dfa56
ML		 2237
2238 if (!(index < MAX_TOD))
2239 return -EINVAL;
2240
2241 channel = &idtcm->channel[index];
2242
2243 channel->idtcm = idtcm;
2244 channel->current_freq_scaled_ppm = 0;
2245
2246 /* Set pll addresses */
2247 err = configure_channel_pll(channel);
2248 if (err)
2249 return err;
2250
2251 /* Set tod addresses */
2252 err = configure_channel_tod(channel, index);
2253 if (err)
2254 return err;
2255
794c3dff 2256 if (idtcm->fw_ver < V487)
da948233 2257 channel->caps = idtcm_caps_deprecated;
7ea5fda2
ML		 2258 else
2259 channel->caps = idtcm_caps;
2260
3a6ba7dc 2261 snprintf(channel->caps.name, sizeof(channel->caps.name),
7ea5fda2
ML		 2262 "IDT CM TOD%u", index);
2263
bec67592
ML		 2264 channel->caps.pin_config = pin_config[index];
2265
2266 for (i = 0; i < channel->caps.n_pins; ++i) {
2267 struct ptp_pin_desc *ppd = &channel->caps.pin_config[i];
2268
2269 snprintf(ppd->name, sizeof(ppd->name), "input_ref%d", i);
2270 ppd->index = i;
2271 ppd->func = PTP_PF_NONE;
2272 ppd->chan = index;
2273 }
2274
da9facf1
ML		 2275 err = initialize_dco_operating_mode(channel);
2276 if (err)
3a6ba7dc
VC		 2277 return err;
2278
2279 err = idtcm_enable_tod(channel);
7ea5fda2 2280 if (err) {
930dfa56 2281 dev_err(idtcm->dev,
1c49d3e9 2282 "Failed at line %d in %s!", __LINE__, __func__);
3a6ba7dc 2283 return err;
7ea5fda2 2284 }
3a6ba7dc 2285
930dfa56
ML		 2286 channel->dco_delay = idtcm_get_dco_delay(channel);
2287
3a6ba7dc
VC		 2288 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2289
2290 if (IS_ERR(channel->ptp_clock)) {
2291 err = PTR_ERR(channel->ptp_clock);
2292 channel->ptp_clock = NULL;
2293 return err;
2294 }
2295
2296 if (!channel->ptp_clock)
2297 return -ENOTSUPP;
2298
930dfa56 2299 dev_info(idtcm->dev, "PLL%d registered as ptp%d",
3a6ba7dc
VC		 2300 index, channel->ptp_clock->index);
2301
2302 return 0;
2303}
2304
930dfa56
ML		 2305static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index)
2306{
2307 struct idtcm_channel *channel;
2308 int err;
2309
2310 if (!(index < MAX_TOD))
2311 return -EINVAL;
2312
2313 channel = &idtcm->channel[index];
2314 channel->idtcm = idtcm;
2315
2316 /* Set tod addresses */
2317 err = configure_channel_tod(channel, index);
2318 if (err)
2319 return err;
2320
2321 channel->idtcm = idtcm;
2322
2323 return 0;
2324}
2325
2326static void idtcm_extts_check(struct work_struct *work)
2327{
2328 struct idtcm *idtcm = container_of(work, struct idtcm, extts_work.work);
bec67592
ML		 2329 struct idtcm_channel *channel;
2330 u8 mask;
2331 int err;
2332 int i;
930dfa56
ML		 2333
2334 if (idtcm->extts_mask == 0)
2335 return;
2336
2337 mutex_lock(idtcm->lock);
bec67592 2338
930dfa56 2339 for (i = 0; i < MAX_TOD; i++) {
bec67592
ML		 2340 mask = 1 << i;
2341
2342 if ((idtcm->extts_mask & mask) == 0)
2343 continue;
2344
2345 err = idtcm_extts_check_channel(idtcm, i);
930dfa56 2346
bec67592 2347 if (err == 0) {
930dfa56 2348 /* trigger clears itself, so clear the mask */
bec67592 2349 if (idtcm->extts_single_shot) {
930dfa56 2350 idtcm->extts_mask &= ~mask;
bec67592
ML		 2351 } else {
2352 /* Re-arm */
2353 channel = &idtcm->channel[i];
2354 arm_tod_read_trig_sel_refclk(channel, channel->refn);
2355 }
930dfa56
ML		 2356 }
2357 }
2358
2359 if (idtcm->extts_mask)
2360 schedule_delayed_work(&idtcm->extts_work,
2361 msecs_to_jiffies(EXTTS_PERIOD_MS));
bec67592 2362
930dfa56
ML		 2363 mutex_unlock(idtcm->lock);
2364}
2365
3a6ba7dc
VC		 2366static void ptp_clock_unregister_all(struct idtcm *idtcm)
2367{
2368 u8 i;
2369 struct idtcm_channel *channel;
2370
7ea5fda2 2371 for (i = 0; i < MAX_TOD; i++) {
3a6ba7dc 2372 channel = &idtcm->channel[i];
3a6ba7dc
VC		 2373 if (channel->ptp_clock)
2374 ptp_clock_unregister(channel->ptp_clock);
2375 }
2376}
2377
2378static void set_default_masks(struct idtcm *idtcm)
2379{
7ea5fda2 2380 idtcm->tod_mask = DEFAULT_TOD_MASK;
930dfa56 2381 idtcm->extts_mask = 0;
7ea5fda2 2382
bec67592
ML		 2383 idtcm->channel[0].tod = 0;
2384 idtcm->channel[1].tod = 1;
2385 idtcm->channel[2].tod = 2;
2386 idtcm->channel[3].tod = 3;
2387
7ea5fda2
ML		 2388 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2389 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2390 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2391 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
3a6ba7dc
VC		 2392
2393 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2394 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2395 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2396 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2397}
2398
930dfa56 2399static int idtcm_probe(struct platform_device *pdev)
3a6ba7dc 2400{
930dfa56 2401 struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent);
3a6ba7dc
VC		 2402 struct idtcm *idtcm;
2403 int err;
2404 u8 i;
2405
930dfa56 2406 idtcm = devm_kzalloc(&pdev->dev, sizeof(struct idtcm), GFP_KERNEL);
3a6ba7dc
VC		 2407
2408 if (!idtcm)
2409 return -ENOMEM;
2410
930dfa56
ML		 2411 idtcm->dev = &pdev->dev;
2412 idtcm->mfd = pdev->dev.parent;
2413 idtcm->lock = &ddata->lock;
2414 idtcm->regmap = ddata->regmap;
3a6ba7dc
VC		 2415 idtcm->calculate_overhead_flag = 0;
2416
930dfa56
ML		 2417 INIT_DELAYED_WORK(&idtcm->extts_work, idtcm_extts_check);
2418
3a6ba7dc
VC		 2419 set_default_masks(idtcm);
2420
930dfa56 2421 mutex_lock(idtcm->lock);
3a6ba7dc 2422
da948233 2423 idtcm_set_version_info(idtcm);
3a6ba7dc 2424
930dfa56
ML		 2425 err = idtcm_load_firmware(idtcm, &pdev->dev);
2426
3a6ba7dc 2427 if (err)
930dfa56 2428 dev_warn(idtcm->dev, "loading firmware failed with %d", err);
3a6ba7dc 2429
797d3186 2430 wait_for_chip_ready(idtcm);
251f4fe2 2431
7ea5fda2
ML		 2432 if (idtcm->tod_mask) {
2433 for (i = 0; i < MAX_TOD; i++) {
930dfa56 2434 if (idtcm->tod_mask & (1 << i))
3a6ba7dc 2435 err = idtcm_enable_channel(idtcm, i);
930dfa56
ML		 2436 else
2437 err = idtcm_enable_extts_channel(idtcm, i);
2438 if (err) {
2439 dev_err(idtcm->dev,
2440 "idtcm_enable_channel %d failed!", i);
2441 break;
3a6ba7dc
VC		 2442 }
2443 }
2444 } else {
930dfa56 2445 dev_err(idtcm->dev,
1c49d3e9 2446 "no PLLs flagged as PHCs, nothing to do");
3a6ba7dc
VC		 2447 err = -ENODEV;
2448 }
2449
930dfa56 2450 mutex_unlock(idtcm->lock);
3a6ba7dc
VC		 2451
2452 if (err) {
2453 ptp_clock_unregister_all(idtcm);
2454 return err;
2455 }
2456
930dfa56 2457 platform_set_drvdata(pdev, idtcm);
3a6ba7dc
VC		 2458
2459 return 0;
2460}
2461
930dfa56 2462static int idtcm_remove(struct platform_device *pdev)
3a6ba7dc 2463{
930dfa56 2464 struct idtcm *idtcm = platform_get_drvdata(pdev);
3a6ba7dc 2465
bec67592 2466 idtcm->extts_mask = 0;
3a6ba7dc 2467 ptp_clock_unregister_all(idtcm);
930dfa56 2468 cancel_delayed_work_sync(&idtcm->extts_work);
3a6ba7dc
VC		 2469
2470 return 0;
2471}
2472
930dfa56 2473static struct platform_driver idtcm_driver = {
3a6ba7dc 2474 .driver = {
930dfa56 2475 .name = "8a3400x-phc",
3a6ba7dc 2476 },
930dfa56
ML		 2477 .probe = idtcm_probe,
2478 .remove = idtcm_remove,
3a6ba7dc
VC		 2479};
2480
930dfa56 2481module_platform_driver(idtcm_driver);
Linux 6.x block layer and io_uring tree(s)