Commit | Line | Data |
---|---|---|
f6cc69f1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2d281d81 | 2 | /* |
3382388d ZR |
3 | * Common code for Intel Running Average Power Limit (RAPL) support. |
4 | * Copyright (c) 2019, Intel Corporation. | |
2d281d81 JP |
5 | */ |
6 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/list.h> | |
11 | #include <linux/types.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/log2.h> | |
15 | #include <linux/bitmap.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/sysfs.h> | |
18 | #include <linux/cpu.h> | |
19 | #include <linux/powercap.h> | |
52b3672c | 20 | #include <linux/suspend.h> |
ff956826 | 21 | #include <linux/intel_rapl.h> |
3382388d | 22 | #include <linux/processor.h> |
abcfaeb3 ZR |
23 | #include <linux/platform_device.h> |
24 | ||
25 | #include <asm/iosf_mbi.h> | |
2d281d81 | 26 | #include <asm/cpu_device_id.h> |
62d16733 | 27 | #include <asm/intel-family.h> |
2d281d81 JP |
28 | |
29 | /* bitmasks for RAPL MSRs, used by primitive access functions */ | |
30 | #define ENERGY_STATUS_MASK 0xffffffff | |
31 | ||
32 | #define POWER_LIMIT1_MASK 0x7FFF | |
33 | #define POWER_LIMIT1_ENABLE BIT(15) | |
34 | #define POWER_LIMIT1_CLAMP BIT(16) | |
35 | ||
36 | #define POWER_LIMIT2_MASK (0x7FFFULL<<32) | |
37 | #define POWER_LIMIT2_ENABLE BIT_ULL(47) | |
38 | #define POWER_LIMIT2_CLAMP BIT_ULL(48) | |
0c2ddedd ZR |
39 | #define POWER_HIGH_LOCK BIT_ULL(63) |
40 | #define POWER_LOW_LOCK BIT(31) | |
2d281d81 | 41 | |
8365a898 SP |
42 | #define POWER_LIMIT4_MASK 0x1FFF |
43 | ||
2d281d81 JP |
44 | #define TIME_WINDOW1_MASK (0x7FULL<<17) |
45 | #define TIME_WINDOW2_MASK (0x7FULL<<49) | |
46 | ||
47 | #define POWER_UNIT_OFFSET 0 | |
48 | #define POWER_UNIT_MASK 0x0F | |
49 | ||
50 | #define ENERGY_UNIT_OFFSET 0x08 | |
51 | #define ENERGY_UNIT_MASK 0x1F00 | |
52 | ||
53 | #define TIME_UNIT_OFFSET 0x10 | |
54 | #define TIME_UNIT_MASK 0xF0000 | |
55 | ||
56 | #define POWER_INFO_MAX_MASK (0x7fffULL<<32) | |
57 | #define POWER_INFO_MIN_MASK (0x7fffULL<<16) | |
58 | #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) | |
59 | #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff | |
60 | ||
61 | #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff | |
62 | #define PP_POLICY_MASK 0x1F | |
63 | ||
931da6a0 ZR |
64 | /* |
65 | * SPR has different layout for Psys Domain PowerLimit registers. | |
66 | * There are 17 bits of PL1 and PL2 instead of 15 bits. | |
67 | * The Enable bits and TimeWindow bits are also shifted as a result. | |
68 | */ | |
69 | #define PSYS_POWER_LIMIT1_MASK 0x1FFFF | |
70 | #define PSYS_POWER_LIMIT1_ENABLE BIT(17) | |
71 | ||
72 | #define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32) | |
73 | #define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) | |
74 | ||
75 | #define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19) | |
76 | #define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51) | |
77 | ||
2d281d81 | 78 | /* Non HW constants */ |
3382388d | 79 | #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ |
2d281d81 JP |
80 | #define RAPL_PRIMITIVE_DUMMY BIT(2) |
81 | ||
2d281d81 JP |
82 | #define TIME_WINDOW_MAX_MSEC 40000 |
83 | #define TIME_WINDOW_MIN_MSEC 250 | |
3382388d | 84 | #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ |
2d281d81 | 85 | enum unit_type { |
3382388d | 86 | ARBITRARY_UNIT, /* no translation */ |
2d281d81 JP |
87 | POWER_UNIT, |
88 | ENERGY_UNIT, | |
89 | TIME_UNIT, | |
90 | }; | |
91 | ||
2d281d81 | 92 | /* per domain data, some are optional */ |
2d281d81 JP |
93 | #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) |
94 | ||
2d281d81 JP |
95 | #define DOMAIN_STATE_INACTIVE BIT(0) |
96 | #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) | |
97 | #define DOMAIN_STATE_BIOS_LOCKED BIT(2) | |
98 | ||
2d281d81 JP |
99 | static const char pl1_name[] = "long_term"; |
100 | static const char pl2_name[] = "short_term"; | |
8365a898 | 101 | static const char pl4_name[] = "peak_power"; |
2d281d81 | 102 | |
2d281d81 JP |
103 | #define power_zone_to_rapl_domain(_zone) \ |
104 | container_of(_zone, struct rapl_domain, power_zone) | |
105 | ||
087e9cba | 106 | struct rapl_defaults { |
51b63409 | 107 | u8 floor_freq_reg_addr; |
087e9cba JP |
108 | int (*check_unit)(struct rapl_package *rp, int cpu); |
109 | void (*set_floor_freq)(struct rapl_domain *rd, bool mode); | |
110 | u64 (*compute_time_window)(struct rapl_package *rp, u64 val, | |
3382388d | 111 | bool to_raw); |
d474a4d3 | 112 | unsigned int dram_domain_energy_unit; |
2d798d9f | 113 | unsigned int psys_domain_energy_unit; |
931da6a0 | 114 | bool spr_psys_bits; |
087e9cba JP |
115 | }; |
116 | static struct rapl_defaults *rapl_defaults; | |
117 | ||
3c2c0845 | 118 | /* Sideband MBI registers */ |
51b63409 AT |
119 | #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2) |
120 | #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf) | |
3c2c0845 | 121 | |
2d281d81 JP |
122 | #define PACKAGE_PLN_INT_SAVED BIT(0) |
123 | #define MAX_PRIM_NAME (32) | |
124 | ||
125 | /* per domain data. used to describe individual knobs such that access function | |
126 | * can be consolidated into one instead of many inline functions. | |
127 | */ | |
128 | struct rapl_primitive_info { | |
129 | const char *name; | |
130 | u64 mask; | |
131 | int shift; | |
f7c4e0c8 | 132 | enum rapl_domain_reg_id id; |
2d281d81 JP |
133 | enum unit_type unit; |
134 | u32 flag; | |
135 | }; | |
136 | ||
137 | #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ | |
138 | .name = #p, \ | |
139 | .mask = m, \ | |
140 | .shift = s, \ | |
141 | .id = i, \ | |
142 | .unit = u, \ | |
143 | .flag = f \ | |
144 | } | |
145 | ||
146 | static void rapl_init_domains(struct rapl_package *rp); | |
147 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
3382388d ZR |
148 | enum rapl_primitives prim, |
149 | bool xlate, u64 *data); | |
2d281d81 | 150 | static int rapl_write_data_raw(struct rapl_domain *rd, |
3382388d ZR |
151 | enum rapl_primitives prim, |
152 | unsigned long long value); | |
309557f5 | 153 | static u64 rapl_unit_xlate(struct rapl_domain *rd, |
3382388d | 154 | enum unit_type type, u64 value, int to_raw); |
309557f5 | 155 | static void package_power_limit_irq_save(struct rapl_package *rp); |
2d281d81 | 156 | |
3382388d | 157 | static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */ |
2d281d81 | 158 | |
3382388d | 159 | static const char *const rapl_domain_names[] = { |
2d281d81 JP |
160 | "package", |
161 | "core", | |
162 | "uncore", | |
163 | "dram", | |
3521ba1c | 164 | "psys", |
2d281d81 JP |
165 | }; |
166 | ||
3382388d ZR |
167 | static int get_energy_counter(struct powercap_zone *power_zone, |
168 | u64 *energy_raw) | |
2d281d81 JP |
169 | { |
170 | struct rapl_domain *rd; | |
171 | u64 energy_now; | |
172 | ||
173 | /* prevent CPU hotplug, make sure the RAPL domain does not go | |
174 | * away while reading the counter. | |
175 | */ | |
5d4c779c | 176 | cpus_read_lock(); |
2d281d81 JP |
177 | rd = power_zone_to_rapl_domain(power_zone); |
178 | ||
179 | if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { | |
180 | *energy_raw = energy_now; | |
5d4c779c | 181 | cpus_read_unlock(); |
2d281d81 JP |
182 | |
183 | return 0; | |
184 | } | |
5d4c779c | 185 | cpus_read_unlock(); |
2d281d81 JP |
186 | |
187 | return -EIO; | |
188 | } | |
189 | ||
190 | static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) | |
191 | { | |
d474a4d3 JP |
192 | struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); |
193 | ||
309557f5 | 194 | *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); |
2d281d81 JP |
195 | return 0; |
196 | } | |
197 | ||
198 | static int release_zone(struct powercap_zone *power_zone) | |
199 | { | |
200 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
309557f5 | 201 | struct rapl_package *rp = rd->rp; |
2d281d81 JP |
202 | |
203 | /* package zone is the last zone of a package, we can free | |
204 | * memory here since all children has been unregistered. | |
205 | */ | |
206 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
2d281d81 JP |
207 | kfree(rd); |
208 | rp->domains = NULL; | |
209 | } | |
210 | ||
211 | return 0; | |
212 | ||
213 | } | |
214 | ||
215 | static int find_nr_power_limit(struct rapl_domain *rd) | |
216 | { | |
e1399ba2 | 217 | int i, nr_pl = 0; |
2d281d81 JP |
218 | |
219 | for (i = 0; i < NR_POWER_LIMITS; i++) { | |
e1399ba2 JP |
220 | if (rd->rpl[i].name) |
221 | nr_pl++; | |
2d281d81 JP |
222 | } |
223 | ||
e1399ba2 | 224 | return nr_pl; |
2d281d81 JP |
225 | } |
226 | ||
227 | static int set_domain_enable(struct powercap_zone *power_zone, bool mode) | |
228 | { | |
229 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
2d281d81 JP |
230 | |
231 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) | |
232 | return -EACCES; | |
3c2c0845 | 233 | |
5d4c779c | 234 | cpus_read_lock(); |
2d281d81 | 235 | rapl_write_data_raw(rd, PL1_ENABLE, mode); |
51b63409 AT |
236 | if (rapl_defaults->set_floor_freq) |
237 | rapl_defaults->set_floor_freq(rd, mode); | |
5d4c779c | 238 | cpus_read_unlock(); |
2d281d81 JP |
239 | |
240 | return 0; | |
241 | } | |
242 | ||
243 | static int get_domain_enable(struct powercap_zone *power_zone, bool *mode) | |
244 | { | |
245 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
246 | u64 val; | |
247 | ||
248 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
249 | *mode = false; | |
250 | return 0; | |
251 | } | |
5d4c779c | 252 | cpus_read_lock(); |
2d281d81 | 253 | if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) { |
5d4c779c | 254 | cpus_read_unlock(); |
2d281d81 JP |
255 | return -EIO; |
256 | } | |
257 | *mode = val; | |
5d4c779c | 258 | cpus_read_unlock(); |
2d281d81 JP |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
263 | /* per RAPL domain ops, in the order of rapl_domain_type */ | |
600c395b | 264 | static const struct powercap_zone_ops zone_ops[] = { |
2d281d81 JP |
265 | /* RAPL_DOMAIN_PACKAGE */ |
266 | { | |
3382388d ZR |
267 | .get_energy_uj = get_energy_counter, |
268 | .get_max_energy_range_uj = get_max_energy_counter, | |
269 | .release = release_zone, | |
270 | .set_enable = set_domain_enable, | |
271 | .get_enable = get_domain_enable, | |
272 | }, | |
2d281d81 JP |
273 | /* RAPL_DOMAIN_PP0 */ |
274 | { | |
3382388d ZR |
275 | .get_energy_uj = get_energy_counter, |
276 | .get_max_energy_range_uj = get_max_energy_counter, | |
277 | .release = release_zone, | |
278 | .set_enable = set_domain_enable, | |
279 | .get_enable = get_domain_enable, | |
280 | }, | |
2d281d81 JP |
281 | /* RAPL_DOMAIN_PP1 */ |
282 | { | |
3382388d ZR |
283 | .get_energy_uj = get_energy_counter, |
284 | .get_max_energy_range_uj = get_max_energy_counter, | |
285 | .release = release_zone, | |
286 | .set_enable = set_domain_enable, | |
287 | .get_enable = get_domain_enable, | |
288 | }, | |
2d281d81 JP |
289 | /* RAPL_DOMAIN_DRAM */ |
290 | { | |
3382388d ZR |
291 | .get_energy_uj = get_energy_counter, |
292 | .get_max_energy_range_uj = get_max_energy_counter, | |
293 | .release = release_zone, | |
294 | .set_enable = set_domain_enable, | |
295 | .get_enable = get_domain_enable, | |
296 | }, | |
3521ba1c SP |
297 | /* RAPL_DOMAIN_PLATFORM */ |
298 | { | |
3382388d ZR |
299 | .get_energy_uj = get_energy_counter, |
300 | .get_max_energy_range_uj = get_max_energy_counter, | |
301 | .release = release_zone, | |
302 | .set_enable = set_domain_enable, | |
303 | .get_enable = get_domain_enable, | |
304 | }, | |
2d281d81 JP |
305 | }; |
306 | ||
e1399ba2 JP |
307 | /* |
308 | * Constraint index used by powercap can be different than power limit (PL) | |
3382388d | 309 | * index in that some PLs maybe missing due to non-existent MSRs. So we |
e1399ba2 JP |
310 | * need to convert here by finding the valid PLs only (name populated). |
311 | */ | |
312 | static int contraint_to_pl(struct rapl_domain *rd, int cid) | |
313 | { | |
314 | int i, j; | |
315 | ||
316 | for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) { | |
317 | if ((rd->rpl[i].name) && j++ == cid) { | |
318 | pr_debug("%s: index %d\n", __func__, i); | |
319 | return i; | |
320 | } | |
321 | } | |
cb43f81b | 322 | pr_err("Cannot find matching power limit for constraint %d\n", cid); |
e1399ba2 JP |
323 | |
324 | return -EINVAL; | |
325 | } | |
326 | ||
327 | static int set_power_limit(struct powercap_zone *power_zone, int cid, | |
3382388d | 328 | u64 power_limit) |
2d281d81 JP |
329 | { |
330 | struct rapl_domain *rd; | |
331 | struct rapl_package *rp; | |
332 | int ret = 0; | |
e1399ba2 | 333 | int id; |
2d281d81 | 334 | |
5d4c779c | 335 | cpus_read_lock(); |
2d281d81 | 336 | rd = power_zone_to_rapl_domain(power_zone); |
e1399ba2 | 337 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
338 | if (id < 0) { |
339 | ret = id; | |
340 | goto set_exit; | |
341 | } | |
e1399ba2 | 342 | |
309557f5 | 343 | rp = rd->rp; |
2d281d81 JP |
344 | |
345 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
3382388d ZR |
346 | dev_warn(&power_zone->dev, |
347 | "%s locked by BIOS, monitoring only\n", rd->name); | |
2d281d81 JP |
348 | ret = -EACCES; |
349 | goto set_exit; | |
350 | } | |
351 | ||
352 | switch (rd->rpl[id].prim_id) { | |
353 | case PL1_ENABLE: | |
354 | rapl_write_data_raw(rd, POWER_LIMIT1, power_limit); | |
355 | break; | |
356 | case PL2_ENABLE: | |
357 | rapl_write_data_raw(rd, POWER_LIMIT2, power_limit); | |
358 | break; | |
8365a898 SP |
359 | case PL4_ENABLE: |
360 | rapl_write_data_raw(rd, POWER_LIMIT4, power_limit); | |
361 | break; | |
2d281d81 JP |
362 | default: |
363 | ret = -EINVAL; | |
364 | } | |
365 | if (!ret) | |
309557f5 | 366 | package_power_limit_irq_save(rp); |
2d281d81 | 367 | set_exit: |
5d4c779c | 368 | cpus_read_unlock(); |
2d281d81 JP |
369 | return ret; |
370 | } | |
371 | ||
e1399ba2 | 372 | static int get_current_power_limit(struct powercap_zone *power_zone, int cid, |
3382388d | 373 | u64 *data) |
2d281d81 JP |
374 | { |
375 | struct rapl_domain *rd; | |
376 | u64 val; | |
377 | int prim; | |
378 | int ret = 0; | |
e1399ba2 | 379 | int id; |
2d281d81 | 380 | |
5d4c779c | 381 | cpus_read_lock(); |
2d281d81 | 382 | rd = power_zone_to_rapl_domain(power_zone); |
e1399ba2 | 383 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
384 | if (id < 0) { |
385 | ret = id; | |
386 | goto get_exit; | |
387 | } | |
388 | ||
2d281d81 JP |
389 | switch (rd->rpl[id].prim_id) { |
390 | case PL1_ENABLE: | |
391 | prim = POWER_LIMIT1; | |
392 | break; | |
393 | case PL2_ENABLE: | |
394 | prim = POWER_LIMIT2; | |
395 | break; | |
8365a898 SP |
396 | case PL4_ENABLE: |
397 | prim = POWER_LIMIT4; | |
398 | break; | |
2d281d81 | 399 | default: |
5d4c779c | 400 | cpus_read_unlock(); |
2d281d81 JP |
401 | return -EINVAL; |
402 | } | |
403 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
404 | ret = -EIO; | |
405 | else | |
406 | *data = val; | |
407 | ||
cb43f81b | 408 | get_exit: |
5d4c779c | 409 | cpus_read_unlock(); |
2d281d81 JP |
410 | |
411 | return ret; | |
412 | } | |
413 | ||
e1399ba2 | 414 | static int set_time_window(struct powercap_zone *power_zone, int cid, |
3382388d | 415 | u64 window) |
2d281d81 JP |
416 | { |
417 | struct rapl_domain *rd; | |
418 | int ret = 0; | |
e1399ba2 | 419 | int id; |
2d281d81 | 420 | |
5d4c779c | 421 | cpus_read_lock(); |
2d281d81 | 422 | rd = power_zone_to_rapl_domain(power_zone); |
e1399ba2 | 423 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
424 | if (id < 0) { |
425 | ret = id; | |
426 | goto set_time_exit; | |
427 | } | |
e1399ba2 | 428 | |
2d281d81 JP |
429 | switch (rd->rpl[id].prim_id) { |
430 | case PL1_ENABLE: | |
431 | rapl_write_data_raw(rd, TIME_WINDOW1, window); | |
432 | break; | |
433 | case PL2_ENABLE: | |
434 | rapl_write_data_raw(rd, TIME_WINDOW2, window); | |
435 | break; | |
436 | default: | |
437 | ret = -EINVAL; | |
438 | } | |
cb43f81b JP |
439 | |
440 | set_time_exit: | |
5d4c779c | 441 | cpus_read_unlock(); |
2d281d81 JP |
442 | return ret; |
443 | } | |
444 | ||
3382388d ZR |
445 | static int get_time_window(struct powercap_zone *power_zone, int cid, |
446 | u64 *data) | |
2d281d81 JP |
447 | { |
448 | struct rapl_domain *rd; | |
449 | u64 val; | |
450 | int ret = 0; | |
e1399ba2 | 451 | int id; |
2d281d81 | 452 | |
5d4c779c | 453 | cpus_read_lock(); |
2d281d81 | 454 | rd = power_zone_to_rapl_domain(power_zone); |
e1399ba2 | 455 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
456 | if (id < 0) { |
457 | ret = id; | |
458 | goto get_time_exit; | |
459 | } | |
e1399ba2 | 460 | |
2d281d81 JP |
461 | switch (rd->rpl[id].prim_id) { |
462 | case PL1_ENABLE: | |
463 | ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val); | |
464 | break; | |
465 | case PL2_ENABLE: | |
466 | ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val); | |
467 | break; | |
8365a898 SP |
468 | case PL4_ENABLE: |
469 | /* | |
470 | * Time window parameter is not applicable for PL4 entry | |
471 | * so assigining '0' as default value. | |
472 | */ | |
473 | val = 0; | |
474 | break; | |
2d281d81 | 475 | default: |
5d4c779c | 476 | cpus_read_unlock(); |
2d281d81 JP |
477 | return -EINVAL; |
478 | } | |
479 | if (!ret) | |
480 | *data = val; | |
cb43f81b JP |
481 | |
482 | get_time_exit: | |
5d4c779c | 483 | cpus_read_unlock(); |
2d281d81 JP |
484 | |
485 | return ret; | |
486 | } | |
487 | ||
3382388d ZR |
488 | static const char *get_constraint_name(struct powercap_zone *power_zone, |
489 | int cid) | |
2d281d81 | 490 | { |
2d281d81 | 491 | struct rapl_domain *rd; |
e1399ba2 | 492 | int id; |
2d281d81 JP |
493 | |
494 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 JP |
495 | id = contraint_to_pl(rd, cid); |
496 | if (id >= 0) | |
497 | return rd->rpl[id].name; | |
2d281d81 | 498 | |
e1399ba2 | 499 | return NULL; |
2d281d81 JP |
500 | } |
501 | ||
3382388d | 502 | static int get_max_power(struct powercap_zone *power_zone, int id, u64 *data) |
2d281d81 JP |
503 | { |
504 | struct rapl_domain *rd; | |
505 | u64 val; | |
506 | int prim; | |
507 | int ret = 0; | |
508 | ||
5d4c779c | 509 | cpus_read_lock(); |
2d281d81 JP |
510 | rd = power_zone_to_rapl_domain(power_zone); |
511 | switch (rd->rpl[id].prim_id) { | |
512 | case PL1_ENABLE: | |
513 | prim = THERMAL_SPEC_POWER; | |
514 | break; | |
515 | case PL2_ENABLE: | |
516 | prim = MAX_POWER; | |
517 | break; | |
8365a898 SP |
518 | case PL4_ENABLE: |
519 | prim = MAX_POWER; | |
520 | break; | |
2d281d81 | 521 | default: |
5d4c779c | 522 | cpus_read_unlock(); |
2d281d81 JP |
523 | return -EINVAL; |
524 | } | |
525 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
526 | ret = -EIO; | |
527 | else | |
528 | *data = val; | |
529 | ||
8365a898 SP |
530 | /* As a generalization rule, PL4 would be around two times PL2. */ |
531 | if (rd->rpl[id].prim_id == PL4_ENABLE) | |
532 | *data = *data * 2; | |
533 | ||
5d4c779c | 534 | cpus_read_unlock(); |
2d281d81 JP |
535 | |
536 | return ret; | |
537 | } | |
538 | ||
600c395b | 539 | static const struct powercap_zone_constraint_ops constraint_ops = { |
2d281d81 JP |
540 | .set_power_limit_uw = set_power_limit, |
541 | .get_power_limit_uw = get_current_power_limit, | |
542 | .set_time_window_us = set_time_window, | |
543 | .get_time_window_us = get_time_window, | |
544 | .get_max_power_uw = get_max_power, | |
545 | .get_name = get_constraint_name, | |
546 | }; | |
547 | ||
548 | /* called after domain detection and package level data are set */ | |
549 | static void rapl_init_domains(struct rapl_package *rp) | |
550 | { | |
0c2ddedd ZR |
551 | enum rapl_domain_type i; |
552 | enum rapl_domain_reg_id j; | |
2d281d81 JP |
553 | struct rapl_domain *rd = rp->domains; |
554 | ||
555 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
556 | unsigned int mask = rp->domain_map & (1 << i); | |
7fde2712 | 557 | |
0c2ddedd ZR |
558 | if (!mask) |
559 | continue; | |
560 | ||
561 | rd->rp = rp; | |
f1e8d756 ZR |
562 | |
563 | if (i == RAPL_DOMAIN_PLATFORM && rp->id > 0) { | |
564 | snprintf(rd->name, RAPL_DOMAIN_NAME_LENGTH, "psys-%d", | |
65348ba2 | 565 | topology_physical_package_id(rp->lead_cpu)); |
f1e8d756 ZR |
566 | } else |
567 | snprintf(rd->name, RAPL_DOMAIN_NAME_LENGTH, "%s", | |
568 | rapl_domain_names[i]); | |
569 | ||
0c2ddedd ZR |
570 | rd->id = i; |
571 | rd->rpl[0].prim_id = PL1_ENABLE; | |
572 | rd->rpl[0].name = pl1_name; | |
8365a898 SP |
573 | |
574 | /* | |
575 | * The PL2 power domain is applicable for limits two | |
576 | * and limits three | |
577 | */ | |
578 | if (rp->priv->limits[i] >= 2) { | |
2d281d81 JP |
579 | rd->rpl[1].prim_id = PL2_ENABLE; |
580 | rd->rpl[1].name = pl2_name; | |
0c2ddedd ZR |
581 | } |
582 | ||
8365a898 SP |
583 | /* Enable PL4 domain if the total power limits are three */ |
584 | if (rp->priv->limits[i] == 3) { | |
585 | rd->rpl[2].prim_id = PL4_ENABLE; | |
586 | rd->rpl[2].name = pl4_name; | |
587 | } | |
588 | ||
0c2ddedd ZR |
589 | for (j = 0; j < RAPL_DOMAIN_REG_MAX; j++) |
590 | rd->regs[j] = rp->priv->regs[i][j]; | |
591 | ||
2d798d9f ZR |
592 | switch (i) { |
593 | case RAPL_DOMAIN_DRAM: | |
d474a4d3 | 594 | rd->domain_energy_unit = |
3382388d | 595 | rapl_defaults->dram_domain_energy_unit; |
d474a4d3 JP |
596 | if (rd->domain_energy_unit) |
597 | pr_info("DRAM domain energy unit %dpj\n", | |
598 | rd->domain_energy_unit); | |
2d798d9f ZR |
599 | break; |
600 | case RAPL_DOMAIN_PLATFORM: | |
601 | rd->domain_energy_unit = | |
602 | rapl_defaults->psys_domain_energy_unit; | |
603 | if (rd->domain_energy_unit) | |
604 | pr_info("Platform domain energy unit %dpj\n", | |
605 | rd->domain_energy_unit); | |
606 | break; | |
607 | default: | |
608 | break; | |
2d281d81 | 609 | } |
0c2ddedd | 610 | rd++; |
2d281d81 JP |
611 | } |
612 | } | |
613 | ||
309557f5 | 614 | static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type, |
3382388d | 615 | u64 value, int to_raw) |
2d281d81 | 616 | { |
3c2c0845 | 617 | u64 units = 1; |
309557f5 | 618 | struct rapl_package *rp = rd->rp; |
d474a4d3 | 619 | u64 scale = 1; |
2d281d81 | 620 | |
2d281d81 JP |
621 | switch (type) { |
622 | case POWER_UNIT: | |
3c2c0845 | 623 | units = rp->power_unit; |
2d281d81 JP |
624 | break; |
625 | case ENERGY_UNIT: | |
d474a4d3 JP |
626 | scale = ENERGY_UNIT_SCALE; |
627 | /* per domain unit takes precedence */ | |
cb43f81b | 628 | if (rd->domain_energy_unit) |
d474a4d3 JP |
629 | units = rd->domain_energy_unit; |
630 | else | |
631 | units = rp->energy_unit; | |
2d281d81 JP |
632 | break; |
633 | case TIME_UNIT: | |
3c2c0845 | 634 | return rapl_defaults->compute_time_window(rp, value, to_raw); |
2d281d81 JP |
635 | case ARBITRARY_UNIT: |
636 | default: | |
637 | return value; | |
a8193af7 | 638 | } |
2d281d81 JP |
639 | |
640 | if (to_raw) | |
d474a4d3 | 641 | return div64_u64(value, units) * scale; |
3c2c0845 JP |
642 | |
643 | value *= units; | |
644 | ||
d474a4d3 | 645 | return div64_u64(value, scale); |
2d281d81 JP |
646 | } |
647 | ||
648 | /* in the order of enum rapl_primitives */ | |
649 | static struct rapl_primitive_info rpi[] = { | |
650 | /* name, mask, shift, msr index, unit divisor */ | |
651 | PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, | |
3382388d | 652 | RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), |
2d281d81 | 653 | PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, |
3382388d | 654 | RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), |
2d281d81 | 655 | PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, |
3382388d | 656 | RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), |
8365a898 SP |
657 | PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0, |
658 | RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), | |
0c2ddedd | 659 | PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, |
3382388d | 660 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 661 | PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, |
3382388d | 662 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 663 | PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, |
3382388d | 664 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 665 | PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, |
3382388d | 666 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
2d281d81 | 667 | PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, |
3382388d | 668 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), |
8365a898 SP |
669 | PRIMITIVE_INFO_INIT(PL4_ENABLE, POWER_LIMIT4_MASK, 0, |
670 | RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), | |
2d281d81 | 671 | PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, |
3382388d | 672 | RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), |
2d281d81 | 673 | PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, |
3382388d | 674 | RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), |
2d281d81 | 675 | PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK, |
3382388d | 676 | 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), |
2d281d81 | 677 | PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, |
3382388d | 678 | RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), |
2d281d81 | 679 | PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, |
3382388d | 680 | RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), |
2d281d81 | 681 | PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48, |
3382388d | 682 | RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), |
2d281d81 | 683 | PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, |
3382388d | 684 | RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), |
2d281d81 | 685 | PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, |
3382388d | 686 | RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), |
931da6a0 ZR |
687 | PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0, |
688 | RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), | |
689 | PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK, 32, | |
690 | RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), | |
691 | PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE, 17, | |
692 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), | |
693 | PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE, 49, | |
694 | RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), | |
695 | PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK, 19, | |
696 | RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), | |
697 | PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK, 51, | |
698 | RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), | |
2d281d81 JP |
699 | /* non-hardware */ |
700 | PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT, | |
3382388d | 701 | RAPL_PRIMITIVE_DERIVED), |
2d281d81 JP |
702 | {NULL, 0, 0, 0}, |
703 | }; | |
704 | ||
931da6a0 ZR |
705 | static enum rapl_primitives |
706 | prim_fixups(struct rapl_domain *rd, enum rapl_primitives prim) | |
707 | { | |
708 | if (!rapl_defaults->spr_psys_bits) | |
709 | return prim; | |
710 | ||
711 | if (rd->id != RAPL_DOMAIN_PLATFORM) | |
712 | return prim; | |
713 | ||
714 | switch (prim) { | |
715 | case POWER_LIMIT1: | |
716 | return PSYS_POWER_LIMIT1; | |
717 | case POWER_LIMIT2: | |
718 | return PSYS_POWER_LIMIT2; | |
719 | case PL1_ENABLE: | |
720 | return PSYS_PL1_ENABLE; | |
721 | case PL2_ENABLE: | |
722 | return PSYS_PL2_ENABLE; | |
723 | case TIME_WINDOW1: | |
724 | return PSYS_TIME_WINDOW1; | |
725 | case TIME_WINDOW2: | |
726 | return PSYS_TIME_WINDOW2; | |
727 | default: | |
728 | return prim; | |
729 | } | |
730 | } | |
731 | ||
2d281d81 JP |
732 | /* Read primitive data based on its related struct rapl_primitive_info. |
733 | * if xlate flag is set, return translated data based on data units, i.e. | |
734 | * time, energy, and power. | |
735 | * RAPL MSRs are non-architectual and are laid out not consistently across | |
736 | * domains. Here we use primitive info to allow writing consolidated access | |
737 | * functions. | |
738 | * For a given primitive, it is processed by MSR mask and shift. Unit conversion | |
739 | * is pre-assigned based on RAPL unit MSRs read at init time. | |
740 | * 63-------------------------- 31--------------------------- 0 | |
741 | * | xxxxx (mask) | | |
742 | * | |<- shift ----------------| | |
743 | * 63-------------------------- 31--------------------------- 0 | |
744 | */ | |
745 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
3382388d | 746 | enum rapl_primitives prim, bool xlate, u64 *data) |
2d281d81 | 747 | { |
beea8df8 | 748 | u64 value; |
931da6a0 ZR |
749 | enum rapl_primitives prim_fixed = prim_fixups(rd, prim); |
750 | struct rapl_primitive_info *rp = &rpi[prim_fixed]; | |
beea8df8 | 751 | struct reg_action ra; |
2d281d81 JP |
752 | int cpu; |
753 | ||
754 | if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY) | |
755 | return -EINVAL; | |
756 | ||
beea8df8 ZR |
757 | ra.reg = rd->regs[rp->id]; |
758 | if (!ra.reg) | |
2d281d81 | 759 | return -EINVAL; |
323ee64a JP |
760 | |
761 | cpu = rd->rp->lead_cpu; | |
2d281d81 | 762 | |
0c2ddedd ZR |
763 | /* domain with 2 limits has different bit */ |
764 | if (prim == FW_LOCK && rd->rp->priv->limits[rd->id] == 2) { | |
765 | rp->mask = POWER_HIGH_LOCK; | |
2d281d81 JP |
766 | rp->shift = 63; |
767 | } | |
768 | /* non-hardware data are collected by the polling thread */ | |
769 | if (rp->flag & RAPL_PRIMITIVE_DERIVED) { | |
770 | *data = rd->rdd.primitives[prim]; | |
771 | return 0; | |
772 | } | |
773 | ||
beea8df8 ZR |
774 | ra.mask = rp->mask; |
775 | ||
776 | if (rd->rp->priv->read_raw(cpu, &ra)) { | |
d978e755 | 777 | pr_debug("failed to read reg 0x%llx on cpu %d\n", ra.reg, cpu); |
2d281d81 JP |
778 | return -EIO; |
779 | } | |
780 | ||
beea8df8 ZR |
781 | value = ra.value >> rp->shift; |
782 | ||
2d281d81 | 783 | if (xlate) |
beea8df8 | 784 | *data = rapl_unit_xlate(rd, rp->unit, value, 0); |
2d281d81 | 785 | else |
beea8df8 | 786 | *data = value; |
2d281d81 JP |
787 | |
788 | return 0; | |
789 | } | |
790 | ||
791 | /* Similar use of primitive info in the read counterpart */ | |
792 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
3382388d ZR |
793 | enum rapl_primitives prim, |
794 | unsigned long long value) | |
2d281d81 | 795 | { |
931da6a0 ZR |
796 | enum rapl_primitives prim_fixed = prim_fixups(rd, prim); |
797 | struct rapl_primitive_info *rp = &rpi[prim_fixed]; | |
2d281d81 | 798 | int cpu; |
f14a1396 | 799 | u64 bits; |
beea8df8 | 800 | struct reg_action ra; |
f14a1396 | 801 | int ret; |
2d281d81 | 802 | |
323ee64a | 803 | cpu = rd->rp->lead_cpu; |
309557f5 | 804 | bits = rapl_unit_xlate(rd, rp->unit, value, 1); |
edbdabc6 AL |
805 | bits <<= rp->shift; |
806 | bits &= rp->mask; | |
807 | ||
beea8df8 | 808 | memset(&ra, 0, sizeof(ra)); |
f14a1396 | 809 | |
beea8df8 ZR |
810 | ra.reg = rd->regs[rp->id]; |
811 | ra.mask = rp->mask; | |
812 | ra.value = bits; | |
f14a1396 | 813 | |
beea8df8 | 814 | ret = rd->rp->priv->write_raw(cpu, &ra); |
f14a1396 JP |
815 | |
816 | return ret; | |
2d281d81 JP |
817 | } |
818 | ||
3c2c0845 JP |
819 | /* |
820 | * Raw RAPL data stored in MSRs are in certain scales. We need to | |
821 | * convert them into standard units based on the units reported in | |
822 | * the RAPL unit MSRs. This is specific to CPUs as the method to | |
823 | * calculate units differ on different CPUs. | |
824 | * We convert the units to below format based on CPUs. | |
825 | * i.e. | |
d474a4d3 | 826 | * energy unit: picoJoules : Represented in picoJoules by default |
3c2c0845 JP |
827 | * power unit : microWatts : Represented in milliWatts by default |
828 | * time unit : microseconds: Represented in seconds by default | |
829 | */ | |
830 | static int rapl_check_unit_core(struct rapl_package *rp, int cpu) | |
2d281d81 | 831 | { |
1193b165 | 832 | struct reg_action ra; |
2d281d81 JP |
833 | u32 value; |
834 | ||
1193b165 ZR |
835 | ra.reg = rp->priv->reg_unit; |
836 | ra.mask = ~0; | |
837 | if (rp->priv->read_raw(cpu, &ra)) { | |
d978e755 | 838 | pr_err("Failed to read power unit REG 0x%llx on CPU %d, exit.\n", |
3382388d | 839 | rp->priv->reg_unit, cpu); |
2d281d81 JP |
840 | return -ENODEV; |
841 | } | |
842 | ||
1193b165 | 843 | value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; |
d474a4d3 | 844 | rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); |
2d281d81 | 845 | |
1193b165 | 846 | value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; |
3c2c0845 | 847 | rp->power_unit = 1000000 / (1 << value); |
2d281d81 | 848 | |
1193b165 | 849 | value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; |
3c2c0845 | 850 | rp->time_unit = 1000000 / (1 << value); |
2d281d81 | 851 | |
9ea7612c | 852 | pr_debug("Core CPU %s energy=%dpJ, time=%dus, power=%duW\n", |
3382388d | 853 | rp->name, rp->energy_unit, rp->time_unit, rp->power_unit); |
2d281d81 JP |
854 | |
855 | return 0; | |
856 | } | |
857 | ||
3c2c0845 JP |
858 | static int rapl_check_unit_atom(struct rapl_package *rp, int cpu) |
859 | { | |
1193b165 | 860 | struct reg_action ra; |
3c2c0845 JP |
861 | u32 value; |
862 | ||
1193b165 ZR |
863 | ra.reg = rp->priv->reg_unit; |
864 | ra.mask = ~0; | |
865 | if (rp->priv->read_raw(cpu, &ra)) { | |
d978e755 | 866 | pr_err("Failed to read power unit REG 0x%llx on CPU %d, exit.\n", |
3382388d | 867 | rp->priv->reg_unit, cpu); |
3c2c0845 JP |
868 | return -ENODEV; |
869 | } | |
1193b165 ZR |
870 | |
871 | value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; | |
d474a4d3 | 872 | rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value; |
3c2c0845 | 873 | |
1193b165 | 874 | value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; |
3c2c0845 JP |
875 | rp->power_unit = (1 << value) * 1000; |
876 | ||
1193b165 | 877 | value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; |
3c2c0845 JP |
878 | rp->time_unit = 1000000 / (1 << value); |
879 | ||
9ea7612c | 880 | pr_debug("Atom %s energy=%dpJ, time=%dus, power=%duW\n", |
3382388d | 881 | rp->name, rp->energy_unit, rp->time_unit, rp->power_unit); |
3c2c0845 JP |
882 | |
883 | return 0; | |
884 | } | |
885 | ||
f14a1396 JP |
886 | static void power_limit_irq_save_cpu(void *info) |
887 | { | |
888 | u32 l, h = 0; | |
889 | struct rapl_package *rp = (struct rapl_package *)info; | |
890 | ||
891 | /* save the state of PLN irq mask bit before disabling it */ | |
892 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
893 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) { | |
894 | rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE; | |
895 | rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED; | |
896 | } | |
897 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
898 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
899 | } | |
900 | ||
2d281d81 JP |
901 | /* REVISIT: |
902 | * When package power limit is set artificially low by RAPL, LVT | |
903 | * thermal interrupt for package power limit should be ignored | |
904 | * since we are not really exceeding the real limit. The intention | |
905 | * is to avoid excessive interrupts while we are trying to save power. | |
906 | * A useful feature might be routing the package_power_limit interrupt | |
907 | * to userspace via eventfd. once we have a usecase, this is simple | |
908 | * to do by adding an atomic notifier. | |
909 | */ | |
910 | ||
309557f5 | 911 | static void package_power_limit_irq_save(struct rapl_package *rp) |
2d281d81 | 912 | { |
f14a1396 JP |
913 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) |
914 | return; | |
915 | ||
323ee64a | 916 | smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1); |
f14a1396 JP |
917 | } |
918 | ||
58705069 TG |
919 | /* |
920 | * Restore per package power limit interrupt enable state. Called from cpu | |
921 | * hotplug code on package removal. | |
922 | */ | |
923 | static void package_power_limit_irq_restore(struct rapl_package *rp) | |
f14a1396 | 924 | { |
58705069 TG |
925 | u32 l, h; |
926 | ||
927 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) | |
928 | return; | |
929 | ||
930 | /* irq enable state not saved, nothing to restore */ | |
931 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) | |
932 | return; | |
f14a1396 JP |
933 | |
934 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
935 | ||
936 | if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE) | |
937 | l |= PACKAGE_THERM_INT_PLN_ENABLE; | |
938 | else | |
939 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
940 | ||
941 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
2d281d81 JP |
942 | } |
943 | ||
3c2c0845 JP |
944 | static void set_floor_freq_default(struct rapl_domain *rd, bool mode) |
945 | { | |
946 | int nr_powerlimit = find_nr_power_limit(rd); | |
947 | ||
948 | /* always enable clamp such that p-state can go below OS requested | |
949 | * range. power capping priority over guranteed frequency. | |
950 | */ | |
951 | rapl_write_data_raw(rd, PL1_CLAMP, mode); | |
952 | ||
953 | /* some domains have pl2 */ | |
954 | if (nr_powerlimit > 1) { | |
955 | rapl_write_data_raw(rd, PL2_ENABLE, mode); | |
956 | rapl_write_data_raw(rd, PL2_CLAMP, mode); | |
957 | } | |
958 | } | |
959 | ||
960 | static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) | |
961 | { | |
962 | static u32 power_ctrl_orig_val; | |
963 | u32 mdata; | |
964 | ||
51b63409 AT |
965 | if (!rapl_defaults->floor_freq_reg_addr) { |
966 | pr_err("Invalid floor frequency config register\n"); | |
967 | return; | |
968 | } | |
969 | ||
3c2c0845 | 970 | if (!power_ctrl_orig_val) |
4077a387 AS |
971 | iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, |
972 | rapl_defaults->floor_freq_reg_addr, | |
973 | &power_ctrl_orig_val); | |
3c2c0845 JP |
974 | mdata = power_ctrl_orig_val; |
975 | if (enable) { | |
976 | mdata &= ~(0x7f << 8); | |
977 | mdata |= 1 << 8; | |
978 | } | |
4077a387 AS |
979 | iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, |
980 | rapl_defaults->floor_freq_reg_addr, mdata); | |
3c2c0845 JP |
981 | } |
982 | ||
983 | static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value, | |
3382388d | 984 | bool to_raw) |
3c2c0845 | 985 | { |
3382388d | 986 | u64 f, y; /* fraction and exp. used for time unit */ |
3c2c0845 JP |
987 | |
988 | /* | |
989 | * Special processing based on 2^Y*(1+F/4), refer | |
990 | * to Intel Software Developer's manual Vol.3B: CH 14.9.3. | |
991 | */ | |
992 | if (!to_raw) { | |
993 | f = (value & 0x60) >> 5; | |
994 | y = value & 0x1f; | |
995 | value = (1 << y) * (4 + f) * rp->time_unit / 4; | |
996 | } else { | |
997 | do_div(value, rp->time_unit); | |
998 | y = ilog2(value); | |
999 | f = div64_u64(4 * (value - (1 << y)), 1 << y); | |
1000 | value = (y & 0x1f) | ((f & 0x3) << 5); | |
1001 | } | |
1002 | return value; | |
1003 | } | |
1004 | ||
1005 | static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value, | |
3382388d | 1006 | bool to_raw) |
3c2c0845 JP |
1007 | { |
1008 | /* | |
1009 | * Atom time unit encoding is straight forward val * time_unit, | |
1010 | * where time_unit is default to 1 sec. Never 0. | |
1011 | */ | |
1012 | if (!to_raw) | |
59cafa72 | 1013 | return (value) ? value * rp->time_unit : rp->time_unit; |
3382388d ZR |
1014 | |
1015 | value = div64_u64(value, rp->time_unit); | |
3c2c0845 JP |
1016 | |
1017 | return value; | |
1018 | } | |
1019 | ||
087e9cba | 1020 | static const struct rapl_defaults rapl_defaults_core = { |
51b63409 | 1021 | .floor_freq_reg_addr = 0, |
3c2c0845 JP |
1022 | .check_unit = rapl_check_unit_core, |
1023 | .set_floor_freq = set_floor_freq_default, | |
1024 | .compute_time_window = rapl_compute_time_window_core, | |
087e9cba JP |
1025 | }; |
1026 | ||
d474a4d3 JP |
1027 | static const struct rapl_defaults rapl_defaults_hsw_server = { |
1028 | .check_unit = rapl_check_unit_core, | |
1029 | .set_floor_freq = set_floor_freq_default, | |
1030 | .compute_time_window = rapl_compute_time_window_core, | |
1031 | .dram_domain_energy_unit = 15300, | |
1032 | }; | |
1033 | ||
2d798d9f ZR |
1034 | static const struct rapl_defaults rapl_defaults_spr_server = { |
1035 | .check_unit = rapl_check_unit_core, | |
1036 | .set_floor_freq = set_floor_freq_default, | |
1037 | .compute_time_window = rapl_compute_time_window_core, | |
1038 | .dram_domain_energy_unit = 15300, | |
1039 | .psys_domain_energy_unit = 1000000000, | |
931da6a0 | 1040 | .spr_psys_bits = true, |
2d798d9f ZR |
1041 | }; |
1042 | ||
51b63409 AT |
1043 | static const struct rapl_defaults rapl_defaults_byt = { |
1044 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, | |
1045 | .check_unit = rapl_check_unit_atom, | |
1046 | .set_floor_freq = set_floor_freq_atom, | |
1047 | .compute_time_window = rapl_compute_time_window_atom, | |
1048 | }; | |
1049 | ||
1050 | static const struct rapl_defaults rapl_defaults_tng = { | |
1051 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, | |
3c2c0845 JP |
1052 | .check_unit = rapl_check_unit_atom, |
1053 | .set_floor_freq = set_floor_freq_atom, | |
1054 | .compute_time_window = rapl_compute_time_window_atom, | |
087e9cba JP |
1055 | }; |
1056 | ||
51b63409 AT |
1057 | static const struct rapl_defaults rapl_defaults_ann = { |
1058 | .floor_freq_reg_addr = 0, | |
1059 | .check_unit = rapl_check_unit_atom, | |
1060 | .set_floor_freq = NULL, | |
1061 | .compute_time_window = rapl_compute_time_window_atom, | |
1062 | }; | |
1063 | ||
1064 | static const struct rapl_defaults rapl_defaults_cht = { | |
1065 | .floor_freq_reg_addr = 0, | |
1066 | .check_unit = rapl_check_unit_atom, | |
1067 | .set_floor_freq = NULL, | |
1068 | .compute_time_window = rapl_compute_time_window_atom, | |
1069 | }; | |
1070 | ||
43756a29 VD |
1071 | static const struct rapl_defaults rapl_defaults_amd = { |
1072 | .check_unit = rapl_check_unit_core, | |
1073 | }; | |
1074 | ||
ea85dbca | 1075 | static const struct x86_cpu_id rapl_ids[] __initconst = { |
f0722512 TG |
1076 | X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &rapl_defaults_core), |
1077 | X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &rapl_defaults_core), | |
1078 | ||
1079 | X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &rapl_defaults_core), | |
1080 | X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &rapl_defaults_core), | |
1081 | ||
1082 | X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &rapl_defaults_core), | |
1083 | X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &rapl_defaults_core), | |
1084 | X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &rapl_defaults_core), | |
1085 | X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &rapl_defaults_hsw_server), | |
1086 | ||
1087 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &rapl_defaults_core), | |
1088 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &rapl_defaults_core), | |
1089 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &rapl_defaults_core), | |
1090 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &rapl_defaults_hsw_server), | |
1091 | ||
1092 | X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &rapl_defaults_core), | |
1093 | X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &rapl_defaults_core), | |
1094 | X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &rapl_defaults_hsw_server), | |
1095 | X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &rapl_defaults_core), | |
1096 | X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &rapl_defaults_core), | |
1097 | X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &rapl_defaults_core), | |
1098 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &rapl_defaults_core), | |
1099 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &rapl_defaults_core), | |
1100 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &rapl_defaults_core), | |
1101 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &rapl_defaults_hsw_server), | |
1102 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &rapl_defaults_hsw_server), | |
1103 | X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &rapl_defaults_core), | |
1104 | X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &rapl_defaults_core), | |
1105 | X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &rapl_defaults_core), | |
57a2fb06 | 1106 | X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &rapl_defaults_core), |
64e5f367 | 1107 | X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &rapl_defaults_core), |
ba92a420 | 1108 | X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &rapl_defaults_core), |
cca26b66 | 1109 | X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &rapl_defaults_core), |
f125bdbd | 1110 | X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, &rapl_defaults_core), |
ae0dc7ed | 1111 | X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &rapl_defaults_core), |
27557146 | 1112 | X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &rapl_defaults_core), |
2d798d9f | 1113 | X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), |
e1c2d96c | 1114 | X86_MATCH_INTEL_FAM6_MODEL(LAKEFIELD, &rapl_defaults_core), |
f0722512 TG |
1115 | |
1116 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &rapl_defaults_byt), | |
1117 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &rapl_defaults_cht), | |
1118 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &rapl_defaults_tng), | |
1119 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID, &rapl_defaults_ann), | |
1120 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &rapl_defaults_core), | |
1121 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &rapl_defaults_core), | |
1122 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &rapl_defaults_core), | |
33c98003 | 1123 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &rapl_defaults_core), |
f0722512 TG |
1124 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &rapl_defaults_core), |
1125 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &rapl_defaults_core), | |
1126 | ||
1127 | X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &rapl_defaults_hsw_server), | |
1128 | X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &rapl_defaults_hsw_server), | |
43756a29 VD |
1129 | |
1130 | X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), | |
8a9d881f | 1131 | X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), |
a7405612 | 1132 | X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd), |
2d281d81 JP |
1133 | {} |
1134 | }; | |
1135 | MODULE_DEVICE_TABLE(x86cpu, rapl_ids); | |
1136 | ||
bed5ab63 TG |
1137 | /* Read once for all raw primitive data for domains */ |
1138 | static void rapl_update_domain_data(struct rapl_package *rp) | |
2d281d81 JP |
1139 | { |
1140 | int dmn, prim; | |
1141 | u64 val; | |
2d281d81 | 1142 | |
bed5ab63 | 1143 | for (dmn = 0; dmn < rp->nr_domains; dmn++) { |
9ea7612c | 1144 | pr_debug("update %s domain %s data\n", rp->name, |
bed5ab63 TG |
1145 | rp->domains[dmn].name); |
1146 | /* exclude non-raw primitives */ | |
1147 | for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) { | |
1148 | if (!rapl_read_data_raw(&rp->domains[dmn], prim, | |
1149 | rpi[prim].unit, &val)) | |
3382388d | 1150 | rp->domains[dmn].rdd.primitives[prim] = val; |
2d281d81 JP |
1151 | } |
1152 | } | |
1153 | ||
1154 | } | |
1155 | ||
2d281d81 JP |
1156 | static int rapl_package_register_powercap(struct rapl_package *rp) |
1157 | { | |
1158 | struct rapl_domain *rd; | |
2d281d81 | 1159 | struct powercap_zone *power_zone = NULL; |
01857cf7 | 1160 | int nr_pl, ret; |
bed5ab63 TG |
1161 | |
1162 | /* Update the domain data of the new package */ | |
1163 | rapl_update_domain_data(rp); | |
2d281d81 | 1164 | |
3382388d | 1165 | /* first we register package domain as the parent zone */ |
2d281d81 JP |
1166 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { |
1167 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
1168 | nr_pl = find_nr_power_limit(rd); | |
9ea7612c | 1169 | pr_debug("register package domain %s\n", rp->name); |
2d281d81 | 1170 | power_zone = powercap_register_zone(&rd->power_zone, |
3382388d ZR |
1171 | rp->priv->control_type, rp->name, |
1172 | NULL, &zone_ops[rd->id], nr_pl, | |
1173 | &constraint_ops); | |
2d281d81 | 1174 | if (IS_ERR(power_zone)) { |
9ea7612c | 1175 | pr_debug("failed to register power zone %s\n", |
3382388d | 1176 | rp->name); |
bed5ab63 | 1177 | return PTR_ERR(power_zone); |
2d281d81 JP |
1178 | } |
1179 | /* track parent zone in per package/socket data */ | |
1180 | rp->power_zone = power_zone; | |
1181 | /* done, only one package domain per socket */ | |
1182 | break; | |
1183 | } | |
1184 | } | |
1185 | if (!power_zone) { | |
1186 | pr_err("no package domain found, unknown topology!\n"); | |
bed5ab63 | 1187 | return -ENODEV; |
2d281d81 | 1188 | } |
3382388d | 1189 | /* now register domains as children of the socket/package */ |
2d281d81 | 1190 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { |
f1e8d756 ZR |
1191 | struct powercap_zone *parent = rp->power_zone; |
1192 | ||
2d281d81 JP |
1193 | if (rd->id == RAPL_DOMAIN_PACKAGE) |
1194 | continue; | |
f1e8d756 ZR |
1195 | if (rd->id == RAPL_DOMAIN_PLATFORM) |
1196 | parent = NULL; | |
2d281d81 JP |
1197 | /* number of power limits per domain varies */ |
1198 | nr_pl = find_nr_power_limit(rd); | |
1199 | power_zone = powercap_register_zone(&rd->power_zone, | |
3382388d | 1200 | rp->priv->control_type, |
f1e8d756 | 1201 | rd->name, parent, |
3382388d ZR |
1202 | &zone_ops[rd->id], nr_pl, |
1203 | &constraint_ops); | |
2d281d81 JP |
1204 | |
1205 | if (IS_ERR(power_zone)) { | |
9ea7612c | 1206 | pr_debug("failed to register power_zone, %s:%s\n", |
3382388d | 1207 | rp->name, rd->name); |
2d281d81 JP |
1208 | ret = PTR_ERR(power_zone); |
1209 | goto err_cleanup; | |
1210 | } | |
1211 | } | |
bed5ab63 | 1212 | return 0; |
2d281d81 | 1213 | |
2d281d81 | 1214 | err_cleanup: |
58705069 TG |
1215 | /* |
1216 | * Clean up previously initialized domains within the package if we | |
2d281d81 JP |
1217 | * failed after the first domain setup. |
1218 | */ | |
1219 | while (--rd >= rp->domains) { | |
9ea7612c | 1220 | pr_debug("unregister %s domain %s\n", rp->name, rd->name); |
3382388d ZR |
1221 | powercap_unregister_zone(rp->priv->control_type, |
1222 | &rd->power_zone); | |
2d281d81 JP |
1223 | } |
1224 | ||
1225 | return ret; | |
1226 | } | |
1227 | ||
7fde2712 | 1228 | static int rapl_check_domain(int cpu, int domain, struct rapl_package *rp) |
2d281d81 | 1229 | { |
1193b165 | 1230 | struct reg_action ra; |
2d281d81 JP |
1231 | |
1232 | switch (domain) { | |
1233 | case RAPL_DOMAIN_PACKAGE: | |
2d281d81 | 1234 | case RAPL_DOMAIN_PP0: |
2d281d81 | 1235 | case RAPL_DOMAIN_PP1: |
2d281d81 | 1236 | case RAPL_DOMAIN_DRAM: |
f1e8d756 | 1237 | case RAPL_DOMAIN_PLATFORM: |
1193b165 | 1238 | ra.reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS]; |
2d281d81 JP |
1239 | break; |
1240 | default: | |
1241 | pr_err("invalid domain id %d\n", domain); | |
1242 | return -EINVAL; | |
1243 | } | |
9d31c676 JP |
1244 | /* make sure domain counters are available and contains non-zero |
1245 | * values, otherwise skip it. | |
7b874772 | 1246 | */ |
1193b165 | 1247 | |
7a57e9f1 | 1248 | ra.mask = ENERGY_STATUS_MASK; |
1193b165 | 1249 | if (rp->priv->read_raw(cpu, &ra) || !ra.value) |
9d31c676 | 1250 | return -ENODEV; |
2d281d81 | 1251 | |
9d31c676 | 1252 | return 0; |
2d281d81 JP |
1253 | } |
1254 | ||
e1399ba2 JP |
1255 | /* |
1256 | * Check if power limits are available. Two cases when they are not available: | |
1257 | * 1. Locked by BIOS, in this case we still provide read-only access so that | |
1258 | * users can see what limit is set by the BIOS. | |
1259 | * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not | |
3382388d | 1260 | * exist at all. In this case, we do not show the constraints in powercap. |
e1399ba2 JP |
1261 | * |
1262 | * Called after domains are detected and initialized. | |
1263 | */ | |
1264 | static void rapl_detect_powerlimit(struct rapl_domain *rd) | |
1265 | { | |
1266 | u64 val64; | |
1267 | int i; | |
1268 | ||
1269 | /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */ | |
1270 | if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) { | |
1271 | if (val64) { | |
9ea7612c ZR |
1272 | pr_info("RAPL %s domain %s locked by BIOS\n", |
1273 | rd->rp->name, rd->name); | |
e1399ba2 JP |
1274 | rd->state |= DOMAIN_STATE_BIOS_LOCKED; |
1275 | } | |
1276 | } | |
3382388d | 1277 | /* check if power limit MSR exists, otherwise domain is monitoring only */ |
e1399ba2 JP |
1278 | for (i = 0; i < NR_POWER_LIMITS; i++) { |
1279 | int prim = rd->rpl[i].prim_id; | |
3382388d | 1280 | |
e1399ba2 JP |
1281 | if (rapl_read_data_raw(rd, prim, false, &val64)) |
1282 | rd->rpl[i].name = NULL; | |
1283 | } | |
1284 | } | |
1285 | ||
2d281d81 JP |
1286 | /* Detect active and valid domains for the given CPU, caller must |
1287 | * ensure the CPU belongs to the targeted package and CPU hotlug is disabled. | |
1288 | */ | |
1289 | static int rapl_detect_domains(struct rapl_package *rp, int cpu) | |
1290 | { | |
2d281d81 | 1291 | struct rapl_domain *rd; |
58705069 | 1292 | int i; |
2d281d81 JP |
1293 | |
1294 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
1295 | /* use physical package id to read counters */ | |
7fde2712 | 1296 | if (!rapl_check_domain(cpu, i, rp)) { |
2d281d81 | 1297 | rp->domain_map |= 1 << i; |
fcdf1797 JP |
1298 | pr_info("Found RAPL domain %s\n", rapl_domain_names[i]); |
1299 | } | |
2d281d81 | 1300 | } |
3382388d | 1301 | rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX); |
2d281d81 | 1302 | if (!rp->nr_domains) { |
9ea7612c | 1303 | pr_debug("no valid rapl domains found in %s\n", rp->name); |
58705069 | 1304 | return -ENODEV; |
2d281d81 | 1305 | } |
9ea7612c | 1306 | pr_debug("found %d domains on %s\n", rp->nr_domains, rp->name); |
2d281d81 JP |
1307 | |
1308 | rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain), | |
3382388d | 1309 | GFP_KERNEL); |
58705069 TG |
1310 | if (!rp->domains) |
1311 | return -ENOMEM; | |
1312 | ||
2d281d81 JP |
1313 | rapl_init_domains(rp); |
1314 | ||
e1399ba2 JP |
1315 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) |
1316 | rapl_detect_powerlimit(rd); | |
1317 | ||
2d281d81 JP |
1318 | return 0; |
1319 | } | |
1320 | ||
1321 | /* called from CPU hotplug notifier, hotplug lock held */ | |
3382388d | 1322 | void rapl_remove_package(struct rapl_package *rp) |
2d281d81 JP |
1323 | { |
1324 | struct rapl_domain *rd, *rd_package = NULL; | |
1325 | ||
58705069 TG |
1326 | package_power_limit_irq_restore(rp); |
1327 | ||
2d281d81 | 1328 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { |
58705069 TG |
1329 | rapl_write_data_raw(rd, PL1_ENABLE, 0); |
1330 | rapl_write_data_raw(rd, PL1_CLAMP, 0); | |
1331 | if (find_nr_power_limit(rd) > 1) { | |
1332 | rapl_write_data_raw(rd, PL2_ENABLE, 0); | |
1333 | rapl_write_data_raw(rd, PL2_CLAMP, 0); | |
8365a898 | 1334 | rapl_write_data_raw(rd, PL4_ENABLE, 0); |
58705069 | 1335 | } |
2d281d81 JP |
1336 | if (rd->id == RAPL_DOMAIN_PACKAGE) { |
1337 | rd_package = rd; | |
1338 | continue; | |
1339 | } | |
9ea7612c ZR |
1340 | pr_debug("remove package, undo power limit on %s: %s\n", |
1341 | rp->name, rd->name); | |
3382388d ZR |
1342 | powercap_unregister_zone(rp->priv->control_type, |
1343 | &rd->power_zone); | |
2d281d81 JP |
1344 | } |
1345 | /* do parent zone last */ | |
3382388d ZR |
1346 | powercap_unregister_zone(rp->priv->control_type, |
1347 | &rd_package->power_zone); | |
2d281d81 JP |
1348 | list_del(&rp->plist); |
1349 | kfree(rp); | |
1350 | } | |
3382388d ZR |
1351 | EXPORT_SYMBOL_GPL(rapl_remove_package); |
1352 | ||
1353 | /* caller to ensure CPU hotplug lock is held */ | |
1354 | struct rapl_package *rapl_find_package_domain(int cpu, struct rapl_if_priv *priv) | |
1355 | { | |
1356 | int id = topology_logical_die_id(cpu); | |
1357 | struct rapl_package *rp; | |
1358 | ||
1359 | list_for_each_entry(rp, &rapl_packages, plist) { | |
1360 | if (rp->id == id | |
1361 | && rp->priv->control_type == priv->control_type) | |
1362 | return rp; | |
1363 | } | |
1364 | ||
1365 | return NULL; | |
1366 | } | |
1367 | EXPORT_SYMBOL_GPL(rapl_find_package_domain); | |
2d281d81 JP |
1368 | |
1369 | /* called from CPU hotplug notifier, hotplug lock held */ | |
3382388d | 1370 | struct rapl_package *rapl_add_package(int cpu, struct rapl_if_priv *priv) |
2d281d81 | 1371 | { |
32fb480e | 1372 | int id = topology_logical_die_id(cpu); |
2d281d81 | 1373 | struct rapl_package *rp; |
b4005e92 | 1374 | int ret; |
2d281d81 | 1375 | |
3aa3c588 HP |
1376 | if (!rapl_defaults) |
1377 | return ERR_PTR(-ENODEV); | |
1378 | ||
2d281d81 JP |
1379 | rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL); |
1380 | if (!rp) | |
b4005e92 | 1381 | return ERR_PTR(-ENOMEM); |
2d281d81 JP |
1382 | |
1383 | /* add the new package to the list */ | |
aadf7b38 | 1384 | rp->id = id; |
323ee64a | 1385 | rp->lead_cpu = cpu; |
7ebf8eff | 1386 | rp->priv = priv; |
323ee64a | 1387 | |
9ea7612c ZR |
1388 | if (topology_max_die_per_package() > 1) |
1389 | snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, | |
88ffce95 YY |
1390 | "package-%d-die-%d", |
1391 | topology_physical_package_id(cpu), topology_die_id(cpu)); | |
9ea7612c ZR |
1392 | else |
1393 | snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d", | |
88ffce95 | 1394 | topology_physical_package_id(cpu)); |
9ea7612c | 1395 | |
2d281d81 | 1396 | /* check if the package contains valid domains */ |
3382388d | 1397 | if (rapl_detect_domains(rp, cpu) || rapl_defaults->check_unit(rp, cpu)) { |
2d281d81 JP |
1398 | ret = -ENODEV; |
1399 | goto err_free_package; | |
1400 | } | |
a74f4367 TG |
1401 | ret = rapl_package_register_powercap(rp); |
1402 | if (!ret) { | |
2d281d81 JP |
1403 | INIT_LIST_HEAD(&rp->plist); |
1404 | list_add(&rp->plist, &rapl_packages); | |
b4005e92 | 1405 | return rp; |
2d281d81 JP |
1406 | } |
1407 | ||
1408 | err_free_package: | |
1409 | kfree(rp->domains); | |
1410 | kfree(rp); | |
b4005e92 | 1411 | return ERR_PTR(ret); |
2d281d81 | 1412 | } |
3382388d | 1413 | EXPORT_SYMBOL_GPL(rapl_add_package); |
2d281d81 | 1414 | |
52b3672c ZH |
1415 | static void power_limit_state_save(void) |
1416 | { | |
1417 | struct rapl_package *rp; | |
1418 | struct rapl_domain *rd; | |
1419 | int nr_pl, ret, i; | |
1420 | ||
5d4c779c | 1421 | cpus_read_lock(); |
52b3672c ZH |
1422 | list_for_each_entry(rp, &rapl_packages, plist) { |
1423 | if (!rp->power_zone) | |
1424 | continue; | |
1425 | rd = power_zone_to_rapl_domain(rp->power_zone); | |
1426 | nr_pl = find_nr_power_limit(rd); | |
1427 | for (i = 0; i < nr_pl; i++) { | |
1428 | switch (rd->rpl[i].prim_id) { | |
1429 | case PL1_ENABLE: | |
1430 | ret = rapl_read_data_raw(rd, | |
3382388d ZR |
1431 | POWER_LIMIT1, true, |
1432 | &rd->rpl[i].last_power_limit); | |
52b3672c ZH |
1433 | if (ret) |
1434 | rd->rpl[i].last_power_limit = 0; | |
1435 | break; | |
1436 | case PL2_ENABLE: | |
1437 | ret = rapl_read_data_raw(rd, | |
3382388d ZR |
1438 | POWER_LIMIT2, true, |
1439 | &rd->rpl[i].last_power_limit); | |
52b3672c ZH |
1440 | if (ret) |
1441 | rd->rpl[i].last_power_limit = 0; | |
1442 | break; | |
8365a898 SP |
1443 | case PL4_ENABLE: |
1444 | ret = rapl_read_data_raw(rd, | |
1445 | POWER_LIMIT4, true, | |
1446 | &rd->rpl[i].last_power_limit); | |
1447 | if (ret) | |
1448 | rd->rpl[i].last_power_limit = 0; | |
1449 | break; | |
52b3672c ZH |
1450 | } |
1451 | } | |
1452 | } | |
5d4c779c | 1453 | cpus_read_unlock(); |
52b3672c ZH |
1454 | } |
1455 | ||
1456 | static void power_limit_state_restore(void) | |
1457 | { | |
1458 | struct rapl_package *rp; | |
1459 | struct rapl_domain *rd; | |
1460 | int nr_pl, i; | |
1461 | ||
5d4c779c | 1462 | cpus_read_lock(); |
52b3672c ZH |
1463 | list_for_each_entry(rp, &rapl_packages, plist) { |
1464 | if (!rp->power_zone) | |
1465 | continue; | |
1466 | rd = power_zone_to_rapl_domain(rp->power_zone); | |
1467 | nr_pl = find_nr_power_limit(rd); | |
1468 | for (i = 0; i < nr_pl; i++) { | |
1469 | switch (rd->rpl[i].prim_id) { | |
1470 | case PL1_ENABLE: | |
1471 | if (rd->rpl[i].last_power_limit) | |
3382388d ZR |
1472 | rapl_write_data_raw(rd, POWER_LIMIT1, |
1473 | rd->rpl[i].last_power_limit); | |
52b3672c ZH |
1474 | break; |
1475 | case PL2_ENABLE: | |
1476 | if (rd->rpl[i].last_power_limit) | |
3382388d ZR |
1477 | rapl_write_data_raw(rd, POWER_LIMIT2, |
1478 | rd->rpl[i].last_power_limit); | |
52b3672c | 1479 | break; |
8365a898 SP |
1480 | case PL4_ENABLE: |
1481 | if (rd->rpl[i].last_power_limit) | |
1482 | rapl_write_data_raw(rd, POWER_LIMIT4, | |
1483 | rd->rpl[i].last_power_limit); | |
1484 | break; | |
52b3672c ZH |
1485 | } |
1486 | } | |
1487 | } | |
5d4c779c | 1488 | cpus_read_unlock(); |
52b3672c ZH |
1489 | } |
1490 | ||
1491 | static int rapl_pm_callback(struct notifier_block *nb, | |
3382388d | 1492 | unsigned long mode, void *_unused) |
52b3672c ZH |
1493 | { |
1494 | switch (mode) { | |
1495 | case PM_SUSPEND_PREPARE: | |
1496 | power_limit_state_save(); | |
1497 | break; | |
1498 | case PM_POST_SUSPEND: | |
1499 | power_limit_state_restore(); | |
1500 | break; | |
1501 | } | |
1502 | return NOTIFY_OK; | |
1503 | } | |
1504 | ||
1505 | static struct notifier_block rapl_pm_notifier = { | |
1506 | .notifier_call = rapl_pm_callback, | |
1507 | }; | |
1508 | ||
abcfaeb3 ZR |
1509 | static struct platform_device *rapl_msr_platdev; |
1510 | ||
1511 | static int __init rapl_init(void) | |
2d281d81 | 1512 | { |
087e9cba | 1513 | const struct x86_cpu_id *id; |
58705069 | 1514 | int ret; |
2d281d81 | 1515 | |
087e9cba JP |
1516 | id = x86_match_cpu(rapl_ids); |
1517 | if (!id) { | |
2d281d81 | 1518 | pr_err("driver does not support CPU family %d model %d\n", |
3382388d | 1519 | boot_cpu_data.x86, boot_cpu_data.x86_model); |
2d281d81 JP |
1520 | |
1521 | return -ENODEV; | |
1522 | } | |
009f225e | 1523 | |
087e9cba JP |
1524 | rapl_defaults = (struct rapl_defaults *)id->driver_data; |
1525 | ||
52b3672c | 1526 | ret = register_pm_notifier(&rapl_pm_notifier); |
abcfaeb3 ZR |
1527 | if (ret) |
1528 | return ret; | |
52b3672c | 1529 | |
abcfaeb3 ZR |
1530 | rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0); |
1531 | if (!rapl_msr_platdev) { | |
1532 | ret = -ENOMEM; | |
1533 | goto end; | |
1534 | } | |
1535 | ||
1536 | ret = platform_device_add(rapl_msr_platdev); | |
1537 | if (ret) | |
1538 | platform_device_put(rapl_msr_platdev); | |
1539 | ||
1540 | end: | |
1541 | if (ret) | |
1542 | unregister_pm_notifier(&rapl_pm_notifier); | |
1543 | ||
1544 | return ret; | |
2d281d81 JP |
1545 | } |
1546 | ||
abcfaeb3 | 1547 | static void __exit rapl_exit(void) |
2d281d81 | 1548 | { |
abcfaeb3 | 1549 | platform_device_unregister(rapl_msr_platdev); |
52b3672c | 1550 | unregister_pm_notifier(&rapl_pm_notifier); |
2d281d81 JP |
1551 | } |
1552 | ||
f76cb066 | 1553 | fs_initcall(rapl_init); |
abcfaeb3 ZR |
1554 | module_exit(rapl_exit); |
1555 | ||
3382388d | 1556 | MODULE_DESCRIPTION("Intel Runtime Average Power Limit (RAPL) common code"); |
2d281d81 JP |
1557 | MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); |
1558 | MODULE_LICENSE("GPL v2"); |