Commit | Line | Data |
---|---|---|
2d281d81 JP |
1 | /* |
2 | * Intel Running Average Power Limit (RAPL) Driver | |
3 | * Copyright (c) 2013, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc. | |
16 | * | |
17 | */ | |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/log2.h> | |
27 | #include <linux/bitmap.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/sysfs.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/powercap.h> | |
3c2c0845 | 32 | #include <asm/iosf_mbi.h> |
2d281d81 JP |
33 | |
34 | #include <asm/processor.h> | |
35 | #include <asm/cpu_device_id.h> | |
62d16733 | 36 | #include <asm/intel-family.h> |
2d281d81 | 37 | |
3521ba1c SP |
38 | /* Local defines */ |
39 | #define MSR_PLATFORM_POWER_LIMIT 0x0000065C | |
40 | ||
2d281d81 JP |
41 | /* bitmasks for RAPL MSRs, used by primitive access functions */ |
42 | #define ENERGY_STATUS_MASK 0xffffffff | |
43 | ||
44 | #define POWER_LIMIT1_MASK 0x7FFF | |
45 | #define POWER_LIMIT1_ENABLE BIT(15) | |
46 | #define POWER_LIMIT1_CLAMP BIT(16) | |
47 | ||
48 | #define POWER_LIMIT2_MASK (0x7FFFULL<<32) | |
49 | #define POWER_LIMIT2_ENABLE BIT_ULL(47) | |
50 | #define POWER_LIMIT2_CLAMP BIT_ULL(48) | |
51 | #define POWER_PACKAGE_LOCK BIT_ULL(63) | |
52 | #define POWER_PP_LOCK BIT(31) | |
53 | ||
54 | #define TIME_WINDOW1_MASK (0x7FULL<<17) | |
55 | #define TIME_WINDOW2_MASK (0x7FULL<<49) | |
56 | ||
57 | #define POWER_UNIT_OFFSET 0 | |
58 | #define POWER_UNIT_MASK 0x0F | |
59 | ||
60 | #define ENERGY_UNIT_OFFSET 0x08 | |
61 | #define ENERGY_UNIT_MASK 0x1F00 | |
62 | ||
63 | #define TIME_UNIT_OFFSET 0x10 | |
64 | #define TIME_UNIT_MASK 0xF0000 | |
65 | ||
66 | #define POWER_INFO_MAX_MASK (0x7fffULL<<32) | |
67 | #define POWER_INFO_MIN_MASK (0x7fffULL<<16) | |
68 | #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) | |
69 | #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff | |
70 | ||
71 | #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff | |
72 | #define PP_POLICY_MASK 0x1F | |
73 | ||
74 | /* Non HW constants */ | |
75 | #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ | |
76 | #define RAPL_PRIMITIVE_DUMMY BIT(2) | |
77 | ||
2d281d81 JP |
78 | #define TIME_WINDOW_MAX_MSEC 40000 |
79 | #define TIME_WINDOW_MIN_MSEC 250 | |
d474a4d3 | 80 | #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ |
2d281d81 JP |
81 | enum unit_type { |
82 | ARBITRARY_UNIT, /* no translation */ | |
83 | POWER_UNIT, | |
84 | ENERGY_UNIT, | |
85 | TIME_UNIT, | |
86 | }; | |
87 | ||
88 | enum rapl_domain_type { | |
89 | RAPL_DOMAIN_PACKAGE, /* entire package/socket */ | |
90 | RAPL_DOMAIN_PP0, /* core power plane */ | |
91 | RAPL_DOMAIN_PP1, /* graphics uncore */ | |
92 | RAPL_DOMAIN_DRAM,/* DRAM control_type */ | |
3521ba1c | 93 | RAPL_DOMAIN_PLATFORM, /* PSys control_type */ |
2d281d81 JP |
94 | RAPL_DOMAIN_MAX, |
95 | }; | |
96 | ||
97 | enum rapl_domain_msr_id { | |
98 | RAPL_DOMAIN_MSR_LIMIT, | |
99 | RAPL_DOMAIN_MSR_STATUS, | |
100 | RAPL_DOMAIN_MSR_PERF, | |
101 | RAPL_DOMAIN_MSR_POLICY, | |
102 | RAPL_DOMAIN_MSR_INFO, | |
103 | RAPL_DOMAIN_MSR_MAX, | |
104 | }; | |
105 | ||
106 | /* per domain data, some are optional */ | |
107 | enum rapl_primitives { | |
108 | ENERGY_COUNTER, | |
109 | POWER_LIMIT1, | |
110 | POWER_LIMIT2, | |
111 | FW_LOCK, | |
112 | ||
113 | PL1_ENABLE, /* power limit 1, aka long term */ | |
114 | PL1_CLAMP, /* allow frequency to go below OS request */ | |
115 | PL2_ENABLE, /* power limit 2, aka short term, instantaneous */ | |
116 | PL2_CLAMP, | |
117 | ||
118 | TIME_WINDOW1, /* long term */ | |
119 | TIME_WINDOW2, /* short term */ | |
120 | THERMAL_SPEC_POWER, | |
121 | MAX_POWER, | |
122 | ||
123 | MIN_POWER, | |
124 | MAX_TIME_WINDOW, | |
125 | THROTTLED_TIME, | |
126 | PRIORITY_LEVEL, | |
127 | ||
128 | /* below are not raw primitive data */ | |
129 | AVERAGE_POWER, | |
130 | NR_RAPL_PRIMITIVES, | |
131 | }; | |
132 | ||
133 | #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) | |
134 | ||
135 | /* Can be expanded to include events, etc.*/ | |
136 | struct rapl_domain_data { | |
137 | u64 primitives[NR_RAPL_PRIMITIVES]; | |
138 | unsigned long timestamp; | |
139 | }; | |
140 | ||
f14a1396 JP |
141 | struct msrl_action { |
142 | u32 msr_no; | |
143 | u64 clear_mask; | |
144 | u64 set_mask; | |
145 | int err; | |
146 | }; | |
2d281d81 JP |
147 | |
148 | #define DOMAIN_STATE_INACTIVE BIT(0) | |
149 | #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) | |
150 | #define DOMAIN_STATE_BIOS_LOCKED BIT(2) | |
151 | ||
152 | #define NR_POWER_LIMITS (2) | |
153 | struct rapl_power_limit { | |
154 | struct powercap_zone_constraint *constraint; | |
155 | int prim_id; /* primitive ID used to enable */ | |
156 | struct rapl_domain *domain; | |
157 | const char *name; | |
158 | }; | |
159 | ||
160 | static const char pl1_name[] = "long_term"; | |
161 | static const char pl2_name[] = "short_term"; | |
162 | ||
309557f5 | 163 | struct rapl_package; |
2d281d81 JP |
164 | struct rapl_domain { |
165 | const char *name; | |
166 | enum rapl_domain_type id; | |
167 | int msrs[RAPL_DOMAIN_MSR_MAX]; | |
168 | struct powercap_zone power_zone; | |
169 | struct rapl_domain_data rdd; | |
170 | struct rapl_power_limit rpl[NR_POWER_LIMITS]; | |
171 | u64 attr_map; /* track capabilities */ | |
172 | unsigned int state; | |
d474a4d3 | 173 | unsigned int domain_energy_unit; |
309557f5 | 174 | struct rapl_package *rp; |
2d281d81 JP |
175 | }; |
176 | #define power_zone_to_rapl_domain(_zone) \ | |
177 | container_of(_zone, struct rapl_domain, power_zone) | |
178 | ||
179 | ||
180 | /* Each physical package contains multiple domains, these are the common | |
181 | * data across RAPL domains within a package. | |
182 | */ | |
183 | struct rapl_package { | |
184 | unsigned int id; /* physical package/socket id */ | |
185 | unsigned int nr_domains; | |
186 | unsigned long domain_map; /* bit map of active domains */ | |
3c2c0845 JP |
187 | unsigned int power_unit; |
188 | unsigned int energy_unit; | |
189 | unsigned int time_unit; | |
2d281d81 JP |
190 | struct rapl_domain *domains; /* array of domains, sized at runtime */ |
191 | struct powercap_zone *power_zone; /* keep track of parent zone */ | |
192 | int nr_cpus; /* active cpus on the package, topology info is lost during | |
193 | * cpu hotplug. so we have to track ourselves. | |
194 | */ | |
195 | unsigned long power_limit_irq; /* keep track of package power limit | |
196 | * notify interrupt enable status. | |
197 | */ | |
198 | struct list_head plist; | |
323ee64a | 199 | int lead_cpu; /* one active cpu per package for access */ |
2d281d81 | 200 | }; |
087e9cba JP |
201 | |
202 | struct rapl_defaults { | |
51b63409 | 203 | u8 floor_freq_reg_addr; |
087e9cba JP |
204 | int (*check_unit)(struct rapl_package *rp, int cpu); |
205 | void (*set_floor_freq)(struct rapl_domain *rd, bool mode); | |
206 | u64 (*compute_time_window)(struct rapl_package *rp, u64 val, | |
207 | bool to_raw); | |
d474a4d3 | 208 | unsigned int dram_domain_energy_unit; |
087e9cba JP |
209 | }; |
210 | static struct rapl_defaults *rapl_defaults; | |
211 | ||
3c2c0845 | 212 | /* Sideband MBI registers */ |
51b63409 AT |
213 | #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2) |
214 | #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf) | |
3c2c0845 | 215 | |
2d281d81 JP |
216 | #define PACKAGE_PLN_INT_SAVED BIT(0) |
217 | #define MAX_PRIM_NAME (32) | |
218 | ||
219 | /* per domain data. used to describe individual knobs such that access function | |
220 | * can be consolidated into one instead of many inline functions. | |
221 | */ | |
222 | struct rapl_primitive_info { | |
223 | const char *name; | |
224 | u64 mask; | |
225 | int shift; | |
226 | enum rapl_domain_msr_id id; | |
227 | enum unit_type unit; | |
228 | u32 flag; | |
229 | }; | |
230 | ||
231 | #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ | |
232 | .name = #p, \ | |
233 | .mask = m, \ | |
234 | .shift = s, \ | |
235 | .id = i, \ | |
236 | .unit = u, \ | |
237 | .flag = f \ | |
238 | } | |
239 | ||
240 | static void rapl_init_domains(struct rapl_package *rp); | |
241 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
242 | enum rapl_primitives prim, | |
243 | bool xlate, u64 *data); | |
244 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
245 | enum rapl_primitives prim, | |
246 | unsigned long long value); | |
309557f5 | 247 | static u64 rapl_unit_xlate(struct rapl_domain *rd, |
d474a4d3 | 248 | enum unit_type type, u64 value, |
2d281d81 | 249 | int to_raw); |
309557f5 | 250 | static void package_power_limit_irq_save(struct rapl_package *rp); |
2d281d81 JP |
251 | |
252 | static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */ | |
253 | ||
254 | static const char * const rapl_domain_names[] = { | |
255 | "package", | |
256 | "core", | |
257 | "uncore", | |
258 | "dram", | |
3521ba1c | 259 | "psys", |
2d281d81 JP |
260 | }; |
261 | ||
262 | static struct powercap_control_type *control_type; /* PowerCap Controller */ | |
3521ba1c | 263 | static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */ |
2d281d81 JP |
264 | |
265 | /* caller to ensure CPU hotplug lock is held */ | |
266 | static struct rapl_package *find_package_by_id(int id) | |
267 | { | |
268 | struct rapl_package *rp; | |
269 | ||
270 | list_for_each_entry(rp, &rapl_packages, plist) { | |
271 | if (rp->id == id) | |
272 | return rp; | |
273 | } | |
274 | ||
275 | return NULL; | |
276 | } | |
277 | ||
2d281d81 JP |
278 | /* caller must hold cpu hotplug lock */ |
279 | static void rapl_cleanup_data(void) | |
280 | { | |
281 | struct rapl_package *p, *tmp; | |
282 | ||
283 | list_for_each_entry_safe(p, tmp, &rapl_packages, plist) { | |
284 | kfree(p->domains); | |
285 | list_del(&p->plist); | |
286 | kfree(p); | |
287 | } | |
288 | } | |
289 | ||
290 | static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw) | |
291 | { | |
292 | struct rapl_domain *rd; | |
293 | u64 energy_now; | |
294 | ||
295 | /* prevent CPU hotplug, make sure the RAPL domain does not go | |
296 | * away while reading the counter. | |
297 | */ | |
298 | get_online_cpus(); | |
299 | rd = power_zone_to_rapl_domain(power_zone); | |
300 | ||
301 | if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { | |
302 | *energy_raw = energy_now; | |
303 | put_online_cpus(); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | put_online_cpus(); | |
308 | ||
309 | return -EIO; | |
310 | } | |
311 | ||
312 | static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) | |
313 | { | |
d474a4d3 JP |
314 | struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); |
315 | ||
309557f5 | 316 | *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); |
2d281d81 JP |
317 | return 0; |
318 | } | |
319 | ||
320 | static int release_zone(struct powercap_zone *power_zone) | |
321 | { | |
322 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
309557f5 | 323 | struct rapl_package *rp = rd->rp; |
2d281d81 JP |
324 | |
325 | /* package zone is the last zone of a package, we can free | |
326 | * memory here since all children has been unregistered. | |
327 | */ | |
328 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
2d281d81 JP |
329 | kfree(rd); |
330 | rp->domains = NULL; | |
331 | } | |
332 | ||
333 | return 0; | |
334 | ||
335 | } | |
336 | ||
337 | static int find_nr_power_limit(struct rapl_domain *rd) | |
338 | { | |
e1399ba2 | 339 | int i, nr_pl = 0; |
2d281d81 JP |
340 | |
341 | for (i = 0; i < NR_POWER_LIMITS; i++) { | |
e1399ba2 JP |
342 | if (rd->rpl[i].name) |
343 | nr_pl++; | |
2d281d81 JP |
344 | } |
345 | ||
e1399ba2 | 346 | return nr_pl; |
2d281d81 JP |
347 | } |
348 | ||
349 | static int set_domain_enable(struct powercap_zone *power_zone, bool mode) | |
350 | { | |
351 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
2d281d81 JP |
352 | |
353 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) | |
354 | return -EACCES; | |
3c2c0845 | 355 | |
2d281d81 | 356 | get_online_cpus(); |
2d281d81 | 357 | rapl_write_data_raw(rd, PL1_ENABLE, mode); |
51b63409 AT |
358 | if (rapl_defaults->set_floor_freq) |
359 | rapl_defaults->set_floor_freq(rd, mode); | |
2d281d81 JP |
360 | put_online_cpus(); |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static int get_domain_enable(struct powercap_zone *power_zone, bool *mode) | |
366 | { | |
367 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
368 | u64 val; | |
369 | ||
370 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
371 | *mode = false; | |
372 | return 0; | |
373 | } | |
374 | get_online_cpus(); | |
375 | if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) { | |
376 | put_online_cpus(); | |
377 | return -EIO; | |
378 | } | |
379 | *mode = val; | |
380 | put_online_cpus(); | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | /* per RAPL domain ops, in the order of rapl_domain_type */ | |
600c395b | 386 | static const struct powercap_zone_ops zone_ops[] = { |
2d281d81 JP |
387 | /* RAPL_DOMAIN_PACKAGE */ |
388 | { | |
389 | .get_energy_uj = get_energy_counter, | |
390 | .get_max_energy_range_uj = get_max_energy_counter, | |
391 | .release = release_zone, | |
392 | .set_enable = set_domain_enable, | |
393 | .get_enable = get_domain_enable, | |
394 | }, | |
395 | /* RAPL_DOMAIN_PP0 */ | |
396 | { | |
397 | .get_energy_uj = get_energy_counter, | |
398 | .get_max_energy_range_uj = get_max_energy_counter, | |
399 | .release = release_zone, | |
400 | .set_enable = set_domain_enable, | |
401 | .get_enable = get_domain_enable, | |
402 | }, | |
403 | /* RAPL_DOMAIN_PP1 */ | |
404 | { | |
405 | .get_energy_uj = get_energy_counter, | |
406 | .get_max_energy_range_uj = get_max_energy_counter, | |
407 | .release = release_zone, | |
408 | .set_enable = set_domain_enable, | |
409 | .get_enable = get_domain_enable, | |
410 | }, | |
411 | /* RAPL_DOMAIN_DRAM */ | |
412 | { | |
413 | .get_energy_uj = get_energy_counter, | |
414 | .get_max_energy_range_uj = get_max_energy_counter, | |
415 | .release = release_zone, | |
416 | .set_enable = set_domain_enable, | |
417 | .get_enable = get_domain_enable, | |
418 | }, | |
3521ba1c SP |
419 | /* RAPL_DOMAIN_PLATFORM */ |
420 | { | |
421 | .get_energy_uj = get_energy_counter, | |
422 | .get_max_energy_range_uj = get_max_energy_counter, | |
423 | .release = release_zone, | |
424 | .set_enable = set_domain_enable, | |
425 | .get_enable = get_domain_enable, | |
426 | }, | |
2d281d81 JP |
427 | }; |
428 | ||
e1399ba2 JP |
429 | |
430 | /* | |
431 | * Constraint index used by powercap can be different than power limit (PL) | |
432 | * index in that some PLs maybe missing due to non-existant MSRs. So we | |
433 | * need to convert here by finding the valid PLs only (name populated). | |
434 | */ | |
435 | static int contraint_to_pl(struct rapl_domain *rd, int cid) | |
436 | { | |
437 | int i, j; | |
438 | ||
439 | for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) { | |
440 | if ((rd->rpl[i].name) && j++ == cid) { | |
441 | pr_debug("%s: index %d\n", __func__, i); | |
442 | return i; | |
443 | } | |
444 | } | |
445 | ||
446 | return -EINVAL; | |
447 | } | |
448 | ||
449 | static int set_power_limit(struct powercap_zone *power_zone, int cid, | |
2d281d81 JP |
450 | u64 power_limit) |
451 | { | |
452 | struct rapl_domain *rd; | |
453 | struct rapl_package *rp; | |
454 | int ret = 0; | |
e1399ba2 | 455 | int id; |
2d281d81 JP |
456 | |
457 | get_online_cpus(); | |
458 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 JP |
459 | id = contraint_to_pl(rd, cid); |
460 | ||
309557f5 | 461 | rp = rd->rp; |
2d281d81 JP |
462 | |
463 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
464 | dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n", | |
465 | rd->name); | |
466 | ret = -EACCES; | |
467 | goto set_exit; | |
468 | } | |
469 | ||
470 | switch (rd->rpl[id].prim_id) { | |
471 | case PL1_ENABLE: | |
472 | rapl_write_data_raw(rd, POWER_LIMIT1, power_limit); | |
473 | break; | |
474 | case PL2_ENABLE: | |
475 | rapl_write_data_raw(rd, POWER_LIMIT2, power_limit); | |
476 | break; | |
477 | default: | |
478 | ret = -EINVAL; | |
479 | } | |
480 | if (!ret) | |
309557f5 | 481 | package_power_limit_irq_save(rp); |
2d281d81 JP |
482 | set_exit: |
483 | put_online_cpus(); | |
484 | return ret; | |
485 | } | |
486 | ||
e1399ba2 | 487 | static int get_current_power_limit(struct powercap_zone *power_zone, int cid, |
2d281d81 JP |
488 | u64 *data) |
489 | { | |
490 | struct rapl_domain *rd; | |
491 | u64 val; | |
492 | int prim; | |
493 | int ret = 0; | |
e1399ba2 | 494 | int id; |
2d281d81 JP |
495 | |
496 | get_online_cpus(); | |
497 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 498 | id = contraint_to_pl(rd, cid); |
2d281d81 JP |
499 | switch (rd->rpl[id].prim_id) { |
500 | case PL1_ENABLE: | |
501 | prim = POWER_LIMIT1; | |
502 | break; | |
503 | case PL2_ENABLE: | |
504 | prim = POWER_LIMIT2; | |
505 | break; | |
506 | default: | |
507 | put_online_cpus(); | |
508 | return -EINVAL; | |
509 | } | |
510 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
511 | ret = -EIO; | |
512 | else | |
513 | *data = val; | |
514 | ||
515 | put_online_cpus(); | |
516 | ||
517 | return ret; | |
518 | } | |
519 | ||
e1399ba2 | 520 | static int set_time_window(struct powercap_zone *power_zone, int cid, |
2d281d81 JP |
521 | u64 window) |
522 | { | |
523 | struct rapl_domain *rd; | |
524 | int ret = 0; | |
e1399ba2 | 525 | int id; |
2d281d81 JP |
526 | |
527 | get_online_cpus(); | |
528 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 JP |
529 | id = contraint_to_pl(rd, cid); |
530 | ||
2d281d81 JP |
531 | switch (rd->rpl[id].prim_id) { |
532 | case PL1_ENABLE: | |
533 | rapl_write_data_raw(rd, TIME_WINDOW1, window); | |
534 | break; | |
535 | case PL2_ENABLE: | |
536 | rapl_write_data_raw(rd, TIME_WINDOW2, window); | |
537 | break; | |
538 | default: | |
539 | ret = -EINVAL; | |
540 | } | |
541 | put_online_cpus(); | |
542 | return ret; | |
543 | } | |
544 | ||
e1399ba2 | 545 | static int get_time_window(struct powercap_zone *power_zone, int cid, u64 *data) |
2d281d81 JP |
546 | { |
547 | struct rapl_domain *rd; | |
548 | u64 val; | |
549 | int ret = 0; | |
e1399ba2 | 550 | int id; |
2d281d81 JP |
551 | |
552 | get_online_cpus(); | |
553 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 JP |
554 | id = contraint_to_pl(rd, cid); |
555 | ||
2d281d81 JP |
556 | switch (rd->rpl[id].prim_id) { |
557 | case PL1_ENABLE: | |
558 | ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val); | |
559 | break; | |
560 | case PL2_ENABLE: | |
561 | ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val); | |
562 | break; | |
563 | default: | |
564 | put_online_cpus(); | |
565 | return -EINVAL; | |
566 | } | |
567 | if (!ret) | |
568 | *data = val; | |
569 | put_online_cpus(); | |
570 | ||
571 | return ret; | |
572 | } | |
573 | ||
e1399ba2 | 574 | static const char *get_constraint_name(struct powercap_zone *power_zone, int cid) |
2d281d81 | 575 | { |
2d281d81 | 576 | struct rapl_domain *rd; |
e1399ba2 | 577 | int id; |
2d281d81 JP |
578 | |
579 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 JP |
580 | id = contraint_to_pl(rd, cid); |
581 | if (id >= 0) | |
582 | return rd->rpl[id].name; | |
2d281d81 | 583 | |
e1399ba2 | 584 | return NULL; |
2d281d81 JP |
585 | } |
586 | ||
587 | ||
588 | static int get_max_power(struct powercap_zone *power_zone, int id, | |
589 | u64 *data) | |
590 | { | |
591 | struct rapl_domain *rd; | |
592 | u64 val; | |
593 | int prim; | |
594 | int ret = 0; | |
595 | ||
596 | get_online_cpus(); | |
597 | rd = power_zone_to_rapl_domain(power_zone); | |
598 | switch (rd->rpl[id].prim_id) { | |
599 | case PL1_ENABLE: | |
600 | prim = THERMAL_SPEC_POWER; | |
601 | break; | |
602 | case PL2_ENABLE: | |
603 | prim = MAX_POWER; | |
604 | break; | |
605 | default: | |
606 | put_online_cpus(); | |
607 | return -EINVAL; | |
608 | } | |
609 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
610 | ret = -EIO; | |
611 | else | |
612 | *data = val; | |
613 | ||
614 | put_online_cpus(); | |
615 | ||
616 | return ret; | |
617 | } | |
618 | ||
600c395b | 619 | static const struct powercap_zone_constraint_ops constraint_ops = { |
2d281d81 JP |
620 | .set_power_limit_uw = set_power_limit, |
621 | .get_power_limit_uw = get_current_power_limit, | |
622 | .set_time_window_us = set_time_window, | |
623 | .get_time_window_us = get_time_window, | |
624 | .get_max_power_uw = get_max_power, | |
625 | .get_name = get_constraint_name, | |
626 | }; | |
627 | ||
628 | /* called after domain detection and package level data are set */ | |
629 | static void rapl_init_domains(struct rapl_package *rp) | |
630 | { | |
631 | int i; | |
632 | struct rapl_domain *rd = rp->domains; | |
633 | ||
634 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
635 | unsigned int mask = rp->domain_map & (1 << i); | |
636 | switch (mask) { | |
637 | case BIT(RAPL_DOMAIN_PACKAGE): | |
638 | rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE]; | |
639 | rd->id = RAPL_DOMAIN_PACKAGE; | |
640 | rd->msrs[0] = MSR_PKG_POWER_LIMIT; | |
641 | rd->msrs[1] = MSR_PKG_ENERGY_STATUS; | |
642 | rd->msrs[2] = MSR_PKG_PERF_STATUS; | |
643 | rd->msrs[3] = 0; | |
644 | rd->msrs[4] = MSR_PKG_POWER_INFO; | |
645 | rd->rpl[0].prim_id = PL1_ENABLE; | |
646 | rd->rpl[0].name = pl1_name; | |
647 | rd->rpl[1].prim_id = PL2_ENABLE; | |
648 | rd->rpl[1].name = pl2_name; | |
649 | break; | |
650 | case BIT(RAPL_DOMAIN_PP0): | |
651 | rd->name = rapl_domain_names[RAPL_DOMAIN_PP0]; | |
652 | rd->id = RAPL_DOMAIN_PP0; | |
653 | rd->msrs[0] = MSR_PP0_POWER_LIMIT; | |
654 | rd->msrs[1] = MSR_PP0_ENERGY_STATUS; | |
655 | rd->msrs[2] = 0; | |
656 | rd->msrs[3] = MSR_PP0_POLICY; | |
657 | rd->msrs[4] = 0; | |
658 | rd->rpl[0].prim_id = PL1_ENABLE; | |
659 | rd->rpl[0].name = pl1_name; | |
660 | break; | |
661 | case BIT(RAPL_DOMAIN_PP1): | |
662 | rd->name = rapl_domain_names[RAPL_DOMAIN_PP1]; | |
663 | rd->id = RAPL_DOMAIN_PP1; | |
664 | rd->msrs[0] = MSR_PP1_POWER_LIMIT; | |
665 | rd->msrs[1] = MSR_PP1_ENERGY_STATUS; | |
666 | rd->msrs[2] = 0; | |
667 | rd->msrs[3] = MSR_PP1_POLICY; | |
668 | rd->msrs[4] = 0; | |
669 | rd->rpl[0].prim_id = PL1_ENABLE; | |
670 | rd->rpl[0].name = pl1_name; | |
671 | break; | |
672 | case BIT(RAPL_DOMAIN_DRAM): | |
673 | rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM]; | |
674 | rd->id = RAPL_DOMAIN_DRAM; | |
675 | rd->msrs[0] = MSR_DRAM_POWER_LIMIT; | |
676 | rd->msrs[1] = MSR_DRAM_ENERGY_STATUS; | |
677 | rd->msrs[2] = MSR_DRAM_PERF_STATUS; | |
678 | rd->msrs[3] = 0; | |
679 | rd->msrs[4] = MSR_DRAM_POWER_INFO; | |
680 | rd->rpl[0].prim_id = PL1_ENABLE; | |
681 | rd->rpl[0].name = pl1_name; | |
d474a4d3 JP |
682 | rd->domain_energy_unit = |
683 | rapl_defaults->dram_domain_energy_unit; | |
684 | if (rd->domain_energy_unit) | |
685 | pr_info("DRAM domain energy unit %dpj\n", | |
686 | rd->domain_energy_unit); | |
2d281d81 JP |
687 | break; |
688 | } | |
689 | if (mask) { | |
309557f5 | 690 | rd->rp = rp; |
2d281d81 JP |
691 | rd++; |
692 | } | |
693 | } | |
694 | } | |
695 | ||
309557f5 JP |
696 | static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type, |
697 | u64 value, int to_raw) | |
2d281d81 | 698 | { |
3c2c0845 | 699 | u64 units = 1; |
309557f5 | 700 | struct rapl_package *rp = rd->rp; |
d474a4d3 | 701 | u64 scale = 1; |
2d281d81 | 702 | |
2d281d81 JP |
703 | switch (type) { |
704 | case POWER_UNIT: | |
3c2c0845 | 705 | units = rp->power_unit; |
2d281d81 JP |
706 | break; |
707 | case ENERGY_UNIT: | |
d474a4d3 JP |
708 | scale = ENERGY_UNIT_SCALE; |
709 | /* per domain unit takes precedence */ | |
710 | if (rd && rd->domain_energy_unit) | |
711 | units = rd->domain_energy_unit; | |
712 | else | |
713 | units = rp->energy_unit; | |
2d281d81 JP |
714 | break; |
715 | case TIME_UNIT: | |
3c2c0845 | 716 | return rapl_defaults->compute_time_window(rp, value, to_raw); |
2d281d81 JP |
717 | case ARBITRARY_UNIT: |
718 | default: | |
719 | return value; | |
720 | }; | |
721 | ||
722 | if (to_raw) | |
d474a4d3 | 723 | return div64_u64(value, units) * scale; |
3c2c0845 JP |
724 | |
725 | value *= units; | |
726 | ||
d474a4d3 | 727 | return div64_u64(value, scale); |
2d281d81 JP |
728 | } |
729 | ||
730 | /* in the order of enum rapl_primitives */ | |
731 | static struct rapl_primitive_info rpi[] = { | |
732 | /* name, mask, shift, msr index, unit divisor */ | |
733 | PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, | |
734 | RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0), | |
735 | PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, | |
736 | RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0), | |
737 | PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, | |
738 | RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0), | |
739 | PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31, | |
740 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
741 | PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, | |
742 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
743 | PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, | |
744 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
745 | PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, | |
746 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
747 | PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, | |
748 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
749 | PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, | |
750 | RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0), | |
751 | PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, | |
752 | RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0), | |
753 | PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK, | |
754 | 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
755 | PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, | |
756 | RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
757 | PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, | |
758 | RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
759 | PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48, | |
760 | RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0), | |
761 | PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, | |
762 | RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0), | |
763 | PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, | |
764 | RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0), | |
765 | /* non-hardware */ | |
766 | PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT, | |
767 | RAPL_PRIMITIVE_DERIVED), | |
768 | {NULL, 0, 0, 0}, | |
769 | }; | |
770 | ||
771 | /* Read primitive data based on its related struct rapl_primitive_info. | |
772 | * if xlate flag is set, return translated data based on data units, i.e. | |
773 | * time, energy, and power. | |
774 | * RAPL MSRs are non-architectual and are laid out not consistently across | |
775 | * domains. Here we use primitive info to allow writing consolidated access | |
776 | * functions. | |
777 | * For a given primitive, it is processed by MSR mask and shift. Unit conversion | |
778 | * is pre-assigned based on RAPL unit MSRs read at init time. | |
779 | * 63-------------------------- 31--------------------------- 0 | |
780 | * | xxxxx (mask) | | |
781 | * | |<- shift ----------------| | |
782 | * 63-------------------------- 31--------------------------- 0 | |
783 | */ | |
784 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
785 | enum rapl_primitives prim, | |
786 | bool xlate, u64 *data) | |
787 | { | |
788 | u64 value, final; | |
789 | u32 msr; | |
790 | struct rapl_primitive_info *rp = &rpi[prim]; | |
791 | int cpu; | |
792 | ||
793 | if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY) | |
794 | return -EINVAL; | |
795 | ||
796 | msr = rd->msrs[rp->id]; | |
797 | if (!msr) | |
798 | return -EINVAL; | |
323ee64a JP |
799 | |
800 | cpu = rd->rp->lead_cpu; | |
2d281d81 JP |
801 | |
802 | /* special-case package domain, which uses a different bit*/ | |
803 | if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) { | |
804 | rp->mask = POWER_PACKAGE_LOCK; | |
805 | rp->shift = 63; | |
806 | } | |
807 | /* non-hardware data are collected by the polling thread */ | |
808 | if (rp->flag & RAPL_PRIMITIVE_DERIVED) { | |
809 | *data = rd->rdd.primitives[prim]; | |
810 | return 0; | |
811 | } | |
812 | ||
813 | if (rdmsrl_safe_on_cpu(cpu, msr, &value)) { | |
814 | pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu); | |
815 | return -EIO; | |
816 | } | |
817 | ||
818 | final = value & rp->mask; | |
819 | final = final >> rp->shift; | |
820 | if (xlate) | |
309557f5 | 821 | *data = rapl_unit_xlate(rd, rp->unit, final, 0); |
2d281d81 JP |
822 | else |
823 | *data = final; | |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
f14a1396 JP |
828 | |
829 | static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask) | |
830 | { | |
831 | int err; | |
832 | u64 val; | |
833 | ||
834 | err = rdmsrl_safe(msr_no, &val); | |
835 | if (err) | |
836 | goto out; | |
837 | ||
838 | val &= ~clear_mask; | |
839 | val |= set_mask; | |
840 | ||
841 | err = wrmsrl_safe(msr_no, val); | |
842 | ||
843 | out: | |
844 | return err; | |
845 | } | |
846 | ||
847 | static void msrl_update_func(void *info) | |
848 | { | |
849 | struct msrl_action *ma = info; | |
850 | ||
851 | ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask); | |
852 | } | |
853 | ||
2d281d81 JP |
854 | /* Similar use of primitive info in the read counterpart */ |
855 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
856 | enum rapl_primitives prim, | |
857 | unsigned long long value) | |
858 | { | |
2d281d81 JP |
859 | struct rapl_primitive_info *rp = &rpi[prim]; |
860 | int cpu; | |
f14a1396 JP |
861 | u64 bits; |
862 | struct msrl_action ma; | |
863 | int ret; | |
2d281d81 | 864 | |
323ee64a | 865 | cpu = rd->rp->lead_cpu; |
309557f5 | 866 | bits = rapl_unit_xlate(rd, rp->unit, value, 1); |
f14a1396 JP |
867 | bits |= bits << rp->shift; |
868 | memset(&ma, 0, sizeof(ma)); | |
869 | ||
870 | ma.msr_no = rd->msrs[rp->id]; | |
871 | ma.clear_mask = rp->mask; | |
872 | ma.set_mask = bits; | |
873 | ||
874 | ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1); | |
875 | if (ret) | |
876 | WARN_ON_ONCE(ret); | |
877 | else | |
878 | ret = ma.err; | |
879 | ||
880 | return ret; | |
2d281d81 JP |
881 | } |
882 | ||
3c2c0845 JP |
883 | /* |
884 | * Raw RAPL data stored in MSRs are in certain scales. We need to | |
885 | * convert them into standard units based on the units reported in | |
886 | * the RAPL unit MSRs. This is specific to CPUs as the method to | |
887 | * calculate units differ on different CPUs. | |
888 | * We convert the units to below format based on CPUs. | |
889 | * i.e. | |
d474a4d3 | 890 | * energy unit: picoJoules : Represented in picoJoules by default |
3c2c0845 JP |
891 | * power unit : microWatts : Represented in milliWatts by default |
892 | * time unit : microseconds: Represented in seconds by default | |
893 | */ | |
894 | static int rapl_check_unit_core(struct rapl_package *rp, int cpu) | |
2d281d81 JP |
895 | { |
896 | u64 msr_val; | |
897 | u32 value; | |
898 | ||
899 | if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) { | |
900 | pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n", | |
901 | MSR_RAPL_POWER_UNIT, cpu); | |
902 | return -ENODEV; | |
903 | } | |
904 | ||
2d281d81 | 905 | value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; |
d474a4d3 | 906 | rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); |
2d281d81 JP |
907 | |
908 | value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; | |
3c2c0845 | 909 | rp->power_unit = 1000000 / (1 << value); |
2d281d81 JP |
910 | |
911 | value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; | |
3c2c0845 | 912 | rp->time_unit = 1000000 / (1 << value); |
2d281d81 | 913 | |
d474a4d3 | 914 | pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n", |
3c2c0845 | 915 | rp->id, rp->energy_unit, rp->time_unit, rp->power_unit); |
2d281d81 JP |
916 | |
917 | return 0; | |
918 | } | |
919 | ||
3c2c0845 JP |
920 | static int rapl_check_unit_atom(struct rapl_package *rp, int cpu) |
921 | { | |
922 | u64 msr_val; | |
923 | u32 value; | |
924 | ||
925 | if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) { | |
926 | pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n", | |
927 | MSR_RAPL_POWER_UNIT, cpu); | |
928 | return -ENODEV; | |
929 | } | |
930 | value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; | |
d474a4d3 | 931 | rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value; |
3c2c0845 JP |
932 | |
933 | value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; | |
934 | rp->power_unit = (1 << value) * 1000; | |
935 | ||
936 | value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; | |
937 | rp->time_unit = 1000000 / (1 << value); | |
938 | ||
d474a4d3 | 939 | pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n", |
3c2c0845 JP |
940 | rp->id, rp->energy_unit, rp->time_unit, rp->power_unit); |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
f14a1396 JP |
945 | static void power_limit_irq_save_cpu(void *info) |
946 | { | |
947 | u32 l, h = 0; | |
948 | struct rapl_package *rp = (struct rapl_package *)info; | |
949 | ||
950 | /* save the state of PLN irq mask bit before disabling it */ | |
951 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
952 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) { | |
953 | rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE; | |
954 | rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED; | |
955 | } | |
956 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
957 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
958 | } | |
959 | ||
3c2c0845 | 960 | |
2d281d81 JP |
961 | /* REVISIT: |
962 | * When package power limit is set artificially low by RAPL, LVT | |
963 | * thermal interrupt for package power limit should be ignored | |
964 | * since we are not really exceeding the real limit. The intention | |
965 | * is to avoid excessive interrupts while we are trying to save power. | |
966 | * A useful feature might be routing the package_power_limit interrupt | |
967 | * to userspace via eventfd. once we have a usecase, this is simple | |
968 | * to do by adding an atomic notifier. | |
969 | */ | |
970 | ||
309557f5 | 971 | static void package_power_limit_irq_save(struct rapl_package *rp) |
2d281d81 | 972 | { |
f14a1396 JP |
973 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) |
974 | return; | |
975 | ||
323ee64a | 976 | smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1); |
f14a1396 JP |
977 | } |
978 | ||
979 | static void power_limit_irq_restore_cpu(void *info) | |
980 | { | |
981 | u32 l, h = 0; | |
982 | struct rapl_package *rp = (struct rapl_package *)info; | |
983 | ||
984 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
985 | ||
986 | if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE) | |
987 | l |= PACKAGE_THERM_INT_PLN_ENABLE; | |
988 | else | |
989 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
990 | ||
991 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
2d281d81 JP |
992 | } |
993 | ||
994 | /* restore per package power limit interrupt enable state */ | |
309557f5 | 995 | static void package_power_limit_irq_restore(struct rapl_package *rp) |
2d281d81 | 996 | { |
2d281d81 JP |
997 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) |
998 | return; | |
999 | ||
2d281d81 JP |
1000 | /* irq enable state not saved, nothing to restore */ |
1001 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) | |
1002 | return; | |
2d281d81 | 1003 | |
323ee64a | 1004 | smp_call_function_single(rp->lead_cpu, power_limit_irq_restore_cpu, rp, 1); |
2d281d81 JP |
1005 | } |
1006 | ||
3c2c0845 JP |
1007 | static void set_floor_freq_default(struct rapl_domain *rd, bool mode) |
1008 | { | |
1009 | int nr_powerlimit = find_nr_power_limit(rd); | |
1010 | ||
1011 | /* always enable clamp such that p-state can go below OS requested | |
1012 | * range. power capping priority over guranteed frequency. | |
1013 | */ | |
1014 | rapl_write_data_raw(rd, PL1_CLAMP, mode); | |
1015 | ||
1016 | /* some domains have pl2 */ | |
1017 | if (nr_powerlimit > 1) { | |
1018 | rapl_write_data_raw(rd, PL2_ENABLE, mode); | |
1019 | rapl_write_data_raw(rd, PL2_CLAMP, mode); | |
1020 | } | |
1021 | } | |
1022 | ||
1023 | static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) | |
1024 | { | |
1025 | static u32 power_ctrl_orig_val; | |
1026 | u32 mdata; | |
1027 | ||
51b63409 AT |
1028 | if (!rapl_defaults->floor_freq_reg_addr) { |
1029 | pr_err("Invalid floor frequency config register\n"); | |
1030 | return; | |
1031 | } | |
1032 | ||
3c2c0845 | 1033 | if (!power_ctrl_orig_val) |
4077a387 AS |
1034 | iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, |
1035 | rapl_defaults->floor_freq_reg_addr, | |
1036 | &power_ctrl_orig_val); | |
3c2c0845 JP |
1037 | mdata = power_ctrl_orig_val; |
1038 | if (enable) { | |
1039 | mdata &= ~(0x7f << 8); | |
1040 | mdata |= 1 << 8; | |
1041 | } | |
4077a387 AS |
1042 | iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, |
1043 | rapl_defaults->floor_freq_reg_addr, mdata); | |
3c2c0845 JP |
1044 | } |
1045 | ||
1046 | static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value, | |
1047 | bool to_raw) | |
1048 | { | |
1049 | u64 f, y; /* fraction and exp. used for time unit */ | |
1050 | ||
1051 | /* | |
1052 | * Special processing based on 2^Y*(1+F/4), refer | |
1053 | * to Intel Software Developer's manual Vol.3B: CH 14.9.3. | |
1054 | */ | |
1055 | if (!to_raw) { | |
1056 | f = (value & 0x60) >> 5; | |
1057 | y = value & 0x1f; | |
1058 | value = (1 << y) * (4 + f) * rp->time_unit / 4; | |
1059 | } else { | |
1060 | do_div(value, rp->time_unit); | |
1061 | y = ilog2(value); | |
1062 | f = div64_u64(4 * (value - (1 << y)), 1 << y); | |
1063 | value = (y & 0x1f) | ((f & 0x3) << 5); | |
1064 | } | |
1065 | return value; | |
1066 | } | |
1067 | ||
1068 | static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value, | |
1069 | bool to_raw) | |
1070 | { | |
1071 | /* | |
1072 | * Atom time unit encoding is straight forward val * time_unit, | |
1073 | * where time_unit is default to 1 sec. Never 0. | |
1074 | */ | |
1075 | if (!to_raw) | |
1076 | return (value) ? value *= rp->time_unit : rp->time_unit; | |
1077 | else | |
1078 | value = div64_u64(value, rp->time_unit); | |
1079 | ||
1080 | return value; | |
1081 | } | |
1082 | ||
087e9cba | 1083 | static const struct rapl_defaults rapl_defaults_core = { |
51b63409 | 1084 | .floor_freq_reg_addr = 0, |
3c2c0845 JP |
1085 | .check_unit = rapl_check_unit_core, |
1086 | .set_floor_freq = set_floor_freq_default, | |
1087 | .compute_time_window = rapl_compute_time_window_core, | |
087e9cba JP |
1088 | }; |
1089 | ||
d474a4d3 JP |
1090 | static const struct rapl_defaults rapl_defaults_hsw_server = { |
1091 | .check_unit = rapl_check_unit_core, | |
1092 | .set_floor_freq = set_floor_freq_default, | |
1093 | .compute_time_window = rapl_compute_time_window_core, | |
1094 | .dram_domain_energy_unit = 15300, | |
1095 | }; | |
1096 | ||
51b63409 AT |
1097 | static const struct rapl_defaults rapl_defaults_byt = { |
1098 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, | |
1099 | .check_unit = rapl_check_unit_atom, | |
1100 | .set_floor_freq = set_floor_freq_atom, | |
1101 | .compute_time_window = rapl_compute_time_window_atom, | |
1102 | }; | |
1103 | ||
1104 | static const struct rapl_defaults rapl_defaults_tng = { | |
1105 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, | |
3c2c0845 JP |
1106 | .check_unit = rapl_check_unit_atom, |
1107 | .set_floor_freq = set_floor_freq_atom, | |
1108 | .compute_time_window = rapl_compute_time_window_atom, | |
087e9cba JP |
1109 | }; |
1110 | ||
51b63409 AT |
1111 | static const struct rapl_defaults rapl_defaults_ann = { |
1112 | .floor_freq_reg_addr = 0, | |
1113 | .check_unit = rapl_check_unit_atom, | |
1114 | .set_floor_freq = NULL, | |
1115 | .compute_time_window = rapl_compute_time_window_atom, | |
1116 | }; | |
1117 | ||
1118 | static const struct rapl_defaults rapl_defaults_cht = { | |
1119 | .floor_freq_reg_addr = 0, | |
1120 | .check_unit = rapl_check_unit_atom, | |
1121 | .set_floor_freq = NULL, | |
1122 | .compute_time_window = rapl_compute_time_window_atom, | |
1123 | }; | |
1124 | ||
087e9cba JP |
1125 | #define RAPL_CPU(_model, _ops) { \ |
1126 | .vendor = X86_VENDOR_INTEL, \ | |
1127 | .family = 6, \ | |
1128 | .model = _model, \ | |
1129 | .driver_data = (kernel_ulong_t)&_ops, \ | |
1130 | } | |
1131 | ||
ea85dbca | 1132 | static const struct x86_cpu_id rapl_ids[] __initconst = { |
62d16733 DH |
1133 | RAPL_CPU(INTEL_FAM6_SANDYBRIDGE, rapl_defaults_core), |
1134 | RAPL_CPU(INTEL_FAM6_SANDYBRIDGE_X, rapl_defaults_core), | |
0bb04b5f | 1135 | |
62d16733 | 1136 | RAPL_CPU(INTEL_FAM6_IVYBRIDGE, rapl_defaults_core), |
7d188478 | 1137 | RAPL_CPU(INTEL_FAM6_IVYBRIDGE_X, rapl_defaults_core), |
0bb04b5f | 1138 | |
62d16733 | 1139 | RAPL_CPU(INTEL_FAM6_HASWELL_CORE, rapl_defaults_core), |
62d16733 DH |
1140 | RAPL_CPU(INTEL_FAM6_HASWELL_ULT, rapl_defaults_core), |
1141 | RAPL_CPU(INTEL_FAM6_HASWELL_GT3E, rapl_defaults_core), | |
0bb04b5f DH |
1142 | RAPL_CPU(INTEL_FAM6_HASWELL_X, rapl_defaults_hsw_server), |
1143 | ||
1144 | RAPL_CPU(INTEL_FAM6_BROADWELL_CORE, rapl_defaults_core), | |
62d16733 | 1145 | RAPL_CPU(INTEL_FAM6_BROADWELL_GT3E, rapl_defaults_core), |
0bb04b5f DH |
1146 | RAPL_CPU(INTEL_FAM6_BROADWELL_XEON_D, rapl_defaults_core), |
1147 | RAPL_CPU(INTEL_FAM6_BROADWELL_X, rapl_defaults_hsw_server), | |
1148 | ||
1149 | RAPL_CPU(INTEL_FAM6_SKYLAKE_DESKTOP, rapl_defaults_core), | |
62d16733 | 1150 | RAPL_CPU(INTEL_FAM6_SKYLAKE_MOBILE, rapl_defaults_core), |
d40671e3 | 1151 | RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server), |
0bb04b5f DH |
1152 | RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core), |
1153 | RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core), | |
1154 | ||
1155 | RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt), | |
62d16733 | 1156 | RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht), |
f5fbf848 AS |
1157 | RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD, rapl_defaults_tng), |
1158 | RAPL_CPU(INTEL_FAM6_ATOM_MOOREFIELD, rapl_defaults_ann), | |
62d16733 | 1159 | RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT, rapl_defaults_core), |
ab0d15df | 1160 | RAPL_CPU(INTEL_FAM6_ATOM_DENVERTON, rapl_defaults_core), |
0bb04b5f | 1161 | |
62d16733 | 1162 | RAPL_CPU(INTEL_FAM6_XEON_PHI_KNL, rapl_defaults_hsw_server), |
2d281d81 JP |
1163 | {} |
1164 | }; | |
1165 | MODULE_DEVICE_TABLE(x86cpu, rapl_ids); | |
1166 | ||
1167 | /* read once for all raw primitive data for all packages, domains */ | |
1168 | static void rapl_update_domain_data(void) | |
1169 | { | |
1170 | int dmn, prim; | |
1171 | u64 val; | |
1172 | struct rapl_package *rp; | |
1173 | ||
1174 | list_for_each_entry(rp, &rapl_packages, plist) { | |
1175 | for (dmn = 0; dmn < rp->nr_domains; dmn++) { | |
1176 | pr_debug("update package %d domain %s data\n", rp->id, | |
1177 | rp->domains[dmn].name); | |
1178 | /* exclude non-raw primitives */ | |
1179 | for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) | |
1180 | if (!rapl_read_data_raw(&rp->domains[dmn], prim, | |
1181 | rpi[prim].unit, | |
1182 | &val)) | |
1183 | rp->domains[dmn].rdd.primitives[prim] = | |
1184 | val; | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | } | |
1189 | ||
1190 | static int rapl_unregister_powercap(void) | |
1191 | { | |
1192 | struct rapl_package *rp; | |
1193 | struct rapl_domain *rd, *rd_package = NULL; | |
1194 | ||
1195 | /* unregister all active rapl packages from the powercap layer, | |
1196 | * hotplug lock held | |
1197 | */ | |
1198 | list_for_each_entry(rp, &rapl_packages, plist) { | |
309557f5 | 1199 | package_power_limit_irq_restore(rp); |
2d281d81 JP |
1200 | |
1201 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; | |
1202 | rd++) { | |
1203 | pr_debug("remove package, undo power limit on %d: %s\n", | |
1204 | rp->id, rd->name); | |
1205 | rapl_write_data_raw(rd, PL1_ENABLE, 0); | |
2d281d81 | 1206 | rapl_write_data_raw(rd, PL1_CLAMP, 0); |
5021282c SI |
1207 | if (find_nr_power_limit(rd) > 1) { |
1208 | rapl_write_data_raw(rd, PL2_ENABLE, 0); | |
1209 | rapl_write_data_raw(rd, PL2_CLAMP, 0); | |
1210 | } | |
2d281d81 JP |
1211 | if (rd->id == RAPL_DOMAIN_PACKAGE) { |
1212 | rd_package = rd; | |
1213 | continue; | |
1214 | } | |
1215 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1216 | } | |
1217 | /* do the package zone last */ | |
1218 | if (rd_package) | |
1219 | powercap_unregister_zone(control_type, | |
1220 | &rd_package->power_zone); | |
1221 | } | |
3521ba1c SP |
1222 | |
1223 | if (platform_rapl_domain) { | |
1224 | powercap_unregister_zone(control_type, | |
1225 | &platform_rapl_domain->power_zone); | |
1226 | kfree(platform_rapl_domain); | |
1227 | } | |
1228 | ||
2d281d81 JP |
1229 | powercap_unregister_control_type(control_type); |
1230 | ||
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | static int rapl_package_register_powercap(struct rapl_package *rp) | |
1235 | { | |
1236 | struct rapl_domain *rd; | |
1237 | int ret = 0; | |
1238 | char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/ | |
1239 | struct powercap_zone *power_zone = NULL; | |
1240 | int nr_pl; | |
1241 | ||
1242 | /* first we register package domain as the parent zone*/ | |
1243 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1244 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
1245 | nr_pl = find_nr_power_limit(rd); | |
1246 | pr_debug("register socket %d package domain %s\n", | |
1247 | rp->id, rd->name); | |
1248 | memset(dev_name, 0, sizeof(dev_name)); | |
1249 | snprintf(dev_name, sizeof(dev_name), "%s-%d", | |
1250 | rd->name, rp->id); | |
1251 | power_zone = powercap_register_zone(&rd->power_zone, | |
1252 | control_type, | |
1253 | dev_name, NULL, | |
1254 | &zone_ops[rd->id], | |
1255 | nr_pl, | |
1256 | &constraint_ops); | |
1257 | if (IS_ERR(power_zone)) { | |
1258 | pr_debug("failed to register package, %d\n", | |
1259 | rp->id); | |
1260 | ret = PTR_ERR(power_zone); | |
1261 | goto exit_package; | |
1262 | } | |
1263 | /* track parent zone in per package/socket data */ | |
1264 | rp->power_zone = power_zone; | |
1265 | /* done, only one package domain per socket */ | |
1266 | break; | |
1267 | } | |
1268 | } | |
1269 | if (!power_zone) { | |
1270 | pr_err("no package domain found, unknown topology!\n"); | |
1271 | ret = -ENODEV; | |
1272 | goto exit_package; | |
1273 | } | |
1274 | /* now register domains as children of the socket/package*/ | |
1275 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1276 | if (rd->id == RAPL_DOMAIN_PACKAGE) | |
1277 | continue; | |
1278 | /* number of power limits per domain varies */ | |
1279 | nr_pl = find_nr_power_limit(rd); | |
1280 | power_zone = powercap_register_zone(&rd->power_zone, | |
1281 | control_type, rd->name, | |
1282 | rp->power_zone, | |
1283 | &zone_ops[rd->id], nr_pl, | |
1284 | &constraint_ops); | |
1285 | ||
1286 | if (IS_ERR(power_zone)) { | |
1287 | pr_debug("failed to register power_zone, %d:%s:%s\n", | |
1288 | rp->id, rd->name, dev_name); | |
1289 | ret = PTR_ERR(power_zone); | |
1290 | goto err_cleanup; | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | exit_package: | |
1295 | return ret; | |
1296 | err_cleanup: | |
1297 | /* clean up previously initialized domains within the package if we | |
1298 | * failed after the first domain setup. | |
1299 | */ | |
1300 | while (--rd >= rp->domains) { | |
1301 | pr_debug("unregister package %d domain %s\n", rp->id, rd->name); | |
1302 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1303 | } | |
1304 | ||
1305 | return ret; | |
1306 | } | |
1307 | ||
3521ba1c SP |
1308 | static int rapl_register_psys(void) |
1309 | { | |
1310 | struct rapl_domain *rd; | |
1311 | struct powercap_zone *power_zone; | |
1312 | u64 val; | |
1313 | ||
1314 | if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val) | |
1315 | return -ENODEV; | |
1316 | ||
1317 | if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val) | |
1318 | return -ENODEV; | |
1319 | ||
1320 | rd = kzalloc(sizeof(*rd), GFP_KERNEL); | |
1321 | if (!rd) | |
1322 | return -ENOMEM; | |
1323 | ||
1324 | rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM]; | |
1325 | rd->id = RAPL_DOMAIN_PLATFORM; | |
1326 | rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT; | |
1327 | rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS; | |
1328 | rd->rpl[0].prim_id = PL1_ENABLE; | |
1329 | rd->rpl[0].name = pl1_name; | |
1330 | rd->rpl[1].prim_id = PL2_ENABLE; | |
1331 | rd->rpl[1].name = pl2_name; | |
1332 | rd->rp = find_package_by_id(0); | |
1333 | ||
1334 | power_zone = powercap_register_zone(&rd->power_zone, control_type, | |
1335 | "psys", NULL, | |
1336 | &zone_ops[RAPL_DOMAIN_PLATFORM], | |
1337 | 2, &constraint_ops); | |
1338 | ||
1339 | if (IS_ERR(power_zone)) { | |
1340 | kfree(rd); | |
1341 | return PTR_ERR(power_zone); | |
1342 | } | |
1343 | ||
1344 | platform_rapl_domain = rd; | |
1345 | ||
1346 | return 0; | |
1347 | } | |
1348 | ||
2d281d81 JP |
1349 | static int rapl_register_powercap(void) |
1350 | { | |
1351 | struct rapl_domain *rd; | |
1352 | struct rapl_package *rp; | |
1353 | int ret = 0; | |
1354 | ||
1355 | control_type = powercap_register_control_type(NULL, "intel-rapl", NULL); | |
1356 | if (IS_ERR(control_type)) { | |
1357 | pr_debug("failed to register powercap control_type.\n"); | |
1358 | return PTR_ERR(control_type); | |
1359 | } | |
1360 | /* read the initial data */ | |
1361 | rapl_update_domain_data(); | |
1362 | list_for_each_entry(rp, &rapl_packages, plist) | |
1363 | if (rapl_package_register_powercap(rp)) | |
1364 | goto err_cleanup_package; | |
3521ba1c SP |
1365 | |
1366 | /* Don't bail out if PSys is not supported */ | |
1367 | rapl_register_psys(); | |
1368 | ||
2d281d81 JP |
1369 | return ret; |
1370 | ||
1371 | err_cleanup_package: | |
1372 | /* clean up previously initialized packages */ | |
1373 | list_for_each_entry_continue_reverse(rp, &rapl_packages, plist) { | |
1374 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; | |
1375 | rd++) { | |
1376 | pr_debug("unregister zone/package %d, %s domain\n", | |
1377 | rp->id, rd->name); | |
1378 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | return ret; | |
1383 | } | |
1384 | ||
1385 | static int rapl_check_domain(int cpu, int domain) | |
1386 | { | |
1387 | unsigned msr; | |
9d31c676 | 1388 | u64 val = 0; |
2d281d81 JP |
1389 | |
1390 | switch (domain) { | |
1391 | case RAPL_DOMAIN_PACKAGE: | |
1392 | msr = MSR_PKG_ENERGY_STATUS; | |
1393 | break; | |
1394 | case RAPL_DOMAIN_PP0: | |
1395 | msr = MSR_PP0_ENERGY_STATUS; | |
1396 | break; | |
1397 | case RAPL_DOMAIN_PP1: | |
1398 | msr = MSR_PP1_ENERGY_STATUS; | |
1399 | break; | |
1400 | case RAPL_DOMAIN_DRAM: | |
1401 | msr = MSR_DRAM_ENERGY_STATUS; | |
1402 | break; | |
3521ba1c SP |
1403 | case RAPL_DOMAIN_PLATFORM: |
1404 | /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */ | |
1405 | return -EINVAL; | |
2d281d81 JP |
1406 | default: |
1407 | pr_err("invalid domain id %d\n", domain); | |
1408 | return -EINVAL; | |
1409 | } | |
9d31c676 JP |
1410 | /* make sure domain counters are available and contains non-zero |
1411 | * values, otherwise skip it. | |
7b874772 | 1412 | */ |
9d31c676 JP |
1413 | if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val) |
1414 | return -ENODEV; | |
2d281d81 | 1415 | |
9d31c676 | 1416 | return 0; |
2d281d81 JP |
1417 | } |
1418 | ||
e1399ba2 JP |
1419 | |
1420 | /* | |
1421 | * Check if power limits are available. Two cases when they are not available: | |
1422 | * 1. Locked by BIOS, in this case we still provide read-only access so that | |
1423 | * users can see what limit is set by the BIOS. | |
1424 | * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not | |
1425 | * exist at all. In this case, we do not show the contraints in powercap. | |
1426 | * | |
1427 | * Called after domains are detected and initialized. | |
1428 | */ | |
1429 | static void rapl_detect_powerlimit(struct rapl_domain *rd) | |
1430 | { | |
1431 | u64 val64; | |
1432 | int i; | |
1433 | ||
1434 | /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */ | |
1435 | if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) { | |
1436 | if (val64) { | |
1437 | pr_info("RAPL package %d domain %s locked by BIOS\n", | |
1438 | rd->rp->id, rd->name); | |
1439 | rd->state |= DOMAIN_STATE_BIOS_LOCKED; | |
1440 | } | |
1441 | } | |
1442 | /* check if power limit MSRs exists, otherwise domain is monitoring only */ | |
1443 | for (i = 0; i < NR_POWER_LIMITS; i++) { | |
1444 | int prim = rd->rpl[i].prim_id; | |
1445 | if (rapl_read_data_raw(rd, prim, false, &val64)) | |
1446 | rd->rpl[i].name = NULL; | |
1447 | } | |
1448 | } | |
1449 | ||
2d281d81 JP |
1450 | /* Detect active and valid domains for the given CPU, caller must |
1451 | * ensure the CPU belongs to the targeted package and CPU hotlug is disabled. | |
1452 | */ | |
1453 | static int rapl_detect_domains(struct rapl_package *rp, int cpu) | |
1454 | { | |
1455 | int i; | |
1456 | int ret = 0; | |
1457 | struct rapl_domain *rd; | |
2d281d81 JP |
1458 | |
1459 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
1460 | /* use physical package id to read counters */ | |
fcdf1797 | 1461 | if (!rapl_check_domain(cpu, i)) { |
2d281d81 | 1462 | rp->domain_map |= 1 << i; |
fcdf1797 JP |
1463 | pr_info("Found RAPL domain %s\n", rapl_domain_names[i]); |
1464 | } | |
2d281d81 JP |
1465 | } |
1466 | rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX); | |
1467 | if (!rp->nr_domains) { | |
e1a27e87 | 1468 | pr_debug("no valid rapl domains found in package %d\n", rp->id); |
2d281d81 JP |
1469 | ret = -ENODEV; |
1470 | goto done; | |
1471 | } | |
1472 | pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id); | |
1473 | ||
1474 | rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain), | |
1475 | GFP_KERNEL); | |
1476 | if (!rp->domains) { | |
1477 | ret = -ENOMEM; | |
1478 | goto done; | |
1479 | } | |
1480 | rapl_init_domains(rp); | |
1481 | ||
e1399ba2 JP |
1482 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) |
1483 | rapl_detect_powerlimit(rd); | |
1484 | ||
2d281d81 JP |
1485 | |
1486 | ||
1487 | done: | |
1488 | return ret; | |
1489 | } | |
1490 | ||
1491 | static bool is_package_new(int package) | |
1492 | { | |
1493 | struct rapl_package *rp; | |
1494 | ||
1495 | /* caller prevents cpu hotplug, there will be no new packages added | |
1496 | * or deleted while traversing the package list, no need for locking. | |
1497 | */ | |
1498 | list_for_each_entry(rp, &rapl_packages, plist) | |
1499 | if (package == rp->id) | |
1500 | return false; | |
1501 | ||
1502 | return true; | |
1503 | } | |
1504 | ||
1505 | /* RAPL interface can be made of a two-level hierarchy: package level and domain | |
1506 | * level. We first detect the number of packages then domains of each package. | |
1507 | * We have to consider the possiblity of CPU online/offline due to hotplug and | |
1508 | * other scenarios. | |
1509 | */ | |
1510 | static int rapl_detect_topology(void) | |
1511 | { | |
1512 | int i; | |
1513 | int phy_package_id; | |
1514 | struct rapl_package *new_package, *rp; | |
1515 | ||
1516 | for_each_online_cpu(i) { | |
1517 | phy_package_id = topology_physical_package_id(i); | |
1518 | if (is_package_new(phy_package_id)) { | |
1519 | new_package = kzalloc(sizeof(*rp), GFP_KERNEL); | |
1520 | if (!new_package) { | |
1521 | rapl_cleanup_data(); | |
1522 | return -ENOMEM; | |
1523 | } | |
1524 | /* add the new package to the list */ | |
1525 | new_package->id = phy_package_id; | |
1526 | new_package->nr_cpus = 1; | |
323ee64a JP |
1527 | /* use the first active cpu of the package to access */ |
1528 | new_package->lead_cpu = i; | |
2d281d81 JP |
1529 | /* check if the package contains valid domains */ |
1530 | if (rapl_detect_domains(new_package, i) || | |
3c2c0845 | 1531 | rapl_defaults->check_unit(new_package, i)) { |
2d281d81 JP |
1532 | kfree(new_package->domains); |
1533 | kfree(new_package); | |
1534 | /* free up the packages already initialized */ | |
1535 | rapl_cleanup_data(); | |
1536 | return -ENODEV; | |
1537 | } | |
1538 | INIT_LIST_HEAD(&new_package->plist); | |
1539 | list_add(&new_package->plist, &rapl_packages); | |
1540 | } else { | |
1541 | rp = find_package_by_id(phy_package_id); | |
1542 | if (rp) | |
1543 | ++rp->nr_cpus; | |
1544 | } | |
1545 | } | |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
1550 | /* called from CPU hotplug notifier, hotplug lock held */ | |
1551 | static void rapl_remove_package(struct rapl_package *rp) | |
1552 | { | |
1553 | struct rapl_domain *rd, *rd_package = NULL; | |
1554 | ||
1555 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1556 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
1557 | rd_package = rd; | |
1558 | continue; | |
1559 | } | |
1560 | pr_debug("remove package %d, %s domain\n", rp->id, rd->name); | |
1561 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1562 | } | |
1563 | /* do parent zone last */ | |
1564 | powercap_unregister_zone(control_type, &rd_package->power_zone); | |
1565 | list_del(&rp->plist); | |
1566 | kfree(rp); | |
1567 | } | |
1568 | ||
1569 | /* called from CPU hotplug notifier, hotplug lock held */ | |
1570 | static int rapl_add_package(int cpu) | |
1571 | { | |
1572 | int ret = 0; | |
1573 | int phy_package_id; | |
1574 | struct rapl_package *rp; | |
1575 | ||
1576 | phy_package_id = topology_physical_package_id(cpu); | |
1577 | rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL); | |
1578 | if (!rp) | |
1579 | return -ENOMEM; | |
1580 | ||
1581 | /* add the new package to the list */ | |
1582 | rp->id = phy_package_id; | |
1583 | rp->nr_cpus = 1; | |
323ee64a JP |
1584 | rp->lead_cpu = cpu; |
1585 | ||
2d281d81 JP |
1586 | /* check if the package contains valid domains */ |
1587 | if (rapl_detect_domains(rp, cpu) || | |
3c2c0845 | 1588 | rapl_defaults->check_unit(rp, cpu)) { |
2d281d81 JP |
1589 | ret = -ENODEV; |
1590 | goto err_free_package; | |
1591 | } | |
1592 | if (!rapl_package_register_powercap(rp)) { | |
1593 | INIT_LIST_HEAD(&rp->plist); | |
1594 | list_add(&rp->plist, &rapl_packages); | |
1595 | return ret; | |
1596 | } | |
1597 | ||
1598 | err_free_package: | |
1599 | kfree(rp->domains); | |
1600 | kfree(rp); | |
1601 | ||
1602 | return ret; | |
1603 | } | |
1604 | ||
1605 | /* Handles CPU hotplug on multi-socket systems. | |
1606 | * If a CPU goes online as the first CPU of the physical package | |
1607 | * we add the RAPL package to the system. Similarly, when the last | |
1608 | * CPU of the package is removed, we remove the RAPL package and its | |
1609 | * associated domains. Cooling devices are handled accordingly at | |
1610 | * per-domain level. | |
1611 | */ | |
1612 | static int rapl_cpu_callback(struct notifier_block *nfb, | |
1613 | unsigned long action, void *hcpu) | |
1614 | { | |
1615 | unsigned long cpu = (unsigned long)hcpu; | |
1616 | int phy_package_id; | |
1617 | struct rapl_package *rp; | |
323ee64a | 1618 | int lead_cpu; |
2d281d81 JP |
1619 | |
1620 | phy_package_id = topology_physical_package_id(cpu); | |
1621 | switch (action) { | |
1622 | case CPU_ONLINE: | |
1623 | case CPU_ONLINE_FROZEN: | |
1624 | case CPU_DOWN_FAILED: | |
1625 | case CPU_DOWN_FAILED_FROZEN: | |
1626 | rp = find_package_by_id(phy_package_id); | |
1627 | if (rp) | |
1628 | ++rp->nr_cpus; | |
1629 | else | |
1630 | rapl_add_package(cpu); | |
1631 | break; | |
1632 | case CPU_DOWN_PREPARE: | |
1633 | case CPU_DOWN_PREPARE_FROZEN: | |
1634 | rp = find_package_by_id(phy_package_id); | |
1635 | if (!rp) | |
1636 | break; | |
1637 | if (--rp->nr_cpus == 0) | |
1638 | rapl_remove_package(rp); | |
323ee64a JP |
1639 | else if (cpu == rp->lead_cpu) { |
1640 | /* choose another active cpu in the package */ | |
1641 | lead_cpu = cpumask_any_but(topology_core_cpumask(cpu), cpu); | |
1642 | if (lead_cpu < nr_cpu_ids) | |
1643 | rp->lead_cpu = lead_cpu; | |
1644 | else /* should never go here */ | |
1645 | pr_err("no active cpu available for package %d\n", | |
1646 | phy_package_id); | |
1647 | } | |
2d281d81 JP |
1648 | } |
1649 | ||
1650 | return NOTIFY_OK; | |
1651 | } | |
1652 | ||
1653 | static struct notifier_block rapl_cpu_notifier = { | |
1654 | .notifier_call = rapl_cpu_callback, | |
1655 | }; | |
1656 | ||
1657 | static int __init rapl_init(void) | |
1658 | { | |
1659 | int ret = 0; | |
087e9cba | 1660 | const struct x86_cpu_id *id; |
2d281d81 | 1661 | |
087e9cba JP |
1662 | id = x86_match_cpu(rapl_ids); |
1663 | if (!id) { | |
2d281d81 JP |
1664 | pr_err("driver does not support CPU family %d model %d\n", |
1665 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
1666 | ||
1667 | return -ENODEV; | |
1668 | } | |
009f225e | 1669 | |
087e9cba JP |
1670 | rapl_defaults = (struct rapl_defaults *)id->driver_data; |
1671 | ||
009f225e SB |
1672 | cpu_notifier_register_begin(); |
1673 | ||
2d281d81 JP |
1674 | /* prevent CPU hotplug during detection */ |
1675 | get_online_cpus(); | |
1676 | ret = rapl_detect_topology(); | |
1677 | if (ret) | |
1678 | goto done; | |
1679 | ||
1680 | if (rapl_register_powercap()) { | |
1681 | rapl_cleanup_data(); | |
1682 | ret = -ENODEV; | |
1683 | goto done; | |
1684 | } | |
009f225e | 1685 | __register_hotcpu_notifier(&rapl_cpu_notifier); |
2d281d81 JP |
1686 | done: |
1687 | put_online_cpus(); | |
009f225e | 1688 | cpu_notifier_register_done(); |
2d281d81 JP |
1689 | |
1690 | return ret; | |
1691 | } | |
1692 | ||
1693 | static void __exit rapl_exit(void) | |
1694 | { | |
009f225e | 1695 | cpu_notifier_register_begin(); |
2d281d81 | 1696 | get_online_cpus(); |
009f225e | 1697 | __unregister_hotcpu_notifier(&rapl_cpu_notifier); |
2d281d81 JP |
1698 | rapl_unregister_powercap(); |
1699 | rapl_cleanup_data(); | |
1700 | put_online_cpus(); | |
009f225e | 1701 | cpu_notifier_register_done(); |
2d281d81 JP |
1702 | } |
1703 | ||
1704 | module_init(rapl_init); | |
1705 | module_exit(rapl_exit); | |
1706 | ||
1707 | MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)"); | |
1708 | MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); | |
1709 | MODULE_LICENSE("GPL v2"); |