Commit | Line | Data |
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2d281d81 JP |
1 | /* |
2 | * Intel Running Average Power Limit (RAPL) Driver | |
3 | * Copyright (c) 2013, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc. | |
16 | * | |
17 | */ | |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/log2.h> | |
27 | #include <linux/bitmap.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/sysfs.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/powercap.h> | |
3c2c0845 | 32 | #include <asm/iosf_mbi.h> |
2d281d81 JP |
33 | |
34 | #include <asm/processor.h> | |
35 | #include <asm/cpu_device_id.h> | |
62d16733 | 36 | #include <asm/intel-family.h> |
2d281d81 | 37 | |
3521ba1c SP |
38 | /* Local defines */ |
39 | #define MSR_PLATFORM_POWER_LIMIT 0x0000065C | |
40 | ||
2d281d81 JP |
41 | /* bitmasks for RAPL MSRs, used by primitive access functions */ |
42 | #define ENERGY_STATUS_MASK 0xffffffff | |
43 | ||
44 | #define POWER_LIMIT1_MASK 0x7FFF | |
45 | #define POWER_LIMIT1_ENABLE BIT(15) | |
46 | #define POWER_LIMIT1_CLAMP BIT(16) | |
47 | ||
48 | #define POWER_LIMIT2_MASK (0x7FFFULL<<32) | |
49 | #define POWER_LIMIT2_ENABLE BIT_ULL(47) | |
50 | #define POWER_LIMIT2_CLAMP BIT_ULL(48) | |
51 | #define POWER_PACKAGE_LOCK BIT_ULL(63) | |
52 | #define POWER_PP_LOCK BIT(31) | |
53 | ||
54 | #define TIME_WINDOW1_MASK (0x7FULL<<17) | |
55 | #define TIME_WINDOW2_MASK (0x7FULL<<49) | |
56 | ||
57 | #define POWER_UNIT_OFFSET 0 | |
58 | #define POWER_UNIT_MASK 0x0F | |
59 | ||
60 | #define ENERGY_UNIT_OFFSET 0x08 | |
61 | #define ENERGY_UNIT_MASK 0x1F00 | |
62 | ||
63 | #define TIME_UNIT_OFFSET 0x10 | |
64 | #define TIME_UNIT_MASK 0xF0000 | |
65 | ||
66 | #define POWER_INFO_MAX_MASK (0x7fffULL<<32) | |
67 | #define POWER_INFO_MIN_MASK (0x7fffULL<<16) | |
68 | #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) | |
69 | #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff | |
70 | ||
71 | #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff | |
72 | #define PP_POLICY_MASK 0x1F | |
73 | ||
74 | /* Non HW constants */ | |
75 | #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ | |
76 | #define RAPL_PRIMITIVE_DUMMY BIT(2) | |
77 | ||
2d281d81 JP |
78 | #define TIME_WINDOW_MAX_MSEC 40000 |
79 | #define TIME_WINDOW_MIN_MSEC 250 | |
d474a4d3 | 80 | #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ |
2d281d81 JP |
81 | enum unit_type { |
82 | ARBITRARY_UNIT, /* no translation */ | |
83 | POWER_UNIT, | |
84 | ENERGY_UNIT, | |
85 | TIME_UNIT, | |
86 | }; | |
87 | ||
88 | enum rapl_domain_type { | |
89 | RAPL_DOMAIN_PACKAGE, /* entire package/socket */ | |
90 | RAPL_DOMAIN_PP0, /* core power plane */ | |
91 | RAPL_DOMAIN_PP1, /* graphics uncore */ | |
92 | RAPL_DOMAIN_DRAM,/* DRAM control_type */ | |
3521ba1c | 93 | RAPL_DOMAIN_PLATFORM, /* PSys control_type */ |
2d281d81 JP |
94 | RAPL_DOMAIN_MAX, |
95 | }; | |
96 | ||
97 | enum rapl_domain_msr_id { | |
98 | RAPL_DOMAIN_MSR_LIMIT, | |
99 | RAPL_DOMAIN_MSR_STATUS, | |
100 | RAPL_DOMAIN_MSR_PERF, | |
101 | RAPL_DOMAIN_MSR_POLICY, | |
102 | RAPL_DOMAIN_MSR_INFO, | |
103 | RAPL_DOMAIN_MSR_MAX, | |
104 | }; | |
105 | ||
106 | /* per domain data, some are optional */ | |
107 | enum rapl_primitives { | |
108 | ENERGY_COUNTER, | |
109 | POWER_LIMIT1, | |
110 | POWER_LIMIT2, | |
111 | FW_LOCK, | |
112 | ||
113 | PL1_ENABLE, /* power limit 1, aka long term */ | |
114 | PL1_CLAMP, /* allow frequency to go below OS request */ | |
115 | PL2_ENABLE, /* power limit 2, aka short term, instantaneous */ | |
116 | PL2_CLAMP, | |
117 | ||
118 | TIME_WINDOW1, /* long term */ | |
119 | TIME_WINDOW2, /* short term */ | |
120 | THERMAL_SPEC_POWER, | |
121 | MAX_POWER, | |
122 | ||
123 | MIN_POWER, | |
124 | MAX_TIME_WINDOW, | |
125 | THROTTLED_TIME, | |
126 | PRIORITY_LEVEL, | |
127 | ||
128 | /* below are not raw primitive data */ | |
129 | AVERAGE_POWER, | |
130 | NR_RAPL_PRIMITIVES, | |
131 | }; | |
132 | ||
133 | #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) | |
134 | ||
135 | /* Can be expanded to include events, etc.*/ | |
136 | struct rapl_domain_data { | |
137 | u64 primitives[NR_RAPL_PRIMITIVES]; | |
138 | unsigned long timestamp; | |
139 | }; | |
140 | ||
f14a1396 JP |
141 | struct msrl_action { |
142 | u32 msr_no; | |
143 | u64 clear_mask; | |
144 | u64 set_mask; | |
145 | int err; | |
146 | }; | |
2d281d81 JP |
147 | |
148 | #define DOMAIN_STATE_INACTIVE BIT(0) | |
149 | #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) | |
150 | #define DOMAIN_STATE_BIOS_LOCKED BIT(2) | |
151 | ||
152 | #define NR_POWER_LIMITS (2) | |
153 | struct rapl_power_limit { | |
154 | struct powercap_zone_constraint *constraint; | |
155 | int prim_id; /* primitive ID used to enable */ | |
156 | struct rapl_domain *domain; | |
157 | const char *name; | |
158 | }; | |
159 | ||
160 | static const char pl1_name[] = "long_term"; | |
161 | static const char pl2_name[] = "short_term"; | |
162 | ||
309557f5 | 163 | struct rapl_package; |
2d281d81 JP |
164 | struct rapl_domain { |
165 | const char *name; | |
166 | enum rapl_domain_type id; | |
167 | int msrs[RAPL_DOMAIN_MSR_MAX]; | |
168 | struct powercap_zone power_zone; | |
169 | struct rapl_domain_data rdd; | |
170 | struct rapl_power_limit rpl[NR_POWER_LIMITS]; | |
171 | u64 attr_map; /* track capabilities */ | |
172 | unsigned int state; | |
d474a4d3 | 173 | unsigned int domain_energy_unit; |
309557f5 | 174 | struct rapl_package *rp; |
2d281d81 JP |
175 | }; |
176 | #define power_zone_to_rapl_domain(_zone) \ | |
177 | container_of(_zone, struct rapl_domain, power_zone) | |
178 | ||
179 | ||
180 | /* Each physical package contains multiple domains, these are the common | |
181 | * data across RAPL domains within a package. | |
182 | */ | |
183 | struct rapl_package { | |
184 | unsigned int id; /* physical package/socket id */ | |
185 | unsigned int nr_domains; | |
186 | unsigned long domain_map; /* bit map of active domains */ | |
3c2c0845 JP |
187 | unsigned int power_unit; |
188 | unsigned int energy_unit; | |
189 | unsigned int time_unit; | |
2d281d81 JP |
190 | struct rapl_domain *domains; /* array of domains, sized at runtime */ |
191 | struct powercap_zone *power_zone; /* keep track of parent zone */ | |
2d281d81 JP |
192 | unsigned long power_limit_irq; /* keep track of package power limit |
193 | * notify interrupt enable status. | |
194 | */ | |
195 | struct list_head plist; | |
323ee64a | 196 | int lead_cpu; /* one active cpu per package for access */ |
b4005e92 TG |
197 | /* Track active cpus */ |
198 | struct cpumask cpumask; | |
2d281d81 | 199 | }; |
087e9cba JP |
200 | |
201 | struct rapl_defaults { | |
51b63409 | 202 | u8 floor_freq_reg_addr; |
087e9cba JP |
203 | int (*check_unit)(struct rapl_package *rp, int cpu); |
204 | void (*set_floor_freq)(struct rapl_domain *rd, bool mode); | |
205 | u64 (*compute_time_window)(struct rapl_package *rp, u64 val, | |
206 | bool to_raw); | |
d474a4d3 | 207 | unsigned int dram_domain_energy_unit; |
087e9cba JP |
208 | }; |
209 | static struct rapl_defaults *rapl_defaults; | |
210 | ||
3c2c0845 | 211 | /* Sideband MBI registers */ |
51b63409 AT |
212 | #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2) |
213 | #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf) | |
3c2c0845 | 214 | |
2d281d81 JP |
215 | #define PACKAGE_PLN_INT_SAVED BIT(0) |
216 | #define MAX_PRIM_NAME (32) | |
217 | ||
218 | /* per domain data. used to describe individual knobs such that access function | |
219 | * can be consolidated into one instead of many inline functions. | |
220 | */ | |
221 | struct rapl_primitive_info { | |
222 | const char *name; | |
223 | u64 mask; | |
224 | int shift; | |
225 | enum rapl_domain_msr_id id; | |
226 | enum unit_type unit; | |
227 | u32 flag; | |
228 | }; | |
229 | ||
230 | #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ | |
231 | .name = #p, \ | |
232 | .mask = m, \ | |
233 | .shift = s, \ | |
234 | .id = i, \ | |
235 | .unit = u, \ | |
236 | .flag = f \ | |
237 | } | |
238 | ||
239 | static void rapl_init_domains(struct rapl_package *rp); | |
240 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
241 | enum rapl_primitives prim, | |
242 | bool xlate, u64 *data); | |
243 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
244 | enum rapl_primitives prim, | |
245 | unsigned long long value); | |
309557f5 | 246 | static u64 rapl_unit_xlate(struct rapl_domain *rd, |
d474a4d3 | 247 | enum unit_type type, u64 value, |
2d281d81 | 248 | int to_raw); |
309557f5 | 249 | static void package_power_limit_irq_save(struct rapl_package *rp); |
2d281d81 JP |
250 | |
251 | static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */ | |
252 | ||
253 | static const char * const rapl_domain_names[] = { | |
254 | "package", | |
255 | "core", | |
256 | "uncore", | |
257 | "dram", | |
3521ba1c | 258 | "psys", |
2d281d81 JP |
259 | }; |
260 | ||
261 | static struct powercap_control_type *control_type; /* PowerCap Controller */ | |
3521ba1c | 262 | static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */ |
2d281d81 JP |
263 | |
264 | /* caller to ensure CPU hotplug lock is held */ | |
265 | static struct rapl_package *find_package_by_id(int id) | |
266 | { | |
267 | struct rapl_package *rp; | |
268 | ||
269 | list_for_each_entry(rp, &rapl_packages, plist) { | |
270 | if (rp->id == id) | |
271 | return rp; | |
272 | } | |
273 | ||
274 | return NULL; | |
275 | } | |
276 | ||
2d281d81 JP |
277 | static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw) |
278 | { | |
279 | struct rapl_domain *rd; | |
280 | u64 energy_now; | |
281 | ||
282 | /* prevent CPU hotplug, make sure the RAPL domain does not go | |
283 | * away while reading the counter. | |
284 | */ | |
285 | get_online_cpus(); | |
286 | rd = power_zone_to_rapl_domain(power_zone); | |
287 | ||
288 | if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { | |
289 | *energy_raw = energy_now; | |
290 | put_online_cpus(); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | put_online_cpus(); | |
295 | ||
296 | return -EIO; | |
297 | } | |
298 | ||
299 | static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) | |
300 | { | |
d474a4d3 JP |
301 | struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); |
302 | ||
309557f5 | 303 | *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); |
2d281d81 JP |
304 | return 0; |
305 | } | |
306 | ||
307 | static int release_zone(struct powercap_zone *power_zone) | |
308 | { | |
309 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
309557f5 | 310 | struct rapl_package *rp = rd->rp; |
2d281d81 JP |
311 | |
312 | /* package zone is the last zone of a package, we can free | |
313 | * memory here since all children has been unregistered. | |
314 | */ | |
315 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
2d281d81 JP |
316 | kfree(rd); |
317 | rp->domains = NULL; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | ||
322 | } | |
323 | ||
324 | static int find_nr_power_limit(struct rapl_domain *rd) | |
325 | { | |
e1399ba2 | 326 | int i, nr_pl = 0; |
2d281d81 JP |
327 | |
328 | for (i = 0; i < NR_POWER_LIMITS; i++) { | |
e1399ba2 JP |
329 | if (rd->rpl[i].name) |
330 | nr_pl++; | |
2d281d81 JP |
331 | } |
332 | ||
e1399ba2 | 333 | return nr_pl; |
2d281d81 JP |
334 | } |
335 | ||
336 | static int set_domain_enable(struct powercap_zone *power_zone, bool mode) | |
337 | { | |
338 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
2d281d81 JP |
339 | |
340 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) | |
341 | return -EACCES; | |
3c2c0845 | 342 | |
2d281d81 | 343 | get_online_cpus(); |
2d281d81 | 344 | rapl_write_data_raw(rd, PL1_ENABLE, mode); |
51b63409 AT |
345 | if (rapl_defaults->set_floor_freq) |
346 | rapl_defaults->set_floor_freq(rd, mode); | |
2d281d81 JP |
347 | put_online_cpus(); |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | static int get_domain_enable(struct powercap_zone *power_zone, bool *mode) | |
353 | { | |
354 | struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); | |
355 | u64 val; | |
356 | ||
357 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
358 | *mode = false; | |
359 | return 0; | |
360 | } | |
361 | get_online_cpus(); | |
362 | if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) { | |
363 | put_online_cpus(); | |
364 | return -EIO; | |
365 | } | |
366 | *mode = val; | |
367 | put_online_cpus(); | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | /* per RAPL domain ops, in the order of rapl_domain_type */ | |
600c395b | 373 | static const struct powercap_zone_ops zone_ops[] = { |
2d281d81 JP |
374 | /* RAPL_DOMAIN_PACKAGE */ |
375 | { | |
376 | .get_energy_uj = get_energy_counter, | |
377 | .get_max_energy_range_uj = get_max_energy_counter, | |
378 | .release = release_zone, | |
379 | .set_enable = set_domain_enable, | |
380 | .get_enable = get_domain_enable, | |
381 | }, | |
382 | /* RAPL_DOMAIN_PP0 */ | |
383 | { | |
384 | .get_energy_uj = get_energy_counter, | |
385 | .get_max_energy_range_uj = get_max_energy_counter, | |
386 | .release = release_zone, | |
387 | .set_enable = set_domain_enable, | |
388 | .get_enable = get_domain_enable, | |
389 | }, | |
390 | /* RAPL_DOMAIN_PP1 */ | |
391 | { | |
392 | .get_energy_uj = get_energy_counter, | |
393 | .get_max_energy_range_uj = get_max_energy_counter, | |
394 | .release = release_zone, | |
395 | .set_enable = set_domain_enable, | |
396 | .get_enable = get_domain_enable, | |
397 | }, | |
398 | /* RAPL_DOMAIN_DRAM */ | |
399 | { | |
400 | .get_energy_uj = get_energy_counter, | |
401 | .get_max_energy_range_uj = get_max_energy_counter, | |
402 | .release = release_zone, | |
403 | .set_enable = set_domain_enable, | |
404 | .get_enable = get_domain_enable, | |
405 | }, | |
3521ba1c SP |
406 | /* RAPL_DOMAIN_PLATFORM */ |
407 | { | |
408 | .get_energy_uj = get_energy_counter, | |
409 | .get_max_energy_range_uj = get_max_energy_counter, | |
410 | .release = release_zone, | |
411 | .set_enable = set_domain_enable, | |
412 | .get_enable = get_domain_enable, | |
413 | }, | |
2d281d81 JP |
414 | }; |
415 | ||
e1399ba2 JP |
416 | |
417 | /* | |
418 | * Constraint index used by powercap can be different than power limit (PL) | |
419 | * index in that some PLs maybe missing due to non-existant MSRs. So we | |
420 | * need to convert here by finding the valid PLs only (name populated). | |
421 | */ | |
422 | static int contraint_to_pl(struct rapl_domain *rd, int cid) | |
423 | { | |
424 | int i, j; | |
425 | ||
426 | for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) { | |
427 | if ((rd->rpl[i].name) && j++ == cid) { | |
428 | pr_debug("%s: index %d\n", __func__, i); | |
429 | return i; | |
430 | } | |
431 | } | |
cb43f81b | 432 | pr_err("Cannot find matching power limit for constraint %d\n", cid); |
e1399ba2 JP |
433 | |
434 | return -EINVAL; | |
435 | } | |
436 | ||
437 | static int set_power_limit(struct powercap_zone *power_zone, int cid, | |
2d281d81 JP |
438 | u64 power_limit) |
439 | { | |
440 | struct rapl_domain *rd; | |
441 | struct rapl_package *rp; | |
442 | int ret = 0; | |
e1399ba2 | 443 | int id; |
2d281d81 JP |
444 | |
445 | get_online_cpus(); | |
446 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 447 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
448 | if (id < 0) { |
449 | ret = id; | |
450 | goto set_exit; | |
451 | } | |
e1399ba2 | 452 | |
309557f5 | 453 | rp = rd->rp; |
2d281d81 JP |
454 | |
455 | if (rd->state & DOMAIN_STATE_BIOS_LOCKED) { | |
456 | dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n", | |
457 | rd->name); | |
458 | ret = -EACCES; | |
459 | goto set_exit; | |
460 | } | |
461 | ||
462 | switch (rd->rpl[id].prim_id) { | |
463 | case PL1_ENABLE: | |
464 | rapl_write_data_raw(rd, POWER_LIMIT1, power_limit); | |
465 | break; | |
466 | case PL2_ENABLE: | |
467 | rapl_write_data_raw(rd, POWER_LIMIT2, power_limit); | |
468 | break; | |
469 | default: | |
470 | ret = -EINVAL; | |
471 | } | |
472 | if (!ret) | |
309557f5 | 473 | package_power_limit_irq_save(rp); |
2d281d81 JP |
474 | set_exit: |
475 | put_online_cpus(); | |
476 | return ret; | |
477 | } | |
478 | ||
e1399ba2 | 479 | static int get_current_power_limit(struct powercap_zone *power_zone, int cid, |
2d281d81 JP |
480 | u64 *data) |
481 | { | |
482 | struct rapl_domain *rd; | |
483 | u64 val; | |
484 | int prim; | |
485 | int ret = 0; | |
e1399ba2 | 486 | int id; |
2d281d81 JP |
487 | |
488 | get_online_cpus(); | |
489 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 490 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
491 | if (id < 0) { |
492 | ret = id; | |
493 | goto get_exit; | |
494 | } | |
495 | ||
2d281d81 JP |
496 | switch (rd->rpl[id].prim_id) { |
497 | case PL1_ENABLE: | |
498 | prim = POWER_LIMIT1; | |
499 | break; | |
500 | case PL2_ENABLE: | |
501 | prim = POWER_LIMIT2; | |
502 | break; | |
503 | default: | |
504 | put_online_cpus(); | |
505 | return -EINVAL; | |
506 | } | |
507 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
508 | ret = -EIO; | |
509 | else | |
510 | *data = val; | |
511 | ||
cb43f81b | 512 | get_exit: |
2d281d81 JP |
513 | put_online_cpus(); |
514 | ||
515 | return ret; | |
516 | } | |
517 | ||
e1399ba2 | 518 | static int set_time_window(struct powercap_zone *power_zone, int cid, |
2d281d81 JP |
519 | u64 window) |
520 | { | |
521 | struct rapl_domain *rd; | |
522 | int ret = 0; | |
e1399ba2 | 523 | int id; |
2d281d81 JP |
524 | |
525 | get_online_cpus(); | |
526 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 527 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
528 | if (id < 0) { |
529 | ret = id; | |
530 | goto set_time_exit; | |
531 | } | |
e1399ba2 | 532 | |
2d281d81 JP |
533 | switch (rd->rpl[id].prim_id) { |
534 | case PL1_ENABLE: | |
535 | rapl_write_data_raw(rd, TIME_WINDOW1, window); | |
536 | break; | |
537 | case PL2_ENABLE: | |
538 | rapl_write_data_raw(rd, TIME_WINDOW2, window); | |
539 | break; | |
540 | default: | |
541 | ret = -EINVAL; | |
542 | } | |
cb43f81b JP |
543 | |
544 | set_time_exit: | |
2d281d81 JP |
545 | put_online_cpus(); |
546 | return ret; | |
547 | } | |
548 | ||
e1399ba2 | 549 | static int get_time_window(struct powercap_zone *power_zone, int cid, u64 *data) |
2d281d81 JP |
550 | { |
551 | struct rapl_domain *rd; | |
552 | u64 val; | |
553 | int ret = 0; | |
e1399ba2 | 554 | int id; |
2d281d81 JP |
555 | |
556 | get_online_cpus(); | |
557 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 | 558 | id = contraint_to_pl(rd, cid); |
cb43f81b JP |
559 | if (id < 0) { |
560 | ret = id; | |
561 | goto get_time_exit; | |
562 | } | |
e1399ba2 | 563 | |
2d281d81 JP |
564 | switch (rd->rpl[id].prim_id) { |
565 | case PL1_ENABLE: | |
566 | ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val); | |
567 | break; | |
568 | case PL2_ENABLE: | |
569 | ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val); | |
570 | break; | |
571 | default: | |
572 | put_online_cpus(); | |
573 | return -EINVAL; | |
574 | } | |
575 | if (!ret) | |
576 | *data = val; | |
cb43f81b JP |
577 | |
578 | get_time_exit: | |
2d281d81 JP |
579 | put_online_cpus(); |
580 | ||
581 | return ret; | |
582 | } | |
583 | ||
e1399ba2 | 584 | static const char *get_constraint_name(struct powercap_zone *power_zone, int cid) |
2d281d81 | 585 | { |
2d281d81 | 586 | struct rapl_domain *rd; |
e1399ba2 | 587 | int id; |
2d281d81 JP |
588 | |
589 | rd = power_zone_to_rapl_domain(power_zone); | |
e1399ba2 JP |
590 | id = contraint_to_pl(rd, cid); |
591 | if (id >= 0) | |
592 | return rd->rpl[id].name; | |
2d281d81 | 593 | |
e1399ba2 | 594 | return NULL; |
2d281d81 JP |
595 | } |
596 | ||
597 | ||
598 | static int get_max_power(struct powercap_zone *power_zone, int id, | |
599 | u64 *data) | |
600 | { | |
601 | struct rapl_domain *rd; | |
602 | u64 val; | |
603 | int prim; | |
604 | int ret = 0; | |
605 | ||
606 | get_online_cpus(); | |
607 | rd = power_zone_to_rapl_domain(power_zone); | |
608 | switch (rd->rpl[id].prim_id) { | |
609 | case PL1_ENABLE: | |
610 | prim = THERMAL_SPEC_POWER; | |
611 | break; | |
612 | case PL2_ENABLE: | |
613 | prim = MAX_POWER; | |
614 | break; | |
615 | default: | |
616 | put_online_cpus(); | |
617 | return -EINVAL; | |
618 | } | |
619 | if (rapl_read_data_raw(rd, prim, true, &val)) | |
620 | ret = -EIO; | |
621 | else | |
622 | *data = val; | |
623 | ||
624 | put_online_cpus(); | |
625 | ||
626 | return ret; | |
627 | } | |
628 | ||
600c395b | 629 | static const struct powercap_zone_constraint_ops constraint_ops = { |
2d281d81 JP |
630 | .set_power_limit_uw = set_power_limit, |
631 | .get_power_limit_uw = get_current_power_limit, | |
632 | .set_time_window_us = set_time_window, | |
633 | .get_time_window_us = get_time_window, | |
634 | .get_max_power_uw = get_max_power, | |
635 | .get_name = get_constraint_name, | |
636 | }; | |
637 | ||
638 | /* called after domain detection and package level data are set */ | |
639 | static void rapl_init_domains(struct rapl_package *rp) | |
640 | { | |
641 | int i; | |
642 | struct rapl_domain *rd = rp->domains; | |
643 | ||
644 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
645 | unsigned int mask = rp->domain_map & (1 << i); | |
646 | switch (mask) { | |
647 | case BIT(RAPL_DOMAIN_PACKAGE): | |
648 | rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE]; | |
649 | rd->id = RAPL_DOMAIN_PACKAGE; | |
650 | rd->msrs[0] = MSR_PKG_POWER_LIMIT; | |
651 | rd->msrs[1] = MSR_PKG_ENERGY_STATUS; | |
652 | rd->msrs[2] = MSR_PKG_PERF_STATUS; | |
653 | rd->msrs[3] = 0; | |
654 | rd->msrs[4] = MSR_PKG_POWER_INFO; | |
655 | rd->rpl[0].prim_id = PL1_ENABLE; | |
656 | rd->rpl[0].name = pl1_name; | |
657 | rd->rpl[1].prim_id = PL2_ENABLE; | |
658 | rd->rpl[1].name = pl2_name; | |
659 | break; | |
660 | case BIT(RAPL_DOMAIN_PP0): | |
661 | rd->name = rapl_domain_names[RAPL_DOMAIN_PP0]; | |
662 | rd->id = RAPL_DOMAIN_PP0; | |
663 | rd->msrs[0] = MSR_PP0_POWER_LIMIT; | |
664 | rd->msrs[1] = MSR_PP0_ENERGY_STATUS; | |
665 | rd->msrs[2] = 0; | |
666 | rd->msrs[3] = MSR_PP0_POLICY; | |
667 | rd->msrs[4] = 0; | |
668 | rd->rpl[0].prim_id = PL1_ENABLE; | |
669 | rd->rpl[0].name = pl1_name; | |
670 | break; | |
671 | case BIT(RAPL_DOMAIN_PP1): | |
672 | rd->name = rapl_domain_names[RAPL_DOMAIN_PP1]; | |
673 | rd->id = RAPL_DOMAIN_PP1; | |
674 | rd->msrs[0] = MSR_PP1_POWER_LIMIT; | |
675 | rd->msrs[1] = MSR_PP1_ENERGY_STATUS; | |
676 | rd->msrs[2] = 0; | |
677 | rd->msrs[3] = MSR_PP1_POLICY; | |
678 | rd->msrs[4] = 0; | |
679 | rd->rpl[0].prim_id = PL1_ENABLE; | |
680 | rd->rpl[0].name = pl1_name; | |
681 | break; | |
682 | case BIT(RAPL_DOMAIN_DRAM): | |
683 | rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM]; | |
684 | rd->id = RAPL_DOMAIN_DRAM; | |
685 | rd->msrs[0] = MSR_DRAM_POWER_LIMIT; | |
686 | rd->msrs[1] = MSR_DRAM_ENERGY_STATUS; | |
687 | rd->msrs[2] = MSR_DRAM_PERF_STATUS; | |
688 | rd->msrs[3] = 0; | |
689 | rd->msrs[4] = MSR_DRAM_POWER_INFO; | |
690 | rd->rpl[0].prim_id = PL1_ENABLE; | |
691 | rd->rpl[0].name = pl1_name; | |
d474a4d3 JP |
692 | rd->domain_energy_unit = |
693 | rapl_defaults->dram_domain_energy_unit; | |
694 | if (rd->domain_energy_unit) | |
695 | pr_info("DRAM domain energy unit %dpj\n", | |
696 | rd->domain_energy_unit); | |
2d281d81 JP |
697 | break; |
698 | } | |
699 | if (mask) { | |
309557f5 | 700 | rd->rp = rp; |
2d281d81 JP |
701 | rd++; |
702 | } | |
703 | } | |
704 | } | |
705 | ||
309557f5 JP |
706 | static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type, |
707 | u64 value, int to_raw) | |
2d281d81 | 708 | { |
3c2c0845 | 709 | u64 units = 1; |
309557f5 | 710 | struct rapl_package *rp = rd->rp; |
d474a4d3 | 711 | u64 scale = 1; |
2d281d81 | 712 | |
2d281d81 JP |
713 | switch (type) { |
714 | case POWER_UNIT: | |
3c2c0845 | 715 | units = rp->power_unit; |
2d281d81 JP |
716 | break; |
717 | case ENERGY_UNIT: | |
d474a4d3 JP |
718 | scale = ENERGY_UNIT_SCALE; |
719 | /* per domain unit takes precedence */ | |
cb43f81b | 720 | if (rd->domain_energy_unit) |
d474a4d3 JP |
721 | units = rd->domain_energy_unit; |
722 | else | |
723 | units = rp->energy_unit; | |
2d281d81 JP |
724 | break; |
725 | case TIME_UNIT: | |
3c2c0845 | 726 | return rapl_defaults->compute_time_window(rp, value, to_raw); |
2d281d81 JP |
727 | case ARBITRARY_UNIT: |
728 | default: | |
729 | return value; | |
730 | }; | |
731 | ||
732 | if (to_raw) | |
d474a4d3 | 733 | return div64_u64(value, units) * scale; |
3c2c0845 JP |
734 | |
735 | value *= units; | |
736 | ||
d474a4d3 | 737 | return div64_u64(value, scale); |
2d281d81 JP |
738 | } |
739 | ||
740 | /* in the order of enum rapl_primitives */ | |
741 | static struct rapl_primitive_info rpi[] = { | |
742 | /* name, mask, shift, msr index, unit divisor */ | |
743 | PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, | |
744 | RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0), | |
745 | PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, | |
746 | RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0), | |
747 | PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, | |
748 | RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0), | |
749 | PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31, | |
750 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
751 | PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, | |
752 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
753 | PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, | |
754 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
755 | PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, | |
756 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
757 | PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, | |
758 | RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0), | |
759 | PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, | |
760 | RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0), | |
761 | PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, | |
762 | RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0), | |
763 | PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK, | |
764 | 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
765 | PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, | |
766 | RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
767 | PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, | |
768 | RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0), | |
769 | PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48, | |
770 | RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0), | |
771 | PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, | |
772 | RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0), | |
773 | PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, | |
774 | RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0), | |
775 | /* non-hardware */ | |
776 | PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT, | |
777 | RAPL_PRIMITIVE_DERIVED), | |
778 | {NULL, 0, 0, 0}, | |
779 | }; | |
780 | ||
781 | /* Read primitive data based on its related struct rapl_primitive_info. | |
782 | * if xlate flag is set, return translated data based on data units, i.e. | |
783 | * time, energy, and power. | |
784 | * RAPL MSRs are non-architectual and are laid out not consistently across | |
785 | * domains. Here we use primitive info to allow writing consolidated access | |
786 | * functions. | |
787 | * For a given primitive, it is processed by MSR mask and shift. Unit conversion | |
788 | * is pre-assigned based on RAPL unit MSRs read at init time. | |
789 | * 63-------------------------- 31--------------------------- 0 | |
790 | * | xxxxx (mask) | | |
791 | * | |<- shift ----------------| | |
792 | * 63-------------------------- 31--------------------------- 0 | |
793 | */ | |
794 | static int rapl_read_data_raw(struct rapl_domain *rd, | |
795 | enum rapl_primitives prim, | |
796 | bool xlate, u64 *data) | |
797 | { | |
798 | u64 value, final; | |
799 | u32 msr; | |
800 | struct rapl_primitive_info *rp = &rpi[prim]; | |
801 | int cpu; | |
802 | ||
803 | if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY) | |
804 | return -EINVAL; | |
805 | ||
806 | msr = rd->msrs[rp->id]; | |
807 | if (!msr) | |
808 | return -EINVAL; | |
323ee64a JP |
809 | |
810 | cpu = rd->rp->lead_cpu; | |
2d281d81 JP |
811 | |
812 | /* special-case package domain, which uses a different bit*/ | |
813 | if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) { | |
814 | rp->mask = POWER_PACKAGE_LOCK; | |
815 | rp->shift = 63; | |
816 | } | |
817 | /* non-hardware data are collected by the polling thread */ | |
818 | if (rp->flag & RAPL_PRIMITIVE_DERIVED) { | |
819 | *data = rd->rdd.primitives[prim]; | |
820 | return 0; | |
821 | } | |
822 | ||
823 | if (rdmsrl_safe_on_cpu(cpu, msr, &value)) { | |
824 | pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu); | |
825 | return -EIO; | |
826 | } | |
827 | ||
828 | final = value & rp->mask; | |
829 | final = final >> rp->shift; | |
830 | if (xlate) | |
309557f5 | 831 | *data = rapl_unit_xlate(rd, rp->unit, final, 0); |
2d281d81 JP |
832 | else |
833 | *data = final; | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
f14a1396 JP |
838 | |
839 | static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask) | |
840 | { | |
841 | int err; | |
842 | u64 val; | |
843 | ||
844 | err = rdmsrl_safe(msr_no, &val); | |
845 | if (err) | |
846 | goto out; | |
847 | ||
848 | val &= ~clear_mask; | |
849 | val |= set_mask; | |
850 | ||
851 | err = wrmsrl_safe(msr_no, val); | |
852 | ||
853 | out: | |
854 | return err; | |
855 | } | |
856 | ||
857 | static void msrl_update_func(void *info) | |
858 | { | |
859 | struct msrl_action *ma = info; | |
860 | ||
861 | ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask); | |
862 | } | |
863 | ||
2d281d81 JP |
864 | /* Similar use of primitive info in the read counterpart */ |
865 | static int rapl_write_data_raw(struct rapl_domain *rd, | |
866 | enum rapl_primitives prim, | |
867 | unsigned long long value) | |
868 | { | |
2d281d81 JP |
869 | struct rapl_primitive_info *rp = &rpi[prim]; |
870 | int cpu; | |
f14a1396 JP |
871 | u64 bits; |
872 | struct msrl_action ma; | |
873 | int ret; | |
2d281d81 | 874 | |
323ee64a | 875 | cpu = rd->rp->lead_cpu; |
309557f5 | 876 | bits = rapl_unit_xlate(rd, rp->unit, value, 1); |
edbdabc6 AL |
877 | bits <<= rp->shift; |
878 | bits &= rp->mask; | |
879 | ||
f14a1396 JP |
880 | memset(&ma, 0, sizeof(ma)); |
881 | ||
882 | ma.msr_no = rd->msrs[rp->id]; | |
883 | ma.clear_mask = rp->mask; | |
884 | ma.set_mask = bits; | |
885 | ||
886 | ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1); | |
887 | if (ret) | |
888 | WARN_ON_ONCE(ret); | |
889 | else | |
890 | ret = ma.err; | |
891 | ||
892 | return ret; | |
2d281d81 JP |
893 | } |
894 | ||
3c2c0845 JP |
895 | /* |
896 | * Raw RAPL data stored in MSRs are in certain scales. We need to | |
897 | * convert them into standard units based on the units reported in | |
898 | * the RAPL unit MSRs. This is specific to CPUs as the method to | |
899 | * calculate units differ on different CPUs. | |
900 | * We convert the units to below format based on CPUs. | |
901 | * i.e. | |
d474a4d3 | 902 | * energy unit: picoJoules : Represented in picoJoules by default |
3c2c0845 JP |
903 | * power unit : microWatts : Represented in milliWatts by default |
904 | * time unit : microseconds: Represented in seconds by default | |
905 | */ | |
906 | static int rapl_check_unit_core(struct rapl_package *rp, int cpu) | |
2d281d81 JP |
907 | { |
908 | u64 msr_val; | |
909 | u32 value; | |
910 | ||
911 | if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) { | |
912 | pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n", | |
913 | MSR_RAPL_POWER_UNIT, cpu); | |
914 | return -ENODEV; | |
915 | } | |
916 | ||
2d281d81 | 917 | value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; |
d474a4d3 | 918 | rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); |
2d281d81 JP |
919 | |
920 | value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; | |
3c2c0845 | 921 | rp->power_unit = 1000000 / (1 << value); |
2d281d81 JP |
922 | |
923 | value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; | |
3c2c0845 | 924 | rp->time_unit = 1000000 / (1 << value); |
2d281d81 | 925 | |
d474a4d3 | 926 | pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n", |
3c2c0845 | 927 | rp->id, rp->energy_unit, rp->time_unit, rp->power_unit); |
2d281d81 JP |
928 | |
929 | return 0; | |
930 | } | |
931 | ||
3c2c0845 JP |
932 | static int rapl_check_unit_atom(struct rapl_package *rp, int cpu) |
933 | { | |
934 | u64 msr_val; | |
935 | u32 value; | |
936 | ||
937 | if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) { | |
938 | pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n", | |
939 | MSR_RAPL_POWER_UNIT, cpu); | |
940 | return -ENODEV; | |
941 | } | |
942 | value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; | |
d474a4d3 | 943 | rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value; |
3c2c0845 JP |
944 | |
945 | value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; | |
946 | rp->power_unit = (1 << value) * 1000; | |
947 | ||
948 | value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; | |
949 | rp->time_unit = 1000000 / (1 << value); | |
950 | ||
d474a4d3 | 951 | pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n", |
3c2c0845 JP |
952 | rp->id, rp->energy_unit, rp->time_unit, rp->power_unit); |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
f14a1396 JP |
957 | static void power_limit_irq_save_cpu(void *info) |
958 | { | |
959 | u32 l, h = 0; | |
960 | struct rapl_package *rp = (struct rapl_package *)info; | |
961 | ||
962 | /* save the state of PLN irq mask bit before disabling it */ | |
963 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
964 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) { | |
965 | rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE; | |
966 | rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED; | |
967 | } | |
968 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
969 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
970 | } | |
971 | ||
3c2c0845 | 972 | |
2d281d81 JP |
973 | /* REVISIT: |
974 | * When package power limit is set artificially low by RAPL, LVT | |
975 | * thermal interrupt for package power limit should be ignored | |
976 | * since we are not really exceeding the real limit. The intention | |
977 | * is to avoid excessive interrupts while we are trying to save power. | |
978 | * A useful feature might be routing the package_power_limit interrupt | |
979 | * to userspace via eventfd. once we have a usecase, this is simple | |
980 | * to do by adding an atomic notifier. | |
981 | */ | |
982 | ||
309557f5 | 983 | static void package_power_limit_irq_save(struct rapl_package *rp) |
2d281d81 | 984 | { |
f14a1396 JP |
985 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) |
986 | return; | |
987 | ||
323ee64a | 988 | smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1); |
f14a1396 JP |
989 | } |
990 | ||
58705069 TG |
991 | /* |
992 | * Restore per package power limit interrupt enable state. Called from cpu | |
993 | * hotplug code on package removal. | |
994 | */ | |
995 | static void package_power_limit_irq_restore(struct rapl_package *rp) | |
f14a1396 | 996 | { |
58705069 TG |
997 | u32 l, h; |
998 | ||
999 | if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) | |
1000 | return; | |
1001 | ||
1002 | /* irq enable state not saved, nothing to restore */ | |
1003 | if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) | |
1004 | return; | |
f14a1396 JP |
1005 | |
1006 | rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); | |
1007 | ||
1008 | if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE) | |
1009 | l |= PACKAGE_THERM_INT_PLN_ENABLE; | |
1010 | else | |
1011 | l &= ~PACKAGE_THERM_INT_PLN_ENABLE; | |
1012 | ||
1013 | wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
2d281d81 JP |
1014 | } |
1015 | ||
3c2c0845 JP |
1016 | static void set_floor_freq_default(struct rapl_domain *rd, bool mode) |
1017 | { | |
1018 | int nr_powerlimit = find_nr_power_limit(rd); | |
1019 | ||
1020 | /* always enable clamp such that p-state can go below OS requested | |
1021 | * range. power capping priority over guranteed frequency. | |
1022 | */ | |
1023 | rapl_write_data_raw(rd, PL1_CLAMP, mode); | |
1024 | ||
1025 | /* some domains have pl2 */ | |
1026 | if (nr_powerlimit > 1) { | |
1027 | rapl_write_data_raw(rd, PL2_ENABLE, mode); | |
1028 | rapl_write_data_raw(rd, PL2_CLAMP, mode); | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) | |
1033 | { | |
1034 | static u32 power_ctrl_orig_val; | |
1035 | u32 mdata; | |
1036 | ||
51b63409 AT |
1037 | if (!rapl_defaults->floor_freq_reg_addr) { |
1038 | pr_err("Invalid floor frequency config register\n"); | |
1039 | return; | |
1040 | } | |
1041 | ||
3c2c0845 | 1042 | if (!power_ctrl_orig_val) |
4077a387 AS |
1043 | iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, |
1044 | rapl_defaults->floor_freq_reg_addr, | |
1045 | &power_ctrl_orig_val); | |
3c2c0845 JP |
1046 | mdata = power_ctrl_orig_val; |
1047 | if (enable) { | |
1048 | mdata &= ~(0x7f << 8); | |
1049 | mdata |= 1 << 8; | |
1050 | } | |
4077a387 AS |
1051 | iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, |
1052 | rapl_defaults->floor_freq_reg_addr, mdata); | |
3c2c0845 JP |
1053 | } |
1054 | ||
1055 | static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value, | |
1056 | bool to_raw) | |
1057 | { | |
1058 | u64 f, y; /* fraction and exp. used for time unit */ | |
1059 | ||
1060 | /* | |
1061 | * Special processing based on 2^Y*(1+F/4), refer | |
1062 | * to Intel Software Developer's manual Vol.3B: CH 14.9.3. | |
1063 | */ | |
1064 | if (!to_raw) { | |
1065 | f = (value & 0x60) >> 5; | |
1066 | y = value & 0x1f; | |
1067 | value = (1 << y) * (4 + f) * rp->time_unit / 4; | |
1068 | } else { | |
1069 | do_div(value, rp->time_unit); | |
1070 | y = ilog2(value); | |
1071 | f = div64_u64(4 * (value - (1 << y)), 1 << y); | |
1072 | value = (y & 0x1f) | ((f & 0x3) << 5); | |
1073 | } | |
1074 | return value; | |
1075 | } | |
1076 | ||
1077 | static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value, | |
1078 | bool to_raw) | |
1079 | { | |
1080 | /* | |
1081 | * Atom time unit encoding is straight forward val * time_unit, | |
1082 | * where time_unit is default to 1 sec. Never 0. | |
1083 | */ | |
1084 | if (!to_raw) | |
1085 | return (value) ? value *= rp->time_unit : rp->time_unit; | |
1086 | else | |
1087 | value = div64_u64(value, rp->time_unit); | |
1088 | ||
1089 | return value; | |
1090 | } | |
1091 | ||
087e9cba | 1092 | static const struct rapl_defaults rapl_defaults_core = { |
51b63409 | 1093 | .floor_freq_reg_addr = 0, |
3c2c0845 JP |
1094 | .check_unit = rapl_check_unit_core, |
1095 | .set_floor_freq = set_floor_freq_default, | |
1096 | .compute_time_window = rapl_compute_time_window_core, | |
087e9cba JP |
1097 | }; |
1098 | ||
d474a4d3 JP |
1099 | static const struct rapl_defaults rapl_defaults_hsw_server = { |
1100 | .check_unit = rapl_check_unit_core, | |
1101 | .set_floor_freq = set_floor_freq_default, | |
1102 | .compute_time_window = rapl_compute_time_window_core, | |
1103 | .dram_domain_energy_unit = 15300, | |
1104 | }; | |
1105 | ||
51b63409 AT |
1106 | static const struct rapl_defaults rapl_defaults_byt = { |
1107 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, | |
1108 | .check_unit = rapl_check_unit_atom, | |
1109 | .set_floor_freq = set_floor_freq_atom, | |
1110 | .compute_time_window = rapl_compute_time_window_atom, | |
1111 | }; | |
1112 | ||
1113 | static const struct rapl_defaults rapl_defaults_tng = { | |
1114 | .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, | |
3c2c0845 JP |
1115 | .check_unit = rapl_check_unit_atom, |
1116 | .set_floor_freq = set_floor_freq_atom, | |
1117 | .compute_time_window = rapl_compute_time_window_atom, | |
087e9cba JP |
1118 | }; |
1119 | ||
51b63409 AT |
1120 | static const struct rapl_defaults rapl_defaults_ann = { |
1121 | .floor_freq_reg_addr = 0, | |
1122 | .check_unit = rapl_check_unit_atom, | |
1123 | .set_floor_freq = NULL, | |
1124 | .compute_time_window = rapl_compute_time_window_atom, | |
1125 | }; | |
1126 | ||
1127 | static const struct rapl_defaults rapl_defaults_cht = { | |
1128 | .floor_freq_reg_addr = 0, | |
1129 | .check_unit = rapl_check_unit_atom, | |
1130 | .set_floor_freq = NULL, | |
1131 | .compute_time_window = rapl_compute_time_window_atom, | |
1132 | }; | |
1133 | ||
087e9cba JP |
1134 | #define RAPL_CPU(_model, _ops) { \ |
1135 | .vendor = X86_VENDOR_INTEL, \ | |
1136 | .family = 6, \ | |
1137 | .model = _model, \ | |
1138 | .driver_data = (kernel_ulong_t)&_ops, \ | |
1139 | } | |
1140 | ||
ea85dbca | 1141 | static const struct x86_cpu_id rapl_ids[] __initconst = { |
62d16733 DH |
1142 | RAPL_CPU(INTEL_FAM6_SANDYBRIDGE, rapl_defaults_core), |
1143 | RAPL_CPU(INTEL_FAM6_SANDYBRIDGE_X, rapl_defaults_core), | |
0bb04b5f | 1144 | |
62d16733 | 1145 | RAPL_CPU(INTEL_FAM6_IVYBRIDGE, rapl_defaults_core), |
7d188478 | 1146 | RAPL_CPU(INTEL_FAM6_IVYBRIDGE_X, rapl_defaults_core), |
0bb04b5f | 1147 | |
62d16733 | 1148 | RAPL_CPU(INTEL_FAM6_HASWELL_CORE, rapl_defaults_core), |
62d16733 DH |
1149 | RAPL_CPU(INTEL_FAM6_HASWELL_ULT, rapl_defaults_core), |
1150 | RAPL_CPU(INTEL_FAM6_HASWELL_GT3E, rapl_defaults_core), | |
0bb04b5f DH |
1151 | RAPL_CPU(INTEL_FAM6_HASWELL_X, rapl_defaults_hsw_server), |
1152 | ||
1153 | RAPL_CPU(INTEL_FAM6_BROADWELL_CORE, rapl_defaults_core), | |
62d16733 | 1154 | RAPL_CPU(INTEL_FAM6_BROADWELL_GT3E, rapl_defaults_core), |
0bb04b5f DH |
1155 | RAPL_CPU(INTEL_FAM6_BROADWELL_XEON_D, rapl_defaults_core), |
1156 | RAPL_CPU(INTEL_FAM6_BROADWELL_X, rapl_defaults_hsw_server), | |
1157 | ||
1158 | RAPL_CPU(INTEL_FAM6_SKYLAKE_DESKTOP, rapl_defaults_core), | |
62d16733 | 1159 | RAPL_CPU(INTEL_FAM6_SKYLAKE_MOBILE, rapl_defaults_core), |
d40671e3 | 1160 | RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server), |
0bb04b5f DH |
1161 | RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core), |
1162 | RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core), | |
1163 | ||
1164 | RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt), | |
62d16733 | 1165 | RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht), |
f5fbf848 AS |
1166 | RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD, rapl_defaults_tng), |
1167 | RAPL_CPU(INTEL_FAM6_ATOM_MOOREFIELD, rapl_defaults_ann), | |
62d16733 | 1168 | RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT, rapl_defaults_core), |
4486740d | 1169 | RAPL_CPU(INTEL_FAM6_ATOM_GEMINI_LAKE, rapl_defaults_core), |
ab0d15df | 1170 | RAPL_CPU(INTEL_FAM6_ATOM_DENVERTON, rapl_defaults_core), |
0bb04b5f | 1171 | |
62d16733 | 1172 | RAPL_CPU(INTEL_FAM6_XEON_PHI_KNL, rapl_defaults_hsw_server), |
bd908916 | 1173 | RAPL_CPU(INTEL_FAM6_XEON_PHI_KNM, rapl_defaults_hsw_server), |
2d281d81 JP |
1174 | {} |
1175 | }; | |
1176 | MODULE_DEVICE_TABLE(x86cpu, rapl_ids); | |
1177 | ||
bed5ab63 TG |
1178 | /* Read once for all raw primitive data for domains */ |
1179 | static void rapl_update_domain_data(struct rapl_package *rp) | |
2d281d81 JP |
1180 | { |
1181 | int dmn, prim; | |
1182 | u64 val; | |
2d281d81 | 1183 | |
bed5ab63 TG |
1184 | for (dmn = 0; dmn < rp->nr_domains; dmn++) { |
1185 | pr_debug("update package %d domain %s data\n", rp->id, | |
1186 | rp->domains[dmn].name); | |
1187 | /* exclude non-raw primitives */ | |
1188 | for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) { | |
1189 | if (!rapl_read_data_raw(&rp->domains[dmn], prim, | |
1190 | rpi[prim].unit, &val)) | |
1191 | rp->domains[dmn].rdd.primitives[prim] = val; | |
2d281d81 JP |
1192 | } |
1193 | } | |
1194 | ||
1195 | } | |
1196 | ||
58705069 | 1197 | static void rapl_unregister_powercap(void) |
2d281d81 | 1198 | { |
3521ba1c SP |
1199 | if (platform_rapl_domain) { |
1200 | powercap_unregister_zone(control_type, | |
1201 | &platform_rapl_domain->power_zone); | |
1202 | kfree(platform_rapl_domain); | |
1203 | } | |
2d281d81 | 1204 | powercap_unregister_control_type(control_type); |
2d281d81 JP |
1205 | } |
1206 | ||
1207 | static int rapl_package_register_powercap(struct rapl_package *rp) | |
1208 | { | |
1209 | struct rapl_domain *rd; | |
2d281d81 JP |
1210 | char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/ |
1211 | struct powercap_zone *power_zone = NULL; | |
bed5ab63 TG |
1212 | int nr_pl, ret;; |
1213 | ||
1214 | /* Update the domain data of the new package */ | |
1215 | rapl_update_domain_data(rp); | |
2d281d81 JP |
1216 | |
1217 | /* first we register package domain as the parent zone*/ | |
1218 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1219 | if (rd->id == RAPL_DOMAIN_PACKAGE) { | |
1220 | nr_pl = find_nr_power_limit(rd); | |
1221 | pr_debug("register socket %d package domain %s\n", | |
1222 | rp->id, rd->name); | |
1223 | memset(dev_name, 0, sizeof(dev_name)); | |
1224 | snprintf(dev_name, sizeof(dev_name), "%s-%d", | |
1225 | rd->name, rp->id); | |
1226 | power_zone = powercap_register_zone(&rd->power_zone, | |
1227 | control_type, | |
1228 | dev_name, NULL, | |
1229 | &zone_ops[rd->id], | |
1230 | nr_pl, | |
1231 | &constraint_ops); | |
1232 | if (IS_ERR(power_zone)) { | |
1233 | pr_debug("failed to register package, %d\n", | |
1234 | rp->id); | |
bed5ab63 | 1235 | return PTR_ERR(power_zone); |
2d281d81 JP |
1236 | } |
1237 | /* track parent zone in per package/socket data */ | |
1238 | rp->power_zone = power_zone; | |
1239 | /* done, only one package domain per socket */ | |
1240 | break; | |
1241 | } | |
1242 | } | |
1243 | if (!power_zone) { | |
1244 | pr_err("no package domain found, unknown topology!\n"); | |
bed5ab63 | 1245 | return -ENODEV; |
2d281d81 JP |
1246 | } |
1247 | /* now register domains as children of the socket/package*/ | |
1248 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { | |
1249 | if (rd->id == RAPL_DOMAIN_PACKAGE) | |
1250 | continue; | |
1251 | /* number of power limits per domain varies */ | |
1252 | nr_pl = find_nr_power_limit(rd); | |
1253 | power_zone = powercap_register_zone(&rd->power_zone, | |
1254 | control_type, rd->name, | |
1255 | rp->power_zone, | |
1256 | &zone_ops[rd->id], nr_pl, | |
1257 | &constraint_ops); | |
1258 | ||
1259 | if (IS_ERR(power_zone)) { | |
1260 | pr_debug("failed to register power_zone, %d:%s:%s\n", | |
1261 | rp->id, rd->name, dev_name); | |
1262 | ret = PTR_ERR(power_zone); | |
1263 | goto err_cleanup; | |
1264 | } | |
1265 | } | |
bed5ab63 | 1266 | return 0; |
2d281d81 | 1267 | |
2d281d81 | 1268 | err_cleanup: |
58705069 TG |
1269 | /* |
1270 | * Clean up previously initialized domains within the package if we | |
2d281d81 JP |
1271 | * failed after the first domain setup. |
1272 | */ | |
1273 | while (--rd >= rp->domains) { | |
1274 | pr_debug("unregister package %d domain %s\n", rp->id, rd->name); | |
1275 | powercap_unregister_zone(control_type, &rd->power_zone); | |
1276 | } | |
1277 | ||
1278 | return ret; | |
1279 | } | |
1280 | ||
58705069 | 1281 | static int __init rapl_register_psys(void) |
3521ba1c SP |
1282 | { |
1283 | struct rapl_domain *rd; | |
1284 | struct powercap_zone *power_zone; | |
1285 | u64 val; | |
1286 | ||
1287 | if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val) | |
1288 | return -ENODEV; | |
1289 | ||
1290 | if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val) | |
1291 | return -ENODEV; | |
1292 | ||
1293 | rd = kzalloc(sizeof(*rd), GFP_KERNEL); | |
1294 | if (!rd) | |
1295 | return -ENOMEM; | |
1296 | ||
1297 | rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM]; | |
1298 | rd->id = RAPL_DOMAIN_PLATFORM; | |
1299 | rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT; | |
1300 | rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS; | |
1301 | rd->rpl[0].prim_id = PL1_ENABLE; | |
1302 | rd->rpl[0].name = pl1_name; | |
1303 | rd->rpl[1].prim_id = PL2_ENABLE; | |
1304 | rd->rpl[1].name = pl2_name; | |
1305 | rd->rp = find_package_by_id(0); | |
1306 | ||
1307 | power_zone = powercap_register_zone(&rd->power_zone, control_type, | |
1308 | "psys", NULL, | |
1309 | &zone_ops[RAPL_DOMAIN_PLATFORM], | |
1310 | 2, &constraint_ops); | |
1311 | ||
1312 | if (IS_ERR(power_zone)) { | |
1313 | kfree(rd); | |
1314 | return PTR_ERR(power_zone); | |
1315 | } | |
1316 | ||
1317 | platform_rapl_domain = rd; | |
1318 | ||
1319 | return 0; | |
1320 | } | |
1321 | ||
58705069 | 1322 | static int __init rapl_register_powercap(void) |
2d281d81 | 1323 | { |
2d281d81 JP |
1324 | control_type = powercap_register_control_type(NULL, "intel-rapl", NULL); |
1325 | if (IS_ERR(control_type)) { | |
1326 | pr_debug("failed to register powercap control_type.\n"); | |
1327 | return PTR_ERR(control_type); | |
1328 | } | |
58705069 | 1329 | return 0; |
2d281d81 JP |
1330 | } |
1331 | ||
1332 | static int rapl_check_domain(int cpu, int domain) | |
1333 | { | |
1334 | unsigned msr; | |
9d31c676 | 1335 | u64 val = 0; |
2d281d81 JP |
1336 | |
1337 | switch (domain) { | |
1338 | case RAPL_DOMAIN_PACKAGE: | |
1339 | msr = MSR_PKG_ENERGY_STATUS; | |
1340 | break; | |
1341 | case RAPL_DOMAIN_PP0: | |
1342 | msr = MSR_PP0_ENERGY_STATUS; | |
1343 | break; | |
1344 | case RAPL_DOMAIN_PP1: | |
1345 | msr = MSR_PP1_ENERGY_STATUS; | |
1346 | break; | |
1347 | case RAPL_DOMAIN_DRAM: | |
1348 | msr = MSR_DRAM_ENERGY_STATUS; | |
1349 | break; | |
3521ba1c SP |
1350 | case RAPL_DOMAIN_PLATFORM: |
1351 | /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */ | |
1352 | return -EINVAL; | |
2d281d81 JP |
1353 | default: |
1354 | pr_err("invalid domain id %d\n", domain); | |
1355 | return -EINVAL; | |
1356 | } | |
9d31c676 JP |
1357 | /* make sure domain counters are available and contains non-zero |
1358 | * values, otherwise skip it. | |
7b874772 | 1359 | */ |
9d31c676 JP |
1360 | if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val) |
1361 | return -ENODEV; | |
2d281d81 | 1362 | |
9d31c676 | 1363 | return 0; |
2d281d81 JP |
1364 | } |
1365 | ||
e1399ba2 JP |
1366 | |
1367 | /* | |
1368 | * Check if power limits are available. Two cases when they are not available: | |
1369 | * 1. Locked by BIOS, in this case we still provide read-only access so that | |
1370 | * users can see what limit is set by the BIOS. | |
1371 | * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not | |
1372 | * exist at all. In this case, we do not show the contraints in powercap. | |
1373 | * | |
1374 | * Called after domains are detected and initialized. | |
1375 | */ | |
1376 | static void rapl_detect_powerlimit(struct rapl_domain *rd) | |
1377 | { | |
1378 | u64 val64; | |
1379 | int i; | |
1380 | ||
1381 | /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */ | |
1382 | if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) { | |
1383 | if (val64) { | |
1384 | pr_info("RAPL package %d domain %s locked by BIOS\n", | |
1385 | rd->rp->id, rd->name); | |
1386 | rd->state |= DOMAIN_STATE_BIOS_LOCKED; | |
1387 | } | |
1388 | } | |
1389 | /* check if power limit MSRs exists, otherwise domain is monitoring only */ | |
1390 | for (i = 0; i < NR_POWER_LIMITS; i++) { | |
1391 | int prim = rd->rpl[i].prim_id; | |
1392 | if (rapl_read_data_raw(rd, prim, false, &val64)) | |
1393 | rd->rpl[i].name = NULL; | |
1394 | } | |
1395 | } | |
1396 | ||
2d281d81 JP |
1397 | /* Detect active and valid domains for the given CPU, caller must |
1398 | * ensure the CPU belongs to the targeted package and CPU hotlug is disabled. | |
1399 | */ | |
1400 | static int rapl_detect_domains(struct rapl_package *rp, int cpu) | |
1401 | { | |
2d281d81 | 1402 | struct rapl_domain *rd; |
58705069 | 1403 | int i; |
2d281d81 JP |
1404 | |
1405 | for (i = 0; i < RAPL_DOMAIN_MAX; i++) { | |
1406 | /* use physical package id to read counters */ | |
fcdf1797 | 1407 | if (!rapl_check_domain(cpu, i)) { |
2d281d81 | 1408 | rp->domain_map |= 1 << i; |
fcdf1797 JP |
1409 | pr_info("Found RAPL domain %s\n", rapl_domain_names[i]); |
1410 | } | |
2d281d81 JP |
1411 | } |
1412 | rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX); | |
1413 | if (!rp->nr_domains) { | |
e1a27e87 | 1414 | pr_debug("no valid rapl domains found in package %d\n", rp->id); |
58705069 | 1415 | return -ENODEV; |
2d281d81 JP |
1416 | } |
1417 | pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id); | |
1418 | ||
1419 | rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain), | |
1420 | GFP_KERNEL); | |
58705069 TG |
1421 | if (!rp->domains) |
1422 | return -ENOMEM; | |
1423 | ||
2d281d81 JP |
1424 | rapl_init_domains(rp); |
1425 | ||
e1399ba2 JP |
1426 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) |
1427 | rapl_detect_powerlimit(rd); | |
1428 | ||
2d281d81 JP |
1429 | return 0; |
1430 | } | |
1431 | ||
1432 | /* called from CPU hotplug notifier, hotplug lock held */ | |
1433 | static void rapl_remove_package(struct rapl_package *rp) | |
1434 | { | |
1435 | struct rapl_domain *rd, *rd_package = NULL; | |
1436 | ||
58705069 TG |
1437 | package_power_limit_irq_restore(rp); |
1438 | ||
2d281d81 | 1439 | for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { |
58705069 TG |
1440 | rapl_write_data_raw(rd, PL1_ENABLE, 0); |
1441 | rapl_write_data_raw(rd, PL1_CLAMP, 0); | |
1442 | if (find_nr_power_limit(rd) > 1) { | |
1443 | rapl_write_data_raw(rd, PL2_ENABLE, 0); | |
1444 | rapl_write_data_raw(rd, PL2_CLAMP, 0); | |
1445 | } | |
2d281d81 JP |
1446 | if (rd->id == RAPL_DOMAIN_PACKAGE) { |
1447 | rd_package = rd; | |
1448 | continue; | |
1449 | } | |
58705069 TG |
1450 | pr_debug("remove package, undo power limit on %d: %s\n", |
1451 | rp->id, rd->name); | |
2d281d81 JP |
1452 | powercap_unregister_zone(control_type, &rd->power_zone); |
1453 | } | |
1454 | /* do parent zone last */ | |
1455 | powercap_unregister_zone(control_type, &rd_package->power_zone); | |
1456 | list_del(&rp->plist); | |
1457 | kfree(rp); | |
1458 | } | |
1459 | ||
1460 | /* called from CPU hotplug notifier, hotplug lock held */ | |
b4005e92 | 1461 | static struct rapl_package *rapl_add_package(int cpu, int pkgid) |
2d281d81 | 1462 | { |
2d281d81 | 1463 | struct rapl_package *rp; |
b4005e92 | 1464 | int ret; |
2d281d81 | 1465 | |
2d281d81 JP |
1466 | rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL); |
1467 | if (!rp) | |
b4005e92 | 1468 | return ERR_PTR(-ENOMEM); |
2d281d81 JP |
1469 | |
1470 | /* add the new package to the list */ | |
b4005e92 | 1471 | rp->id = pkgid; |
323ee64a JP |
1472 | rp->lead_cpu = cpu; |
1473 | ||
2d281d81 JP |
1474 | /* check if the package contains valid domains */ |
1475 | if (rapl_detect_domains(rp, cpu) || | |
3c2c0845 | 1476 | rapl_defaults->check_unit(rp, cpu)) { |
2d281d81 JP |
1477 | ret = -ENODEV; |
1478 | goto err_free_package; | |
1479 | } | |
a74f4367 TG |
1480 | ret = rapl_package_register_powercap(rp); |
1481 | if (!ret) { | |
2d281d81 JP |
1482 | INIT_LIST_HEAD(&rp->plist); |
1483 | list_add(&rp->plist, &rapl_packages); | |
b4005e92 | 1484 | return rp; |
2d281d81 JP |
1485 | } |
1486 | ||
1487 | err_free_package: | |
1488 | kfree(rp->domains); | |
1489 | kfree(rp); | |
b4005e92 | 1490 | return ERR_PTR(ret); |
2d281d81 JP |
1491 | } |
1492 | ||
1493 | /* Handles CPU hotplug on multi-socket systems. | |
1494 | * If a CPU goes online as the first CPU of the physical package | |
1495 | * we add the RAPL package to the system. Similarly, when the last | |
1496 | * CPU of the package is removed, we remove the RAPL package and its | |
1497 | * associated domains. Cooling devices are handled accordingly at | |
1498 | * per-domain level. | |
1499 | */ | |
5e4dc791 SAS |
1500 | static int rapl_cpu_online(unsigned int cpu) |
1501 | { | |
b4005e92 | 1502 | int pkgid = topology_physical_package_id(cpu); |
5e4dc791 | 1503 | struct rapl_package *rp; |
5e4dc791 | 1504 | |
b4005e92 TG |
1505 | rp = find_package_by_id(pkgid); |
1506 | if (!rp) { | |
1507 | rp = rapl_add_package(cpu, pkgid); | |
1508 | if (IS_ERR(rp)) | |
1509 | return PTR_ERR(rp); | |
58705069 | 1510 | } |
b4005e92 TG |
1511 | cpumask_set_cpu(cpu, &rp->cpumask); |
1512 | return 0; | |
5e4dc791 SAS |
1513 | } |
1514 | ||
1515 | static int rapl_cpu_down_prep(unsigned int cpu) | |
2d281d81 | 1516 | { |
b4005e92 | 1517 | int pkgid = topology_physical_package_id(cpu); |
2d281d81 | 1518 | struct rapl_package *rp; |
323ee64a | 1519 | int lead_cpu; |
2d281d81 | 1520 | |
b4005e92 | 1521 | rp = find_package_by_id(pkgid); |
5e4dc791 SAS |
1522 | if (!rp) |
1523 | return 0; | |
b4005e92 TG |
1524 | |
1525 | cpumask_clear_cpu(cpu, &rp->cpumask); | |
1526 | lead_cpu = cpumask_first(&rp->cpumask); | |
1527 | if (lead_cpu >= nr_cpu_ids) | |
5e4dc791 | 1528 | rapl_remove_package(rp); |
b4005e92 TG |
1529 | else if (rp->lead_cpu == cpu) |
1530 | rp->lead_cpu = lead_cpu; | |
5e4dc791 | 1531 | return 0; |
2d281d81 JP |
1532 | } |
1533 | ||
5e4dc791 | 1534 | static enum cpuhp_state pcap_rapl_online; |
2d281d81 JP |
1535 | |
1536 | static int __init rapl_init(void) | |
1537 | { | |
087e9cba | 1538 | const struct x86_cpu_id *id; |
58705069 | 1539 | int ret; |
2d281d81 | 1540 | |
087e9cba JP |
1541 | id = x86_match_cpu(rapl_ids); |
1542 | if (!id) { | |
2d281d81 JP |
1543 | pr_err("driver does not support CPU family %d model %d\n", |
1544 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
1545 | ||
1546 | return -ENODEV; | |
1547 | } | |
009f225e | 1548 | |
087e9cba JP |
1549 | rapl_defaults = (struct rapl_defaults *)id->driver_data; |
1550 | ||
58705069 | 1551 | ret = rapl_register_powercap(); |
2d281d81 | 1552 | if (ret) |
58705069 | 1553 | return ret; |
2d281d81 | 1554 | |
58705069 TG |
1555 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online", |
1556 | rapl_cpu_online, rapl_cpu_down_prep); | |
5e4dc791 SAS |
1557 | if (ret < 0) |
1558 | goto err_unreg; | |
1559 | pcap_rapl_online = ret; | |
58705069 TG |
1560 | |
1561 | /* Don't bail out if PSys is not supported */ | |
1562 | rapl_register_psys(); | |
5e4dc791 SAS |
1563 | return 0; |
1564 | ||
1565 | err_unreg: | |
1566 | rapl_unregister_powercap(); | |
2d281d81 JP |
1567 | return ret; |
1568 | } | |
1569 | ||
1570 | static void __exit rapl_exit(void) | |
1571 | { | |
5e4dc791 | 1572 | cpuhp_remove_state(pcap_rapl_online); |
2d281d81 | 1573 | rapl_unregister_powercap(); |
2d281d81 JP |
1574 | } |
1575 | ||
1576 | module_init(rapl_init); | |
1577 | module_exit(rapl_exit); | |
1578 | ||
1579 | MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)"); | |
1580 | MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); | |
1581 | MODULE_LICENSE("GPL v2"); |