[linux-block.git] / drivers / power / reset / keystone-reset.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * TI keystone reboot driver
 *
 * Copyright (C) 2014 Texas Instruments Incorporated. https://www.ti.com/
 *
 * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
 */

#include <linux/io.h>
#include <linux/module.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/of_platform.h>

#define RSTYPE_RG			0x0
#define RSCTRL_RG			0x4
#define RSCFG_RG			0x8
#define RSISO_RG			0xc

#define RSCTRL_KEY_MASK			0x0000ffff
#define RSCTRL_RESET_MASK		BIT(16)
#define RSCTRL_KEY			0x5a69

#define RSMUX_OMODE_MASK		0xe
#define RSMUX_OMODE_RESET_ON		0xa
#define RSMUX_OMODE_RESET_OFF		0x0
#define RSMUX_LOCK_MASK			0x1
#define RSMUX_LOCK_SET			0x1

#define RSCFG_RSTYPE_SOFT		0x300f
#define RSCFG_RSTYPE_HARD		0x0

#define WDT_MUX_NUMBER			0x4

static int rspll_offset;
static struct regmap *pllctrl_regs;

/**
 * rsctrl_enable_rspll_write - enable access to RSCTRL, RSCFG
 * To be able to access to RSCTRL, RSCFG registers
 * we have to write a key before
 */
static inline int rsctrl_enable_rspll_write(void)
{
	return regmap_update_bits(pllctrl_regs, rspll_offset + RSCTRL_RG,
				  RSCTRL_KEY_MASK, RSCTRL_KEY);
}

static int rsctrl_restart_handler(struct notifier_block *this,
				  unsigned long mode, void *cmd)
{
	/* enable write access to RSTCTRL */
	rsctrl_enable_rspll_write();

	/* reset the SOC */
	regmap_update_bits(pllctrl_regs, rspll_offset + RSCTRL_RG,
			   RSCTRL_RESET_MASK, 0);

	return NOTIFY_DONE;
}

static struct notifier_block rsctrl_restart_nb = {
	.notifier_call = rsctrl_restart_handler,
	.priority = 128,
};

static const struct of_device_id rsctrl_of_match[] = {
	{.compatible = "ti,keystone-reset", },
	{},
};

static int rsctrl_probe(struct platform_device *pdev)
{
	int i;
	int ret;
	u32 val;
	unsigned int rg;
	u32 rsmux_offset;
	struct regmap *devctrl_regs;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;

	if (!np)
		return -ENODEV;

	/* get regmaps */
	pllctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pll");
	if (IS_ERR(pllctrl_regs))
		return PTR_ERR(pllctrl_regs);

	devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-dev");
	if (IS_ERR(devctrl_regs))
		return PTR_ERR(devctrl_regs);

	ret = of_property_read_u32_index(np, "ti,syscon-pll", 1, &rspll_offset);
	if (ret) {
		dev_err(dev, "couldn't read the reset pll offset!\n");
		return -EINVAL;
	}

	ret = of_property_read_u32_index(np, "ti,syscon-dev", 1, &rsmux_offset);
	if (ret) {
		dev_err(dev, "couldn't read the rsmux offset!\n");
		return -EINVAL;
	}

	/* set soft/hard reset */
	val = of_property_read_bool(np, "ti,soft-reset");
	val = val ? RSCFG_RSTYPE_SOFT : RSCFG_RSTYPE_HARD;

	ret = rsctrl_enable_rspll_write();
	if (ret)
		return ret;

	ret = regmap_write(pllctrl_regs, rspll_offset + RSCFG_RG, val);
	if (ret)
		return ret;

	/* disable a reset isolation for all module clocks */
	ret = regmap_write(pllctrl_regs, rspll_offset + RSISO_RG, 0);
	if (ret)
		return ret;

	/* enable a reset for watchdogs from wdt-list */
	for (i = 0; i < WDT_MUX_NUMBER; i++) {
		ret = of_property_read_u32_index(np, "ti,wdt-list", i, &val);
		if (ret == -EOVERFLOW && !i) {
			dev_err(dev, "ti,wdt-list property has to contain at"
				"least one entry\n");
			return -EINVAL;
		} else if (ret) {
			break;
		}

		if (val >= WDT_MUX_NUMBER) {
			dev_err(dev, "ti,wdt-list property can contain "
				"only numbers < 4\n");
			return -EINVAL;
		}

		rg = rsmux_offset + val * 4;

		ret = regmap_update_bits(devctrl_regs, rg, RSMUX_OMODE_MASK,
					 RSMUX_OMODE_RESET_ON |
					 RSMUX_LOCK_SET);
		if (ret)
			return ret;
	}

	ret = register_restart_handler(&rsctrl_restart_nb);
	if (ret)
		dev_err(dev, "cannot register restart handler (err=%d)\n", ret);

	return ret;
}

static struct platform_driver rsctrl_driver = {
	.probe = rsctrl_probe,
	.driver = {
		.name = KBUILD_MODNAME,
		.of_match_table = rsctrl_of_match,
	},
};
module_platform_driver(rsctrl_driver);

MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>");
MODULE_DESCRIPTION("Texas Instruments keystone reset driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" KBUILD_MODNAME);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
a3e01e80 IK	2	/*
	3	* TI keystone reboot driver
	4	*
f03a3497	5	* Copyright (C) 2014 Texas Instruments Incorporated. https://www.ti.com/
a3e01e80 IK	6	*
a3e01e80 IK	7	* Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
a3e01e80 IK	8	*/
	9
	10	#include <linux/io.h>
	11	#include <linux/module.h>
f59a42d4	12	#include <linux/notifier.h>
a3e01e80 IK	13	#include <linux/reboot.h>
a3e01e80 IK	14	#include <linux/regmap.h>
a3e01e80 IK	15	#include <linux/mfd/syscon.h>
	16	#include <linux/of_platform.h>
	17
	18	#define RSTYPE_RG 0x0
	19	#define RSCTRL_RG 0x4
	20	#define RSCFG_RG 0x8
	21	#define RSISO_RG 0xc
	22
	23	#define RSCTRL_KEY_MASK 0x0000ffff
	24	#define RSCTRL_RESET_MASK BIT(16)
	25	#define RSCTRL_KEY 0x5a69
	26
	27	#define RSMUX_OMODE_MASK 0xe
	28	#define RSMUX_OMODE_RESET_ON 0xa
	29	#define RSMUX_OMODE_RESET_OFF 0x0
	30	#define RSMUX_LOCK_MASK 0x1
	31	#define RSMUX_LOCK_SET 0x1
	32
	33	#define RSCFG_RSTYPE_SOFT 0x300f
	34	#define RSCFG_RSTYPE_HARD 0x0
	35
	36	#define WDT_MUX_NUMBER 0x4
	37
	38	static int rspll_offset;
	39	static struct regmap *pllctrl_regs;
	40
	41	/**
	42	* rsctrl_enable_rspll_write - enable access to RSCTRL, RSCFG
	43	* To be able to access to RSCTRL, RSCFG registers
	44	* we have to write a key before
	45	*/
	46	static inline int rsctrl_enable_rspll_write(void)
	47	{
	48	return regmap_update_bits(pllctrl_regs, rspll_offset + RSCTRL_RG,
	49	RSCTRL_KEY_MASK, RSCTRL_KEY);
	50	}
	51
f59a42d4 GR	52	static int rsctrl_restart_handler(struct notifier_block *this,
f59a42d4 GR	53	unsigned long mode, void *cmd)
a3e01e80 IK	54	{
	55	/* enable write access to RSTCTRL */
	56	rsctrl_enable_rspll_write();
	57
	58	/* reset the SOC */
	59	regmap_update_bits(pllctrl_regs, rspll_offset + RSCTRL_RG,
	60	RSCTRL_RESET_MASK, 0);
f59a42d4 GR	61
f59a42d4 GR	62	return NOTIFY_DONE;
a3e01e80 IK	63	}
a3e01e80 IK	64
f59a42d4 GR	65	static struct notifier_block rsctrl_restart_nb = {
	66	.notifier_call = rsctrl_restart_handler,
	67	.priority = 128,
	68	};
	69
8fb08855	70	static const struct of_device_id rsctrl_of_match[] = {
a3e01e80 IK	71	{.compatible = "ti,keystone-reset", },
	72	{},
	73	};
	74
	75	static int rsctrl_probe(struct platform_device *pdev)
	76	{
	77	int i;
	78	int ret;
	79	u32 val;
	80	unsigned int rg;
	81	u32 rsmux_offset;
	82	struct regmap *devctrl_regs;
	83	struct device *dev = &pdev->dev;
	84	struct device_node *np = dev->of_node;
	85
	86	if (!np)
	87	return -ENODEV;
	88
	89	/* get regmaps */
	90	pllctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pll");
	91	if (IS_ERR(pllctrl_regs))
	92	return PTR_ERR(pllctrl_regs);
	93
	94	devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-dev");
	95	if (IS_ERR(devctrl_regs))
	96	return PTR_ERR(devctrl_regs);
	97
	98	ret = of_property_read_u32_index(np, "ti,syscon-pll", 1, &rspll_offset);
	99	if (ret) {
	100	dev_err(dev, "couldn't read the reset pll offset!\n");
	101	return -EINVAL;
	102	}
	103
	104	ret = of_property_read_u32_index(np, "ti,syscon-dev", 1, &rsmux_offset);
	105	if (ret) {
	106	dev_err(dev, "couldn't read the rsmux offset!\n");
	107	return -EINVAL;
	108	}
	109
	110	/* set soft/hard reset */
	111	val = of_property_read_bool(np, "ti,soft-reset");
	112	val = val ? RSCFG_RSTYPE_SOFT : RSCFG_RSTYPE_HARD;
	113
	114	ret = rsctrl_enable_rspll_write();
	115	if (ret)
	116	return ret;
	117
	118	ret = regmap_write(pllctrl_regs, rspll_offset + RSCFG_RG, val);
	119	if (ret)
	120	return ret;
	121
a3e01e80 IK	122	/* disable a reset isolation for all module clocks */
	123	ret = regmap_write(pllctrl_regs, rspll_offset + RSISO_RG, 0);
	124	if (ret)
	125	return ret;
	126
	127	/* enable a reset for watchdogs from wdt-list */
	128	for (i = 0; i < WDT_MUX_NUMBER; i++) {
	129	ret = of_property_read_u32_index(np, "ti,wdt-list", i, &val);
	130	if (ret == -EOVERFLOW && !i) {
	131	dev_err(dev, "ti,wdt-list property has to contain at"
	132	"least one entry\n");
	133	return -EINVAL;
	134	} else if (ret) {
	135	break;
	136	}
	137
	138	if (val >= WDT_MUX_NUMBER) {
1dff6ce0	139	dev_err(dev, "ti,wdt-list property can contain "
a3e01e80 IK	140	"only numbers < 4\n");
	141	return -EINVAL;
	142	}
	143
	144	rg = rsmux_offset + val * 4;
	145
	146	ret = regmap_update_bits(devctrl_regs, rg, RSMUX_OMODE_MASK,
	147	RSMUX_OMODE_RESET_ON \|
	148	RSMUX_LOCK_SET);
	149	if (ret)
	150	return ret;
	151	}
	152
f59a42d4 GR	153	ret = register_restart_handler(&rsctrl_restart_nb);
	154	if (ret)
	155	dev_err(dev, "cannot register restart handler (err=%d)\n", ret);
	156
	157	return ret;
a3e01e80 IK	158	}
	159
	160	static struct platform_driver rsctrl_driver = {
	161	.probe = rsctrl_probe,
	162	.driver = {
a3e01e80 IK	163	.name = KBUILD_MODNAME,
	164	.of_match_table = rsctrl_of_match,
	165	},
	166	};
	167	module_platform_driver(rsctrl_driver);
	168
	169	MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>");
	170	MODULE_DESCRIPTION("Texas Instruments keystone reset driver");
	171	MODULE_LICENSE("GPL v2");
	172	MODULE_ALIAS("platform:" KBUILD_MODNAME);