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ae499f0f MR |
1 | /* |
2 | * Atmel AT91 SAM9 SoCs reset code | |
3 | * | |
4 | * Copyright (C) 2007 Atmel Corporation. | |
5 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
6 | * Copyright (C) 2014 Free Electrons | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
064380a1 | 13 | #include <linux/clk.h> |
ae499f0f MR |
14 | #include <linux/io.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/printk.h> | |
19 | ||
20 | #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */ | |
21 | #define AT91_SHDW_SHDW BIT(0) /* Shut Down command */ | |
22 | #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ | |
23 | ||
24 | #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */ | |
25 | #define AT91_SHDW_WKMODE0 GENMASK(2, 0) /* Wake-up 0 Mode Selection */ | |
26 | #define AT91_SHDW_CPTWK0_MAX 0xf /* Maximum Counter On Wake Up 0 */ | |
27 | #define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */ | |
28 | #define AT91_SHDW_CPTWK0_(x) ((x) << 4) | |
29 | #define AT91_SHDW_RTTWKEN BIT(16) /* Real Time Timer Wake-up Enable */ | |
30 | #define AT91_SHDW_RTCWKEN BIT(17) /* Real Time Clock Wake-up Enable */ | |
31 | ||
32 | #define AT91_SHDW_SR 0x08 /* Shut Down Status Register */ | |
33 | #define AT91_SHDW_WAKEUP0 BIT(0) /* Wake-up 0 Status */ | |
34 | #define AT91_SHDW_RTTWK BIT(16) /* Real-time Timer Wake-up */ | |
35 | #define AT91_SHDW_RTCWK BIT(17) /* Real-time Clock Wake-up [SAM9RL] */ | |
36 | ||
37 | enum wakeup_type { | |
38 | AT91_SHDW_WKMODE0_NONE = 0, | |
39 | AT91_SHDW_WKMODE0_HIGH = 1, | |
40 | AT91_SHDW_WKMODE0_LOW = 2, | |
41 | AT91_SHDW_WKMODE0_ANYLEVEL = 3, | |
42 | }; | |
43 | ||
44 | static const char *shdwc_wakeup_modes[] = { | |
45 | [AT91_SHDW_WKMODE0_NONE] = "none", | |
46 | [AT91_SHDW_WKMODE0_HIGH] = "high", | |
47 | [AT91_SHDW_WKMODE0_LOW] = "low", | |
48 | [AT91_SHDW_WKMODE0_ANYLEVEL] = "any", | |
49 | }; | |
50 | ||
51 | static void __iomem *at91_shdwc_base; | |
064380a1 | 52 | static struct clk *sclk; |
ae499f0f MR |
53 | |
54 | static void __init at91_wakeup_status(void) | |
55 | { | |
405a72c5 | 56 | u32 reg = readl(at91_shdwc_base + AT91_SHDW_SR); |
ae499f0f MR |
57 | char *reason = "unknown"; |
58 | ||
59 | /* Simple power-on, just bail out */ | |
60 | if (!reg) | |
61 | return; | |
62 | ||
63 | if (reg & AT91_SHDW_RTTWK) | |
64 | reason = "RTT"; | |
65 | else if (reg & AT91_SHDW_RTCWK) | |
66 | reason = "RTC"; | |
67 | ||
68 | pr_info("AT91: Wake-Up source: %s\n", reason); | |
69 | } | |
70 | ||
71 | static void at91_poweroff(void) | |
72 | { | |
73 | writel(AT91_SHDW_KEY | AT91_SHDW_SHDW, at91_shdwc_base + AT91_SHDW_CR); | |
74 | } | |
75 | ||
a538cf04 | 76 | static int at91_poweroff_get_wakeup_mode(struct device_node *np) |
ae499f0f MR |
77 | { |
78 | const char *pm; | |
a538cf04 GR |
79 | unsigned int i; |
80 | int err; | |
ae499f0f MR |
81 | |
82 | err = of_property_read_string(np, "atmel,wakeup-mode", &pm); | |
83 | if (err < 0) | |
84 | return AT91_SHDW_WKMODE0_ANYLEVEL; | |
85 | ||
86 | for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++) | |
87 | if (!strcasecmp(pm, shdwc_wakeup_modes[i])) | |
88 | return i; | |
89 | ||
90 | return -ENODEV; | |
91 | } | |
92 | ||
93 | static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev) | |
94 | { | |
95 | struct device_node *np = pdev->dev.of_node; | |
a538cf04 | 96 | int wakeup_mode; |
ae499f0f MR |
97 | u32 mode = 0, tmp; |
98 | ||
99 | wakeup_mode = at91_poweroff_get_wakeup_mode(np); | |
100 | if (wakeup_mode < 0) { | |
101 | dev_warn(&pdev->dev, "shdwc unknown wakeup mode\n"); | |
102 | return; | |
103 | } | |
104 | ||
105 | if (!of_property_read_u32(np, "atmel,wakeup-counter", &tmp)) { | |
106 | if (tmp > AT91_SHDW_CPTWK0_MAX) { | |
107 | dev_warn(&pdev->dev, | |
108 | "shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n", | |
109 | tmp, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX); | |
110 | tmp = AT91_SHDW_CPTWK0_MAX; | |
111 | } | |
112 | mode |= AT91_SHDW_CPTWK0_(tmp); | |
113 | } | |
114 | ||
115 | if (of_property_read_bool(np, "atmel,wakeup-rtc-timer")) | |
116 | mode |= AT91_SHDW_RTCWKEN; | |
117 | ||
118 | if (of_property_read_bool(np, "atmel,wakeup-rtt-timer")) | |
119 | mode |= AT91_SHDW_RTTWKEN; | |
120 | ||
121 | writel(wakeup_mode | mode, at91_shdwc_base + AT91_SHDW_MR); | |
122 | } | |
123 | ||
6dd1ad1f | 124 | static int __init at91_poweroff_probe(struct platform_device *pdev) |
ae499f0f MR |
125 | { |
126 | struct resource *res; | |
064380a1 | 127 | int ret; |
ae499f0f MR |
128 | |
129 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
130 | at91_shdwc_base = devm_ioremap_resource(&pdev->dev, res); | |
131 | if (IS_ERR(at91_shdwc_base)) { | |
132 | dev_err(&pdev->dev, "Could not map reset controller address\n"); | |
133 | return PTR_ERR(at91_shdwc_base); | |
134 | } | |
135 | ||
064380a1 AB |
136 | sclk = devm_clk_get(&pdev->dev, NULL); |
137 | if (IS_ERR(sclk)) | |
138 | return PTR_ERR(sclk); | |
139 | ||
140 | ret = clk_prepare_enable(sclk); | |
141 | if (ret) { | |
142 | dev_err(&pdev->dev, "Could not enable slow clock\n"); | |
143 | return ret; | |
144 | } | |
145 | ||
ae499f0f MR |
146 | at91_wakeup_status(); |
147 | ||
148 | if (pdev->dev.of_node) | |
149 | at91_poweroff_dt_set_wakeup_mode(pdev); | |
150 | ||
151 | pm_power_off = at91_poweroff; | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
6dd1ad1f AB |
156 | static int __exit at91_poweroff_remove(struct platform_device *pdev) |
157 | { | |
158 | if (pm_power_off == at91_poweroff) | |
159 | pm_power_off = NULL; | |
160 | ||
064380a1 AB |
161 | clk_disable_unprepare(sclk); |
162 | ||
6dd1ad1f AB |
163 | return 0; |
164 | } | |
165 | ||
8fb08855 | 166 | static const struct of_device_id at91_poweroff_of_match[] = { |
ae499f0f MR |
167 | { .compatible = "atmel,at91sam9260-shdwc", }, |
168 | { .compatible = "atmel,at91sam9rl-shdwc", }, | |
169 | { .compatible = "atmel,at91sam9x5-shdwc", }, | |
170 | { /*sentinel*/ } | |
171 | }; | |
172 | ||
173 | static struct platform_driver at91_poweroff_driver = { | |
6dd1ad1f | 174 | .remove = __exit_p(at91_poweroff_remove), |
ae499f0f MR |
175 | .driver = { |
176 | .name = "at91-poweroff", | |
177 | .of_match_table = at91_poweroff_of_match, | |
178 | }, | |
179 | }; | |
6dd1ad1f AB |
180 | module_platform_driver_probe(at91_poweroff_driver, at91_poweroff_probe); |
181 | ||
182 | MODULE_AUTHOR("Atmel Corporation"); | |
183 | MODULE_DESCRIPTION("Shutdown driver for Atmel SoCs"); | |
184 | MODULE_LICENSE("GPL v2"); |