[linux-block.git] / drivers / power / reset / at91-poweroff.c

/*
 * Atmel AT91 SAM9 SoCs reset code
 *
 * Copyright (C) 2007 Atmel Corporation.
 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 * Copyright (C) 2014 Free Electrons
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/printk.h>

#include <soc/at91/at91sam9_ddrsdr.h>

#define AT91_SHDW_CR	0x00		/* Shut Down Control Register */
#define AT91_SHDW_SHDW		BIT(0)			/* Shut Down command */
#define AT91_SHDW_KEY		(0xa5 << 24)		/* KEY Password */

#define AT91_SHDW_MR	0x04		/* Shut Down Mode Register */
#define AT91_SHDW_WKMODE0	GENMASK(2, 0)		/* Wake-up 0 Mode Selection */
#define AT91_SHDW_CPTWK0_MAX	0xf			/* Maximum Counter On Wake Up 0 */
#define AT91_SHDW_CPTWK0	(AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
#define AT91_SHDW_CPTWK0_(x)	((x) << 4)
#define AT91_SHDW_RTTWKEN	BIT(16)			/* Real Time Timer Wake-up Enable */
#define AT91_SHDW_RTCWKEN	BIT(17)			/* Real Time Clock Wake-up Enable */

#define AT91_SHDW_SR	0x08		/* Shut Down Status Register */
#define AT91_SHDW_WAKEUP0	BIT(0)			/* Wake-up 0 Status */
#define AT91_SHDW_RTTWK		BIT(16)			/* Real-time Timer Wake-up */
#define AT91_SHDW_RTCWK		BIT(17)			/* Real-time Clock Wake-up [SAM9RL] */

enum wakeup_type {
	AT91_SHDW_WKMODE0_NONE		= 0,
	AT91_SHDW_WKMODE0_HIGH		= 1,
	AT91_SHDW_WKMODE0_LOW		= 2,
	AT91_SHDW_WKMODE0_ANYLEVEL	= 3,
};

static const char *shdwc_wakeup_modes[] = {
	[AT91_SHDW_WKMODE0_NONE]	= "none",
	[AT91_SHDW_WKMODE0_HIGH]	= "high",
	[AT91_SHDW_WKMODE0_LOW]		= "low",
	[AT91_SHDW_WKMODE0_ANYLEVEL]	= "any",
};

static struct shdwc {
	struct clk *sclk;
	void __iomem *shdwc_base;
	void __iomem *mpddrc_base;
} at91_shdwc;

static void __init at91_wakeup_status(struct platform_device *pdev)
{
	const char *reason;
	u32 reg = readl(at91_shdwc.shdwc_base + AT91_SHDW_SR);

	/* Simple power-on, just bail out */
	if (!reg)
		return;

	if (reg & AT91_SHDW_RTTWK)
		reason = "RTT";
	else if (reg & AT91_SHDW_RTCWK)
		reason = "RTC";
	else
		reason = "unknown";

	dev_info(&pdev->dev, "Wake-Up source: %s\n", reason);
}

static void at91_poweroff(void)
{
	asm volatile(
		/* Align to cache lines */
		".balign 32\n\t"

		/* Ensure AT91_SHDW_CR is in the TLB by reading it */
		"	ldr	r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"

		/* Power down SDRAM0 */
		"	tst	%0, #0\n\t"
		"	beq	1f\n\t"
		"	str	%1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
		/* Shutdown CPU */
		"1:	str	%3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"

		"	b	.\n\t"
		:
		: "r" (at91_shdwc.mpddrc_base),
		  "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
		  "r" (at91_shdwc.shdwc_base),
		  "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
		: "r6");
}

static int at91_poweroff_get_wakeup_mode(struct device_node *np)
{
	const char *pm;
	unsigned int i;
	int err;

	err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
	if (err < 0)
		return AT91_SHDW_WKMODE0_ANYLEVEL;

	for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
		if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
			return i;

	return -ENODEV;
}

static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	int wakeup_mode;
	u32 mode = 0, tmp;

	wakeup_mode = at91_poweroff_get_wakeup_mode(np);
	if (wakeup_mode < 0) {
		dev_warn(&pdev->dev, "shdwc unknown wakeup mode\n");
		return;
	}

	if (!of_property_read_u32(np, "atmel,wakeup-counter", &tmp)) {
		if (tmp > AT91_SHDW_CPTWK0_MAX) {
			dev_warn(&pdev->dev,
				 "shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
				 tmp, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
			tmp = AT91_SHDW_CPTWK0_MAX;
		}
		mode |= AT91_SHDW_CPTWK0_(tmp);
	}

	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
			mode |= AT91_SHDW_RTCWKEN;

	if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
			mode |= AT91_SHDW_RTTWKEN;

	writel(wakeup_mode | mode, at91_shdwc.shdwc_base + AT91_SHDW_MR);
}

static int __init at91_poweroff_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct device_node *np;
	u32 ddr_type;
	int ret;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	at91_shdwc.shdwc_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(at91_shdwc.shdwc_base))
		return PTR_ERR(at91_shdwc.shdwc_base);

	at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(at91_shdwc.sclk))
		return PTR_ERR(at91_shdwc.sclk);

	ret = clk_prepare_enable(at91_shdwc.sclk);
	if (ret) {
		dev_err(&pdev->dev, "Could not enable slow clock\n");
		return ret;
	}

	at91_wakeup_status(pdev);

	if (pdev->dev.of_node)
		at91_poweroff_dt_set_wakeup_mode(pdev);

	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
	if (np) {
		at91_shdwc.mpddrc_base = of_iomap(np, 0);
		of_node_put(np);

		if (!at91_shdwc.mpddrc_base) {
			ret = -ENOMEM;
			goto clk_disable;
		}

		ddr_type = readl(at91_shdwc.mpddrc_base + AT91_DDRSDRC_MDR) &
				 AT91_DDRSDRC_MD;
		if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
		    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
			iounmap(at91_shdwc.mpddrc_base);
			at91_shdwc.mpddrc_base = NULL;
		}
	}

	pm_power_off = at91_poweroff;

	return 0;

clk_disable:
	clk_disable_unprepare(at91_shdwc.sclk);
	return ret;
}

static int __exit at91_poweroff_remove(struct platform_device *pdev)
{
	if (pm_power_off == at91_poweroff)
		pm_power_off = NULL;

	if (at91_shdwc.mpddrc_base)
		iounmap(at91_shdwc.mpddrc_base);

	clk_disable_unprepare(at91_shdwc.sclk);

	return 0;
}

static const struct of_device_id at91_poweroff_of_match[] = {
	{ .compatible = "atmel,at91sam9260-shdwc", },
	{ .compatible = "atmel,at91sam9rl-shdwc", },
	{ .compatible = "atmel,at91sam9x5-shdwc", },
	{ /*sentinel*/ }
};
MODULE_DEVICE_TABLE(of, at91_poweroff_of_match);

static struct platform_driver at91_poweroff_driver = {
	.remove = __exit_p(at91_poweroff_remove),
	.driver = {
		.name = "at91-poweroff",
		.of_match_table = at91_poweroff_of_match,
	},
};
module_platform_driver_probe(at91_poweroff_driver, at91_poweroff_probe);

MODULE_AUTHOR("Atmel Corporation");
MODULE_DESCRIPTION("Shutdown driver for Atmel SoCs");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ae499f0f MR	1	/*
	2	* Atmel AT91 SAM9 SoCs reset code
	3	*
	4	* Copyright (C) 2007 Atmel Corporation.
	5	* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	6	* Copyright (C) 2014 Free Electrons
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
064380a1	13	#include <linux/clk.h>
ae499f0f MR	14	#include <linux/io.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
0b040874	17	#include <linux/of_address.h>
ae499f0f MR	18	#include <linux/platform_device.h>
	19	#include <linux/printk.h>
	20
0b040874 AB	21	#include <soc/at91/at91sam9_ddrsdr.h>
0b040874 AB	22
ae499f0f MR	23	#define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
	24	#define AT91_SHDW_SHDW BIT(0) /* Shut Down command */
	25	#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
	26
	27	#define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
	28	#define AT91_SHDW_WKMODE0 GENMASK(2, 0) /* Wake-up 0 Mode Selection */
	29	#define AT91_SHDW_CPTWK0_MAX 0xf /* Maximum Counter On Wake Up 0 */
	30	#define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
	31	#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
	32	#define AT91_SHDW_RTTWKEN BIT(16) /* Real Time Timer Wake-up Enable */
	33	#define AT91_SHDW_RTCWKEN BIT(17) /* Real Time Clock Wake-up Enable */
	34
	35	#define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
	36	#define AT91_SHDW_WAKEUP0 BIT(0) /* Wake-up 0 Status */
	37	#define AT91_SHDW_RTTWK BIT(16) /* Real-time Timer Wake-up */
	38	#define AT91_SHDW_RTCWK BIT(17) /* Real-time Clock Wake-up [SAM9RL] */
	39
	40	enum wakeup_type {
	41	AT91_SHDW_WKMODE0_NONE = 0,
	42	AT91_SHDW_WKMODE0_HIGH = 1,
	43	AT91_SHDW_WKMODE0_LOW = 2,
	44	AT91_SHDW_WKMODE0_ANYLEVEL = 3,
	45	};
	46
	47	static const char *shdwc_wakeup_modes[] = {
	48	[AT91_SHDW_WKMODE0_NONE] = "none",
	49	[AT91_SHDW_WKMODE0_HIGH] = "high",
	50	[AT91_SHDW_WKMODE0_LOW] = "low",
	51	[AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
	52	};
	53
caa6e150 CB	54	static struct shdwc {
	55	struct clk *sclk;
	56	void __iomem *shdwc_base;
	57	void __iomem *mpddrc_base;
	58	} at91_shdwc;
ae499f0f	59
062836db	60	static void __init at91_wakeup_status(struct platform_device *pdev)
ae499f0f	61	{
062836db	62	const char *reason;
caa6e150	63	u32 reg = readl(at91_shdwc.shdwc_base + AT91_SHDW_SR);
ae499f0f MR	64
	65	/* Simple power-on, just bail out */
	66	if (!reg)
	67	return;
	68
	69	if (reg & AT91_SHDW_RTTWK)
	70	reason = "RTT";
	71	else if (reg & AT91_SHDW_RTCWK)
	72	reason = "RTC";
062836db LM	73	else
062836db LM	74	reason = "unknown";
ae499f0f	75
062836db	76	dev_info(&pdev->dev, "Wake-Up source: %s\n", reason);
ae499f0f MR	77	}
	78
	79	static void at91_poweroff(void)
0b040874 AB	80	{
	81	asm volatile(
	82	/* Align to cache lines */
	83	".balign 32\n\t"
	84
	85	/* Ensure AT91_SHDW_CR is in the TLB by reading it */
	86	" ldr r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
	87
	88	/* Power down SDRAM0 */
996463fd CB	89	" tst %0, #0\n\t"
996463fd CB	90	" beq 1f\n\t"
0b040874 AB	91	" str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
0b040874 AB	92	/* Shutdown CPU */
996463fd	93	"1: str %3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
0b040874 AB	94
	95	" b .\n\t"
	96	:
caa6e150	97	: "r" (at91_shdwc.mpddrc_base),
0b040874	98	"r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
caa6e150	99	"r" (at91_shdwc.shdwc_base),
0b040874	100	"r" cpu_to_le32(AT91_SHDW_KEY \| AT91_SHDW_SHDW)
2e9bbbf6	101	: "r6");
0b040874 AB	102	}
0b040874 AB	103
a538cf04	104	static int at91_poweroff_get_wakeup_mode(struct device_node *np)
ae499f0f MR	105	{
ae499f0f MR	106	const char *pm;
a538cf04 GR	107	unsigned int i;
a538cf04 GR	108	int err;
ae499f0f MR	109
	110	err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
	111	if (err < 0)
	112	return AT91_SHDW_WKMODE0_ANYLEVEL;
	113
	114	for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
	115	if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
	116	return i;
	117
	118	return -ENODEV;
	119	}
	120
	121	static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
	122	{
	123	struct device_node *np = pdev->dev.of_node;
a538cf04	124	int wakeup_mode;
ae499f0f MR	125	u32 mode = 0, tmp;
	126
	127	wakeup_mode = at91_poweroff_get_wakeup_mode(np);
	128	if (wakeup_mode < 0) {
	129	dev_warn(&pdev->dev, "shdwc unknown wakeup mode\n");
	130	return;
	131	}
	132
	133	if (!of_property_read_u32(np, "atmel,wakeup-counter", &tmp)) {
	134	if (tmp > AT91_SHDW_CPTWK0_MAX) {
	135	dev_warn(&pdev->dev,
	136	"shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
	137	tmp, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
	138	tmp = AT91_SHDW_CPTWK0_MAX;
	139	}
	140	mode \|= AT91_SHDW_CPTWK0_(tmp);
	141	}
	142
	143	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
	144	mode \|= AT91_SHDW_RTCWKEN;
	145
	146	if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
	147	mode \|= AT91_SHDW_RTTWKEN;
	148
caa6e150	149	writel(wakeup_mode \| mode, at91_shdwc.shdwc_base + AT91_SHDW_MR);
ae499f0f MR	150	}
ae499f0f MR	151
6dd1ad1f	152	static int __init at91_poweroff_probe(struct platform_device *pdev)
ae499f0f MR	153	{
ae499f0f MR	154	struct resource *res;
0b040874 AB	155	struct device_node *np;
0b040874 AB	156	u32 ddr_type;
064380a1	157	int ret;
ae499f0f MR	158
ae499f0f MR	159	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
caa6e150 CB	160	at91_shdwc.shdwc_base = devm_ioremap_resource(&pdev->dev, res);
	161	if (IS_ERR(at91_shdwc.shdwc_base))
	162	return PTR_ERR(at91_shdwc.shdwc_base);
ae499f0f	163
caa6e150 CB	164	at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL);
	165	if (IS_ERR(at91_shdwc.sclk))
	166	return PTR_ERR(at91_shdwc.sclk);
064380a1	167
caa6e150	168	ret = clk_prepare_enable(at91_shdwc.sclk);
064380a1 AB	169	if (ret) {
	170	dev_err(&pdev->dev, "Could not enable slow clock\n");
	171	return ret;
	172	}
	173
062836db	174	at91_wakeup_status(pdev);
ae499f0f MR	175
	176	if (pdev->dev.of_node)
	177	at91_poweroff_dt_set_wakeup_mode(pdev);
	178
0b040874	179	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
996463fd	180	if (np) {
caa6e150	181	at91_shdwc.mpddrc_base = of_iomap(np, 0);
996463fd	182	of_node_put(np);
0b040874	183
caa6e150	184	if (!at91_shdwc.mpddrc_base) {
996463fd CB	185	ret = -ENOMEM;
	186	goto clk_disable;
	187	}
0b040874	188
caa6e150	189	ddr_type = readl(at91_shdwc.mpddrc_base + AT91_DDRSDRC_MDR) &
996463fd CB	190	AT91_DDRSDRC_MD;
	191	if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
	192	ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
caa6e150 CB	193	iounmap(at91_shdwc.mpddrc_base);
caa6e150 CB	194	at91_shdwc.mpddrc_base = NULL;
996463fd CB	195	}
996463fd CB	196	}
0b040874	197
996463fd	198	pm_power_off = at91_poweroff;
0b040874	199
ae499f0f	200	return 0;
996463fd CB	201
996463fd CB	202	clk_disable:
caa6e150	203	clk_disable_unprepare(at91_shdwc.sclk);
996463fd	204	return ret;
ae499f0f MR	205	}
ae499f0f MR	206
6dd1ad1f AB	207	static int __exit at91_poweroff_remove(struct platform_device *pdev)
6dd1ad1f AB	208	{
996463fd	209	if (pm_power_off == at91_poweroff)
6dd1ad1f AB	210	pm_power_off = NULL;
6dd1ad1f AB	211
caa6e150 CB	212	if (at91_shdwc.mpddrc_base)
caa6e150 CB	213	iounmap(at91_shdwc.mpddrc_base);
996463fd	214
caa6e150	215	clk_disable_unprepare(at91_shdwc.sclk);
064380a1	216
6dd1ad1f AB	217	return 0;
	218	}
	219
8fb08855	220	static const struct of_device_id at91_poweroff_of_match[] = {
ae499f0f MR	221	{ .compatible = "atmel,at91sam9260-shdwc", },
	222	{ .compatible = "atmel,at91sam9rl-shdwc", },
	223	{ .compatible = "atmel,at91sam9x5-shdwc", },
	224	{ /sentinel/ }
	225	};
c9ba9b77	226	MODULE_DEVICE_TABLE(of, at91_poweroff_of_match);
ae499f0f MR	227
ae499f0f MR	228	static struct platform_driver at91_poweroff_driver = {
6dd1ad1f	229	.remove = __exit_p(at91_poweroff_remove),
ae499f0f MR	230	.driver = {
	231	.name = "at91-poweroff",
	232	.of_match_table = at91_poweroff_of_match,
	233	},
	234	};
6dd1ad1f AB	235	module_platform_driver_probe(at91_poweroff_driver, at91_poweroff_probe);
	236
	237	MODULE_AUTHOR("Atmel Corporation");
	238	MODULE_DESCRIPTION("Shutdown driver for Atmel SoCs");
	239	MODULE_LICENSE("GPL v2");