[linux-block.git] / drivers / pnp / quirks.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  This file contains quirk handling code for PnP devices
 *  Some devices do not report all their resources, and need to have extra
 *  resources added. This is most easily accomplished at initialisation time
 *  when building up the resource structure for the first time.
 *
 *  Copyright (c) 2000 Peter Denison <peterd@pnd-pc.demon.co.uk>
 *  Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
 *	Bjorn Helgaas <bjorn.helgaas@hp.com>
 *
 *  Heavily based on PCI quirks handling which is
 *
 *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/pnp.h>
#include <linux/io.h>
#include "base.h"

static void quirk_awe32_add_ports(struct pnp_dev *dev,
				  struct pnp_option *option,
				  unsigned int offset)
{
	struct pnp_option *new_option;

	new_option = kmalloc(sizeof(struct pnp_option), GFP_KERNEL);
	if (!new_option) {
		dev_err(&dev->dev, "couldn't add ioport region to option set "
			"%d\n", pnp_option_set(option));
		return;
	}

	*new_option = *option;
	new_option->u.port.min += offset;
	new_option->u.port.max += offset;
	list_add(&new_option->list, &option->list);

	dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n",
		(unsigned long long) new_option->u.port.min,
		(unsigned long long) new_option->u.port.max,
		pnp_option_set(option));
}

static void quirk_awe32_resources(struct pnp_dev *dev)
{
	struct pnp_option *option;
	unsigned int set = ~0;

	/*
	 * Add two extra ioport regions (at offset 0x400 and 0x800 from the
	 * one given) to every dependent option set.
	 */
	list_for_each_entry(option, &dev->options, list) {
		if (pnp_option_is_dependent(option) &&
		    pnp_option_set(option) != set) {
			set = pnp_option_set(option);
			quirk_awe32_add_ports(dev, option, 0x800);
			quirk_awe32_add_ports(dev, option, 0x400);
		}
	}
}

static void quirk_cmi8330_resources(struct pnp_dev *dev)
{
	struct pnp_option *option;
	struct pnp_irq *irq;
	struct pnp_dma *dma;

	list_for_each_entry(option, &dev->options, list) {
		if (!pnp_option_is_dependent(option))
			continue;

		if (option->type == IORESOURCE_IRQ) {
			irq = &option->u.irq;
			bitmap_zero(irq->map.bits, PNP_IRQ_NR);
			__set_bit(5, irq->map.bits);
			__set_bit(7, irq->map.bits);
			__set_bit(10, irq->map.bits);
			dev_info(&dev->dev, "set possible IRQs in "
				 "option set %d to 5, 7, 10\n",
				 pnp_option_set(option));
		} else if (option->type == IORESOURCE_DMA) {
			dma = &option->u.dma;
			if ((dma->flags & IORESOURCE_DMA_TYPE_MASK) ==
						IORESOURCE_DMA_8BIT &&
			    dma->map != 0x0A) {
				dev_info(&dev->dev, "changing possible "
					 "DMA channel mask in option set %d "
					 "from %#02x to 0x0A (1, 3)\n",
					 pnp_option_set(option), dma->map);
				dma->map = 0x0A;
			}
		}
	}
}

static void quirk_sb16audio_resources(struct pnp_dev *dev)
{
	struct pnp_option *option;
	unsigned int prev_option_flags = ~0, n = 0;
	struct pnp_port *port;

	/*
	 * The default range on the OPL port for these devices is 0x388-0x388.
	 * Here we increase that range so that two such cards can be
	 * auto-configured.
	 */
	list_for_each_entry(option, &dev->options, list) {
		if (prev_option_flags != option->flags) {
			prev_option_flags = option->flags;
			n = 0;
		}

		if (pnp_option_is_dependent(option) &&
		    option->type == IORESOURCE_IO) {
			n++;
			port = &option->u.port;
			if (n == 3 && port->min == port->max) {
				port->max += 0x70;
				dev_info(&dev->dev, "increased option port "
					 "range from %#llx-%#llx to "
					 "%#llx-%#llx\n",
					 (unsigned long long) port->min,
					 (unsigned long long) port->min,
					 (unsigned long long) port->min,
					 (unsigned long long) port->max);
			}
		}
	}
}

static struct pnp_option *pnp_clone_dependent_set(struct pnp_dev *dev,
						  unsigned int set)
{
	struct pnp_option *tail = NULL, *first_new_option = NULL;
	struct pnp_option *option, *new_option;
	unsigned int flags;

	list_for_each_entry(option, &dev->options, list) {
		if (pnp_option_is_dependent(option))
			tail = option;
	}
	if (!tail) {
		dev_err(&dev->dev, "no dependent option sets\n");
		return NULL;
	}

	flags = pnp_new_dependent_set(dev, PNP_RES_PRIORITY_FUNCTIONAL);
	list_for_each_entry(option, &dev->options, list) {
		if (pnp_option_is_dependent(option) &&
		    pnp_option_set(option) == set) {
			new_option = kmalloc(sizeof(struct pnp_option),
					     GFP_KERNEL);
			if (!new_option) {
				dev_err(&dev->dev, "couldn't clone dependent "
					"set %d\n", set);
				return NULL;
			}

			*new_option = *option;
			new_option->flags = flags;
			if (!first_new_option)
				first_new_option = new_option;

			list_add(&new_option->list, &tail->list);
			tail = new_option;
		}
	}

	return first_new_option;
}


static void quirk_add_irq_optional_dependent_sets(struct pnp_dev *dev)
{
	struct pnp_option *new_option;
	unsigned int num_sets, i, set;
	struct pnp_irq *irq;

	num_sets = dev->num_dependent_sets;
	for (i = 0; i < num_sets; i++) {
		new_option = pnp_clone_dependent_set(dev, i);
		if (!new_option)
			return;

		set = pnp_option_set(new_option);
		while (new_option && pnp_option_set(new_option) == set) {
			if (new_option->type == IORESOURCE_IRQ) {
				irq = &new_option->u.irq;
				irq->flags |= IORESOURCE_IRQ_OPTIONAL;
			}
			dbg_pnp_show_option(dev, new_option);
			new_option = list_entry(new_option->list.next,
						struct pnp_option, list);
		}

		dev_info(&dev->dev, "added dependent option set %d (same as "
			 "set %d except IRQ optional)\n", set, i);
	}
}

static void quirk_ad1815_mpu_resources(struct pnp_dev *dev)
{
	struct pnp_option *option;
	struct pnp_irq *irq = NULL;
	unsigned int independent_irqs = 0;

	list_for_each_entry(option, &dev->options, list) {
		if (option->type == IORESOURCE_IRQ &&
		    !pnp_option_is_dependent(option)) {
			independent_irqs++;
			irq = &option->u.irq;
		}
	}

	if (independent_irqs != 1)
		return;

	irq->flags |= IORESOURCE_IRQ_OPTIONAL;
	dev_info(&dev->dev, "made independent IRQ optional\n");
}

static void quirk_system_pci_resources(struct pnp_dev *dev)
{
	struct pci_dev *pdev = NULL;
	struct resource *res, *r;
	int i, j;

	/*
	 * Some BIOSes have PNP motherboard devices with resources that
	 * partially overlap PCI BARs.  The PNP system driver claims these
	 * motherboard resources, which prevents the normal PCI driver from
	 * requesting them later.
	 *
	 * This patch disables the PNP resources that conflict with PCI BARs
	 * so they won't be claimed by the PNP system driver.
	 */
	for_each_pci_dev(pdev) {
		pci_dev_for_each_resource(pdev, r, i) {
			unsigned long type = resource_type(r);

			if (!(type == IORESOURCE_IO || type == IORESOURCE_MEM) ||
			    resource_size(r) == 0)
				continue;

			if (r->flags & IORESOURCE_UNSET)
				continue;

			for (j = 0;
			     (res = pnp_get_resource(dev, type, j)); j++) {
				if (res->start == 0 && res->end == 0)
					continue;

				/*
				 * If the PNP region doesn't overlap the PCI
				 * region at all, there's no problem.
				 */
				if (!resource_overlaps(res, r))
					continue;

				/*
				 * If the PNP region completely encloses (or is
				 * at least as large as) the PCI region, that's
				 * also OK.  For example, this happens when the
				 * PNP device describes a bridge with PCI
				 * behind it.
				 */
				if (res->start <= r->start && res->end >= r->end)
					continue;

				/*
				 * Otherwise, the PNP region overlaps *part* of
				 * the PCI region, and that might prevent a PCI
				 * driver from requesting its resources.
				 */
				dev_warn(&dev->dev,
					 "disabling %pR because it overlaps %s BAR %d %pR\n",
					 res, pci_name(pdev), i, r);
				res->flags |= IORESOURCE_DISABLED;
			}
		}
	}
}

#ifdef CONFIG_AMD_NB

#include <asm/amd_nb.h>

static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
{
	resource_size_t start, end;
	struct pnp_resource *pnp_res;
	struct resource *res;
	struct resource mmconfig_res, *mmconfig;

	mmconfig = amd_get_mmconfig_range(&mmconfig_res);
	if (!mmconfig)
		return;

	list_for_each_entry(pnp_res, &dev->resources, list) {
		res = &pnp_res->res;
		if (res->end < mmconfig->start || res->start > mmconfig->end ||
		    (res->start == mmconfig->start && res->end == mmconfig->end))
			continue;

		dev_info(&dev->dev, FW_BUG
			 "%pR covers only part of AMD MMCONFIG area %pR; adding more reservations\n",
			 res, mmconfig);
		if (mmconfig->start < res->start) {
			start = mmconfig->start;
			end = res->start - 1;
			pnp_add_mem_resource(dev, start, end, 0);
		}
		if (mmconfig->end > res->end) {
			start = res->end + 1;
			end = mmconfig->end;
			pnp_add_mem_resource(dev, start, end, 0);
		}
		break;
	}
}
#endif

#ifdef CONFIG_PCI
/* Device IDs of parts that have 32KB MCH space */
static const unsigned int mch_quirk_devices[] = {
	0x0154,	/* Ivy Bridge */
	0x0a04, /* Haswell-ULT */
	0x0c00,	/* Haswell */
	0x1604, /* Broadwell */
};

static struct pci_dev *get_intel_host(void)
{
	int i;
	struct pci_dev *host;

	for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
		host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
				      NULL);
		if (host)
			return host;
	}
	return NULL;
}

static void quirk_intel_mch(struct pnp_dev *dev)
{
	struct pci_dev *host;
	u32 addr_lo, addr_hi;
	struct pci_bus_region region;
	struct resource mch;
	struct pnp_resource *pnp_res;
	struct resource *res;

	host = get_intel_host();
	if (!host)
		return;

	/*
	 * MCHBAR is not an architected PCI BAR, so MCH space is usually
	 * reported as a PNP0C02 resource.  The MCH space was originally
	 * 16KB, but is 32KB in newer parts.  Some BIOSes still report a
	 * PNP0C02 resource that is only 16KB, which means the rest of the
	 * MCH space is consumed but unreported.
	 */

	/*
	 * Read MCHBAR for Host Member Mapped Register Range Base
	 * https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
	 * Sec 3.1.12.
	 */
	pci_read_config_dword(host, 0x48, &addr_lo);
	region.start = addr_lo & ~0x7fff;
	pci_read_config_dword(host, 0x4c, &addr_hi);
	region.start |= (u64) addr_hi << 32;
	region.end = region.start + 32*1024 - 1;

	memset(&mch, 0, sizeof(mch));
	mch.flags = IORESOURCE_MEM;
	pcibios_bus_to_resource(host->bus, &mch, &region);

	list_for_each_entry(pnp_res, &dev->resources, list) {
		res = &pnp_res->res;
		if (res->end < mch.start || res->start > mch.end)
			continue;	/* no overlap */
		if (res->start == mch.start && res->end == mch.end)
			continue;	/* exact match */

		dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
			 res, pci_name(host), &mch);
		res->start = mch.start;
		res->end = mch.end;
		break;
	}

	pci_dev_put(host);
}
#endif

/*
 *  PnP Quirks
 *  Cards or devices that need some tweaking due to incomplete resource info
 */

static struct pnp_fixup pnp_fixups[] = {
	/* Soundblaster awe io port quirk */
	{"CTL0021", quirk_awe32_resources},
	{"CTL0022", quirk_awe32_resources},
	{"CTL0023", quirk_awe32_resources},
	/* CMI 8330 interrupt and dma fix */
	{"@X@0001", quirk_cmi8330_resources},
	/* Soundblaster audio device io port range quirk */
	{"CTL0001", quirk_sb16audio_resources},
	{"CTL0031", quirk_sb16audio_resources},
	{"CTL0041", quirk_sb16audio_resources},
	{"CTL0042", quirk_sb16audio_resources},
	{"CTL0043", quirk_sb16audio_resources},
	{"CTL0044", quirk_sb16audio_resources},
	{"CTL0045", quirk_sb16audio_resources},
	/* Add IRQ-optional MPU options */
	{"ADS7151", quirk_ad1815_mpu_resources},
	{"ADS7181", quirk_add_irq_optional_dependent_sets},
	{"AZT0002", quirk_add_irq_optional_dependent_sets},
	/* PnP resources that might overlap PCI BARs */
	{"PNP0c01", quirk_system_pci_resources},
	{"PNP0c02", quirk_system_pci_resources},
#ifdef CONFIG_AMD_NB
	{"PNP0c01", quirk_amd_mmconfig_area},
#endif
#ifdef CONFIG_PCI
	{"PNP0c02", quirk_intel_mch},
#endif
	{""}
};

void pnp_fixup_device(struct pnp_dev *dev)
{
	struct pnp_fixup *f;

	for (f = pnp_fixups; *f->id; f++) {
		if (!compare_pnp_id(dev->id, f->id))
			continue;
		pnp_dbg(&dev->dev, "%s: calling %pS\n", f->id,
			f->quirk_function);
		f->quirk_function(dev);
	}
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* This file contains quirk handling code for PnP devices
	4	* Some devices do not report all their resources, and need to have extra
	5	* resources added. This is most easily accomplished at initialisation time
	6	* when building up the resource structure for the first time.
	7	*
	8	* Copyright (c) 2000 Peter Denison <peterd@pnd-pc.demon.co.uk>
1f32ca31 BH	9	* Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
1f32ca31 BH	10	* Bjorn Helgaas <bjorn.helgaas@hp.com>
1da177e4 LT	11	*
	12	* Heavily based on PCI quirks handling which is
	13	*
	14	* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
	15	*/
	16
1da177e4 LT	17	#include <linux/types.h>
1da177e4 LT	18	#include <linux/kernel.h>
cb171f7a	19	#include <linux/pci.h>
1da177e4 LT	20	#include <linux/string.h>
1da177e4 LT	21	#include <linux/slab.h>
1da177e4	22	#include <linux/pnp.h>
a1e7e636	23	#include <linux/io.h>
1da177e4 LT	24	#include "base.h"
1da177e4 LT	25
1f32ca31 BH	26	static void quirk_awe32_add_ports(struct pnp_dev *dev,
	27	struct pnp_option *option,
	28	unsigned int offset)
	29	{
	30	struct pnp_option *new_option;
	31
	32	new_option = kmalloc(sizeof(struct pnp_option), GFP_KERNEL);
	33	if (!new_option) {
	34	dev_err(&dev->dev, "couldn't add ioport region to option set "
	35	"%d\n", pnp_option_set(option));
	36	return;
	37	}
	38
	39	new_option = option;
	40	new_option->u.port.min += offset;
	41	new_option->u.port.max += offset;
	42	list_add(&new_option->list, &option->list);
	43
	44	dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n",
	45	(unsigned long long) new_option->u.port.min,
	46	(unsigned long long) new_option->u.port.max,
	47	pnp_option_set(option));
	48	}
	49
1da177e4 LT	50	static void quirk_awe32_resources(struct pnp_dev *dev)
1da177e4 LT	51	{
1f32ca31 BH	52	struct pnp_option *option;
1f32ca31 BH	53	unsigned int set = ~0;
1da177e4 LT	54
1da177e4 LT	55	/*
1f32ca31 BH	56	* Add two extra ioport regions (at offset 0x400 and 0x800 from the
1f32ca31 BH	57	* one given) to every dependent option set.
1da177e4	58	*/
1f32ca31 BH	59	list_for_each_entry(option, &dev->options, list) {
	60	if (pnp_option_is_dependent(option) &&
	61	pnp_option_set(option) != set) {
	62	set = pnp_option_set(option);
	63	quirk_awe32_add_ports(dev, option, 0x800);
	64	quirk_awe32_add_ports(dev, option, 0x400);
1da177e4	65	}
1da177e4	66	}
1da177e4 LT	67	}
	68
	69	static void quirk_cmi8330_resources(struct pnp_dev *dev)
	70	{
1f32ca31 BH	71	struct pnp_option *option;
	72	struct pnp_irq *irq;
	73	struct pnp_dma *dma;
1da177e4	74
1f32ca31 BH	75	list_for_each_entry(option, &dev->options, list) {
	76	if (!pnp_option_is_dependent(option))
	77	continue;
1da177e4	78
1f32ca31 BH	79	if (option->type == IORESOURCE_IRQ) {
	80	irq = &option->u.irq;
	81	bitmap_zero(irq->map.bits, PNP_IRQ_NR);
	82	__set_bit(5, irq->map.bits);
	83	__set_bit(7, irq->map.bits);
	84	__set_bit(10, irq->map.bits);
	85	dev_info(&dev->dev, "set possible IRQs in "
	86	"option set %d to 5, 7, 10\n",
	87	pnp_option_set(option));
	88	} else if (option->type == IORESOURCE_DMA) {
	89	dma = &option->u.dma;
9dd78466	90	if ((dma->flags & IORESOURCE_DMA_TYPE_MASK) ==
1f32ca31 BH	91	IORESOURCE_DMA_8BIT &&
	92	dma->map != 0x0A) {
	93	dev_info(&dev->dev, "changing possible "
	94	"DMA channel mask in option set %d "
	95	"from %#02x to 0x0A (1, 3)\n",
	96	pnp_option_set(option), dma->map);
	97	dma->map = 0x0A;
	98	}
7aefff51	99	}
1da177e4	100	}
1da177e4 LT	101	}
	102
	103	static void quirk_sb16audio_resources(struct pnp_dev *dev)
	104	{
1f32ca31 BH	105	struct pnp_option *option;
1f32ca31 BH	106	unsigned int prev_option_flags = ~0, n = 0;
1da177e4	107	struct pnp_port *port;
1da177e4 LT	108
1da177e4 LT	109	/*
1f32ca31	110	* The default range on the OPL port for these devices is 0x388-0x388.
1da177e4 LT	111	* Here we increase that range so that two such cards can be
	112	* auto-configured.
	113	*/
1f32ca31 BH	114	list_for_each_entry(option, &dev->options, list) {
	115	if (prev_option_flags != option->flags) {
	116	prev_option_flags = option->flags;
	117	n = 0;
	118	}
1da177e4	119
1f32ca31 BH	120	if (pnp_option_is_dependent(option) &&
	121	option->type == IORESOURCE_IO) {
	122	n++;
	123	port = &option->u.port;
	124	if (n == 3 && port->min == port->max) {
	125	port->max += 0x70;
	126	dev_info(&dev->dev, "increased option port "
	127	"range from %#llx-%#llx to "
	128	"%#llx-%#llx\n",
	129	(unsigned long long) port->min,
	130	(unsigned long long) port->min,
	131	(unsigned long long) port->min,
	132	(unsigned long long) port->max);
	133	}
	134	}
1da177e4	135	}
1da177e4 LT	136	}
1da177e4 LT	137
1f32ca31 BH	138	static struct pnp_option pnp_clone_dependent_set(struct pnp_dev dev,
1f32ca31 BH	139	unsigned int set)
3b73a223	140	{
1f32ca31 BH	141	struct pnp_option tail = NULL, first_new_option = NULL;
	142	struct pnp_option option, new_option;
	143	unsigned int flags;
3b73a223	144
1f32ca31 BH	145	list_for_each_entry(option, &dev->options, list) {
	146	if (pnp_option_is_dependent(option))
	147	tail = option;
	148	}
	149	if (!tail) {
	150	dev_err(&dev->dev, "no dependent option sets\n");
	151	return NULL;
	152	}
d5ebde6e	153
1f32ca31 BH	154	flags = pnp_new_dependent_set(dev, PNP_RES_PRIORITY_FUNCTIONAL);
	155	list_for_each_entry(option, &dev->options, list) {
	156	if (pnp_option_is_dependent(option) &&
	157	pnp_option_set(option) == set) {
	158	new_option = kmalloc(sizeof(struct pnp_option),
	159	GFP_KERNEL);
	160	if (!new_option) {
	161	dev_err(&dev->dev, "couldn't clone dependent "
	162	"set %d\n", set);
	163	return NULL;
	164	}
3b73a223	165
1f32ca31 BH	166	new_option = option;
	167	new_option->flags = flags;
	168	if (!first_new_option)
	169	first_new_option = new_option;
3b73a223	170
1f32ca31 BH	171	list_add(&new_option->list, &tail->list);
1f32ca31 BH	172	tail = new_option;
3b73a223	173	}
3b73a223	174	}
3b73a223	175
1f32ca31	176	return first_new_option;
3b73a223 RH	177	}
3b73a223 RH	178
1f32ca31 BH	179
1f32ca31 BH	180	static void quirk_add_irq_optional_dependent_sets(struct pnp_dev *dev)
3b73a223	181	{
1f32ca31 BH	182	struct pnp_option *new_option;
1f32ca31 BH	183	unsigned int num_sets, i, set;
3b73a223 RH	184	struct pnp_irq *irq;
3b73a223 RH	185
1f32ca31 BH	186	num_sets = dev->num_dependent_sets;
	187	for (i = 0; i < num_sets; i++) {
	188	new_option = pnp_clone_dependent_set(dev, i);
	189	if (!new_option)
	190	return;
3b73a223	191
1f32ca31 BH	192	set = pnp_option_set(new_option);
	193	while (new_option && pnp_option_set(new_option) == set) {
	194	if (new_option->type == IORESOURCE_IRQ) {
	195	irq = &new_option->u.irq;
	196	irq->flags \|= IORESOURCE_IRQ_OPTIONAL;
	197	}
	198	dbg_pnp_show_option(dev, new_option);
	199	new_option = list_entry(new_option->list.next,
	200	struct pnp_option, list);
	201	}
3b73a223	202
1f32ca31 BH	203	dev_info(&dev->dev, "added dependent option set %d (same as "
	204	"set %d except IRQ optional)\n", set, i);
	205	}
3b73a223 RH	206	}
3b73a223 RH	207
1f32ca31	208	static void quirk_ad1815_mpu_resources(struct pnp_dev *dev)
3b73a223	209	{
1f32ca31 BH	210	struct pnp_option *option;
	211	struct pnp_irq *irq = NULL;
	212	unsigned int independent_irqs = 0;
	213
	214	list_for_each_entry(option, &dev->options, list) {
	215	if (option->type == IORESOURCE_IRQ &&
	216	!pnp_option_is_dependent(option)) {
	217	independent_irqs++;
	218	irq = &option->u.irq;
	219	}
	220	}
3b73a223	221
1f32ca31	222	if (independent_irqs != 1)
3b73a223 RH	223	return;
3b73a223 RH	224
1f32ca31 BH	225	irq->flags \|= IORESOURCE_IRQ_OPTIONAL;
1f32ca31 BH	226	dev_info(&dev->dev, "made independent IRQ optional\n");
3b73a223	227	}
0509ad5e	228
0509ad5e BH	229	static void quirk_system_pci_resources(struct pnp_dev *dev)
	230	{
	231	struct pci_dev *pdev = NULL;
09cc9006	232	struct resource res, r;
0509ad5e BH	233	int i, j;
	234
	235	/*
	236	* Some BIOSes have PNP motherboard devices with resources that
	237	* partially overlap PCI BARs. The PNP system driver claims these
	238	* motherboard resources, which prevents the normal PCI driver from
	239	* requesting them later.
	240	*
	241	* This patch disables the PNP resources that conflict with PCI BARs
	242	* so they won't be claimed by the PNP system driver.
	243	*/
	244	for_each_pci_dev(pdev) {
09cc9006 MW	245	pci_dev_for_each_resource(pdev, r, i) {
09cc9006 MW	246	unsigned long type = resource_type(r);
999ed65a	247
09cc9006 MW	248	if (!(type == IORESOURCE_IO \|\| type == IORESOURCE_MEM) \|\|
09cc9006 MW	249	resource_size(r) == 0)
0509ad5e BH	250	continue;
0509ad5e BH	251
09cc9006	252	if (r->flags & IORESOURCE_UNSET)
f7834c09 BH	253	continue;
f7834c09 BH	254
95ab3669	255	for (j = 0;
999ed65a	256	(res = pnp_get_resource(dev, type, j)); j++) {
aee3ad81	257	if (res->start == 0 && res->end == 0)
0509ad5e BH	258	continue;
0509ad5e BH	259
0509ad5e BH	260	/*
	261	* If the PNP region doesn't overlap the PCI
	262	* region at all, there's no problem.
	263	*/
09cc9006	264	if (!resource_overlaps(res, r))
0509ad5e BH	265	continue;
	266
	267	/*
	268	* If the PNP region completely encloses (or is
	269	* at least as large as) the PCI region, that's
	270	* also OK. For example, this happens when the
	271	* PNP device describes a bridge with PCI
	272	* behind it.
	273	*/
09cc9006	274	if (res->start <= r->start && res->end >= r->end)
0509ad5e BH	275	continue;
	276
	277	/*
	278	* Otherwise, the PNP region overlaps part of
	279	* the PCI region, and that might prevent a PCI
	280	* driver from requesting its resources.
	281	*/
c7dabef8	282	dev_warn(&dev->dev,
09cc9006 MW	283	"disabling %pR because it overlaps %s BAR %d %pR\n",
09cc9006 MW	284	res, pci_name(pdev), i, r);
4b34fe15	285	res->flags \|= IORESOURCE_DISABLED;
0509ad5e BH	286	}
	287	}
	288	}
	289	}
	290
eb31aae8 BH	291	#ifdef CONFIG_AMD_NB
	292
	293	#include <asm/amd_nb.h>
	294
	295	static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
	296	{
	297	resource_size_t start, end;
	298	struct pnp_resource *pnp_res;
	299	struct resource *res;
	300	struct resource mmconfig_res, *mmconfig;
	301
	302	mmconfig = amd_get_mmconfig_range(&mmconfig_res);
	303	if (!mmconfig)
	304	return;
	305
	306	list_for_each_entry(pnp_res, &dev->resources, list) {
	307	res = &pnp_res->res;
	308	if (res->end < mmconfig->start \|\| res->start > mmconfig->end \|\|
	309	(res->start == mmconfig->start && res->end == mmconfig->end))
	310	continue;
	311
	312	dev_info(&dev->dev, FW_BUG
	313	"%pR covers only part of AMD MMCONFIG area %pR; adding more reservations\n",
	314	res, mmconfig);
	315	if (mmconfig->start < res->start) {
	316	start = mmconfig->start;
	317	end = res->start - 1;
	318	pnp_add_mem_resource(dev, start, end, 0);
	319	}
	320	if (mmconfig->end > res->end) {
	321	start = res->end + 1;
	322	end = mmconfig->end;
	323	pnp_add_mem_resource(dev, start, end, 0);
	324	}
	325	break;
	326	}
	327	}
	328	#endif
	329
b3413afb	330	#ifdef CONFIG_PCI
cb171f7a BH	331	/* Device IDs of parts that have 32KB MCH space */
	332	static const unsigned int mch_quirk_devices[] = {
	333	0x0154, /* Ivy Bridge */
ed1f0eee	334	0x0a04, /* Haswell-ULT */
cb171f7a	335	0x0c00, /* Haswell */
a77060f0	336	0x1604, /* Broadwell */
cb171f7a BH	337	};
	338
	339	static struct pci_dev *get_intel_host(void)
	340	{
	341	int i;
	342	struct pci_dev *host;
	343
	344	for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
	345	host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
	346	NULL);
	347	if (host)
	348	return host;
	349	}
	350	return NULL;
	351	}
	352
	353	static void quirk_intel_mch(struct pnp_dev *dev)
	354	{
	355	struct pci_dev *host;
	356	u32 addr_lo, addr_hi;
	357	struct pci_bus_region region;
	358	struct resource mch;
	359	struct pnp_resource *pnp_res;
	360	struct resource *res;
	361
	362	host = get_intel_host();
	363	if (!host)
	364	return;
	365
	366	/*
	367	* MCHBAR is not an architected PCI BAR, so MCH space is usually
	368	* reported as a PNP0C02 resource. The MCH space was originally
	369	* 16KB, but is 32KB in newer parts. Some BIOSes still report a
	370	* PNP0C02 resource that is only 16KB, which means the rest of the
	371	* MCH space is consumed but unreported.
	372	*/
	373
	374	/*
	375	* Read MCHBAR for Host Member Mapped Register Range Base
	376	* https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
	377	* Sec 3.1.12.
	378	*/
	379	pci_read_config_dword(host, 0x48, &addr_lo);
	380	region.start = addr_lo & ~0x7fff;
	381	pci_read_config_dword(host, 0x4c, &addr_hi);
	382	region.start \|= (u64) addr_hi << 32;
	383	region.end = region.start + 32*1024 - 1;
	384
	385	memset(&mch, 0, sizeof(mch));
	386	mch.flags = IORESOURCE_MEM;
	387	pcibios_bus_to_resource(host->bus, &mch, &region);
	388
	389	list_for_each_entry(pnp_res, &dev->resources, list) {
	390	res = &pnp_res->res;
	391	if (res->end < mch.start \|\| res->start > mch.end)
	392	continue; /* no overlap */
	393	if (res->start == mch.start && res->end == mch.end)
	394	continue; /* exact match */
	395
	396	dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
	397	res, pci_name(host), &mch);
	398	res->start = mch.start;
	399	res->end = mch.end;
	400	break;
401	}
402
403	pci_dev_put(host);
404	}
405	#endif
406
1da177e4 LT	407	/*
	408	* PnP Quirks
	409	* Cards or devices that need some tweaking due to incomplete resource info
	410	*/
	411
	412	static struct pnp_fixup pnp_fixups[] = {
	413	/* Soundblaster awe io port quirk */
9dd78466 BH	414	{"CTL0021", quirk_awe32_resources},
	415	{"CTL0022", quirk_awe32_resources},
	416	{"CTL0023", quirk_awe32_resources},
1da177e4	417	/* CMI 8330 interrupt and dma fix */
9dd78466	418	{"@X@0001", quirk_cmi8330_resources},
1da177e4	419	/* Soundblaster audio device io port range quirk */
9dd78466 BH	420	{"CTL0001", quirk_sb16audio_resources},
	421	{"CTL0031", quirk_sb16audio_resources},
	422	{"CTL0041", quirk_sb16audio_resources},
	423	{"CTL0042", quirk_sb16audio_resources},
	424	{"CTL0043", quirk_sb16audio_resources},
	425	{"CTL0044", quirk_sb16audio_resources},
	426	{"CTL0045", quirk_sb16audio_resources},
1f32ca31	427	/* Add IRQ-optional MPU options */
3b73a223	428	{"ADS7151", quirk_ad1815_mpu_resources},
1f32ca31 BH	429	{"ADS7181", quirk_add_irq_optional_dependent_sets},
1f32ca31 BH	430	{"AZT0002", quirk_add_irq_optional_dependent_sets},
3b73a223	431	/* PnP resources that might overlap PCI BARs */
0509ad5e BH	432	{"PNP0c01", quirk_system_pci_resources},
0509ad5e BH	433	{"PNP0c02", quirk_system_pci_resources},
eb31aae8 BH	434	#ifdef CONFIG_AMD_NB
eb31aae8 BH	435	{"PNP0c01", quirk_amd_mmconfig_area},
cb171f7a	436	#endif
b3413afb	437	#ifdef CONFIG_PCI
cb171f7a	438	{"PNP0c02", quirk_intel_mch},
eb31aae8	439	#endif
9dd78466	440	{""}
1da177e4 LT	441	};
	442
	443	void pnp_fixup_device(struct pnp_dev *dev)
	444	{
726a7a3d	445	struct pnp_fixup *f;
a05d0781	446
726a7a3d RH	447	for (f = pnp_fixups; *f->id; f++) {
	448	if (!compare_pnp_id(dev->id, f->id))
	449	continue;
d75f773c	450	pnp_dbg(&dev->dev, "%s: calling %pS\n", f->id,
668b21de	451	f->quirk_function);
726a7a3d	452	f->quirk_function(dev);
1da177e4 LT	453	}
1da177e4 LT	454	}