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9a58a333 SD |
1 | /* |
2 | * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism | |
3 | * | |
4 | * (C) Copyright 2008-2010 Intel Corporation | |
5 | * Author: Sreedhara DS (sreedhara.ds@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
c8440336 | 12 | * SCU running in ARC processor communicates with other entity running in IA |
9a58a333 SD |
13 | * core through IPC mechanism which in turn messaging between IA core ad SCU. |
14 | * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and | |
15 | * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with | |
16 | * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC) | |
17 | * along with other APIs. | |
18 | */ | |
19 | #include <linux/delay.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/init.h> | |
edbaa603 | 22 | #include <linux/device.h> |
9a58a333 SD |
23 | #include <linux/pm.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/interrupt.h> | |
209009b2 | 26 | #include <linux/sfi.h> |
7c52d551 | 27 | #include <linux/module.h> |
05454c26 | 28 | #include <asm/intel-mid.h> |
9a58a333 SD |
29 | #include <asm/intel_scu_ipc.h> |
30 | ||
31 | /* IPC defines the following message types */ | |
32 | #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ | |
33 | #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ | |
34 | #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */ | |
35 | #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ | |
36 | #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ | |
37 | ||
38 | /* Command id associated with message IPCMSG_PCNTRL */ | |
39 | #define IPC_CMD_PCNTRL_W 0 /* Register write */ | |
40 | #define IPC_CMD_PCNTRL_R 1 /* Register read */ | |
41 | #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ | |
42 | ||
9a58a333 SD |
43 | /* |
44 | * IPC register summary | |
45 | * | |
46 | * IPC register blocks are memory mapped at fixed address of 0xFF11C000 | |
47 | * To read or write information to the SCU, driver writes to IPC-1 memory | |
48 | * mapped registers (base address 0xFF11C000). The following is the IPC | |
49 | * mechanism | |
50 | * | |
51 | * 1. IA core cDMI interface claims this transaction and converts it to a | |
52 | * Transaction Layer Packet (TLP) message which is sent across the cDMI. | |
53 | * | |
54 | * 2. South Complex cDMI block receives this message and writes it to | |
55 | * the IPC-1 register block, causing an interrupt to the SCU | |
56 | * | |
57 | * 3. SCU firmware decodes this interrupt and IPC message and the appropriate | |
58 | * message handler is called within firmware. | |
59 | */ | |
60 | ||
51cd525d AV |
61 | #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ |
62 | #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ | |
ed12f295 | 63 | #define IPC_IOC 0x100 /* IPC command register IOC bit */ |
e97a1c98 KS |
64 | |
65 | enum { | |
66 | SCU_IPC_LINCROFT, | |
7f95afb3 KS |
67 | SCU_IPC_PENWELL, |
68 | SCU_IPC_CLOVERVIEW, | |
69 | SCU_IPC_TANGIER, | |
e97a1c98 KS |
70 | }; |
71 | ||
72 | /* intel scu ipc driver data*/ | |
73 | struct intel_scu_ipc_pdata_t { | |
74 | u32 ipc_base; | |
75 | u32 i2c_base; | |
76 | u32 ipc_len; | |
77 | u32 i2c_len; | |
ed12f295 | 78 | u8 irq_mode; |
e97a1c98 KS |
79 | }; |
80 | ||
81 | static struct intel_scu_ipc_pdata_t intel_scu_ipc_pdata[] = { | |
82 | [SCU_IPC_LINCROFT] = { | |
83 | .ipc_base = 0xff11c000, | |
84 | .i2c_base = 0xff12b000, | |
85 | .ipc_len = 0x100, | |
86 | .i2c_len = 0x10, | |
ed12f295 | 87 | .irq_mode = 0, |
e97a1c98 | 88 | }, |
7f95afb3 KS |
89 | [SCU_IPC_PENWELL] = { |
90 | .ipc_base = 0xff11c000, | |
91 | .i2c_base = 0xff12b000, | |
92 | .ipc_len = 0x100, | |
93 | .i2c_len = 0x10, | |
ed12f295 | 94 | .irq_mode = 1, |
7f95afb3 KS |
95 | }, |
96 | [SCU_IPC_CLOVERVIEW] = { | |
97 | .ipc_base = 0xff11c000, | |
98 | .i2c_base = 0xff12b000, | |
99 | .ipc_len = 0x100, | |
100 | .i2c_len = 0x10, | |
ed12f295 | 101 | .irq_mode = 1, |
7f95afb3 KS |
102 | }, |
103 | [SCU_IPC_TANGIER] = { | |
104 | .ipc_base = 0xff009000, | |
105 | .i2c_base = 0xff00d000, | |
106 | .ipc_len = 0x100, | |
107 | .i2c_len = 0x10, | |
ed12f295 | 108 | .irq_mode = 0, |
7f95afb3 | 109 | }, |
e97a1c98 | 110 | }; |
9a58a333 SD |
111 | |
112 | static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id); | |
113 | static void ipc_remove(struct pci_dev *pdev); | |
114 | ||
115 | struct intel_scu_ipc_dev { | |
116 | struct pci_dev *pdev; | |
117 | void __iomem *ipc_base; | |
118 | void __iomem *i2c_base; | |
ed12f295 KS |
119 | struct completion cmd_complete; |
120 | u8 irq_mode; | |
9a58a333 SD |
121 | }; |
122 | ||
123 | static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ | |
124 | ||
14d10f0a | 125 | static int platform; /* Platform type */ |
9a58a333 SD |
126 | |
127 | /* | |
128 | * IPC Read Buffer (Read Only): | |
129 | * 16 byte buffer for receiving data from SCU, if IPC command | |
130 | * processing results in response data | |
131 | */ | |
132 | #define IPC_READ_BUFFER 0x90 | |
133 | ||
134 | #define IPC_I2C_CNTRL_ADDR 0 | |
135 | #define I2C_DATA_ADDR 0x04 | |
136 | ||
137 | static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */ | |
138 | ||
139 | /* | |
140 | * Command Register (Write Only): | |
141 | * A write to this register results in an interrupt to the SCU core processor | |
142 | * Format: | |
143 | * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)| | |
144 | */ | |
145 | static inline void ipc_command(u32 cmd) /* Send ipc command */ | |
146 | { | |
ed12f295 KS |
147 | if (ipcdev.irq_mode) { |
148 | reinit_completion(&ipcdev.cmd_complete); | |
149 | writel(cmd | IPC_IOC, ipcdev.ipc_base); | |
150 | } | |
9a58a333 SD |
151 | writel(cmd, ipcdev.ipc_base); |
152 | } | |
153 | ||
154 | /* | |
155 | * IPC Write Buffer (Write Only): | |
156 | * 16-byte buffer for sending data associated with IPC command to | |
157 | * SCU. Size of the data is specified in the IPC_COMMAND_REG register | |
158 | */ | |
159 | static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */ | |
160 | { | |
161 | writel(data, ipcdev.ipc_base + 0x80 + offset); | |
162 | } | |
163 | ||
9a58a333 SD |
164 | /* |
165 | * Status Register (Read Only): | |
166 | * Driver will read this register to get the ready/busy status of the IPC | |
167 | * block and error status of the IPC command that was just processed by SCU | |
168 | * Format: | |
169 | * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)| | |
170 | */ | |
171 | ||
172 | static inline u8 ipc_read_status(void) | |
173 | { | |
174 | return __raw_readl(ipcdev.ipc_base + 0x04); | |
175 | } | |
176 | ||
177 | static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */ | |
178 | { | |
179 | return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
180 | } | |
181 | ||
e3359fd5 | 182 | static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */ |
9a58a333 SD |
183 | { |
184 | return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
185 | } | |
186 | ||
187 | static inline int busy_loop(void) /* Wait till scu status is busy */ | |
188 | { | |
189 | u32 status = 0; | |
190 | u32 loop_count = 0; | |
191 | ||
192 | status = ipc_read_status(); | |
193 | while (status & 1) { | |
194 | udelay(1); /* scu processing time is in few u secods */ | |
195 | status = ipc_read_status(); | |
196 | loop_count++; | |
197 | /* break if scu doesn't reset busy bit after huge retry */ | |
198 | if (loop_count > 100000) { | |
199 | dev_err(&ipcdev.pdev->dev, "IPC timed out"); | |
200 | return -ETIMEDOUT; | |
201 | } | |
202 | } | |
77e01d6d HL |
203 | if ((status >> 1) & 1) |
204 | return -EIO; | |
205 | ||
206 | return 0; | |
9a58a333 SD |
207 | } |
208 | ||
ed12f295 KS |
209 | /* Wait till ipc ioc interrupt is received or timeout in 3 HZ */ |
210 | static inline int ipc_wait_for_interrupt(void) | |
211 | { | |
212 | int status; | |
213 | ||
214 | if (!wait_for_completion_timeout(&ipcdev.cmd_complete, 3 * HZ)) { | |
215 | struct device *dev = &ipcdev.pdev->dev; | |
216 | dev_err(dev, "IPC timed out\n"); | |
217 | return -ETIMEDOUT; | |
218 | } | |
219 | ||
220 | status = ipc_read_status(); | |
221 | ||
222 | if ((status >> 1) & 1) | |
223 | return -EIO; | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | int intel_scu_ipc_check_status(void) | |
229 | { | |
230 | return ipcdev.irq_mode ? ipc_wait_for_interrupt() : busy_loop(); | |
231 | } | |
232 | ||
9a58a333 SD |
233 | /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ |
234 | static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) | |
235 | { | |
4707375f | 236 | int nc; |
9a58a333 | 237 | u32 offset = 0; |
ecb5646c | 238 | int err; |
e3359fd5 | 239 | u8 cbuf[IPC_WWBUF_SIZE] = { }; |
9a58a333 SD |
240 | u32 *wbuf = (u32 *)&cbuf; |
241 | ||
242 | mutex_lock(&ipclock); | |
e3359fd5 | 243 | |
ed6f2b4d AV |
244 | memset(cbuf, 0, sizeof(cbuf)); |
245 | ||
9a58a333 SD |
246 | if (ipcdev.pdev == NULL) { |
247 | mutex_unlock(&ipclock); | |
248 | return -ENODEV; | |
249 | } | |
250 | ||
4707375f AC |
251 | for (nc = 0; nc < count; nc++, offset += 2) { |
252 | cbuf[offset] = addr[nc]; | |
253 | cbuf[offset + 1] = addr[nc] >> 8; | |
254 | } | |
9a58a333 | 255 | |
4707375f AC |
256 | if (id == IPC_CMD_PCNTRL_R) { |
257 | for (nc = 0, offset = 0; nc < count; nc++, offset += 4) | |
258 | ipc_data_writel(wbuf[nc], offset); | |
259 | ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op); | |
260 | } else if (id == IPC_CMD_PCNTRL_W) { | |
261 | for (nc = 0; nc < count; nc++, offset += 1) | |
262 | cbuf[offset] = data[nc]; | |
263 | for (nc = 0, offset = 0; nc < count; nc++, offset += 4) | |
264 | ipc_data_writel(wbuf[nc], offset); | |
265 | ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op); | |
266 | } else if (id == IPC_CMD_PCNTRL_M) { | |
267 | cbuf[offset] = data[0]; | |
268 | cbuf[offset + 1] = data[1]; | |
269 | ipc_data_writel(wbuf[0], 0); /* Write wbuff */ | |
270 | ipc_command(4 << 16 | id << 12 | 0 << 8 | op); | |
e3359fd5 | 271 | } |
9a58a333 | 272 | |
ed12f295 | 273 | err = intel_scu_ipc_check_status(); |
c7094d1d | 274 | if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ |
9a58a333 | 275 | /* Workaround: values are read as 0 without memcpy_fromio */ |
e3359fd5 | 276 | memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16); |
4707375f AC |
277 | for (nc = 0; nc < count; nc++) |
278 | data[nc] = ipc_data_readb(nc); | |
9a58a333 SD |
279 | } |
280 | mutex_unlock(&ipclock); | |
281 | return err; | |
282 | } | |
283 | ||
284 | /** | |
285 | * intel_scu_ipc_ioread8 - read a word via the SCU | |
286 | * @addr: register on SCU | |
287 | * @data: return pointer for read byte | |
288 | * | |
289 | * Read a single register. Returns 0 on success or an error code. All | |
290 | * locking between SCU accesses is handled for the caller. | |
291 | * | |
292 | * This function may sleep. | |
293 | */ | |
294 | int intel_scu_ipc_ioread8(u16 addr, u8 *data) | |
295 | { | |
296 | return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
297 | } | |
298 | EXPORT_SYMBOL(intel_scu_ipc_ioread8); | |
299 | ||
300 | /** | |
301 | * intel_scu_ipc_ioread16 - read a word via the SCU | |
302 | * @addr: register on SCU | |
303 | * @data: return pointer for read word | |
304 | * | |
305 | * Read a register pair. Returns 0 on success or an error code. All | |
306 | * locking between SCU accesses is handled for the caller. | |
307 | * | |
308 | * This function may sleep. | |
309 | */ | |
310 | int intel_scu_ipc_ioread16(u16 addr, u16 *data) | |
311 | { | |
312 | u16 x[2] = {addr, addr + 1 }; | |
313 | return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
314 | } | |
315 | EXPORT_SYMBOL(intel_scu_ipc_ioread16); | |
316 | ||
317 | /** | |
318 | * intel_scu_ipc_ioread32 - read a dword via the SCU | |
319 | * @addr: register on SCU | |
320 | * @data: return pointer for read dword | |
321 | * | |
322 | * Read four registers. Returns 0 on success or an error code. All | |
323 | * locking between SCU accesses is handled for the caller. | |
324 | * | |
325 | * This function may sleep. | |
326 | */ | |
327 | int intel_scu_ipc_ioread32(u16 addr, u32 *data) | |
328 | { | |
329 | u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; | |
330 | return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
331 | } | |
332 | EXPORT_SYMBOL(intel_scu_ipc_ioread32); | |
333 | ||
334 | /** | |
335 | * intel_scu_ipc_iowrite8 - write a byte via the SCU | |
336 | * @addr: register on SCU | |
337 | * @data: byte to write | |
338 | * | |
339 | * Write a single register. Returns 0 on success or an error code. All | |
340 | * locking between SCU accesses is handled for the caller. | |
341 | * | |
342 | * This function may sleep. | |
343 | */ | |
344 | int intel_scu_ipc_iowrite8(u16 addr, u8 data) | |
345 | { | |
346 | return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
347 | } | |
348 | EXPORT_SYMBOL(intel_scu_ipc_iowrite8); | |
349 | ||
350 | /** | |
351 | * intel_scu_ipc_iowrite16 - write a word via the SCU | |
352 | * @addr: register on SCU | |
353 | * @data: word to write | |
354 | * | |
355 | * Write two registers. Returns 0 on success or an error code. All | |
356 | * locking between SCU accesses is handled for the caller. | |
357 | * | |
358 | * This function may sleep. | |
359 | */ | |
360 | int intel_scu_ipc_iowrite16(u16 addr, u16 data) | |
361 | { | |
362 | u16 x[2] = {addr, addr + 1 }; | |
363 | return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
364 | } | |
365 | EXPORT_SYMBOL(intel_scu_ipc_iowrite16); | |
366 | ||
367 | /** | |
368 | * intel_scu_ipc_iowrite32 - write a dword via the SCU | |
369 | * @addr: register on SCU | |
370 | * @data: dword to write | |
371 | * | |
372 | * Write four registers. Returns 0 on success or an error code. All | |
373 | * locking between SCU accesses is handled for the caller. | |
374 | * | |
375 | * This function may sleep. | |
376 | */ | |
377 | int intel_scu_ipc_iowrite32(u16 addr, u32 data) | |
378 | { | |
379 | u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; | |
380 | return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
381 | } | |
382 | EXPORT_SYMBOL(intel_scu_ipc_iowrite32); | |
383 | ||
384 | /** | |
385 | * intel_scu_ipc_readvv - read a set of registers | |
386 | * @addr: register list | |
387 | * @data: bytes to return | |
388 | * @len: length of array | |
389 | * | |
390 | * Read registers. Returns 0 on success or an error code. All | |
391 | * locking between SCU accesses is handled for the caller. | |
392 | * | |
393 | * The largest array length permitted by the hardware is 5 items. | |
394 | * | |
395 | * This function may sleep. | |
396 | */ | |
397 | int intel_scu_ipc_readv(u16 *addr, u8 *data, int len) | |
398 | { | |
399 | return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); | |
400 | } | |
401 | EXPORT_SYMBOL(intel_scu_ipc_readv); | |
402 | ||
403 | /** | |
404 | * intel_scu_ipc_writev - write a set of registers | |
405 | * @addr: register list | |
406 | * @data: bytes to write | |
407 | * @len: length of array | |
408 | * | |
409 | * Write registers. Returns 0 on success or an error code. All | |
410 | * locking between SCU accesses is handled for the caller. | |
411 | * | |
412 | * The largest array length permitted by the hardware is 5 items. | |
413 | * | |
414 | * This function may sleep. | |
415 | * | |
416 | */ | |
417 | int intel_scu_ipc_writev(u16 *addr, u8 *data, int len) | |
418 | { | |
419 | return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); | |
420 | } | |
421 | EXPORT_SYMBOL(intel_scu_ipc_writev); | |
422 | ||
423 | ||
424 | /** | |
425 | * intel_scu_ipc_update_register - r/m/w a register | |
426 | * @addr: register address | |
427 | * @bits: bits to update | |
428 | * @mask: mask of bits to update | |
429 | * | |
430 | * Read-modify-write power control unit register. The first data argument | |
431 | * must be register value and second is mask value | |
432 | * mask is a bitmap that indicates which bits to update. | |
433 | * 0 = masked. Don't modify this bit, 1 = modify this bit. | |
434 | * returns 0 on success or an error code. | |
435 | * | |
436 | * This function may sleep. Locking between SCU accesses is handled | |
437 | * for the caller. | |
438 | */ | |
439 | int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) | |
440 | { | |
441 | u8 data[2] = { bits, mask }; | |
442 | return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M); | |
443 | } | |
444 | EXPORT_SYMBOL(intel_scu_ipc_update_register); | |
445 | ||
9a58a333 SD |
446 | /** |
447 | * intel_scu_ipc_simple_command - send a simple command | |
448 | * @cmd: command | |
449 | * @sub: sub type | |
450 | * | |
451 | * Issue a simple command to the SCU. Do not use this interface if | |
452 | * you must then access data as any data values may be overwritten | |
453 | * by another SCU access by the time this function returns. | |
454 | * | |
455 | * This function may sleep. Locking for SCU accesses is handled for | |
456 | * the caller. | |
457 | */ | |
458 | int intel_scu_ipc_simple_command(int cmd, int sub) | |
459 | { | |
ecb5646c | 460 | int err; |
9a58a333 SD |
461 | |
462 | mutex_lock(&ipclock); | |
463 | if (ipcdev.pdev == NULL) { | |
464 | mutex_unlock(&ipclock); | |
465 | return -ENODEV; | |
466 | } | |
b4fd4f89 | 467 | ipc_command(sub << 12 | cmd); |
ed12f295 | 468 | err = intel_scu_ipc_check_status(); |
9a58a333 SD |
469 | mutex_unlock(&ipclock); |
470 | return err; | |
471 | } | |
472 | EXPORT_SYMBOL(intel_scu_ipc_simple_command); | |
473 | ||
474 | /** | |
475 | * intel_scu_ipc_command - command with data | |
476 | * @cmd: command | |
477 | * @sub: sub type | |
478 | * @in: input data | |
b4fd4f89 | 479 | * @inlen: input length in dwords |
9a58a333 | 480 | * @out: output data |
b4fd4f89 | 481 | * @outlein: output length in dwords |
9a58a333 SD |
482 | * |
483 | * Issue a command to the SCU which involves data transfers. Do the | |
484 | * data copies under the lock but leave it for the caller to interpret | |
485 | */ | |
486 | ||
487 | int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, | |
488 | u32 *out, int outlen) | |
489 | { | |
ecb5646c | 490 | int i, err; |
9a58a333 SD |
491 | |
492 | mutex_lock(&ipclock); | |
493 | if (ipcdev.pdev == NULL) { | |
494 | mutex_unlock(&ipclock); | |
495 | return -ENODEV; | |
496 | } | |
497 | ||
498 | for (i = 0; i < inlen; i++) | |
499 | ipc_data_writel(*in++, 4 * i); | |
500 | ||
5aa06930 | 501 | ipc_command((inlen << 16) | (sub << 12) | cmd); |
ed12f295 | 502 | err = intel_scu_ipc_check_status(); |
9a58a333 | 503 | |
c7094d1d KS |
504 | if (!err) { |
505 | for (i = 0; i < outlen; i++) | |
506 | *out++ = ipc_data_readl(4 * i); | |
507 | } | |
9a58a333 SD |
508 | |
509 | mutex_unlock(&ipclock); | |
510 | return err; | |
511 | } | |
512 | EXPORT_SYMBOL(intel_scu_ipc_command); | |
513 | ||
514 | /*I2C commands */ | |
515 | #define IPC_I2C_WRITE 1 /* I2C Write command */ | |
516 | #define IPC_I2C_READ 2 /* I2C Read command */ | |
517 | ||
518 | /** | |
519 | * intel_scu_ipc_i2c_cntrl - I2C read/write operations | |
520 | * @addr: I2C address + command bits | |
521 | * @data: data to read/write | |
522 | * | |
523 | * Perform an an I2C read/write operation via the SCU. All locking is | |
524 | * handled for the caller. This function may sleep. | |
525 | * | |
526 | * Returns an error code or 0 on success. | |
527 | * | |
528 | * This has to be in the IPC driver for the locking. | |
529 | */ | |
530 | int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data) | |
531 | { | |
532 | u32 cmd = 0; | |
533 | ||
534 | mutex_lock(&ipclock); | |
b4fd4f89 SD |
535 | if (ipcdev.pdev == NULL) { |
536 | mutex_unlock(&ipclock); | |
537 | return -ENODEV; | |
538 | } | |
9a58a333 SD |
539 | cmd = (addr >> 24) & 0xFF; |
540 | if (cmd == IPC_I2C_READ) { | |
541 | writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); | |
542 | /* Write not getting updated without delay */ | |
543 | mdelay(1); | |
544 | *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR); | |
545 | } else if (cmd == IPC_I2C_WRITE) { | |
32e2f63b | 546 | writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR); |
9a58a333 SD |
547 | mdelay(1); |
548 | writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); | |
549 | } else { | |
550 | dev_err(&ipcdev.pdev->dev, | |
551 | "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd); | |
552 | ||
553 | mutex_unlock(&ipclock); | |
5369c02d | 554 | return -EIO; |
9a58a333 SD |
555 | } |
556 | mutex_unlock(&ipclock); | |
557 | return 0; | |
558 | } | |
559 | EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl); | |
560 | ||
9a58a333 SD |
561 | /* |
562 | * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1 | |
563 | * When ioc bit is set to 1, caller api must wait for interrupt handler called | |
564 | * which in turn unlocks the caller api. Currently this is not used | |
565 | * | |
566 | * This is edge triggered so we need take no action to clear anything | |
567 | */ | |
568 | static irqreturn_t ioc(int irq, void *dev_id) | |
569 | { | |
ed12f295 KS |
570 | if (ipcdev.irq_mode) |
571 | complete(&ipcdev.cmd_complete); | |
572 | ||
9a58a333 SD |
573 | return IRQ_HANDLED; |
574 | } | |
575 | ||
576 | /** | |
577 | * ipc_probe - probe an Intel SCU IPC | |
578 | * @dev: the PCI device matching | |
579 | * @id: entry in the match table | |
580 | * | |
581 | * Enable and install an intel SCU IPC. This appears in the PCI space | |
582 | * but uses some hard coded addresses as well. | |
583 | */ | |
584 | static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
585 | { | |
e97a1c98 KS |
586 | int err, pid; |
587 | struct intel_scu_ipc_pdata_t *pdata; | |
9a58a333 SD |
588 | resource_size_t pci_resource; |
589 | ||
590 | if (ipcdev.pdev) /* We support only one SCU */ | |
591 | return -EBUSY; | |
592 | ||
e97a1c98 KS |
593 | pid = id->driver_data; |
594 | pdata = &intel_scu_ipc_pdata[pid]; | |
595 | ||
9a58a333 | 596 | ipcdev.pdev = pci_dev_get(dev); |
ed12f295 | 597 | ipcdev.irq_mode = pdata->irq_mode; |
9a58a333 SD |
598 | |
599 | err = pci_enable_device(dev); | |
600 | if (err) | |
601 | return err; | |
602 | ||
603 | err = pci_request_regions(dev, "intel_scu_ipc"); | |
604 | if (err) | |
605 | return err; | |
606 | ||
607 | pci_resource = pci_resource_start(dev, 0); | |
608 | if (!pci_resource) | |
609 | return -ENOMEM; | |
610 | ||
ed12f295 KS |
611 | init_completion(&ipcdev.cmd_complete); |
612 | ||
9a58a333 SD |
613 | if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev)) |
614 | return -EBUSY; | |
615 | ||
e97a1c98 | 616 | ipcdev.ipc_base = ioremap_nocache(pdata->ipc_base, pdata->ipc_len); |
9a58a333 SD |
617 | if (!ipcdev.ipc_base) |
618 | return -ENOMEM; | |
619 | ||
e97a1c98 | 620 | ipcdev.i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len); |
9a58a333 SD |
621 | if (!ipcdev.i2c_base) { |
622 | iounmap(ipcdev.ipc_base); | |
623 | return -ENOMEM; | |
624 | } | |
1da4b1c6 FT |
625 | |
626 | intel_scu_devices_create(); | |
627 | ||
9a58a333 SD |
628 | return 0; |
629 | } | |
630 | ||
631 | /** | |
632 | * ipc_remove - remove a bound IPC device | |
633 | * @pdev: PCI device | |
634 | * | |
635 | * In practice the SCU is not removable but this function is also | |
636 | * called for each device on a module unload or cleanup which is the | |
637 | * path that will get used. | |
638 | * | |
639 | * Free up the mappings and release the PCI resources | |
640 | */ | |
641 | static void ipc_remove(struct pci_dev *pdev) | |
642 | { | |
643 | free_irq(pdev->irq, &ipcdev); | |
644 | pci_release_regions(pdev); | |
645 | pci_dev_put(ipcdev.pdev); | |
646 | iounmap(ipcdev.ipc_base); | |
647 | iounmap(ipcdev.i2c_base); | |
648 | ipcdev.pdev = NULL; | |
1da4b1c6 | 649 | intel_scu_devices_destroy(); |
9a58a333 SD |
650 | } |
651 | ||
daa77696 | 652 | static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { |
e97a1c98 | 653 | {PCI_VDEVICE(INTEL, 0x082a), SCU_IPC_LINCROFT}, |
7f95afb3 KS |
654 | {PCI_VDEVICE(INTEL, 0x080e), SCU_IPC_PENWELL}, |
655 | {PCI_VDEVICE(INTEL, 0x08ea), SCU_IPC_CLOVERVIEW}, | |
656 | {PCI_VDEVICE(INTEL, 0x11a0), SCU_IPC_TANGIER}, | |
9a58a333 SD |
657 | { 0,} |
658 | }; | |
659 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
660 | ||
661 | static struct pci_driver ipc_driver = { | |
662 | .name = "intel_scu_ipc", | |
663 | .id_table = pci_ids, | |
664 | .probe = ipc_probe, | |
665 | .remove = ipc_remove, | |
666 | }; | |
667 | ||
668 | ||
669 | static int __init intel_scu_ipc_init(void) | |
670 | { | |
712b6aa8 | 671 | platform = intel_mid_identify_cpu(); |
9dd3adeb AC |
672 | if (platform == 0) |
673 | return -ENODEV; | |
9a58a333 SD |
674 | return pci_register_driver(&ipc_driver); |
675 | } | |
676 | ||
677 | static void __exit intel_scu_ipc_exit(void) | |
678 | { | |
679 | pci_unregister_driver(&ipc_driver); | |
680 | } | |
681 | ||
682 | MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>"); | |
683 | MODULE_DESCRIPTION("Intel SCU IPC driver"); | |
684 | MODULE_LICENSE("GPL"); | |
685 | ||
686 | module_init(intel_scu_ipc_init); | |
687 | module_exit(intel_scu_ipc_exit); |