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ad51f287 | 1 | // SPDX-License-Identifier: GPL-2.0 |
0a8b8353 | 2 | /* |
ad51f287 | 3 | * Driver for the Intel PMC IPC mechanism |
0a8b8353 | 4 | * |
5 | * (C) Copyright 2014-2015 Intel Corporation | |
6 | * | |
ad51f287 | 7 | * This driver is based on Intel SCU IPC driver(intel_scu_ipc.c) by |
0a8b8353 | 8 | * Sreedhara DS <sreedhara.ds@intel.com> |
9 | * | |
0a8b8353 | 10 | * PMC running in ARC processor communicates with other entity running in IA |
11 | * core through IPC mechanism which in turn messaging between IA core ad PMC. | |
12 | */ | |
13 | ||
90881772 AS |
14 | #include <linux/acpi.h> |
15 | #include <linux/atomic.h> | |
16 | #include <linux/bitops.h> | |
0a8b8353 | 17 | #include <linux/delay.h> |
0a8b8353 | 18 | #include <linux/device.h> |
90881772 AS |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io-64-nonatomic-lo-hi.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/notifier.h> | |
0a8b8353 | 25 | #include <linux/pci.h> |
26 | #include <linux/platform_device.h> | |
90881772 | 27 | #include <linux/pm.h> |
0a8b8353 | 28 | #include <linux/pm_qos.h> |
0a8b8353 | 29 | #include <linux/sched.h> |
6687aeb9 | 30 | #include <linux/spinlock.h> |
90881772 | 31 | #include <linux/suspend.h> |
76062b4a | 32 | |
0a8b8353 | 33 | #include <asm/intel_pmc_ipc.h> |
76062b4a | 34 | |
420b54de | 35 | #include <linux/platform_data/itco_wdt.h> |
0a8b8353 | 36 | |
37 | /* | |
38 | * IPC registers | |
39 | * The IA write to IPC_CMD command register triggers an interrupt to the ARC, | |
40 | * The ARC handles the interrupt and services it, writing optional data to | |
41 | * the IPC1 registers, updates the IPC_STS response register with the status. | |
42 | */ | |
43 | #define IPC_CMD 0x0 | |
44 | #define IPC_CMD_MSI 0x100 | |
45 | #define IPC_CMD_SIZE 16 | |
46 | #define IPC_CMD_SUBCMD 12 | |
47 | #define IPC_STATUS 0x04 | |
48 | #define IPC_STATUS_IRQ 0x4 | |
49 | #define IPC_STATUS_ERR 0x2 | |
50 | #define IPC_STATUS_BUSY 0x1 | |
51 | #define IPC_SPTR 0x08 | |
52 | #define IPC_DPTR 0x0C | |
53 | #define IPC_WRITE_BUFFER 0x80 | |
54 | #define IPC_READ_BUFFER 0x90 | |
55 | ||
76062b4a SM |
56 | /* Residency with clock rate at 19.2MHz to usecs */ |
57 | #define S0IX_RESIDENCY_IN_USECS(d, s) \ | |
58 | ({ \ | |
59 | u64 result = 10ull * ((d) + (s)); \ | |
60 | do_div(result, 192); \ | |
61 | result; \ | |
62 | }) | |
63 | ||
0a8b8353 | 64 | /* |
65 | * 16-byte buffer for sending data associated with IPC command. | |
66 | */ | |
67 | #define IPC_DATA_BUFFER_SIZE 16 | |
68 | ||
69 | #define IPC_LOOP_CNT 3000000 | |
70 | #define IPC_MAX_SEC 3 | |
71 | ||
72 | #define IPC_TRIGGER_MODE_IRQ true | |
73 | ||
74 | /* exported resources from IFWI */ | |
75 | #define PLAT_RESOURCE_IPC_INDEX 0 | |
76 | #define PLAT_RESOURCE_IPC_SIZE 0x1000 | |
e6749c89 | 77 | #define PLAT_RESOURCE_GCR_OFFSET 0x1000 |
76062b4a | 78 | #define PLAT_RESOURCE_GCR_SIZE 0x1000 |
8cc7fb4a QZ |
79 | #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 |
80 | #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 | |
48c19170 | 81 | #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3 |
8cc7fb4a QZ |
82 | #define PLAT_RESOURCE_ISP_DATA_INDEX 4 |
83 | #define PLAT_RESOURCE_ISP_IFACE_INDEX 5 | |
84 | #define PLAT_RESOURCE_GTD_DATA_INDEX 6 | |
85 | #define PLAT_RESOURCE_GTD_IFACE_INDEX 7 | |
0a8b8353 | 86 | #define PLAT_RESOURCE_ACPI_IO_INDEX 0 |
87 | ||
88 | /* | |
89 | * BIOS does not create an ACPI device for each PMC function, | |
90 | * but exports multiple resources from one ACPI device(IPC) for | |
91 | * multiple functions. This driver is responsible to create a | |
92 | * platform device and to export resources for those functions. | |
93 | */ | |
94 | #define TCO_DEVICE_NAME "iTCO_wdt" | |
334da2d6 | 95 | #define SMI_EN_OFFSET 0x40 |
0a8b8353 | 96 | #define SMI_EN_SIZE 4 |
97 | #define TCO_BASE_OFFSET 0x60 | |
98 | #define TCO_REGS_SIZE 16 | |
99 | #define PUNIT_DEVICE_NAME "intel_punit_ipc" | |
48c19170 SKC |
100 | #define TELEMETRY_DEVICE_NAME "intel_telemetry" |
101 | #define TELEM_SSRAM_SIZE 240 | |
102 | #define TELEM_PMC_SSRAM_OFFSET 0x1B00 | |
103 | #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00 | |
334da2d6 YJ |
104 | #define TCO_PMC_OFFSET 0x8 |
105 | #define TCO_PMC_SIZE 0x4 | |
0a8b8353 | 106 | |
9d855d46 KS |
107 | /* PMC register bit definitions */ |
108 | ||
109 | /* PMC_CFG_REG bit masks */ | |
110 | #define PMC_CFG_NO_REBOOT_MASK (1 << 4) | |
111 | #define PMC_CFG_NO_REBOOT_EN (1 << 4) | |
112 | #define PMC_CFG_NO_REBOOT_DIS (0 << 4) | |
113 | ||
0a8b8353 | 114 | static struct intel_pmc_ipc_dev { |
115 | struct device *dev; | |
116 | void __iomem *ipc_base; | |
117 | bool irq_mode; | |
118 | int irq; | |
119 | int cmd; | |
120 | struct completion cmd_complete; | |
121 | ||
122 | /* The following PMC BARs share the same ACPI device with the IPC */ | |
b78fb51b | 123 | resource_size_t acpi_io_base; |
0a8b8353 | 124 | int acpi_io_size; |
125 | struct platform_device *tco_dev; | |
126 | ||
127 | /* gcr */ | |
49670206 | 128 | void __iomem *gcr_mem_base; |
76062b4a | 129 | bool has_gcr_regs; |
6687aeb9 | 130 | spinlock_t gcr_lock; |
0a8b8353 | 131 | |
132 | /* punit */ | |
0a8b8353 | 133 | struct platform_device *punit_dev; |
48c19170 SKC |
134 | |
135 | /* Telemetry */ | |
136 | resource_size_t telem_pmc_ssram_base; | |
137 | resource_size_t telem_punit_ssram_base; | |
138 | int telem_pmc_ssram_size; | |
139 | int telem_punit_ssram_size; | |
140 | u8 telem_res_inval; | |
141 | struct platform_device *telemetry_dev; | |
0a8b8353 | 142 | } ipcdev; |
143 | ||
144 | static char *ipc_err_sources[] = { | |
145 | [IPC_ERR_NONE] = | |
146 | "no error", | |
147 | [IPC_ERR_CMD_NOT_SUPPORTED] = | |
148 | "command not supported", | |
149 | [IPC_ERR_CMD_NOT_SERVICED] = | |
150 | "command not serviced", | |
151 | [IPC_ERR_UNABLE_TO_SERVICE] = | |
152 | "unable to service", | |
153 | [IPC_ERR_CMD_INVALID] = | |
154 | "command invalid", | |
155 | [IPC_ERR_CMD_FAILED] = | |
156 | "command failed", | |
157 | [IPC_ERR_EMSECURITY] = | |
158 | "Invalid Battery", | |
159 | [IPC_ERR_UNSIGNEDKERNEL] = | |
160 | "Unsigned kernel", | |
161 | }; | |
162 | ||
163 | /* Prevent concurrent calls to the PMC */ | |
164 | static DEFINE_MUTEX(ipclock); | |
165 | ||
166 | static inline void ipc_send_command(u32 cmd) | |
167 | { | |
168 | ipcdev.cmd = cmd; | |
169 | if (ipcdev.irq_mode) { | |
170 | reinit_completion(&ipcdev.cmd_complete); | |
171 | cmd |= IPC_CMD_MSI; | |
172 | } | |
173 | writel(cmd, ipcdev.ipc_base + IPC_CMD); | |
174 | } | |
175 | ||
176 | static inline u32 ipc_read_status(void) | |
177 | { | |
178 | return readl(ipcdev.ipc_base + IPC_STATUS); | |
179 | } | |
180 | ||
181 | static inline void ipc_data_writel(u32 data, u32 offset) | |
182 | { | |
183 | writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset); | |
184 | } | |
185 | ||
6bee1af9 | 186 | static inline u8 __maybe_unused ipc_data_readb(u32 offset) |
0a8b8353 | 187 | { |
188 | return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
189 | } | |
190 | ||
191 | static inline u32 ipc_data_readl(u32 offset) | |
192 | { | |
193 | return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); | |
194 | } | |
195 | ||
76062b4a SM |
196 | static inline u64 gcr_data_readq(u32 offset) |
197 | { | |
62a7b9c8 | 198 | return readq(ipcdev.gcr_mem_base + offset); |
76062b4a SM |
199 | } |
200 | ||
49670206 KS |
201 | static inline int is_gcr_valid(u32 offset) |
202 | { | |
203 | if (!ipcdev.has_gcr_regs) | |
204 | return -EACCES; | |
205 | ||
206 | if (offset > PLAT_RESOURCE_GCR_SIZE) | |
207 | return -EINVAL; | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | /** | |
9c916549 | 213 | * intel_pmc_gcr_read() - Read a 32-bit PMC GCR register |
49670206 KS |
214 | * @offset: offset of GCR register from GCR address base |
215 | * @data: data pointer for storing the register output | |
216 | * | |
9c916549 | 217 | * Reads the 32-bit PMC GCR register at given offset. |
49670206 KS |
218 | * |
219 | * Return: negative value on error or 0 on success. | |
220 | */ | |
221 | int intel_pmc_gcr_read(u32 offset, u32 *data) | |
222 | { | |
223 | int ret; | |
224 | ||
6687aeb9 | 225 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
226 | |
227 | ret = is_gcr_valid(offset); | |
228 | if (ret < 0) { | |
6687aeb9 | 229 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
230 | return ret; |
231 | } | |
232 | ||
233 | *data = readl(ipcdev.gcr_mem_base + offset); | |
234 | ||
6687aeb9 | 235 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
236 | |
237 | return 0; | |
238 | } | |
239 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_read); | |
240 | ||
9c916549 CS |
241 | /** |
242 | * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register | |
243 | * @offset: offset of GCR register from GCR address base | |
244 | * @data: data pointer for storing the register output | |
245 | * | |
246 | * Reads the 64-bit PMC GCR register at given offset. | |
247 | * | |
248 | * Return: negative value on error or 0 on success. | |
249 | */ | |
250 | int intel_pmc_gcr_read64(u32 offset, u64 *data) | |
251 | { | |
252 | int ret; | |
253 | ||
254 | spin_lock(&ipcdev.gcr_lock); | |
255 | ||
256 | ret = is_gcr_valid(offset); | |
257 | if (ret < 0) { | |
258 | spin_unlock(&ipcdev.gcr_lock); | |
259 | return ret; | |
260 | } | |
261 | ||
262 | *data = readq(ipcdev.gcr_mem_base + offset); | |
263 | ||
264 | spin_unlock(&ipcdev.gcr_lock); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64); | |
269 | ||
49670206 KS |
270 | /** |
271 | * intel_pmc_gcr_write() - Write PMC GCR register | |
272 | * @offset: offset of GCR register from GCR address base | |
273 | * @data: register update value | |
274 | * | |
275 | * Writes the PMC GCR register of given offset with given | |
276 | * value. | |
277 | * | |
278 | * Return: negative value on error or 0 on success. | |
279 | */ | |
280 | int intel_pmc_gcr_write(u32 offset, u32 data) | |
281 | { | |
282 | int ret; | |
283 | ||
6687aeb9 | 284 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
285 | |
286 | ret = is_gcr_valid(offset); | |
287 | if (ret < 0) { | |
6687aeb9 | 288 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
289 | return ret; |
290 | } | |
291 | ||
292 | writel(data, ipcdev.gcr_mem_base + offset); | |
293 | ||
6687aeb9 | 294 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
295 | |
296 | return 0; | |
297 | } | |
298 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_write); | |
299 | ||
300 | /** | |
301 | * intel_pmc_gcr_update() - Update PMC GCR register bits | |
302 | * @offset: offset of GCR register from GCR address base | |
303 | * @mask: bit mask for update operation | |
304 | * @val: update value | |
305 | * | |
306 | * Updates the bits of given GCR register as specified by | |
307 | * @mask and @val. | |
308 | * | |
309 | * Return: negative value on error or 0 on success. | |
310 | */ | |
311 | int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) | |
312 | { | |
313 | u32 new_val; | |
314 | int ret = 0; | |
315 | ||
6687aeb9 | 316 | spin_lock(&ipcdev.gcr_lock); |
49670206 KS |
317 | |
318 | ret = is_gcr_valid(offset); | |
319 | if (ret < 0) | |
320 | goto gcr_ipc_unlock; | |
321 | ||
322 | new_val = readl(ipcdev.gcr_mem_base + offset); | |
323 | ||
324 | new_val &= ~mask; | |
325 | new_val |= val & mask; | |
326 | ||
327 | writel(new_val, ipcdev.gcr_mem_base + offset); | |
328 | ||
329 | new_val = readl(ipcdev.gcr_mem_base + offset); | |
330 | ||
331 | /* check whether the bit update is successful */ | |
332 | if ((new_val & mask) != (val & mask)) { | |
333 | ret = -EIO; | |
334 | goto gcr_ipc_unlock; | |
335 | } | |
336 | ||
337 | gcr_ipc_unlock: | |
6687aeb9 | 338 | spin_unlock(&ipcdev.gcr_lock); |
49670206 KS |
339 | return ret; |
340 | } | |
341 | EXPORT_SYMBOL_GPL(intel_pmc_gcr_update); | |
342 | ||
9d855d46 KS |
343 | static int update_no_reboot_bit(void *priv, bool set) |
344 | { | |
345 | u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS; | |
346 | ||
347 | return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG, | |
348 | PMC_CFG_NO_REBOOT_MASK, value); | |
349 | } | |
350 | ||
0a8b8353 | 351 | static int intel_pmc_ipc_check_status(void) |
352 | { | |
353 | int status; | |
354 | int ret = 0; | |
355 | ||
356 | if (ipcdev.irq_mode) { | |
357 | if (0 == wait_for_completion_timeout( | |
358 | &ipcdev.cmd_complete, IPC_MAX_SEC * HZ)) | |
359 | ret = -ETIMEDOUT; | |
360 | } else { | |
361 | int loop_count = IPC_LOOP_CNT; | |
362 | ||
363 | while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count) | |
364 | udelay(1); | |
365 | if (loop_count == 0) | |
366 | ret = -ETIMEDOUT; | |
367 | } | |
368 | ||
369 | status = ipc_read_status(); | |
370 | if (ret == -ETIMEDOUT) { | |
371 | dev_err(ipcdev.dev, | |
372 | "IPC timed out, TS=0x%x, CMD=0x%x\n", | |
373 | status, ipcdev.cmd); | |
374 | return ret; | |
375 | } | |
376 | ||
377 | if (status & IPC_STATUS_ERR) { | |
378 | int i; | |
379 | ||
380 | ret = -EIO; | |
381 | i = (status >> IPC_CMD_SIZE) & 0xFF; | |
382 | if (i < ARRAY_SIZE(ipc_err_sources)) | |
383 | dev_err(ipcdev.dev, | |
384 | "IPC failed: %s, STS=0x%x, CMD=0x%x\n", | |
385 | ipc_err_sources[i], status, ipcdev.cmd); | |
386 | else | |
387 | dev_err(ipcdev.dev, | |
388 | "IPC failed: unknown, STS=0x%x, CMD=0x%x\n", | |
389 | status, ipcdev.cmd); | |
390 | if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY)) | |
391 | ret = -EACCES; | |
392 | } | |
393 | ||
394 | return ret; | |
395 | } | |
396 | ||
02941007 | 397 | /** |
398 | * intel_pmc_ipc_simple_command() - Simple IPC command | |
399 | * @cmd: IPC command code. | |
400 | * @sub: IPC command sub type. | |
401 | * | |
402 | * Send a simple IPC command to PMC when don't need to specify | |
403 | * input/output data and source/dest pointers. | |
404 | * | |
405 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 406 | */ |
407 | int intel_pmc_ipc_simple_command(int cmd, int sub) | |
408 | { | |
409 | int ret; | |
410 | ||
411 | mutex_lock(&ipclock); | |
412 | if (ipcdev.dev == NULL) { | |
413 | mutex_unlock(&ipclock); | |
414 | return -ENODEV; | |
415 | } | |
416 | ipc_send_command(sub << IPC_CMD_SUBCMD | cmd); | |
417 | ret = intel_pmc_ipc_check_status(); | |
418 | mutex_unlock(&ipclock); | |
419 | ||
420 | return ret; | |
421 | } | |
422 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command); | |
423 | ||
02941007 | 424 | /** |
425 | * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers | |
426 | * @cmd: IPC command code. | |
427 | * @sub: IPC command sub type. | |
428 | * @in: input data of this IPC command. | |
429 | * @inlen: input data length in bytes. | |
430 | * @out: output data of this IPC command. | |
431 | * @outlen: output data length in dwords. | |
432 | * @sptr: data writing to SPTR register. | |
433 | * @dptr: data writing to DPTR register. | |
434 | * | |
435 | * Send an IPC command to PMC with input/output data and source/dest pointers. | |
436 | * | |
437 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 438 | */ |
439 | int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out, | |
440 | u32 outlen, u32 dptr, u32 sptr) | |
441 | { | |
442 | u32 wbuf[4] = { 0 }; | |
443 | int ret; | |
444 | int i; | |
445 | ||
446 | if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4) | |
447 | return -EINVAL; | |
448 | ||
449 | mutex_lock(&ipclock); | |
450 | if (ipcdev.dev == NULL) { | |
451 | mutex_unlock(&ipclock); | |
452 | return -ENODEV; | |
453 | } | |
454 | memcpy(wbuf, in, inlen); | |
455 | writel(dptr, ipcdev.ipc_base + IPC_DPTR); | |
456 | writel(sptr, ipcdev.ipc_base + IPC_SPTR); | |
457 | /* The input data register is 32bit register and inlen is in Byte */ | |
458 | for (i = 0; i < ((inlen + 3) / 4); i++) | |
459 | ipc_data_writel(wbuf[i], 4 * i); | |
460 | ipc_send_command((inlen << IPC_CMD_SIZE) | | |
461 | (sub << IPC_CMD_SUBCMD) | cmd); | |
462 | ret = intel_pmc_ipc_check_status(); | |
463 | if (!ret) { | |
464 | /* out is read from 32bit register and outlen is in 32bit */ | |
465 | for (i = 0; i < outlen; i++) | |
466 | *out++ = ipc_data_readl(4 * i); | |
467 | } | |
468 | mutex_unlock(&ipclock); | |
469 | ||
470 | return ret; | |
471 | } | |
472 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd); | |
473 | ||
02941007 | 474 | /** |
475 | * intel_pmc_ipc_command() - IPC command with input/output data | |
476 | * @cmd: IPC command code. | |
477 | * @sub: IPC command sub type. | |
478 | * @in: input data of this IPC command. | |
479 | * @inlen: input data length in bytes. | |
480 | * @out: output data of this IPC command. | |
481 | * @outlen: output data length in dwords. | |
482 | * | |
483 | * Send an IPC command to PMC with input/output data. | |
484 | * | |
485 | * Return: an IPC error code or 0 on success. | |
0a8b8353 | 486 | */ |
487 | int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, | |
488 | u32 *out, u32 outlen) | |
489 | { | |
490 | return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0); | |
491 | } | |
492 | EXPORT_SYMBOL_GPL(intel_pmc_ipc_command); | |
493 | ||
494 | static irqreturn_t ioc(int irq, void *dev_id) | |
495 | { | |
496 | int status; | |
497 | ||
498 | if (ipcdev.irq_mode) { | |
499 | status = ipc_read_status(); | |
500 | writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS); | |
501 | } | |
502 | complete(&ipcdev.cmd_complete); | |
503 | ||
504 | return IRQ_HANDLED; | |
505 | } | |
506 | ||
507 | static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
508 | { | |
83beee5c | 509 | struct intel_pmc_ipc_dev *pmc = &ipcdev; |
0a8b8353 | 510 | int ret; |
0a8b8353 | 511 | |
83beee5c KS |
512 | /* Only one PMC is supported */ |
513 | if (pmc->dev) | |
514 | return -EBUSY; | |
0a8b8353 | 515 | |
83beee5c KS |
516 | pmc->irq_mode = IPC_TRIGGER_MODE_IRQ; |
517 | ||
6687aeb9 KS |
518 | spin_lock_init(&ipcdev.gcr_lock); |
519 | ||
83beee5c | 520 | ret = pcim_enable_device(pdev); |
0a8b8353 | 521 | if (ret) |
522 | return ret; | |
523 | ||
83beee5c | 524 | ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); |
0a8b8353 | 525 | if (ret) |
526 | return ret; | |
527 | ||
83beee5c | 528 | init_completion(&pmc->cmd_complete); |
0a8b8353 | 529 | |
83beee5c | 530 | pmc->ipc_base = pcim_iomap_table(pdev)[0]; |
0a8b8353 | 531 | |
83beee5c KS |
532 | ret = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_pmc_ipc", |
533 | pmc); | |
534 | if (ret) { | |
0a8b8353 | 535 | dev_err(&pdev->dev, "Failed to request irq\n"); |
83beee5c | 536 | return ret; |
0a8b8353 | 537 | } |
538 | ||
83beee5c | 539 | pmc->dev = &pdev->dev; |
0a8b8353 | 540 | |
83beee5c | 541 | pci_set_drvdata(pdev, pmc); |
0a8b8353 | 542 | |
83beee5c | 543 | return 0; |
0a8b8353 | 544 | } |
545 | ||
546 | static const struct pci_device_id ipc_pci_ids[] = { | |
547 | {PCI_VDEVICE(INTEL, 0x0a94), 0}, | |
548 | {PCI_VDEVICE(INTEL, 0x1a94), 0}, | |
23e775db | 549 | {PCI_VDEVICE(INTEL, 0x5a94), 0}, |
0a8b8353 | 550 | { 0,} |
551 | }; | |
552 | MODULE_DEVICE_TABLE(pci, ipc_pci_ids); | |
553 | ||
554 | static struct pci_driver ipc_pci_driver = { | |
555 | .name = "intel_pmc_ipc", | |
556 | .id_table = ipc_pci_ids, | |
557 | .probe = ipc_pci_probe, | |
0a8b8353 | 558 | }; |
559 | ||
560 | static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev, | |
561 | struct device_attribute *attr, | |
562 | const char *buf, size_t count) | |
563 | { | |
564 | int subcmd; | |
565 | int cmd; | |
566 | int ret; | |
567 | ||
568 | ret = sscanf(buf, "%d %d", &cmd, &subcmd); | |
569 | if (ret != 2) { | |
570 | dev_err(dev, "Error args\n"); | |
571 | return -EINVAL; | |
572 | } | |
573 | ||
574 | ret = intel_pmc_ipc_simple_command(cmd, subcmd); | |
575 | if (ret) { | |
576 | dev_err(dev, "command %d error with %d\n", cmd, ret); | |
577 | return ret; | |
578 | } | |
579 | return (ssize_t)count; | |
580 | } | |
581 | ||
582 | static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev, | |
583 | struct device_attribute *attr, | |
584 | const char *buf, size_t count) | |
585 | { | |
586 | unsigned long val; | |
587 | int subcmd; | |
588 | int ret; | |
589 | ||
590 | if (kstrtoul(buf, 0, &val)) | |
591 | return -EINVAL; | |
592 | ||
593 | if (val) | |
594 | subcmd = 1; | |
595 | else | |
596 | subcmd = 0; | |
597 | ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd); | |
598 | if (ret) { | |
599 | dev_err(dev, "command north %d error with %d\n", subcmd, ret); | |
600 | return ret; | |
601 | } | |
602 | return (ssize_t)count; | |
603 | } | |
604 | ||
605 | static DEVICE_ATTR(simplecmd, S_IWUSR, | |
606 | NULL, intel_pmc_ipc_simple_cmd_store); | |
607 | static DEVICE_ATTR(northpeak, S_IWUSR, | |
608 | NULL, intel_pmc_ipc_northpeak_store); | |
609 | ||
610 | static struct attribute *intel_ipc_attrs[] = { | |
611 | &dev_attr_northpeak.attr, | |
612 | &dev_attr_simplecmd.attr, | |
613 | NULL | |
614 | }; | |
615 | ||
616 | static const struct attribute_group intel_ipc_group = { | |
617 | .attrs = intel_ipc_attrs, | |
618 | }; | |
619 | ||
8cc7fb4a QZ |
620 | static struct resource punit_res_array[] = { |
621 | /* Punit BIOS */ | |
622 | { | |
623 | .flags = IORESOURCE_MEM, | |
624 | }, | |
625 | { | |
626 | .flags = IORESOURCE_MEM, | |
627 | }, | |
628 | /* Punit ISP */ | |
629 | { | |
630 | .flags = IORESOURCE_MEM, | |
631 | }, | |
632 | { | |
633 | .flags = IORESOURCE_MEM, | |
634 | }, | |
635 | /* Punit GTD */ | |
0a8b8353 | 636 | { |
637 | .flags = IORESOURCE_MEM, | |
638 | }, | |
639 | { | |
640 | .flags = IORESOURCE_MEM, | |
641 | }, | |
642 | }; | |
643 | ||
644 | #define TCO_RESOURCE_ACPI_IO 0 | |
645 | #define TCO_RESOURCE_SMI_EN_IO 1 | |
646 | #define TCO_RESOURCE_GCR_MEM 2 | |
647 | static struct resource tco_res[] = { | |
648 | /* ACPI - TCO */ | |
649 | { | |
650 | .flags = IORESOURCE_IO, | |
651 | }, | |
652 | /* ACPI - SMI */ | |
653 | { | |
654 | .flags = IORESOURCE_IO, | |
655 | }, | |
0a8b8353 | 656 | }; |
657 | ||
420b54de | 658 | static struct itco_wdt_platform_data tco_info = { |
0a8b8353 | 659 | .name = "Apollo Lake SoC", |
334da2d6 | 660 | .version = 5, |
9d855d46 KS |
661 | .no_reboot_priv = &ipcdev, |
662 | .update_no_reboot_bit = update_no_reboot_bit, | |
0a8b8353 | 663 | }; |
664 | ||
48c19170 SKC |
665 | #define TELEMETRY_RESOURCE_PUNIT_SSRAM 0 |
666 | #define TELEMETRY_RESOURCE_PMC_SSRAM 1 | |
667 | static struct resource telemetry_res[] = { | |
668 | /*Telemetry*/ | |
669 | { | |
670 | .flags = IORESOURCE_MEM, | |
671 | }, | |
672 | { | |
673 | .flags = IORESOURCE_MEM, | |
674 | }, | |
675 | }; | |
676 | ||
0a8b8353 | 677 | static int ipc_create_punit_device(void) |
678 | { | |
679 | struct platform_device *pdev; | |
ea1a76ba AL |
680 | const struct platform_device_info pdevinfo = { |
681 | .parent = ipcdev.dev, | |
682 | .name = PUNIT_DEVICE_NAME, | |
683 | .id = -1, | |
684 | .res = punit_res_array, | |
685 | .num_res = ARRAY_SIZE(punit_res_array), | |
686 | }; | |
687 | ||
688 | pdev = platform_device_register_full(&pdevinfo); | |
689 | if (IS_ERR(pdev)) | |
690 | return PTR_ERR(pdev); | |
0a8b8353 | 691 | |
0a8b8353 | 692 | ipcdev.punit_dev = pdev; |
693 | ||
694 | return 0; | |
0a8b8353 | 695 | } |
696 | ||
697 | static int ipc_create_tco_device(void) | |
698 | { | |
699 | struct platform_device *pdev; | |
700 | struct resource *res; | |
ea1a76ba AL |
701 | const struct platform_device_info pdevinfo = { |
702 | .parent = ipcdev.dev, | |
703 | .name = TCO_DEVICE_NAME, | |
704 | .id = -1, | |
705 | .res = tco_res, | |
706 | .num_res = ARRAY_SIZE(tco_res), | |
707 | .data = &tco_info, | |
708 | .size_data = sizeof(tco_info), | |
709 | }; | |
0a8b8353 | 710 | |
711 | res = tco_res + TCO_RESOURCE_ACPI_IO; | |
b78fb51b | 712 | res->start = ipcdev.acpi_io_base + TCO_BASE_OFFSET; |
0a8b8353 | 713 | res->end = res->start + TCO_REGS_SIZE - 1; |
714 | ||
715 | res = tco_res + TCO_RESOURCE_SMI_EN_IO; | |
b78fb51b | 716 | res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET; |
0a8b8353 | 717 | res->end = res->start + SMI_EN_SIZE - 1; |
718 | ||
ea1a76ba AL |
719 | pdev = platform_device_register_full(&pdevinfo); |
720 | if (IS_ERR(pdev)) | |
721 | return PTR_ERR(pdev); | |
0a8b8353 | 722 | |
0a8b8353 | 723 | ipcdev.tco_dev = pdev; |
724 | ||
725 | return 0; | |
0a8b8353 | 726 | } |
727 | ||
48c19170 SKC |
728 | static int ipc_create_telemetry_device(void) |
729 | { | |
730 | struct platform_device *pdev; | |
731 | struct resource *res; | |
ea1a76ba AL |
732 | const struct platform_device_info pdevinfo = { |
733 | .parent = ipcdev.dev, | |
734 | .name = TELEMETRY_DEVICE_NAME, | |
735 | .id = -1, | |
736 | .res = telemetry_res, | |
737 | .num_res = ARRAY_SIZE(telemetry_res), | |
738 | }; | |
48c19170 SKC |
739 | |
740 | res = telemetry_res + TELEMETRY_RESOURCE_PUNIT_SSRAM; | |
741 | res->start = ipcdev.telem_punit_ssram_base; | |
742 | res->end = res->start + ipcdev.telem_punit_ssram_size - 1; | |
743 | ||
744 | res = telemetry_res + TELEMETRY_RESOURCE_PMC_SSRAM; | |
745 | res->start = ipcdev.telem_pmc_ssram_base; | |
746 | res->end = res->start + ipcdev.telem_pmc_ssram_size - 1; | |
747 | ||
ea1a76ba AL |
748 | pdev = platform_device_register_full(&pdevinfo); |
749 | if (IS_ERR(pdev)) | |
750 | return PTR_ERR(pdev); | |
48c19170 | 751 | |
48c19170 SKC |
752 | ipcdev.telemetry_dev = pdev; |
753 | ||
754 | return 0; | |
48c19170 SKC |
755 | } |
756 | ||
0a8b8353 | 757 | static int ipc_create_pmc_devices(void) |
758 | { | |
759 | int ret; | |
760 | ||
bba6529e MW |
761 | /* If we have ACPI based watchdog use that instead */ |
762 | if (!acpi_has_watchdog()) { | |
763 | ret = ipc_create_tco_device(); | |
764 | if (ret) { | |
765 | dev_err(ipcdev.dev, "Failed to add tco platform device\n"); | |
766 | return ret; | |
767 | } | |
0a8b8353 | 768 | } |
bba6529e | 769 | |
0a8b8353 | 770 | ret = ipc_create_punit_device(); |
771 | if (ret) { | |
772 | dev_err(ipcdev.dev, "Failed to add punit platform device\n"); | |
773 | platform_device_unregister(ipcdev.tco_dev); | |
774 | } | |
48c19170 SKC |
775 | |
776 | if (!ipcdev.telem_res_inval) { | |
777 | ret = ipc_create_telemetry_device(); | |
778 | if (ret) | |
779 | dev_warn(ipcdev.dev, | |
780 | "Failed to add telemetry platform device\n"); | |
781 | } | |
782 | ||
0a8b8353 | 783 | return ret; |
784 | } | |
785 | ||
786 | static int ipc_plat_get_res(struct platform_device *pdev) | |
787 | { | |
8cc7fb4a | 788 | struct resource *res, *punit_res; |
0a8b8353 | 789 | void __iomem *addr; |
790 | int size; | |
791 | ||
792 | res = platform_get_resource(pdev, IORESOURCE_IO, | |
793 | PLAT_RESOURCE_ACPI_IO_INDEX); | |
794 | if (!res) { | |
795 | dev_err(&pdev->dev, "Failed to get io resource\n"); | |
796 | return -ENXIO; | |
797 | } | |
798 | size = resource_size(res); | |
b78fb51b | 799 | ipcdev.acpi_io_base = res->start; |
0a8b8353 | 800 | ipcdev.acpi_io_size = size; |
8cc7fb4a | 801 | dev_info(&pdev->dev, "io res: %pR\n", res); |
0a8b8353 | 802 | |
8cc7fb4a | 803 | punit_res = punit_res_array; |
5d071633 | 804 | /* This is index 0 to cover BIOS data register */ |
0a8b8353 | 805 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
8cc7fb4a | 806 | PLAT_RESOURCE_BIOS_DATA_INDEX); |
0a8b8353 | 807 | if (!res) { |
8cc7fb4a | 808 | dev_err(&pdev->dev, "Failed to get res of punit BIOS data\n"); |
0a8b8353 | 809 | return -ENXIO; |
810 | } | |
8cc7fb4a QZ |
811 | *punit_res = *res; |
812 | dev_info(&pdev->dev, "punit BIOS data res: %pR\n", res); | |
0a8b8353 | 813 | |
5d071633 | 814 | /* This is index 1 to cover BIOS interface register */ |
0a8b8353 | 815 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
8cc7fb4a | 816 | PLAT_RESOURCE_BIOS_IFACE_INDEX); |
0a8b8353 | 817 | if (!res) { |
8cc7fb4a | 818 | dev_err(&pdev->dev, "Failed to get res of punit BIOS iface\n"); |
0a8b8353 | 819 | return -ENXIO; |
820 | } | |
8cc7fb4a QZ |
821 | *++punit_res = *res; |
822 | dev_info(&pdev->dev, "punit BIOS interface res: %pR\n", res); | |
823 | ||
5d071633 | 824 | /* This is index 2 to cover ISP data register, optional */ |
8cc7fb4a QZ |
825 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
826 | PLAT_RESOURCE_ISP_DATA_INDEX); | |
5d071633 AL |
827 | ++punit_res; |
828 | if (res) { | |
829 | *punit_res = *res; | |
830 | dev_info(&pdev->dev, "punit ISP data res: %pR\n", res); | |
8cc7fb4a | 831 | } |
8cc7fb4a | 832 | |
5d071633 | 833 | /* This is index 3 to cover ISP interface register, optional */ |
8cc7fb4a QZ |
834 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
835 | PLAT_RESOURCE_ISP_IFACE_INDEX); | |
5d071633 AL |
836 | ++punit_res; |
837 | if (res) { | |
838 | *punit_res = *res; | |
839 | dev_info(&pdev->dev, "punit ISP interface res: %pR\n", res); | |
8cc7fb4a | 840 | } |
8cc7fb4a | 841 | |
5d071633 | 842 | /* This is index 4 to cover GTD data register, optional */ |
8cc7fb4a QZ |
843 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
844 | PLAT_RESOURCE_GTD_DATA_INDEX); | |
5d071633 AL |
845 | ++punit_res; |
846 | if (res) { | |
847 | *punit_res = *res; | |
848 | dev_info(&pdev->dev, "punit GTD data res: %pR\n", res); | |
8cc7fb4a | 849 | } |
8cc7fb4a | 850 | |
5d071633 | 851 | /* This is index 5 to cover GTD interface register, optional */ |
8cc7fb4a QZ |
852 | res = platform_get_resource(pdev, IORESOURCE_MEM, |
853 | PLAT_RESOURCE_GTD_IFACE_INDEX); | |
5d071633 AL |
854 | ++punit_res; |
855 | if (res) { | |
856 | *punit_res = *res; | |
857 | dev_info(&pdev->dev, "punit GTD interface res: %pR\n", res); | |
8cc7fb4a | 858 | } |
0a8b8353 | 859 | |
860 | res = platform_get_resource(pdev, IORESOURCE_MEM, | |
861 | PLAT_RESOURCE_IPC_INDEX); | |
862 | if (!res) { | |
863 | dev_err(&pdev->dev, "Failed to get ipc resource\n"); | |
864 | return -ENXIO; | |
865 | } | |
76062b4a | 866 | size = PLAT_RESOURCE_IPC_SIZE + PLAT_RESOURCE_GCR_SIZE; |
83beee5c KS |
867 | res->end = res->start + size - 1; |
868 | ||
869 | addr = devm_ioremap_resource(&pdev->dev, res); | |
870 | if (IS_ERR(addr)) | |
871 | return PTR_ERR(addr); | |
76062b4a | 872 | |
0a8b8353 | 873 | ipcdev.ipc_base = addr; |
874 | ||
49670206 | 875 | ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; |
8cc7fb4a | 876 | dev_info(&pdev->dev, "ipc res: %pR\n", res); |
0a8b8353 | 877 | |
48c19170 SKC |
878 | ipcdev.telem_res_inval = 0; |
879 | res = platform_get_resource(pdev, IORESOURCE_MEM, | |
880 | PLAT_RESOURCE_TELEM_SSRAM_INDEX); | |
881 | if (!res) { | |
882 | dev_err(&pdev->dev, "Failed to get telemetry ssram resource\n"); | |
883 | ipcdev.telem_res_inval = 1; | |
884 | } else { | |
885 | ipcdev.telem_punit_ssram_base = res->start + | |
886 | TELEM_PUNIT_SSRAM_OFFSET; | |
887 | ipcdev.telem_punit_ssram_size = TELEM_SSRAM_SIZE; | |
888 | ipcdev.telem_pmc_ssram_base = res->start + | |
889 | TELEM_PMC_SSRAM_OFFSET; | |
890 | ipcdev.telem_pmc_ssram_size = TELEM_SSRAM_SIZE; | |
891 | dev_info(&pdev->dev, "telemetry ssram res: %pR\n", res); | |
892 | } | |
893 | ||
0a8b8353 | 894 | return 0; |
895 | } | |
896 | ||
76062b4a SM |
897 | /** |
898 | * intel_pmc_s0ix_counter_read() - Read S0ix residency. | |
899 | * @data: Out param that contains current S0ix residency count. | |
900 | * | |
901 | * Return: an error code or 0 on success. | |
902 | */ | |
903 | int intel_pmc_s0ix_counter_read(u64 *data) | |
904 | { | |
905 | u64 deep, shlw; | |
906 | ||
907 | if (!ipcdev.has_gcr_regs) | |
908 | return -EACCES; | |
909 | ||
62a7b9c8 KS |
910 | deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG); |
911 | shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG); | |
76062b4a SM |
912 | |
913 | *data = S0IX_RESIDENCY_IN_USECS(deep, shlw); | |
914 | ||
915 | return 0; | |
916 | } | |
917 | EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read); | |
918 | ||
0a8b8353 | 919 | #ifdef CONFIG_ACPI |
920 | static const struct acpi_device_id ipc_acpi_ids[] = { | |
921 | { "INT34D2", 0}, | |
922 | { } | |
923 | }; | |
924 | MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids); | |
925 | #endif | |
926 | ||
927 | static int ipc_plat_probe(struct platform_device *pdev) | |
928 | { | |
0a8b8353 | 929 | int ret; |
930 | ||
931 | ipcdev.dev = &pdev->dev; | |
932 | ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ; | |
933 | init_completion(&ipcdev.cmd_complete); | |
6687aeb9 | 934 | spin_lock_init(&ipcdev.gcr_lock); |
0a8b8353 | 935 | |
936 | ipcdev.irq = platform_get_irq(pdev, 0); | |
937 | if (ipcdev.irq < 0) { | |
938 | dev_err(&pdev->dev, "Failed to get irq\n"); | |
939 | return -EINVAL; | |
940 | } | |
941 | ||
942 | ret = ipc_plat_get_res(pdev); | |
943 | if (ret) { | |
944 | dev_err(&pdev->dev, "Failed to request resource\n"); | |
945 | return ret; | |
946 | } | |
947 | ||
948 | ret = ipc_create_pmc_devices(); | |
949 | if (ret) { | |
950 | dev_err(&pdev->dev, "Failed to create pmc devices\n"); | |
83beee5c | 951 | return ret; |
0a8b8353 | 952 | } |
953 | ||
83beee5c KS |
954 | if (devm_request_irq(&pdev->dev, ipcdev.irq, ioc, IRQF_NO_SUSPEND, |
955 | "intel_pmc_ipc", &ipcdev)) { | |
0a8b8353 | 956 | dev_err(&pdev->dev, "Failed to request irq\n"); |
957 | ret = -EBUSY; | |
958 | goto err_irq; | |
959 | } | |
960 | ||
961 | ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group); | |
962 | if (ret) { | |
963 | dev_err(&pdev->dev, "Failed to create sysfs group %d\n", | |
964 | ret); | |
965 | goto err_sys; | |
966 | } | |
967 | ||
76062b4a SM |
968 | ipcdev.has_gcr_regs = true; |
969 | ||
0a8b8353 | 970 | return 0; |
971 | err_sys: | |
83beee5c | 972 | devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev); |
0a8b8353 | 973 | err_irq: |
974 | platform_device_unregister(ipcdev.tco_dev); | |
975 | platform_device_unregister(ipcdev.punit_dev); | |
48c19170 | 976 | platform_device_unregister(ipcdev.telemetry_dev); |
83beee5c | 977 | |
0a8b8353 | 978 | return ret; |
979 | } | |
980 | ||
981 | static int ipc_plat_remove(struct platform_device *pdev) | |
982 | { | |
0a8b8353 | 983 | sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group); |
83beee5c | 984 | devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev); |
0a8b8353 | 985 | platform_device_unregister(ipcdev.tco_dev); |
986 | platform_device_unregister(ipcdev.punit_dev); | |
48c19170 | 987 | platform_device_unregister(ipcdev.telemetry_dev); |
0a8b8353 | 988 | ipcdev.dev = NULL; |
989 | return 0; | |
990 | } | |
991 | ||
992 | static struct platform_driver ipc_plat_driver = { | |
993 | .remove = ipc_plat_remove, | |
994 | .probe = ipc_plat_probe, | |
995 | .driver = { | |
996 | .name = "pmc-ipc-plat", | |
997 | .acpi_match_table = ACPI_PTR(ipc_acpi_ids), | |
998 | }, | |
999 | }; | |
1000 | ||
1001 | static int __init intel_pmc_ipc_init(void) | |
1002 | { | |
1003 | int ret; | |
1004 | ||
1005 | ret = platform_driver_register(&ipc_plat_driver); | |
1006 | if (ret) { | |
1007 | pr_err("Failed to register PMC ipc platform driver\n"); | |
1008 | return ret; | |
1009 | } | |
1010 | ret = pci_register_driver(&ipc_pci_driver); | |
1011 | if (ret) { | |
1012 | pr_err("Failed to register PMC ipc pci driver\n"); | |
1013 | platform_driver_unregister(&ipc_plat_driver); | |
1014 | return ret; | |
1015 | } | |
1016 | return ret; | |
1017 | } | |
1018 | ||
1019 | static void __exit intel_pmc_ipc_exit(void) | |
1020 | { | |
1021 | pci_unregister_driver(&ipc_pci_driver); | |
1022 | platform_driver_unregister(&ipc_plat_driver); | |
1023 | } | |
1024 | ||
1025 | MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>"); | |
1026 | MODULE_DESCRIPTION("Intel PMC IPC driver"); | |
ad51f287 | 1027 | MODULE_LICENSE("GPL v2"); |
0a8b8353 | 1028 | |
1029 | /* Some modules are dependent on this, so init earlier */ | |
1030 | fs_initcall(intel_pmc_ipc_init); | |
1031 | module_exit(intel_pmc_ipc_exit); |