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1 | /* |
2 | * Intel Core SoC Power Management Controller Header File | |
3 | * | |
4 | * Copyright (c) 2016, Intel Corporation. | |
5 | * All Rights Reserved. | |
6 | * | |
7 | * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> | |
8 | * Vishwanath Somayaji <vishwanath.somayaji@intel.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms and conditions of the GNU General Public License, | |
12 | * version 2, as published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef PMC_CORE_H | |
22 | #define PMC_CORE_H | |
23 | ||
24 | /* Sunrise Point Power Management Controller PCI Device ID */ | |
25 | #define SPT_PMC_PCI_DEVICE_ID 0x9d21 | |
26 | #define SPT_PMC_BASE_ADDR_OFFSET 0x48 | |
27 | #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c | |
28 | #define SPT_PMC_MMIO_REG_LEN 0x100 | |
29 | #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 | |
30 | ||
31 | /** | |
32 | * struct pmc_dev - pmc device structure | |
33 | * @base_addr: comtains pmc base address | |
34 | * @regbase: pointer to io-remapped memory location | |
35 | * @dbgfs_dir: path to debug fs interface | |
36 | * @feature_available: flag to indicate whether | |
37 | * the feature is available | |
38 | * on a particular platform or not. | |
39 | * | |
40 | * pmc_dev contains info about power management controller device. | |
41 | */ | |
42 | struct pmc_dev { | |
43 | u32 base_addr; | |
44 | void __iomem *regbase; | |
45 | #if IS_ENABLED(CONFIG_DEBUG_FS) | |
46 | struct dentry *dbgfs_dir; | |
47 | #endif /* CONFIG_DEBUG_FS */ | |
48 | bool has_slp_s0_res; | |
49 | }; | |
50 | ||
51 | #endif /* PMC_CORE_H */ |