[linux-2.6-block.git] / drivers / platform / x86 / intel_pmc_core.h

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Core SoC Power Management Controller Header File
 *
 * Copyright (c) 2016, Intel Corporation.
 * All Rights Reserved.
 *
 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
 *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
 */

#ifndef PMC_CORE_H
#define PMC_CORE_H

#include <linux/bits.h>

#define PMC_BASE_ADDR_DEFAULT			0xFE000000

/* Sunrise Point Power Management Controller PCI Device ID */
#define SPT_PMC_PCI_DEVICE_ID			0x9d21
#define SPT_PMC_BASE_ADDR_OFFSET		0x48
#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET	0x13c
#define SPT_PMC_PM_CFG_OFFSET			0x18
#define SPT_PMC_PM_STS_OFFSET			0x1c
#define SPT_PMC_MTPMC_OFFSET			0x20
#define SPT_PMC_MFPMC_OFFSET			0x38
#define SPT_PMC_LTR_IGNORE_OFFSET		0x30C
#define SPT_PMC_MPHY_CORE_STS_0			0x1143
#define SPT_PMC_MPHY_CORE_STS_1			0x1142
#define SPT_PMC_MPHY_COM_STS_0			0x1155
#define SPT_PMC_MMIO_REG_LEN			0x1000
#define SPT_PMC_SLP_S0_RES_COUNTER_STEP		0x64
#define PMC_BASE_ADDR_MASK			~(SPT_PMC_MMIO_REG_LEN - 1)
#define MTPMC_MASK				0xffff0000
#define PPFEAR_MAX_NUM_ENTRIES			12
#define SPT_PPFEAR_NUM_ENTRIES			5
#define SPT_PMC_READ_DISABLE_BIT		0x16
#define SPT_PMC_MSG_FULL_STS_BIT		0x18
#define NUM_RETRIES				100
#define SPT_NUM_IP_IGN_ALLOWED			17

#define SPT_PMC_LTR_CUR_PLT			0x350
#define SPT_PMC_LTR_CUR_ASLT			0x354
#define SPT_PMC_LTR_SPA				0x360
#define SPT_PMC_LTR_SPB				0x364
#define SPT_PMC_LTR_SATA			0x368
#define SPT_PMC_LTR_GBE				0x36C
#define SPT_PMC_LTR_XHCI			0x370
#define SPT_PMC_LTR_RESERVED			0x374
#define SPT_PMC_LTR_ME				0x378
#define SPT_PMC_LTR_EVA				0x37C
#define SPT_PMC_LTR_SPC				0x380
#define SPT_PMC_LTR_AZ				0x384
#define SPT_PMC_LTR_LPSS			0x38C
#define SPT_PMC_LTR_CAM				0x390
#define SPT_PMC_LTR_SPD				0x394
#define SPT_PMC_LTR_SPE				0x398
#define SPT_PMC_LTR_ESPI			0x39C
#define SPT_PMC_LTR_SCC				0x3A0
#define SPT_PMC_LTR_ISH				0x3A4

/* Sunrise Point: PGD PFET Enable Ack Status Registers */
enum ppfear_regs {
	SPT_PMC_XRAM_PPFEAR0A = 0x590,
	SPT_PMC_XRAM_PPFEAR0B,
	SPT_PMC_XRAM_PPFEAR0C,
	SPT_PMC_XRAM_PPFEAR0D,
	SPT_PMC_XRAM_PPFEAR1A,
};

#define SPT_PMC_BIT_PMC				BIT(0)
#define SPT_PMC_BIT_OPI				BIT(1)
#define SPT_PMC_BIT_SPI				BIT(2)
#define SPT_PMC_BIT_XHCI			BIT(3)
#define SPT_PMC_BIT_SPA				BIT(4)
#define SPT_PMC_BIT_SPB				BIT(5)
#define SPT_PMC_BIT_SPC				BIT(6)
#define SPT_PMC_BIT_GBE				BIT(7)

#define SPT_PMC_BIT_SATA			BIT(0)
#define SPT_PMC_BIT_HDA_PGD0			BIT(1)
#define SPT_PMC_BIT_HDA_PGD1			BIT(2)
#define SPT_PMC_BIT_HDA_PGD2			BIT(3)
#define SPT_PMC_BIT_HDA_PGD3			BIT(4)
#define SPT_PMC_BIT_RSVD_0B			BIT(5)
#define SPT_PMC_BIT_LPSS			BIT(6)
#define SPT_PMC_BIT_LPC				BIT(7)

#define SPT_PMC_BIT_SMB				BIT(0)
#define SPT_PMC_BIT_ISH				BIT(1)
#define SPT_PMC_BIT_P2SB			BIT(2)
#define SPT_PMC_BIT_DFX				BIT(3)
#define SPT_PMC_BIT_SCC				BIT(4)
#define SPT_PMC_BIT_RSVD_0C			BIT(5)
#define SPT_PMC_BIT_FUSE			BIT(6)
#define SPT_PMC_BIT_CAMREA			BIT(7)

#define SPT_PMC_BIT_RSVD_0D			BIT(0)
#define SPT_PMC_BIT_USB3_OTG			BIT(1)
#define SPT_PMC_BIT_EXI				BIT(2)
#define SPT_PMC_BIT_CSE				BIT(3)
#define SPT_PMC_BIT_CSME_KVM			BIT(4)
#define SPT_PMC_BIT_CSME_PMT			BIT(5)
#define SPT_PMC_BIT_CSME_CLINK			BIT(6)
#define SPT_PMC_BIT_CSME_PTIO			BIT(7)

#define SPT_PMC_BIT_CSME_USBR			BIT(0)
#define SPT_PMC_BIT_CSME_SUSRAM			BIT(1)
#define SPT_PMC_BIT_CSME_SMT			BIT(2)
#define SPT_PMC_BIT_RSVD_1A			BIT(3)
#define SPT_PMC_BIT_CSME_SMS2			BIT(4)
#define SPT_PMC_BIT_CSME_SMS1			BIT(5)
#define SPT_PMC_BIT_CSME_RTC			BIT(6)
#define SPT_PMC_BIT_CSME_PSF			BIT(7)

#define SPT_PMC_BIT_MPHY_LANE0			BIT(0)
#define SPT_PMC_BIT_MPHY_LANE1			BIT(1)
#define SPT_PMC_BIT_MPHY_LANE2			BIT(2)
#define SPT_PMC_BIT_MPHY_LANE3			BIT(3)
#define SPT_PMC_BIT_MPHY_LANE4			BIT(4)
#define SPT_PMC_BIT_MPHY_LANE5			BIT(5)
#define SPT_PMC_BIT_MPHY_LANE6			BIT(6)
#define SPT_PMC_BIT_MPHY_LANE7			BIT(7)

#define SPT_PMC_BIT_MPHY_LANE8			BIT(0)
#define SPT_PMC_BIT_MPHY_LANE9			BIT(1)
#define SPT_PMC_BIT_MPHY_LANE10			BIT(2)
#define SPT_PMC_BIT_MPHY_LANE11			BIT(3)
#define SPT_PMC_BIT_MPHY_LANE12			BIT(4)
#define SPT_PMC_BIT_MPHY_LANE13			BIT(5)
#define SPT_PMC_BIT_MPHY_LANE14			BIT(6)
#define SPT_PMC_BIT_MPHY_LANE15			BIT(7)

#define SPT_PMC_BIT_MPHY_CMN_LANE0		BIT(0)
#define SPT_PMC_BIT_MPHY_CMN_LANE1		BIT(1)
#define SPT_PMC_BIT_MPHY_CMN_LANE2		BIT(2)
#define SPT_PMC_BIT_MPHY_CMN_LANE3		BIT(3)

/* Cannonlake Power Management Controller register offsets */
#define CNP_PMC_SLPS0_DBG_OFFSET		0x10B4
#define CNP_PMC_PM_CFG_OFFSET			0x1818
#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET	0x193C
#define CNP_PMC_LTR_IGNORE_OFFSET		0x1B0C
/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
#define CNP_PMC_HOST_PPFEAR0A			0x1D90

#define CNP_PMC_LATCH_SLPS0_EVENTS		BIT(31)

#define CNP_PMC_MMIO_REG_LEN			0x2000
#define CNP_PPFEAR_NUM_ENTRIES			8
#define CNP_PMC_READ_DISABLE_BIT		22
#define CNP_NUM_IP_IGN_ALLOWED			19
#define CNP_PMC_LTR_CUR_PLT			0x1B50
#define CNP_PMC_LTR_CUR_ASLT			0x1B54
#define CNP_PMC_LTR_SPA				0x1B60
#define CNP_PMC_LTR_SPB				0x1B64
#define CNP_PMC_LTR_SATA			0x1B68
#define CNP_PMC_LTR_GBE				0x1B6C
#define CNP_PMC_LTR_XHCI			0x1B70
#define CNP_PMC_LTR_RESERVED			0x1B74
#define CNP_PMC_LTR_ME				0x1B78
#define CNP_PMC_LTR_EVA				0x1B7C
#define CNP_PMC_LTR_SPC				0x1B80
#define CNP_PMC_LTR_AZ				0x1B84
#define CNP_PMC_LTR_LPSS			0x1B8C
#define CNP_PMC_LTR_CAM				0x1B90
#define CNP_PMC_LTR_SPD				0x1B94
#define CNP_PMC_LTR_SPE				0x1B98
#define CNP_PMC_LTR_ESPI			0x1B9C
#define CNP_PMC_LTR_SCC				0x1BA0
#define CNP_PMC_LTR_ISH				0x1BA4
#define CNP_PMC_LTR_CNV				0x1BF0
#define CNP_PMC_LTR_EMMC			0x1BF4
#define CNP_PMC_LTR_UFSX2			0x1BF8

#define LTR_DECODED_VAL				GENMASK(9, 0)
#define LTR_DECODED_SCALE			GENMASK(12, 10)
#define LTR_REQ_SNOOP				BIT(15)
#define LTR_REQ_NONSNOOP			BIT(31)

#define ICL_PPFEAR_NUM_ENTRIES			9
#define ICL_NUM_IP_IGN_ALLOWED			20
#define ICL_PMC_LTR_WIGIG			0x1BFC

struct pmc_bit_map {
	const char *name;
	u32 bit_mask;
};

/**
 * struct pmc_reg_map - Structure used to define parameter unique to a
			PCH family
 * @pfear_sts:		Maps name of IP block to PPFEAR* bit
 * @mphy_sts:		Maps name of MPHY lane to MPHY status lane status bit
 * @pll_sts:		Maps name of PLL to corresponding bit status
 * @slps0_dbg_maps:	Array of SLP_S0_DBG* registers containing debug info
 * @ltr_show_sts:	Maps PCH IP Names to their MMIO register offsets
 * @slp_s0_offset:	PWRMBASE offset to read SLP_S0 residency
 * @ltr_ignore_offset:	PWRMBASE offset to read/write LTR ignore bit
 * @regmap_length:	Length of memory to map from PWRMBASE address to access
 * @ppfear0_offset:	PWRMBASE offset to to read PPFEAR*
 * @ppfear_buckets:	Number of 8 bits blocks to read all IP blocks from
 *			PPFEAR
 * @pm_cfg_offset:	PWRMBASE offset to PM_CFG register
 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
 * @slps0_dbg_offset:	PWRMBASE offset to SLP_S0_DEBUG_REG*
 *
 * Each PCH has unique set of register offsets and bit indexes. This structure
 * captures them to have a common implementation.
 */
struct pmc_reg_map {
	const struct pmc_bit_map *pfear_sts;
	const struct pmc_bit_map *mphy_sts;
	const struct pmc_bit_map *pll_sts;
	const struct pmc_bit_map **slps0_dbg_maps;
	const struct pmc_bit_map *ltr_show_sts;
	const u32 slp_s0_offset;
	const u32 ltr_ignore_offset;
	const int regmap_length;
	const u32 ppfear0_offset;
	const int ppfear_buckets;
	const u32 pm_cfg_offset;
	const int pm_read_disable_bit;
	const u32 slps0_dbg_offset;
	const u32 ltr_ignore_max;
};

/**
 * struct pmc_dev - pmc device structure
 * @base_addr:		contains pmc base address
 * @regbase:		pointer to io-remapped memory location
 * @map:		pointer to pmc_reg_map struct that contains platform
 *			specific attributes
 * @dbgfs_dir:		path to debugfs interface
 * @pmc_xram_read_bit:	flag to indicate whether PMC XRAM shadow registers
 *			used to read MPHY PG and PLL status are available
 * @mutex_lock:		mutex to complete one transcation
 *
 * pmc_dev contains info about power management controller device.
 */
struct pmc_dev {
	u32 base_addr;
	void __iomem *regbase;
	const struct pmc_reg_map *map;
#if IS_ENABLED(CONFIG_DEBUG_FS)
	struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
	int pmc_xram_read_bit;
	struct mutex lock; /* generic mutex lock for PMC Core */
};

#endif /* PMC_CORE_H */
Commit	Line	Data
ad51f287	1	// SPDX-License-Identifier: GPL-2.0
b740d2e9 RB	2	/*
	3	* Intel Core SoC Power Management Controller Header File
	4	*
	5	* Copyright (c) 2016, Intel Corporation.
	6	* All Rights Reserved.
	7	*
	8	* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
	9	* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
b740d2e9 RB	10	*/
	11
	12	#ifndef PMC_CORE_H
	13	#define PMC_CORE_H
	14
8122e7cd RB	15	#include <linux/bits.h>
8122e7cd RB	16
21ae4357	17	#define PMC_BASE_ADDR_DEFAULT 0xFE000000
df2294fb	18
661405bd RB	19	/* Sunrise Point Power Management Controller PCI Device ID */
661405bd RB	20	#define SPT_PMC_PCI_DEVICE_ID 0x9d21
b740d2e9 RB	21	#define SPT_PMC_BASE_ADDR_OFFSET 0x48
b740d2e9 RB	22	#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
173943b3 RB	23	#define SPT_PMC_PM_CFG_OFFSET 0x18
	24	#define SPT_PMC_PM_STS_OFFSET 0x1c
	25	#define SPT_PMC_MTPMC_OFFSET 0x20
	26	#define SPT_PMC_MFPMC_OFFSET 0x38
9c2ee199	27	#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
173943b3 RB	28	#define SPT_PMC_MPHY_CORE_STS_0 0x1143
173943b3 RB	29	#define SPT_PMC_MPHY_CORE_STS_1 0x1142
fe748227	30	#define SPT_PMC_MPHY_COM_STS_0 0x1155
8434709b	31	#define SPT_PMC_MMIO_REG_LEN 0x1000
b740d2e9	32	#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64
8434709b	33	#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
173943b3	34	#define MTPMC_MASK 0xffff0000
0e68eeea	35	#define PPFEAR_MAX_NUM_ENTRIES 12
c977b98b	36	#define SPT_PPFEAR_NUM_ENTRIES 5
173943b3 RB	37	#define SPT_PMC_READ_DISABLE_BIT 0x16
	38	#define SPT_PMC_MSG_FULL_STS_BIT 0x18
	39	#define NUM_RETRIES 100
2d649d97	40	#define SPT_NUM_IP_IGN_ALLOWED 17
0bdfaf42	41
2eb15055 RB	42	#define SPT_PMC_LTR_CUR_PLT 0x350
	43	#define SPT_PMC_LTR_CUR_ASLT 0x354
	44	#define SPT_PMC_LTR_SPA 0x360
	45	#define SPT_PMC_LTR_SPB 0x364
	46	#define SPT_PMC_LTR_SATA 0x368
	47	#define SPT_PMC_LTR_GBE 0x36C
	48	#define SPT_PMC_LTR_XHCI 0x370
2a13096a	49	#define SPT_PMC_LTR_RESERVED 0x374
2eb15055 RB	50	#define SPT_PMC_LTR_ME 0x378
	51	#define SPT_PMC_LTR_EVA 0x37C
	52	#define SPT_PMC_LTR_SPC 0x380
	53	#define SPT_PMC_LTR_AZ 0x384
	54	#define SPT_PMC_LTR_LPSS 0x38C
	55	#define SPT_PMC_LTR_CAM 0x390
	56	#define SPT_PMC_LTR_SPD 0x394
	57	#define SPT_PMC_LTR_SPE 0x398
	58	#define SPT_PMC_LTR_ESPI 0x39C
	59	#define SPT_PMC_LTR_SCC 0x3A0
	60	#define SPT_PMC_LTR_ISH 0x3A4
	61
0bdfaf42 RB	62	/* Sunrise Point: PGD PFET Enable Ack Status Registers */
	63	enum ppfear_regs {
	64	SPT_PMC_XRAM_PPFEAR0A = 0x590,
	65	SPT_PMC_XRAM_PPFEAR0B,
	66	SPT_PMC_XRAM_PPFEAR0C,
	67	SPT_PMC_XRAM_PPFEAR0D,
	68	SPT_PMC_XRAM_PPFEAR1A,
	69	};
	70
	71	#define SPT_PMC_BIT_PMC BIT(0)
	72	#define SPT_PMC_BIT_OPI BIT(1)
	73	#define SPT_PMC_BIT_SPI BIT(2)
	74	#define SPT_PMC_BIT_XHCI BIT(3)
	75	#define SPT_PMC_BIT_SPA BIT(4)
	76	#define SPT_PMC_BIT_SPB BIT(5)
	77	#define SPT_PMC_BIT_SPC BIT(6)
	78	#define SPT_PMC_BIT_GBE BIT(7)
	79
	80	#define SPT_PMC_BIT_SATA BIT(0)
	81	#define SPT_PMC_BIT_HDA_PGD0 BIT(1)
	82	#define SPT_PMC_BIT_HDA_PGD1 BIT(2)
	83	#define SPT_PMC_BIT_HDA_PGD2 BIT(3)
	84	#define SPT_PMC_BIT_HDA_PGD3 BIT(4)
	85	#define SPT_PMC_BIT_RSVD_0B BIT(5)
	86	#define SPT_PMC_BIT_LPSS BIT(6)
	87	#define SPT_PMC_BIT_LPC BIT(7)
	88
	89	#define SPT_PMC_BIT_SMB BIT(0)
	90	#define SPT_PMC_BIT_ISH BIT(1)
	91	#define SPT_PMC_BIT_P2SB BIT(2)
	92	#define SPT_PMC_BIT_DFX BIT(3)
	93	#define SPT_PMC_BIT_SCC BIT(4)
	94	#define SPT_PMC_BIT_RSVD_0C BIT(5)
	95	#define SPT_PMC_BIT_FUSE BIT(6)
	96	#define SPT_PMC_BIT_CAMREA BIT(7)
	97
	98	#define SPT_PMC_BIT_RSVD_0D BIT(0)
	99	#define SPT_PMC_BIT_USB3_OTG BIT(1)
	100	#define SPT_PMC_BIT_EXI BIT(2)
	101	#define SPT_PMC_BIT_CSE BIT(3)
	102	#define SPT_PMC_BIT_CSME_KVM BIT(4)
	103	#define SPT_PMC_BIT_CSME_PMT BIT(5)
	104	#define SPT_PMC_BIT_CSME_CLINK BIT(6)
	105	#define SPT_PMC_BIT_CSME_PTIO BIT(7)
	106
	107	#define SPT_PMC_BIT_CSME_USBR BIT(0)
	108	#define SPT_PMC_BIT_CSME_SUSRAM BIT(1)
	109	#define SPT_PMC_BIT_CSME_SMT BIT(2)
	110	#define SPT_PMC_BIT_RSVD_1A BIT(3)
	111	#define SPT_PMC_BIT_CSME_SMS2 BIT(4)
	112	#define SPT_PMC_BIT_CSME_SMS1 BIT(5)
	113	#define SPT_PMC_BIT_CSME_RTC BIT(6)
	114	#define SPT_PMC_BIT_CSME_PSF BIT(7)
	115
173943b3 RB	116	#define SPT_PMC_BIT_MPHY_LANE0 BIT(0)
	117	#define SPT_PMC_BIT_MPHY_LANE1 BIT(1)
	118	#define SPT_PMC_BIT_MPHY_LANE2 BIT(2)
	119	#define SPT_PMC_BIT_MPHY_LANE3 BIT(3)
	120	#define SPT_PMC_BIT_MPHY_LANE4 BIT(4)
	121	#define SPT_PMC_BIT_MPHY_LANE5 BIT(5)
	122	#define SPT_PMC_BIT_MPHY_LANE6 BIT(6)
	123	#define SPT_PMC_BIT_MPHY_LANE7 BIT(7)
	124
	125	#define SPT_PMC_BIT_MPHY_LANE8 BIT(0)
	126	#define SPT_PMC_BIT_MPHY_LANE9 BIT(1)
	127	#define SPT_PMC_BIT_MPHY_LANE10 BIT(2)
	128	#define SPT_PMC_BIT_MPHY_LANE11 BIT(3)
	129	#define SPT_PMC_BIT_MPHY_LANE12 BIT(4)
	130	#define SPT_PMC_BIT_MPHY_LANE13 BIT(5)
	131	#define SPT_PMC_BIT_MPHY_LANE14 BIT(6)
	132	#define SPT_PMC_BIT_MPHY_LANE15 BIT(7)
	133
fe748227 RB	134	#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0)
	135	#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1)
	136	#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
	137	#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
	138
291101f6	139	/* Cannonlake Power Management Controller register offsets */
4cf2afd6	140	#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
2eb15055 RB	141	#define CNP_PMC_PM_CFG_OFFSET 0x1818
	142	#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
	143	#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
291101f6	144	/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
2eb15055	145	#define CNP_PMC_HOST_PPFEAR0A 0x1D90
291101f6	146
4cf2afd6	147	#define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31)
291101f6	148
2eb15055 RB	149	#define CNP_PMC_MMIO_REG_LEN 0x2000
	150	#define CNP_PPFEAR_NUM_ENTRIES 8
	151	#define CNP_PMC_READ_DISABLE_BIT 22
2d649d97	152	#define CNP_NUM_IP_IGN_ALLOWED 19
2eb15055 RB	153	#define CNP_PMC_LTR_CUR_PLT 0x1B50
	154	#define CNP_PMC_LTR_CUR_ASLT 0x1B54
	155	#define CNP_PMC_LTR_SPA 0x1B60
	156	#define CNP_PMC_LTR_SPB 0x1B64
	157	#define CNP_PMC_LTR_SATA 0x1B68
	158	#define CNP_PMC_LTR_GBE 0x1B6C
	159	#define CNP_PMC_LTR_XHCI 0x1B70
2a13096a	160	#define CNP_PMC_LTR_RESERVED 0x1B74
2eb15055 RB	161	#define CNP_PMC_LTR_ME 0x1B78
	162	#define CNP_PMC_LTR_EVA 0x1B7C
	163	#define CNP_PMC_LTR_SPC 0x1B80
	164	#define CNP_PMC_LTR_AZ 0x1B84
	165	#define CNP_PMC_LTR_LPSS 0x1B8C
	166	#define CNP_PMC_LTR_CAM 0x1B90
	167	#define CNP_PMC_LTR_SPD 0x1B94
	168	#define CNP_PMC_LTR_SPE 0x1B98
	169	#define CNP_PMC_LTR_ESPI 0x1B9C
	170	#define CNP_PMC_LTR_SCC 0x1BA0
	171	#define CNP_PMC_LTR_ISH 0x1BA4
	172	#define CNP_PMC_LTR_CNV 0x1BF0
	173	#define CNP_PMC_LTR_EMMC 0x1BF4
	174	#define CNP_PMC_LTR_UFSX2 0x1BF8
	175
8122e7cd RB	176	#define LTR_DECODED_VAL GENMASK(9, 0)
	177	#define LTR_DECODED_SCALE GENMASK(12, 10)
	178	#define LTR_REQ_SNOOP BIT(15)
	179	#define LTR_REQ_NONSNOOP BIT(31)
	180
6769fdbe RB	181	#define ICL_PPFEAR_NUM_ENTRIES 9
	182	#define ICL_NUM_IP_IGN_ALLOWED 20
	183	#define ICL_PMC_LTR_WIGIG 0x1BFC
	184
0bdfaf42 RB	185	struct pmc_bit_map {
	186	const char *name;
	187	u32 bit_mask;
	188	};
	189
c977b98b SP	190	/**
	191	* struct pmc_reg_map - Structure used to define parameter unique to a
	192	PCH family
	193	* @pfear_sts: Maps name of IP block to PPFEAR* bit
	194	* @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit
	195	* @pll_sts: Maps name of PLL to corresponding bit status
4cf2afd6	196	* @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info
2eb15055	197	* @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets
c977b98b SP	198	* @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
c977b98b SP	199	* @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
c977b98b SP	200	* @regmap_length: Length of memory to map from PWRMBASE address to access
	201	* @ppfear0_offset: PWRMBASE offset to to read PPFEAR*
	202	* @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from
	203	* PPFEAR
	204	* @pm_cfg_offset: PWRMBASE offset to PM_CFG register
	205	* @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
4cf2afd6	206	* @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG*
c977b98b SP	207	*
	208	* Each PCH has unique set of register offsets and bit indexes. This structure
	209	* captures them to have a common implementation.
	210	*/
0bdfaf42 RB	211	struct pmc_reg_map {
0bdfaf42 RB	212	const struct pmc_bit_map *pfear_sts;
173943b3	213	const struct pmc_bit_map *mphy_sts;
fe748227	214	const struct pmc_bit_map *pll_sts;
4cf2afd6	215	const struct pmc_bit_map **slps0_dbg_maps;
2eb15055	216	const struct pmc_bit_map *ltr_show_sts;
c977b98b SP	217	const u32 slp_s0_offset;
c977b98b SP	218	const u32 ltr_ignore_offset;
c977b98b SP	219	const int regmap_length;
	220	const u32 ppfear0_offset;
	221	const int ppfear_buckets;
	222	const u32 pm_cfg_offset;
	223	const int pm_read_disable_bit;
4cf2afd6	224	const u32 slps0_dbg_offset;
2d649d97	225	const u32 ltr_ignore_max;
0bdfaf42	226	};
b740d2e9 RB	227
	228	/**
	229	* struct pmc_dev - pmc device structure
7fc65892	230	* @base_addr: contains pmc base address
b740d2e9	231	* @regbase: pointer to io-remapped memory location
7fc65892 RB	232	* @map: pointer to pmc_reg_map struct that contains platform
	233	* specific attributes
	234	* @dbgfs_dir: path to debugfs interface
	235	* @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
	236	* used to read MPHY PG and PLL status are available
	237	* @mutex_lock: mutex to complete one transcation
b740d2e9 RB	238	*
	239	* pmc_dev contains info about power management controller device.
	240	*/
	241	struct pmc_dev {
	242	u32 base_addr;
	243	void __iomem *regbase;
0bdfaf42 RB	244	const struct pmc_reg_map *map;
0bdfaf42 RB	245	#if IS_ENABLED(CONFIG_DEBUG_FS)
b740d2e9	246	struct dentry *dbgfs_dir;
0bdfaf42	247	#endif /* CONFIG_DEBUG_FS */
173943b3 RB	248	int pmc_xram_read_bit;
173943b3 RB	249	struct mutex lock; /* generic mutex lock for PMC Core */
b740d2e9 RB	250	};
	251
	252	#endif /* PMC_CORE_H */