[linux-2.6-block.git] / drivers / platform / x86 / intel_pmc_core.h

/*
 * Intel Core SoC Power Management Controller Header File
 *
 * Copyright (c) 2016, Intel Corporation.
 * All Rights Reserved.
 *
 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
 *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#ifndef PMC_CORE_H
#define PMC_CORE_H

#define PMC_BASE_ADDR_DEFAULT			0xFE000000

#define SPT_PMC_BASE_ADDR_OFFSET		0x48
#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET	0x13c
#define SPT_PMC_PM_CFG_OFFSET			0x18
#define SPT_PMC_PM_STS_OFFSET			0x1c
#define SPT_PMC_MTPMC_OFFSET			0x20
#define SPT_PMC_MFPMC_OFFSET			0x38
#define SPT_PMC_LTR_IGNORE_OFFSET		0x30C
#define SPT_PMC_MPHY_CORE_STS_0			0x1143
#define SPT_PMC_MPHY_CORE_STS_1			0x1142
#define SPT_PMC_MPHY_COM_STS_0			0x1155
#define SPT_PMC_MMIO_REG_LEN			0x1000
#define SPT_PMC_SLP_S0_RES_COUNTER_STEP		0x64
#define PMC_BASE_ADDR_MASK			~(SPT_PMC_MMIO_REG_LEN - 1)
#define MTPMC_MASK				0xffff0000
#define PPFEAR_MAX_NUM_ENTRIES			5
#define SPT_PPFEAR_NUM_ENTRIES			5
#define SPT_PMC_READ_DISABLE_BIT		0x16
#define SPT_PMC_MSG_FULL_STS_BIT		0x18
#define NUM_RETRIES				100
#define NUM_IP_IGN_ALLOWED			17

/* Sunrise Point: PGD PFET Enable Ack Status Registers */
enum ppfear_regs {
	SPT_PMC_XRAM_PPFEAR0A = 0x590,
	SPT_PMC_XRAM_PPFEAR0B,
	SPT_PMC_XRAM_PPFEAR0C,
	SPT_PMC_XRAM_PPFEAR0D,
	SPT_PMC_XRAM_PPFEAR1A,
};

#define SPT_PMC_BIT_PMC				BIT(0)
#define SPT_PMC_BIT_OPI				BIT(1)
#define SPT_PMC_BIT_SPI				BIT(2)
#define SPT_PMC_BIT_XHCI			BIT(3)
#define SPT_PMC_BIT_SPA				BIT(4)
#define SPT_PMC_BIT_SPB				BIT(5)
#define SPT_PMC_BIT_SPC				BIT(6)
#define SPT_PMC_BIT_GBE				BIT(7)

#define SPT_PMC_BIT_SATA			BIT(0)
#define SPT_PMC_BIT_HDA_PGD0			BIT(1)
#define SPT_PMC_BIT_HDA_PGD1			BIT(2)
#define SPT_PMC_BIT_HDA_PGD2			BIT(3)
#define SPT_PMC_BIT_HDA_PGD3			BIT(4)
#define SPT_PMC_BIT_RSVD_0B			BIT(5)
#define SPT_PMC_BIT_LPSS			BIT(6)
#define SPT_PMC_BIT_LPC				BIT(7)

#define SPT_PMC_BIT_SMB				BIT(0)
#define SPT_PMC_BIT_ISH				BIT(1)
#define SPT_PMC_BIT_P2SB			BIT(2)
#define SPT_PMC_BIT_DFX				BIT(3)
#define SPT_PMC_BIT_SCC				BIT(4)
#define SPT_PMC_BIT_RSVD_0C			BIT(5)
#define SPT_PMC_BIT_FUSE			BIT(6)
#define SPT_PMC_BIT_CAMREA			BIT(7)

#define SPT_PMC_BIT_RSVD_0D			BIT(0)
#define SPT_PMC_BIT_USB3_OTG			BIT(1)
#define SPT_PMC_BIT_EXI				BIT(2)
#define SPT_PMC_BIT_CSE				BIT(3)
#define SPT_PMC_BIT_CSME_KVM			BIT(4)
#define SPT_PMC_BIT_CSME_PMT			BIT(5)
#define SPT_PMC_BIT_CSME_CLINK			BIT(6)
#define SPT_PMC_BIT_CSME_PTIO			BIT(7)

#define SPT_PMC_BIT_CSME_USBR			BIT(0)
#define SPT_PMC_BIT_CSME_SUSRAM			BIT(1)
#define SPT_PMC_BIT_CSME_SMT			BIT(2)
#define SPT_PMC_BIT_RSVD_1A			BIT(3)
#define SPT_PMC_BIT_CSME_SMS2			BIT(4)
#define SPT_PMC_BIT_CSME_SMS1			BIT(5)
#define SPT_PMC_BIT_CSME_RTC			BIT(6)
#define SPT_PMC_BIT_CSME_PSF			BIT(7)

#define SPT_PMC_BIT_MPHY_LANE0			BIT(0)
#define SPT_PMC_BIT_MPHY_LANE1			BIT(1)
#define SPT_PMC_BIT_MPHY_LANE2			BIT(2)
#define SPT_PMC_BIT_MPHY_LANE3			BIT(3)
#define SPT_PMC_BIT_MPHY_LANE4			BIT(4)
#define SPT_PMC_BIT_MPHY_LANE5			BIT(5)
#define SPT_PMC_BIT_MPHY_LANE6			BIT(6)
#define SPT_PMC_BIT_MPHY_LANE7			BIT(7)

#define SPT_PMC_BIT_MPHY_LANE8			BIT(0)
#define SPT_PMC_BIT_MPHY_LANE9			BIT(1)
#define SPT_PMC_BIT_MPHY_LANE10			BIT(2)
#define SPT_PMC_BIT_MPHY_LANE11			BIT(3)
#define SPT_PMC_BIT_MPHY_LANE12			BIT(4)
#define SPT_PMC_BIT_MPHY_LANE13			BIT(5)
#define SPT_PMC_BIT_MPHY_LANE14			BIT(6)
#define SPT_PMC_BIT_MPHY_LANE15			BIT(7)

#define SPT_PMC_BIT_MPHY_CMN_LANE0		BIT(0)
#define SPT_PMC_BIT_MPHY_CMN_LANE1		BIT(1)
#define SPT_PMC_BIT_MPHY_CMN_LANE2		BIT(2)
#define SPT_PMC_BIT_MPHY_CMN_LANE3		BIT(3)

/* Cannonlake Power Management Controller register offsets */
#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET      0x193C
#define CNP_PMC_LTR_IGNORE_OFFSET              0x1B0C
#define CNP_PMC_PM_CFG_OFFSET                  0x1818
/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
#define CNP_PMC_HOST_PPFEAR0A                  0x1D90

#define CNP_PMC_MMIO_REG_LEN                   0x2000
#define CNP_PPFEAR_NUM_ENTRIES                 8
#define CNP_PMC_READ_DISABLE_BIT               22

struct pmc_bit_map {
	const char *name;
	u32 bit_mask;
};

/**
 * struct pmc_reg_map - Structure used to define parameter unique to a
			PCH family
 * @pfear_sts:		Maps name of IP block to PPFEAR* bit
 * @mphy_sts:		Maps name of MPHY lane to MPHY status lane status bit
 * @pll_sts:		Maps name of PLL to corresponding bit status
 * @slp_s0_offset:	PWRMBASE offset to read SLP_S0 residency
 * @ltr_ignore_offset:	PWRMBASE offset to read/write LTR ignore bit
 * @regmap_length:	Length of memory to map from PWRMBASE address to access
 * @ppfear0_offset:	PWRMBASE offset to to read PPFEAR*
 * @ppfear_buckets:	Number of 8 bits blocks to read all IP blocks from
 *			PPFEAR
 * @pm_cfg_offset:	PWRMBASE offset to PM_CFG register
 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
 *
 * Each PCH has unique set of register offsets and bit indexes. This structure
 * captures them to have a common implementation.
 */
struct pmc_reg_map {
	const struct pmc_bit_map *pfear_sts;
	const struct pmc_bit_map *mphy_sts;
	const struct pmc_bit_map *pll_sts;
	const u32 slp_s0_offset;
	const u32 ltr_ignore_offset;
	const int regmap_length;
	const u32 ppfear0_offset;
	const int ppfear_buckets;
	const u32 pm_cfg_offset;
	const int pm_read_disable_bit;
};

/**
 * struct pmc_dev - pmc device structure
 * @base_addr:		contains pmc base address
 * @regbase:		pointer to io-remapped memory location
 * @map:		pointer to pmc_reg_map struct that contains platform
 *			specific attributes
 * @dbgfs_dir:		path to debugfs interface
 * @pmc_xram_read_bit:	flag to indicate whether PMC XRAM shadow registers
 *			used to read MPHY PG and PLL status are available
 * @mutex_lock:		mutex to complete one transcation
 *
 * pmc_dev contains info about power management controller device.
 */
struct pmc_dev {
	u32 base_addr;
	void __iomem *regbase;
	const struct pmc_reg_map *map;
#if IS_ENABLED(CONFIG_DEBUG_FS)
	struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
	int pmc_xram_read_bit;
	struct mutex lock; /* generic mutex lock for PMC Core */
};

#endif /* PMC_CORE_H */
Commit	Line	Data
b740d2e9 RB	1	/*
	2	* Intel Core SoC Power Management Controller Header File
	3	*
	4	* Copyright (c) 2016, Intel Corporation.
	5	* All Rights Reserved.
	6	*
	7	* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
	8	* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms and conditions of the GNU General Public License,
	12	* version 2, as published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	*/
	20
	21	#ifndef PMC_CORE_H
	22	#define PMC_CORE_H
	23
21ae4357	24	#define PMC_BASE_ADDR_DEFAULT 0xFE000000
df2294fb	25
b740d2e9 RB	26	#define SPT_PMC_BASE_ADDR_OFFSET 0x48
b740d2e9 RB	27	#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
173943b3 RB	28	#define SPT_PMC_PM_CFG_OFFSET 0x18
	29	#define SPT_PMC_PM_STS_OFFSET 0x1c
	30	#define SPT_PMC_MTPMC_OFFSET 0x20
	31	#define SPT_PMC_MFPMC_OFFSET 0x38
9c2ee199	32	#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
173943b3 RB	33	#define SPT_PMC_MPHY_CORE_STS_0 0x1143
173943b3 RB	34	#define SPT_PMC_MPHY_CORE_STS_1 0x1142
fe748227	35	#define SPT_PMC_MPHY_COM_STS_0 0x1155
8434709b	36	#define SPT_PMC_MMIO_REG_LEN 0x1000
b740d2e9	37	#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64
8434709b	38	#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
173943b3	39	#define MTPMC_MASK 0xffff0000
c977b98b SP	40	#define PPFEAR_MAX_NUM_ENTRIES 5
c977b98b SP	41	#define SPT_PPFEAR_NUM_ENTRIES 5
173943b3 RB	42	#define SPT_PMC_READ_DISABLE_BIT 0x16
	43	#define SPT_PMC_MSG_FULL_STS_BIT 0x18
	44	#define NUM_RETRIES 100
9c2ee199	45	#define NUM_IP_IGN_ALLOWED 17
0bdfaf42 RB	46
	47	/* Sunrise Point: PGD PFET Enable Ack Status Registers */
	48	enum ppfear_regs {
	49	SPT_PMC_XRAM_PPFEAR0A = 0x590,
	50	SPT_PMC_XRAM_PPFEAR0B,
	51	SPT_PMC_XRAM_PPFEAR0C,
	52	SPT_PMC_XRAM_PPFEAR0D,
	53	SPT_PMC_XRAM_PPFEAR1A,
	54	};
	55
	56	#define SPT_PMC_BIT_PMC BIT(0)
	57	#define SPT_PMC_BIT_OPI BIT(1)
	58	#define SPT_PMC_BIT_SPI BIT(2)
	59	#define SPT_PMC_BIT_XHCI BIT(3)
	60	#define SPT_PMC_BIT_SPA BIT(4)
	61	#define SPT_PMC_BIT_SPB BIT(5)
	62	#define SPT_PMC_BIT_SPC BIT(6)
	63	#define SPT_PMC_BIT_GBE BIT(7)
	64
	65	#define SPT_PMC_BIT_SATA BIT(0)
	66	#define SPT_PMC_BIT_HDA_PGD0 BIT(1)
	67	#define SPT_PMC_BIT_HDA_PGD1 BIT(2)
	68	#define SPT_PMC_BIT_HDA_PGD2 BIT(3)
	69	#define SPT_PMC_BIT_HDA_PGD3 BIT(4)
	70	#define SPT_PMC_BIT_RSVD_0B BIT(5)
	71	#define SPT_PMC_BIT_LPSS BIT(6)
	72	#define SPT_PMC_BIT_LPC BIT(7)
	73
	74	#define SPT_PMC_BIT_SMB BIT(0)
	75	#define SPT_PMC_BIT_ISH BIT(1)
	76	#define SPT_PMC_BIT_P2SB BIT(2)
	77	#define SPT_PMC_BIT_DFX BIT(3)
	78	#define SPT_PMC_BIT_SCC BIT(4)
	79	#define SPT_PMC_BIT_RSVD_0C BIT(5)
	80	#define SPT_PMC_BIT_FUSE BIT(6)
	81	#define SPT_PMC_BIT_CAMREA BIT(7)
	82
	83	#define SPT_PMC_BIT_RSVD_0D BIT(0)
	84	#define SPT_PMC_BIT_USB3_OTG BIT(1)
	85	#define SPT_PMC_BIT_EXI BIT(2)
	86	#define SPT_PMC_BIT_CSE BIT(3)
	87	#define SPT_PMC_BIT_CSME_KVM BIT(4)
	88	#define SPT_PMC_BIT_CSME_PMT BIT(5)
	89	#define SPT_PMC_BIT_CSME_CLINK BIT(6)
	90	#define SPT_PMC_BIT_CSME_PTIO BIT(7)
	91
	92	#define SPT_PMC_BIT_CSME_USBR BIT(0)
	93	#define SPT_PMC_BIT_CSME_SUSRAM BIT(1)
	94	#define SPT_PMC_BIT_CSME_SMT BIT(2)
	95	#define SPT_PMC_BIT_RSVD_1A BIT(3)
	96	#define SPT_PMC_BIT_CSME_SMS2 BIT(4)
	97	#define SPT_PMC_BIT_CSME_SMS1 BIT(5)
	98	#define SPT_PMC_BIT_CSME_RTC BIT(6)
	99	#define SPT_PMC_BIT_CSME_PSF BIT(7)
	100
173943b3 RB	101	#define SPT_PMC_BIT_MPHY_LANE0 BIT(0)
	102	#define SPT_PMC_BIT_MPHY_LANE1 BIT(1)
	103	#define SPT_PMC_BIT_MPHY_LANE2 BIT(2)
	104	#define SPT_PMC_BIT_MPHY_LANE3 BIT(3)
	105	#define SPT_PMC_BIT_MPHY_LANE4 BIT(4)
	106	#define SPT_PMC_BIT_MPHY_LANE5 BIT(5)
	107	#define SPT_PMC_BIT_MPHY_LANE6 BIT(6)
	108	#define SPT_PMC_BIT_MPHY_LANE7 BIT(7)
	109
	110	#define SPT_PMC_BIT_MPHY_LANE8 BIT(0)
	111	#define SPT_PMC_BIT_MPHY_LANE9 BIT(1)
	112	#define SPT_PMC_BIT_MPHY_LANE10 BIT(2)
	113	#define SPT_PMC_BIT_MPHY_LANE11 BIT(3)
	114	#define SPT_PMC_BIT_MPHY_LANE12 BIT(4)
	115	#define SPT_PMC_BIT_MPHY_LANE13 BIT(5)
	116	#define SPT_PMC_BIT_MPHY_LANE14 BIT(6)
	117	#define SPT_PMC_BIT_MPHY_LANE15 BIT(7)
	118
fe748227 RB	119	#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0)
	120	#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1)
	121	#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
	122	#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
	123
291101f6 RB	124	/* Cannonlake Power Management Controller register offsets */
	125	#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
	126	#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
	127	#define CNP_PMC_PM_CFG_OFFSET 0x1818
	128	/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
	129	#define CNP_PMC_HOST_PPFEAR0A 0x1D90
	130
	131	#define CNP_PMC_MMIO_REG_LEN 0x2000
	132	#define CNP_PPFEAR_NUM_ENTRIES 8
	133	#define CNP_PMC_READ_DISABLE_BIT 22
	134
0bdfaf42 RB	135	struct pmc_bit_map {
	136	const char *name;
	137	u32 bit_mask;
	138	};
	139
c977b98b SP	140	/**
	141	* struct pmc_reg_map - Structure used to define parameter unique to a
	142	PCH family
	143	* @pfear_sts: Maps name of IP block to PPFEAR* bit
	144	* @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit
	145	* @pll_sts: Maps name of PLL to corresponding bit status
	146	* @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
	147	* @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
c977b98b SP	148	* @regmap_length: Length of memory to map from PWRMBASE address to access
	149	* @ppfear0_offset: PWRMBASE offset to to read PPFEAR*
	150	* @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from
	151	* PPFEAR
	152	* @pm_cfg_offset: PWRMBASE offset to PM_CFG register
	153	* @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
	154	*
	155	* Each PCH has unique set of register offsets and bit indexes. This structure
	156	* captures them to have a common implementation.
	157	*/
0bdfaf42 RB	158	struct pmc_reg_map {
0bdfaf42 RB	159	const struct pmc_bit_map *pfear_sts;
173943b3	160	const struct pmc_bit_map *mphy_sts;
fe748227	161	const struct pmc_bit_map *pll_sts;
c977b98b SP	162	const u32 slp_s0_offset;
c977b98b SP	163	const u32 ltr_ignore_offset;
c977b98b SP	164	const int regmap_length;
	165	const u32 ppfear0_offset;
	166	const int ppfear_buckets;
	167	const u32 pm_cfg_offset;
	168	const int pm_read_disable_bit;
0bdfaf42	169	};
b740d2e9 RB	170
	171	/**
	172	* struct pmc_dev - pmc device structure
7fc65892	173	* @base_addr: contains pmc base address
b740d2e9	174	* @regbase: pointer to io-remapped memory location
7fc65892 RB	175	* @map: pointer to pmc_reg_map struct that contains platform
	176	* specific attributes
	177	* @dbgfs_dir: path to debugfs interface
	178	* @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
	179	* used to read MPHY PG and PLL status are available
	180	* @mutex_lock: mutex to complete one transcation
b740d2e9 RB	181	*
	182	* pmc_dev contains info about power management controller device.
	183	*/
	184	struct pmc_dev {
	185	u32 base_addr;
	186	void __iomem *regbase;
0bdfaf42 RB	187	const struct pmc_reg_map *map;
0bdfaf42 RB	188	#if IS_ENABLED(CONFIG_DEBUG_FS)
b740d2e9	189	struct dentry *dbgfs_dir;
0bdfaf42	190	#endif /* CONFIG_DEBUG_FS */
173943b3 RB	191	int pmc_xram_read_bit;
173943b3 RB	192	struct mutex lock; /* generic mutex lock for PMC Core */
b740d2e9 RB	193	};
	194
	195	#endif /* PMC_CORE_H */