[linux-2.6-block.git] / drivers / platform / x86 / intel_pmc_core.c

/*
 * Intel Core SoC Power Management Controller Driver
 *
 * Copyright (c) 2016, Intel Corporation.
 * All Rights Reserved.
 *
 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
 *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/pci.h>
#include <linux/uaccess.h>

#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include <asm/pmc_core.h>

#include "intel_pmc_core.h"

static struct pmc_dev pmc;

static const struct pmc_bit_map spt_pll_map[] = {
	{"MIPI PLL",			SPT_PMC_BIT_MPHY_CMN_LANE0},
	{"GEN2 USB2PCIE2 PLL",		SPT_PMC_BIT_MPHY_CMN_LANE1},
	{"DMIPCIE3 PLL",		SPT_PMC_BIT_MPHY_CMN_LANE2},
	{"SATA PLL",			SPT_PMC_BIT_MPHY_CMN_LANE3},
	{},
};

static const struct pmc_bit_map spt_mphy_map[] = {
	{"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
	{"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
	{"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
	{"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
	{"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
	{"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
	{"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
	{"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
	{"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
	{"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
	{"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
	{"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
	{"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
	{"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
	{"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
	{"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
	{},
};

static const struct pmc_bit_map spt_pfear_map[] = {
	{"PMC",				SPT_PMC_BIT_PMC},
	{"OPI-DMI",			SPT_PMC_BIT_OPI},
	{"SPI / eSPI",			SPT_PMC_BIT_SPI},
	{"XHCI",			SPT_PMC_BIT_XHCI},
	{"SPA",				SPT_PMC_BIT_SPA},
	{"SPB",				SPT_PMC_BIT_SPB},
	{"SPC",				SPT_PMC_BIT_SPC},
	{"GBE",				SPT_PMC_BIT_GBE},
	{"SATA",			SPT_PMC_BIT_SATA},
	{"HDA-PGD0",			SPT_PMC_BIT_HDA_PGD0},
	{"HDA-PGD1",			SPT_PMC_BIT_HDA_PGD1},
	{"HDA-PGD2",			SPT_PMC_BIT_HDA_PGD2},
	{"HDA-PGD3",			SPT_PMC_BIT_HDA_PGD3},
	{"RSVD",			SPT_PMC_BIT_RSVD_0B},
	{"LPSS",			SPT_PMC_BIT_LPSS},
	{"LPC",				SPT_PMC_BIT_LPC},
	{"SMB",				SPT_PMC_BIT_SMB},
	{"ISH",				SPT_PMC_BIT_ISH},
	{"P2SB",			SPT_PMC_BIT_P2SB},
	{"DFX",				SPT_PMC_BIT_DFX},
	{"SCC",				SPT_PMC_BIT_SCC},
	{"RSVD",			SPT_PMC_BIT_RSVD_0C},
	{"FUSE",			SPT_PMC_BIT_FUSE},
	{"CAMERA",			SPT_PMC_BIT_CAMREA},
	{"RSVD",			SPT_PMC_BIT_RSVD_0D},
	{"USB3-OTG",			SPT_PMC_BIT_USB3_OTG},
	{"EXI",				SPT_PMC_BIT_EXI},
	{"CSE",				SPT_PMC_BIT_CSE},
	{"CSME_KVM",			SPT_PMC_BIT_CSME_KVM},
	{"CSME_PMT",			SPT_PMC_BIT_CSME_PMT},
	{"CSME_CLINK",			SPT_PMC_BIT_CSME_CLINK},
	{"CSME_PTIO",			SPT_PMC_BIT_CSME_PTIO},
	{"CSME_USBR",			SPT_PMC_BIT_CSME_USBR},
	{"CSME_SUSRAM",			SPT_PMC_BIT_CSME_SUSRAM},
	{"CSME_SMT",			SPT_PMC_BIT_CSME_SMT},
	{"RSVD",			SPT_PMC_BIT_RSVD_1A},
	{"CSME_SMS2",			SPT_PMC_BIT_CSME_SMS2},
	{"CSME_SMS1",			SPT_PMC_BIT_CSME_SMS1},
	{"CSME_RTC",			SPT_PMC_BIT_CSME_RTC},
	{"CSME_PSF",			SPT_PMC_BIT_CSME_PSF},
	{},
};

static const struct pmc_reg_map spt_reg_map = {
	.pfear_sts = spt_pfear_map,
	.mphy_sts = spt_mphy_map,
	.pll_sts = spt_pll_map,
};

static const struct pci_device_id pmc_pci_ids[] = {
	{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID),
					(kernel_ulong_t)&spt_reg_map },
	{ 0, },
};

static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
{
	return readb(pmcdev->regbase + offset);
}

static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
{
	return readl(pmcdev->regbase + reg_offset);
}

static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
							reg_offset, u32 val)
{
	writel(val, pmcdev->regbase + reg_offset);
}

static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
{
	return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
}

/**
 * intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency.
 * @data: Out param that contains current SLP_S0 count.
 *
 * This API currently supports Intel Skylake SoC and Sunrise
 * Point Platform Controller Hub. Future platform support
 * should be added for platforms that support low power modes
 * beyond Package C10 state.
 *
 * SLP_S0_RESIDENCY counter counts in 100 us granularity per
 * step hence function populates the multiplied value in out
 * parameter @data.
 *
 * Return: an error code or 0 on success.
 */
int intel_pmc_slp_s0_counter_read(u32 *data)
{
	struct pmc_dev *pmcdev = &pmc;
	u32 value;

	if (!pmcdev->has_slp_s0_res)
		return -EACCES;

	value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
	*data = pmc_core_adjust_slp_s0_step(value);

	return 0;
}
EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);

static int pmc_core_dev_state_get(void *data, u64 *val)
{
	struct pmc_dev *pmcdev = data;
	u32 value;

	value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
	*val = pmc_core_adjust_slp_s0_step(value);

	return 0;
}

DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");

static int pmc_core_check_read_lock_bit(void)
{
	struct pmc_dev *pmcdev = &pmc;
	u32 value;

	value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_CFG_OFFSET);
	return test_bit(SPT_PMC_READ_DISABLE_BIT,
			(unsigned long *)&value);
}

#if IS_ENABLED(CONFIG_DEBUG_FS)
static void pmc_core_display_map(struct seq_file *s, int index,
				 u8 pf_reg, const struct pmc_bit_map *pf_map)
{
	seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
		   index, pf_map[index].name,
		   pf_map[index].bit_mask & pf_reg ? "Off" : "On");
}

static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
{
	struct pmc_dev *pmcdev = s->private;
	const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
	u8 pf_regs[NUM_ENTRIES];
	int index, iter;

	iter = SPT_PMC_XRAM_PPFEAR0A;

	for (index = 0; index < NUM_ENTRIES; index++, iter++)
		pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);

	for (index = 0; map[index].name; index++)
		pmc_core_display_map(s, index, pf_regs[index / 8], map);

	return 0;
}

static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
}

static const struct file_operations pmc_core_ppfear_ops = {
	.open           = pmc_core_ppfear_sts_open,
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

/* This function should return link status, 0 means ready */
static int pmc_core_mtpmc_link_status(void)
{
	struct pmc_dev *pmcdev = &pmc;
	u32 value;

	value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
	return test_bit(SPT_PMC_MSG_FULL_STS_BIT,
			(unsigned long *)&value);
}

static int pmc_core_send_msg(u32 *addr_xram)
{
	struct pmc_dev *pmcdev = &pmc;
	u32 dest;
	int timeout;

	for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
		if (pmc_core_mtpmc_link_status() == 0)
			break;
		msleep(5);
	}

	if (timeout <= 0 && pmc_core_mtpmc_link_status())
		return -EBUSY;

	dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
	pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
	return 0;
}

static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
{
	struct pmc_dev *pmcdev = s->private;
	const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
	u32 mphy_core_reg_low, mphy_core_reg_high;
	u32 val_low, val_high;
	int index, err = 0;

	if (pmcdev->pmc_xram_read_bit) {
		seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
		return 0;
	}

	mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
	mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);

	mutex_lock(&pmcdev->lock);

	if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
		err = -EBUSY;
		goto out_unlock;
	}

	msleep(10);
	val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);

	if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
		err = -EBUSY;
		goto out_unlock;
	}

	msleep(10);
	val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);

	for (index = 0; map[index].name && index < 8; index++) {
		seq_printf(s, "%-32s\tState: %s\n",
			   map[index].name,
			   map[index].bit_mask & val_low ? "Not power gated" :
			   "Power gated");
	}

	for (index = 8; map[index].name; index++) {
		seq_printf(s, "%-32s\tState: %s\n",
			   map[index].name,
			   map[index].bit_mask & val_high ? "Not power gated" :
			   "Power gated");
	}

out_unlock:
	mutex_unlock(&pmcdev->lock);
	return err;
}

static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
}

static const struct file_operations pmc_core_mphy_pg_ops = {
	.open           = pmc_core_mphy_pg_sts_open,
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

static int pmc_core_pll_show(struct seq_file *s, void *unused)
{
	struct pmc_dev *pmcdev = s->private;
	const struct pmc_bit_map *map = pmcdev->map->pll_sts;
	u32 mphy_common_reg, val;
	int index, err = 0;

	if (pmcdev->pmc_xram_read_bit) {
		seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
		return 0;
	}

	mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
	mutex_lock(&pmcdev->lock);

	if (pmc_core_send_msg(&mphy_common_reg) != 0) {
		err = -EBUSY;
		goto out_unlock;
	}

	/* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
	msleep(10);
	val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);

	for (index = 0; map[index].name ; index++) {
		seq_printf(s, "%-32s\tState: %s\n",
			   map[index].name,
			   map[index].bit_mask & val ? "Active" : "Idle");
	}

out_unlock:
	mutex_unlock(&pmcdev->lock);
	return err;
}

static int pmc_core_pll_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_core_pll_show, inode->i_private);
}

static const struct file_operations pmc_core_pll_ops = {
	.open           = pmc_core_pll_open,
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
*userbuf, size_t count, loff_t *ppos)
{
	struct pmc_dev *pmcdev = &pmc;
	u32 val, buf_size, fd;
	int err = 0;

	buf_size = count < 64 ? count : 64;
	mutex_lock(&pmcdev->lock);

	if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
		err = -EFAULT;
		goto out_unlock;
	}

	if (val > NUM_IP_IGN_ALLOWED) {
		err = -EINVAL;
		goto out_unlock;
	}

	fd = pmc_core_reg_read(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET);
	fd |= (1U << val);
	pmc_core_reg_write(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET, fd);

out_unlock:
	mutex_unlock(&pmcdev->lock);
	return err == 0 ? count : err;
}

static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
{
	return 0;
}

static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
}

static const struct file_operations pmc_core_ltr_ignore_ops = {
	.open           = pmc_core_ltr_ignore_open,
	.read           = seq_read,
	.write          = pmc_core_ltr_ignore_write,
	.llseek         = seq_lseek,
	.release        = single_release,
};

static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
{
	debugfs_remove_recursive(pmcdev->dbgfs_dir);
}

static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
{
	struct dentry *dir, *file;

	dir = debugfs_create_dir("pmc_core", NULL);
	if (!dir)
		return -ENOMEM;

	pmcdev->dbgfs_dir = dir;
	file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
				   dir, pmcdev, &pmc_core_dev_state);
	if (!file)
		goto err;

	file = debugfs_create_file("pch_ip_power_gating_status",
				   S_IFREG | S_IRUGO, dir, pmcdev,
				   &pmc_core_ppfear_ops);
	if (!file)
		goto err;

	file = debugfs_create_file("mphy_core_lanes_power_gating_status",
				   S_IFREG | S_IRUGO, dir, pmcdev,
				   &pmc_core_mphy_pg_ops);
	if (!file)
		goto err;

	file = debugfs_create_file("pll_status",
				   S_IFREG | S_IRUGO, dir, pmcdev,
				   &pmc_core_pll_ops);
	if (!file)
		goto err;

	file = debugfs_create_file("ltr_ignore",
				   S_IFREG | S_IRUGO, dir, pmcdev,
				   &pmc_core_ltr_ignore_ops);

	if (!file)
		goto err;

	return 0;
err:
	pmc_core_dbgfs_unregister(pmcdev);
	return -ENODEV;
}
#else
static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
{
	return 0;
}

static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
{
}
#endif /* CONFIG_DEBUG_FS */

static const struct x86_cpu_id intel_pmc_core_ids[] = {
	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
		(kernel_ulong_t)NULL},
	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
		(kernel_ulong_t)NULL},
	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT,
		(kernel_ulong_t)NULL},
	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT,
		(kernel_ulong_t)NULL},
	{}
};

static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct device *ptr_dev = &dev->dev;
	struct pmc_dev *pmcdev = &pmc;
	const struct x86_cpu_id *cpu_id;
	const struct pmc_reg_map *map = (struct pmc_reg_map *)id->driver_data;
	int err;

	cpu_id = x86_match_cpu(intel_pmc_core_ids);
	if (!cpu_id) {
		dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
		return -EINVAL;
	}

	err = pcim_enable_device(dev);
	if (err < 0) {
		dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
		return err;
	}

	err = pci_read_config_dword(dev,
				    SPT_PMC_BASE_ADDR_OFFSET,
				    &pmcdev->base_addr);
	if (err < 0) {
		dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
		return err;
	}
	pmcdev->base_addr &= PMC_BASE_ADDR_MASK;
	dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);

	pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
					      pmcdev->base_addr,
					      SPT_PMC_MMIO_REG_LEN);
	if (!pmcdev->regbase) {
		dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
		return -ENOMEM;
	}

	mutex_init(&pmcdev->lock);
	pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
	pmcdev->map = map;

	err = pmc_core_dbgfs_register(pmcdev);
	if (err < 0)
		dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");

	pmc.has_slp_s0_res = true;
	return 0;
}

static struct pci_driver intel_pmc_core_driver = {
	.name = "intel_pmc_core",
	.id_table = pmc_pci_ids,
	.probe = pmc_core_probe,
};

builtin_pci_driver(intel_pmc_core_driver);
Commit	Line	Data
b740d2e9 RB	1	/*
	2	* Intel Core SoC Power Management Controller Driver
	3	*
	4	* Copyright (c) 2016, Intel Corporation.
	5	* All Rights Reserved.
	6	*
	7	* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
	8	* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms and conditions of the GNU General Public License,
	12	* version 2, as published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	*/
	20
	21	#include <linux/debugfs.h>
9c2ee199	22	#include <linux/delay.h>
b740d2e9 RB	23	#include <linux/device.h>
	24	#include <linux/init.h>
	25	#include <linux/io.h>
	26	#include <linux/pci.h>
9c2ee199	27	#include <linux/uaccess.h>
b740d2e9 RB	28
b740d2e9 RB	29	#include <asm/cpu_device_id.h>
70e0d117	30	#include <asm/intel-family.h>
b740d2e9 RB	31	#include <asm/pmc_core.h>
	32
	33	#include "intel_pmc_core.h"
	34
	35	static struct pmc_dev pmc;
	36
fe748227 RB	37	static const struct pmc_bit_map spt_pll_map[] = {
	38	{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
	39	{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
	40	{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
	41	{"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
	42	{},
	43	};
	44
173943b3 RB	45	static const struct pmc_bit_map spt_mphy_map[] = {
	46	{"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
	47	{"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
	48	{"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
	49	{"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
	50	{"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
	51	{"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
	52	{"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
	53	{"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
	54	{"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
	55	{"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
	56	{"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
	57	{"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
	58	{"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
	59	{"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
	60	{"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
	61	{"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
	62	{},
	63	};
	64
0bdfaf42 RB	65	static const struct pmc_bit_map spt_pfear_map[] = {
	66	{"PMC", SPT_PMC_BIT_PMC},
	67	{"OPI-DMI", SPT_PMC_BIT_OPI},
	68	{"SPI / eSPI", SPT_PMC_BIT_SPI},
	69	{"XHCI", SPT_PMC_BIT_XHCI},
	70	{"SPA", SPT_PMC_BIT_SPA},
	71	{"SPB", SPT_PMC_BIT_SPB},
	72	{"SPC", SPT_PMC_BIT_SPC},
	73	{"GBE", SPT_PMC_BIT_GBE},
	74	{"SATA", SPT_PMC_BIT_SATA},
	75	{"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
	76	{"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
	77	{"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
	78	{"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
	79	{"RSVD", SPT_PMC_BIT_RSVD_0B},
	80	{"LPSS", SPT_PMC_BIT_LPSS},
	81	{"LPC", SPT_PMC_BIT_LPC},
	82	{"SMB", SPT_PMC_BIT_SMB},
	83	{"ISH", SPT_PMC_BIT_ISH},
	84	{"P2SB", SPT_PMC_BIT_P2SB},
	85	{"DFX", SPT_PMC_BIT_DFX},
	86	{"SCC", SPT_PMC_BIT_SCC},
	87	{"RSVD", SPT_PMC_BIT_RSVD_0C},
	88	{"FUSE", SPT_PMC_BIT_FUSE},
	89	{"CAMERA", SPT_PMC_BIT_CAMREA},
	90	{"RSVD", SPT_PMC_BIT_RSVD_0D},
	91	{"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
	92	{"EXI", SPT_PMC_BIT_EXI},
	93	{"CSE", SPT_PMC_BIT_CSE},
	94	{"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
	95	{"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
	96	{"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
	97	{"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
	98	{"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
	99	{"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
	100	{"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
	101	{"RSVD", SPT_PMC_BIT_RSVD_1A},
	102	{"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
	103	{"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
	104	{"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
	105	{"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
	106	{},
	107	};
	108
	109	static const struct pmc_reg_map spt_reg_map = {
	110	.pfear_sts = spt_pfear_map,
173943b3	111	.mphy_sts = spt_mphy_map,
fe748227	112	.pll_sts = spt_pll_map,
0bdfaf42 RB	113	};
0bdfaf42 RB	114
b740d2e9	115	static const struct pci_device_id pmc_pci_ids[] = {
0bdfaf42 RB	116	{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID),
0bdfaf42 RB	117	(kernel_ulong_t)&spt_reg_map },
b740d2e9 RB	118	{ 0, },
	119	};
	120
0bdfaf42 RB	121	static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
	122	{
	123	return readb(pmcdev->regbase + offset);
	124	}
	125
b740d2e9 RB	126	static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
	127	{
	128	return readl(pmcdev->regbase + reg_offset);
	129	}
	130
173943b3 RB	131	static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
	132	reg_offset, u32 val)
	133	{
	134	writel(val, pmcdev->regbase + reg_offset);
	135	}
	136
b740d2e9 RB	137	static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
	138	{
	139	return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
	140	}
	141
	142	/**
	143	* intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency.
	144	* @data: Out param that contains current SLP_S0 count.
	145	*
	146	* This API currently supports Intel Skylake SoC and Sunrise
	147	* Point Platform Controller Hub. Future platform support
	148	* should be added for platforms that support low power modes
	149	* beyond Package C10 state.
	150	*
	151	* SLP_S0_RESIDENCY counter counts in 100 us granularity per
	152	* step hence function populates the multiplied value in out
	153	* parameter @data.
	154	*
	155	* Return: an error code or 0 on success.
	156	*/
	157	int intel_pmc_slp_s0_counter_read(u32 *data)
	158	{
	159	struct pmc_dev *pmcdev = &pmc;
	160	u32 value;
	161
	162	if (!pmcdev->has_slp_s0_res)
	163	return -EACCES;
	164
	165	value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
	166	*data = pmc_core_adjust_slp_s0_step(value);
	167
	168	return 0;
	169	}
	170	EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);
	171
df2294fb	172	static int pmc_core_dev_state_get(void data, u64 val)
b740d2e9	173	{
df2294fb AS	174	struct pmc_dev *pmcdev = data;
df2294fb AS	175	u32 value;
b740d2e9	176
df2294fb AS	177	value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
df2294fb AS	178	*val = pmc_core_adjust_slp_s0_step(value);
b740d2e9 RB	179
	180	return 0;
	181	}
	182
df2294fb	183	DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
b740d2e9	184
173943b3 RB	185	static int pmc_core_check_read_lock_bit(void)
	186	{
	187	struct pmc_dev *pmcdev = &pmc;
	188	u32 value;
	189
	190	value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_CFG_OFFSET);
	191	return test_bit(SPT_PMC_READ_DISABLE_BIT,
	192	(unsigned long *)&value);
	193	}
	194
0bdfaf42 RB	195	#if IS_ENABLED(CONFIG_DEBUG_FS)
	196	static void pmc_core_display_map(struct seq_file *s, int index,
	197	u8 pf_reg, const struct pmc_bit_map *pf_map)
	198	{
	199	seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
	200	index, pf_map[index].name,
	201	pf_map[index].bit_mask & pf_reg ? "Off" : "On");
	202	}
	203
	204	static int pmc_core_ppfear_sts_show(struct seq_file s, void unused)
	205	{
	206	struct pmc_dev *pmcdev = s->private;
	207	const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
	208	u8 pf_regs[NUM_ENTRIES];
	209	int index, iter;
	210
	211	iter = SPT_PMC_XRAM_PPFEAR0A;
	212
	213	for (index = 0; index < NUM_ENTRIES; index++, iter++)
	214	pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
	215
	216	for (index = 0; map[index].name; index++)
	217	pmc_core_display_map(s, index, pf_regs[index / 8], map);
	218
	219	return 0;
	220	}
	221
	222	static int pmc_core_ppfear_sts_open(struct inode inode, struct file file)
	223	{
	224	return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
	225	}
	226
	227	static const struct file_operations pmc_core_ppfear_ops = {
	228	.open = pmc_core_ppfear_sts_open,
	229	.read = seq_read,
	230	.llseek = seq_lseek,
	231	.release = single_release,
	232	};
	233
173943b3 RB	234	/* This function should return link status, 0 means ready */
	235	static int pmc_core_mtpmc_link_status(void)
	236	{
	237	struct pmc_dev *pmcdev = &pmc;
	238	u32 value;
	239
	240	value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
	241	return test_bit(SPT_PMC_MSG_FULL_STS_BIT,
	242	(unsigned long *)&value);
	243	}
	244
	245	static int pmc_core_send_msg(u32 *addr_xram)
	246	{
	247	struct pmc_dev *pmcdev = &pmc;
	248	u32 dest;
	249	int timeout;
	250
	251	for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
	252	if (pmc_core_mtpmc_link_status() == 0)
	253	break;
	254	msleep(5);
	255	}
	256
	257	if (timeout <= 0 && pmc_core_mtpmc_link_status())
	258	return -EBUSY;
	259
	260	dest = (*addr_xram & MTPMC_MASK) \| (1U << 1);
	261	pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
	262	return 0;
	263	}
	264
	265	static int pmc_core_mphy_pg_sts_show(struct seq_file s, void unused)
	266	{
	267	struct pmc_dev *pmcdev = s->private;
	268	const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
	269	u32 mphy_core_reg_low, mphy_core_reg_high;
	270	u32 val_low, val_high;
	271	int index, err = 0;
	272
	273	if (pmcdev->pmc_xram_read_bit) {
	274	seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
	275	return 0;
	276	}
	277
	278	mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
	279	mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
	280
	281	mutex_lock(&pmcdev->lock);
	282
	283	if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
	284	err = -EBUSY;
	285	goto out_unlock;
	286	}
	287
	288	msleep(10);
	289	val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
	290
	291	if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
	292	err = -EBUSY;
	293	goto out_unlock;
	294	}
	295
	296	msleep(10);
	297	val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
298
299	for (index = 0; map[index].name && index < 8; index++) {
300	seq_printf(s, "%-32s\tState: %s\n",
301	map[index].name,
302	map[index].bit_mask & val_low ? "Not power gated" :
303	"Power gated");
304	}
305
306	for (index = 8; map[index].name; index++) {
307	seq_printf(s, "%-32s\tState: %s\n",
308	map[index].name,
309	map[index].bit_mask & val_high ? "Not power gated" :
310	"Power gated");
311	}
312
313	out_unlock:
314	mutex_unlock(&pmcdev->lock);
315	return err;
316	}
317
318	static int pmc_core_mphy_pg_sts_open(struct inode inode, struct file file)
319	{
320	return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
321	}
322
323	static const struct file_operations pmc_core_mphy_pg_ops = {
324	.open = pmc_core_mphy_pg_sts_open,
325	.read = seq_read,
326	.llseek = seq_lseek,
327	.release = single_release,
328	};
329
fe748227 RB	330	static int pmc_core_pll_show(struct seq_file s, void unused)
	331	{
	332	struct pmc_dev *pmcdev = s->private;
	333	const struct pmc_bit_map *map = pmcdev->map->pll_sts;
	334	u32 mphy_common_reg, val;
	335	int index, err = 0;
	336
	337	if (pmcdev->pmc_xram_read_bit) {
	338	seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
	339	return 0;
	340	}
	341
	342	mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
	343	mutex_lock(&pmcdev->lock);
	344
	345	if (pmc_core_send_msg(&mphy_common_reg) != 0) {
	346	err = -EBUSY;
	347	goto out_unlock;
	348	}
	349
	350	/* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
	351	msleep(10);
	352	val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
	353
	354	for (index = 0; map[index].name ; index++) {
	355	seq_printf(s, "%-32s\tState: %s\n",
	356	map[index].name,
	357	map[index].bit_mask & val ? "Active" : "Idle");
	358	}
	359
	360	out_unlock:
	361	mutex_unlock(&pmcdev->lock);
	362	return err;
	363	}
	364
	365	static int pmc_core_pll_open(struct inode inode, struct file file)
	366	{
	367	return single_open(file, pmc_core_pll_show, inode->i_private);
	368	}
	369
	370	static const struct file_operations pmc_core_pll_ops = {
	371	.open = pmc_core_pll_open,
	372	.read = seq_read,
	373	.llseek = seq_lseek,
	374	.release = single_release,
	375	};
	376
9c2ee199 RB	377	static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
	378	userbuf, size_t count, loff_t ppos)
	379	{
	380	struct pmc_dev *pmcdev = &pmc;
	381	u32 val, buf_size, fd;
	382	int err = 0;
	383
	384	buf_size = count < 64 ? count : 64;
	385	mutex_lock(&pmcdev->lock);
	386
	387	if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
	388	err = -EFAULT;
	389	goto out_unlock;
	390	}
	391
	392	if (val > NUM_IP_IGN_ALLOWED) {
	393	err = -EINVAL;
	394	goto out_unlock;
	395	}
	396
	397	fd = pmc_core_reg_read(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET);
	398	fd \|= (1U << val);
	399	pmc_core_reg_write(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET, fd);
	400
	401	out_unlock:
	402	mutex_unlock(&pmcdev->lock);
	403	return err == 0 ? count : err;
	404	}
	405
	406	static int pmc_core_ltr_ignore_show(struct seq_file s, void unused)
	407	{
	408	return 0;
	409	}
	410
	411	static int pmc_core_ltr_ignore_open(struct inode inode, struct file file)
	412	{
	413	return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
	414	}
	415
	416	static const struct file_operations pmc_core_ltr_ignore_ops = {
	417	.open = pmc_core_ltr_ignore_open,
	418	.read = seq_read,
	419	.write = pmc_core_ltr_ignore_write,
	420	.llseek = seq_lseek,
	421	.release = single_release,
	422	};
	423
b740d2e9 RB	424	static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
	425	{
	426	debugfs_remove_recursive(pmcdev->dbgfs_dir);
	427	}
	428
	429	static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
	430	{
	431	struct dentry dir, file;
	432
	433	dir = debugfs_create_dir("pmc_core", NULL);
127595ed	434	if (!dir)
b740d2e9 RB	435	return -ENOMEM;
	436
	437	pmcdev->dbgfs_dir = dir;
	438	file = debugfs_create_file("slp_s0_residency_usec", S_IFREG \| S_IRUGO,
df2294fb	439	dir, pmcdev, &pmc_core_dev_state);
0bdfaf42 RB	440	if (!file)
0bdfaf42 RB	441	goto err;
b740d2e9	442
0bdfaf42 RB	443	file = debugfs_create_file("pch_ip_power_gating_status",
	444	S_IFREG \| S_IRUGO, dir, pmcdev,
	445	&pmc_core_ppfear_ops);
	446	if (!file)
	447	goto err;
b740d2e9	448
173943b3 RB	449	file = debugfs_create_file("mphy_core_lanes_power_gating_status",
	450	S_IFREG \| S_IRUGO, dir, pmcdev,
	451	&pmc_core_mphy_pg_ops);
	452	if (!file)
	453	goto err;
	454
fe748227 RB	455	file = debugfs_create_file("pll_status",
	456	S_IFREG \| S_IRUGO, dir, pmcdev,
	457	&pmc_core_pll_ops);
	458	if (!file)
	459	goto err;
9c2ee199 RB	460
	461	file = debugfs_create_file("ltr_ignore",
	462	S_IFREG \| S_IRUGO, dir, pmcdev,
	463	&pmc_core_ltr_ignore_ops);
	464
	465	if (!file)
	466	goto err;
0bdfaf42	467
fe748227	468	return 0;
0bdfaf42 RB	469	err:
	470	pmc_core_dbgfs_unregister(pmcdev);
	471	return -ENODEV;
	472	}
	473	#else
	474	static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
	475	{
	476	return 0;
	477	}
	478
	479	static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
	480	{
b740d2e9	481	}
0bdfaf42	482	#endif /* CONFIG_DEBUG_FS */
b740d2e9 RB	483
b740d2e9 RB	484	static const struct x86_cpu_id intel_pmc_core_ids[] = {
70e0d117 DH	485	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
	486	(kernel_ulong_t)NULL},
	487	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
	488	(kernel_ulong_t)NULL},
daf5d143 RB	489	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT,
	490	(kernel_ulong_t)NULL},
	491	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT,
	492	(kernel_ulong_t)NULL},
b740d2e9 RB	493	{}
	494	};
	495
	496	static int pmc_core_probe(struct pci_dev dev, const struct pci_device_id id)
	497	{
	498	struct device *ptr_dev = &dev->dev;
	499	struct pmc_dev *pmcdev = &pmc;
	500	const struct x86_cpu_id *cpu_id;
0bdfaf42	501	const struct pmc_reg_map map = (struct pmc_reg_map )id->driver_data;
b740d2e9 RB	502	int err;
	503
	504	cpu_id = x86_match_cpu(intel_pmc_core_ids);
	505	if (!cpu_id) {
	506	dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
	507	return -EINVAL;
	508	}
	509
	510	err = pcim_enable_device(dev);
	511	if (err < 0) {
	512	dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
	513	return err;
	514	}
	515
	516	err = pci_read_config_dword(dev,
	517	SPT_PMC_BASE_ADDR_OFFSET,
	518	&pmcdev->base_addr);
	519	if (err < 0) {
	520	dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
	521	return err;
	522	}
8434709b	523	pmcdev->base_addr &= PMC_BASE_ADDR_MASK;
b740d2e9 RB	524	dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
	525
	526	pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
	527	pmcdev->base_addr,
	528	SPT_PMC_MMIO_REG_LEN);
	529	if (!pmcdev->regbase) {
	530	dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
	531	return -ENOMEM;
	532	}
	533
173943b3 RB	534	mutex_init(&pmcdev->lock);
	535	pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
	536	pmcdev->map = map;
	537
b740d2e9	538	err = pmc_core_dbgfs_register(pmcdev);
df2294fb AS	539	if (err < 0)
df2294fb AS	540	dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
b740d2e9 RB	541
	542	pmc.has_slp_s0_res = true;
	543	return 0;
	544	}
	545
	546	static struct pci_driver intel_pmc_core_driver = {
	547	.name = "intel_pmc_core",
	548	.id_table = pmc_pci_ids,
	549	.probe = pmc_core_probe,
	550	};
	551
	552	builtin_pci_driver(intel_pmc_core_driver);