[linux-2.6-block.git] / drivers / platform / x86 / intel_pmc_core.c

/*
 * Intel Core SoC Power Management Controller Driver
 *
 * Copyright (c) 2016, Intel Corporation.
 * All Rights Reserved.
 *
 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
 *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/uaccess.h>

#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>

#include "intel_pmc_core.h"

#define ICPU(model, data) \
	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data }

static struct pmc_dev pmc;

static const struct pmc_bit_map spt_pll_map[] = {
	{"MIPI PLL",			SPT_PMC_BIT_MPHY_CMN_LANE0},
	{"GEN2 USB2PCIE2 PLL",		SPT_PMC_BIT_MPHY_CMN_LANE1},
	{"DMIPCIE3 PLL",		SPT_PMC_BIT_MPHY_CMN_LANE2},
	{"SATA PLL",			SPT_PMC_BIT_MPHY_CMN_LANE3},
	{},
};

static const struct pmc_bit_map spt_mphy_map[] = {
	{"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
	{"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
	{"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
	{"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
	{"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
	{"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
	{"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
	{"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
	{"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
	{"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
	{"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
	{"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
	{"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
	{"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
	{"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
	{"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
	{},
};

static const struct pmc_bit_map spt_pfear_map[] = {
	{"PMC",				SPT_PMC_BIT_PMC},
	{"OPI-DMI",			SPT_PMC_BIT_OPI},
	{"SPI / eSPI",			SPT_PMC_BIT_SPI},
	{"XHCI",			SPT_PMC_BIT_XHCI},
	{"SPA",				SPT_PMC_BIT_SPA},
	{"SPB",				SPT_PMC_BIT_SPB},
	{"SPC",				SPT_PMC_BIT_SPC},
	{"GBE",				SPT_PMC_BIT_GBE},
	{"SATA",			SPT_PMC_BIT_SATA},
	{"HDA-PGD0",			SPT_PMC_BIT_HDA_PGD0},
	{"HDA-PGD1",			SPT_PMC_BIT_HDA_PGD1},
	{"HDA-PGD2",			SPT_PMC_BIT_HDA_PGD2},
	{"HDA-PGD3",			SPT_PMC_BIT_HDA_PGD3},
	{"RSVD",			SPT_PMC_BIT_RSVD_0B},
	{"LPSS",			SPT_PMC_BIT_LPSS},
	{"LPC",				SPT_PMC_BIT_LPC},
	{"SMB",				SPT_PMC_BIT_SMB},
	{"ISH",				SPT_PMC_BIT_ISH},
	{"P2SB",			SPT_PMC_BIT_P2SB},
	{"DFX",				SPT_PMC_BIT_DFX},
	{"SCC",				SPT_PMC_BIT_SCC},
	{"RSVD",			SPT_PMC_BIT_RSVD_0C},
	{"FUSE",			SPT_PMC_BIT_FUSE},
	{"CAMERA",			SPT_PMC_BIT_CAMREA},
	{"RSVD",			SPT_PMC_BIT_RSVD_0D},
	{"USB3-OTG",			SPT_PMC_BIT_USB3_OTG},
	{"EXI",				SPT_PMC_BIT_EXI},
	{"CSE",				SPT_PMC_BIT_CSE},
	{"CSME_KVM",			SPT_PMC_BIT_CSME_KVM},
	{"CSME_PMT",			SPT_PMC_BIT_CSME_PMT},
	{"CSME_CLINK",			SPT_PMC_BIT_CSME_CLINK},
	{"CSME_PTIO",			SPT_PMC_BIT_CSME_PTIO},
	{"CSME_USBR",			SPT_PMC_BIT_CSME_USBR},
	{"CSME_SUSRAM",			SPT_PMC_BIT_CSME_SUSRAM},
	{"CSME_SMT",			SPT_PMC_BIT_CSME_SMT},
	{"RSVD",			SPT_PMC_BIT_RSVD_1A},
	{"CSME_SMS2",			SPT_PMC_BIT_CSME_SMS2},
	{"CSME_SMS1",			SPT_PMC_BIT_CSME_SMS1},
	{"CSME_RTC",			SPT_PMC_BIT_CSME_RTC},
	{"CSME_PSF",			SPT_PMC_BIT_CSME_PSF},
	{},
};

static const struct pmc_reg_map spt_reg_map = {
	.pfear_sts = spt_pfear_map,
	.mphy_sts = spt_mphy_map,
	.pll_sts = spt_pll_map,
	.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
	.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
	.regmap_length = SPT_PMC_MMIO_REG_LEN,
	.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
	.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
	.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
	.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
};

static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
{
	return readb(pmcdev->regbase + offset);
}

static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
{
	return readl(pmcdev->regbase + reg_offset);
}

static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
							reg_offset, u32 val)
{
	writel(val, pmcdev->regbase + reg_offset);
}

static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
{
	return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
}

static int pmc_core_dev_state_get(void *data, u64 *val)
{
	struct pmc_dev *pmcdev = data;
	const struct pmc_reg_map *map = pmcdev->map;
	u32 value;

	value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
	*val = pmc_core_adjust_slp_s0_step(value);

	return 0;
}

DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");

static int pmc_core_check_read_lock_bit(void)
{
	struct pmc_dev *pmcdev = &pmc;
	u32 value;

	value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
	return value & BIT(pmcdev->map->pm_read_disable_bit);
}

#if IS_ENABLED(CONFIG_DEBUG_FS)
static void pmc_core_display_map(struct seq_file *s, int index,
				 u8 pf_reg, const struct pmc_bit_map *pf_map)
{
	seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
		   index, pf_map[index].name,
		   pf_map[index].bit_mask & pf_reg ? "Off" : "On");
}

static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
{
	struct pmc_dev *pmcdev = s->private;
	const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
	u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
	int index, iter;

	iter = pmcdev->map->ppfear0_offset;

	for (index = 0; index < pmcdev->map->ppfear_buckets &&
	     index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
		pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);

	for (index = 0; map[index].name; index++)
		pmc_core_display_map(s, index, pf_regs[index / 8], map);

	return 0;
}

static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
}

static const struct file_operations pmc_core_ppfear_ops = {
	.open           = pmc_core_ppfear_sts_open,
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

/* This function should return link status, 0 means ready */
static int pmc_core_mtpmc_link_status(void)
{
	struct pmc_dev *pmcdev = &pmc;
	u32 value;

	value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
	return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
}

static int pmc_core_send_msg(u32 *addr_xram)
{
	struct pmc_dev *pmcdev = &pmc;
	u32 dest;
	int timeout;

	for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
		if (pmc_core_mtpmc_link_status() == 0)
			break;
		msleep(5);
	}

	if (timeout <= 0 && pmc_core_mtpmc_link_status())
		return -EBUSY;

	dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
	pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
	return 0;
}

static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
{
	struct pmc_dev *pmcdev = s->private;
	const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
	u32 mphy_core_reg_low, mphy_core_reg_high;
	u32 val_low, val_high;
	int index, err = 0;

	if (pmcdev->pmc_xram_read_bit) {
		seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
		return 0;
	}

	mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
	mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);

	mutex_lock(&pmcdev->lock);

	if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
		err = -EBUSY;
		goto out_unlock;
	}

	msleep(10);
	val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);

	if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
		err = -EBUSY;
		goto out_unlock;
	}

	msleep(10);
	val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);

	for (index = 0; map[index].name && index < 8; index++) {
		seq_printf(s, "%-32s\tState: %s\n",
			   map[index].name,
			   map[index].bit_mask & val_low ? "Not power gated" :
			   "Power gated");
	}

	for (index = 8; map[index].name; index++) {
		seq_printf(s, "%-32s\tState: %s\n",
			   map[index].name,
			   map[index].bit_mask & val_high ? "Not power gated" :
			   "Power gated");
	}

out_unlock:
	mutex_unlock(&pmcdev->lock);
	return err;
}

static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
}

static const struct file_operations pmc_core_mphy_pg_ops = {
	.open           = pmc_core_mphy_pg_sts_open,
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

static int pmc_core_pll_show(struct seq_file *s, void *unused)
{
	struct pmc_dev *pmcdev = s->private;
	const struct pmc_bit_map *map = pmcdev->map->pll_sts;
	u32 mphy_common_reg, val;
	int index, err = 0;

	if (pmcdev->pmc_xram_read_bit) {
		seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
		return 0;
	}

	mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
	mutex_lock(&pmcdev->lock);

	if (pmc_core_send_msg(&mphy_common_reg) != 0) {
		err = -EBUSY;
		goto out_unlock;
	}

	/* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
	msleep(10);
	val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);

	for (index = 0; map[index].name ; index++) {
		seq_printf(s, "%-32s\tState: %s\n",
			   map[index].name,
			   map[index].bit_mask & val ? "Active" : "Idle");
	}

out_unlock:
	mutex_unlock(&pmcdev->lock);
	return err;
}

static int pmc_core_pll_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_core_pll_show, inode->i_private);
}

static const struct file_operations pmc_core_pll_ops = {
	.open           = pmc_core_pll_open,
	.read           = seq_read,
	.llseek         = seq_lseek,
	.release        = single_release,
};

static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
*userbuf, size_t count, loff_t *ppos)
{
	struct pmc_dev *pmcdev = &pmc;
	const struct pmc_reg_map *map = pmcdev->map;
	u32 val, buf_size, fd;
	int err = 0;

	buf_size = count < 64 ? count : 64;
	mutex_lock(&pmcdev->lock);

	if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
		err = -EFAULT;
		goto out_unlock;
	}

	if (val > NUM_IP_IGN_ALLOWED) {
		err = -EINVAL;
		goto out_unlock;
	}

	fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
	fd |= (1U << val);
	pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);

out_unlock:
	mutex_unlock(&pmcdev->lock);
	return err == 0 ? count : err;
}

static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
{
	return 0;
}

static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
}

static const struct file_operations pmc_core_ltr_ignore_ops = {
	.open           = pmc_core_ltr_ignore_open,
	.read           = seq_read,
	.write          = pmc_core_ltr_ignore_write,
	.llseek         = seq_lseek,
	.release        = single_release,
};

static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
{
	debugfs_remove_recursive(pmcdev->dbgfs_dir);
}

static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
{
	struct dentry *dir;

	dir = debugfs_create_dir("pmc_core", NULL);
	if (!dir)
		return -ENOMEM;

	pmcdev->dbgfs_dir = dir;

	debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
			    &pmc_core_dev_state);

	debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
			    &pmc_core_ppfear_ops);

	debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
			    &pmc_core_ltr_ignore_ops);

	if (pmcdev->map->pll_sts)
		debugfs_create_file("pll_status", 0444, dir, pmcdev,
				    &pmc_core_pll_ops);

	if (pmcdev->map->mphy_sts)
		debugfs_create_file("mphy_core_lanes_power_gating_status",
				    0444, dir, pmcdev,
				    &pmc_core_mphy_pg_ops);

	return 0;
}
#else
static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
{
	return 0;
}

static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
{
}
#endif /* CONFIG_DEBUG_FS */

static const struct x86_cpu_id intel_pmc_core_ids[] = {
	ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map),
	ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
	ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
	ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
	{}
};

MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);

static int __init pmc_core_probe(void)
{
	struct pmc_dev *pmcdev = &pmc;
	const struct x86_cpu_id *cpu_id;
	int err;

	cpu_id = x86_match_cpu(intel_pmc_core_ids);
	if (!cpu_id)
		return -ENODEV;

	pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
	pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
	pmcdev->regbase = ioremap(pmcdev->base_addr,
				  pmcdev->map->regmap_length);
	if (!pmcdev->regbase)
		return -ENOMEM;

	mutex_init(&pmcdev->lock);
	pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();

	err = pmc_core_dbgfs_register(pmcdev);
	if (err < 0) {
		pr_warn(" debugfs register failed.\n");
		iounmap(pmcdev->regbase);
		return err;
	}

	pr_info(" initialized\n");
	return 0;
}
module_init(pmc_core_probe)

static void __exit pmc_core_remove(void)
{
	struct pmc_dev *pmcdev = &pmc;

	pmc_core_dbgfs_unregister(pmcdev);
	mutex_destroy(&pmcdev->lock);
	iounmap(pmcdev->regbase);
}
module_exit(pmc_core_remove)

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel PMC Core Driver");
Commit	Line	Data
b740d2e9 RB	1	/*
	2	* Intel Core SoC Power Management Controller Driver
	3	*
	4	* Copyright (c) 2016, Intel Corporation.
	5	* All Rights Reserved.
	6	*
	7	* Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
	8	* Vishwanath Somayaji <vishwanath.somayaji@intel.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms and conditions of the GNU General Public License,
	12	* version 2, as published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	*/
	20
21ae4357 SP	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21ae4357 SP	22
b740d2e9	23	#include <linux/debugfs.h>
9c2ee199	24	#include <linux/delay.h>
b740d2e9	25	#include <linux/io.h>
2854a0aa	26	#include <linux/module.h>
9c2ee199	27	#include <linux/uaccess.h>
b740d2e9 RB	28
b740d2e9 RB	29	#include <asm/cpu_device_id.h>
70e0d117	30	#include <asm/intel-family.h>
b740d2e9 RB	31
	32	#include "intel_pmc_core.h"
	33
00f8b2fc RB	34	#define ICPU(model, data) \
	35	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data }
	36
b740d2e9 RB	37	static struct pmc_dev pmc;
b740d2e9 RB	38
fe748227 RB	39	static const struct pmc_bit_map spt_pll_map[] = {
	40	{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
	41	{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
	42	{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
	43	{"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
	44	{},
	45	};
	46
173943b3 RB	47	static const struct pmc_bit_map spt_mphy_map[] = {
	48	{"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
	49	{"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
	50	{"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
	51	{"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
	52	{"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
	53	{"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
	54	{"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
	55	{"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
	56	{"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
	57	{"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
	58	{"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
	59	{"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
	60	{"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
	61	{"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
	62	{"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
	63	{"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
	64	{},
	65	};
	66
0bdfaf42 RB	67	static const struct pmc_bit_map spt_pfear_map[] = {
	68	{"PMC", SPT_PMC_BIT_PMC},
	69	{"OPI-DMI", SPT_PMC_BIT_OPI},
	70	{"SPI / eSPI", SPT_PMC_BIT_SPI},
	71	{"XHCI", SPT_PMC_BIT_XHCI},
	72	{"SPA", SPT_PMC_BIT_SPA},
	73	{"SPB", SPT_PMC_BIT_SPB},
	74	{"SPC", SPT_PMC_BIT_SPC},
	75	{"GBE", SPT_PMC_BIT_GBE},
	76	{"SATA", SPT_PMC_BIT_SATA},
	77	{"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
	78	{"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
	79	{"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
	80	{"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
	81	{"RSVD", SPT_PMC_BIT_RSVD_0B},
	82	{"LPSS", SPT_PMC_BIT_LPSS},
	83	{"LPC", SPT_PMC_BIT_LPC},
	84	{"SMB", SPT_PMC_BIT_SMB},
	85	{"ISH", SPT_PMC_BIT_ISH},
	86	{"P2SB", SPT_PMC_BIT_P2SB},
	87	{"DFX", SPT_PMC_BIT_DFX},
	88	{"SCC", SPT_PMC_BIT_SCC},
	89	{"RSVD", SPT_PMC_BIT_RSVD_0C},
	90	{"FUSE", SPT_PMC_BIT_FUSE},
	91	{"CAMERA", SPT_PMC_BIT_CAMREA},
	92	{"RSVD", SPT_PMC_BIT_RSVD_0D},
	93	{"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
	94	{"EXI", SPT_PMC_BIT_EXI},
	95	{"CSE", SPT_PMC_BIT_CSE},
	96	{"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
	97	{"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
	98	{"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
	99	{"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
	100	{"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
	101	{"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
	102	{"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
	103	{"RSVD", SPT_PMC_BIT_RSVD_1A},
	104	{"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
	105	{"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
	106	{"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
	107	{"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
	108	{},
	109	};
	110
	111	static const struct pmc_reg_map spt_reg_map = {
	112	.pfear_sts = spt_pfear_map,
173943b3	113	.mphy_sts = spt_mphy_map,
fe748227	114	.pll_sts = spt_pll_map,
c977b98b SP	115	.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
	116	.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
	117	.regmap_length = SPT_PMC_MMIO_REG_LEN,
	118	.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
	119	.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
	120	.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
	121	.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
0bdfaf42 RB	122	};
0bdfaf42 RB	123
0bdfaf42 RB	124	static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
	125	{
	126	return readb(pmcdev->regbase + offset);
	127	}
	128
b740d2e9 RB	129	static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
	130	{
	131	return readl(pmcdev->regbase + reg_offset);
	132	}
	133
173943b3 RB	134	static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
	135	reg_offset, u32 val)
	136	{
	137	writel(val, pmcdev->regbase + reg_offset);
	138	}
	139
b740d2e9 RB	140	static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
	141	{
	142	return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
	143	}
	144
df2294fb	145	static int pmc_core_dev_state_get(void data, u64 val)
b740d2e9	146	{
df2294fb	147	struct pmc_dev *pmcdev = data;
c977b98b	148	const struct pmc_reg_map *map = pmcdev->map;
df2294fb	149	u32 value;
b740d2e9	150
c977b98b	151	value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
df2294fb	152	*val = pmc_core_adjust_slp_s0_step(value);
b740d2e9 RB	153
	154	return 0;
	155	}
	156
df2294fb	157	DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
b740d2e9	158
173943b3 RB	159	static int pmc_core_check_read_lock_bit(void)
	160	{
	161	struct pmc_dev *pmcdev = &pmc;
	162	u32 value;
	163
c977b98b SP	164	value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
c977b98b SP	165	return value & BIT(pmcdev->map->pm_read_disable_bit);
173943b3 RB	166	}
173943b3 RB	167
0bdfaf42 RB	168	#if IS_ENABLED(CONFIG_DEBUG_FS)
	169	static void pmc_core_display_map(struct seq_file *s, int index,
	170	u8 pf_reg, const struct pmc_bit_map *pf_map)
	171	{
	172	seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
	173	index, pf_map[index].name,
	174	pf_map[index].bit_mask & pf_reg ? "Off" : "On");
	175	}
	176
	177	static int pmc_core_ppfear_sts_show(struct seq_file s, void unused)
	178	{
	179	struct pmc_dev *pmcdev = s->private;
	180	const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
c977b98b	181	u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
0bdfaf42 RB	182	int index, iter;
0bdfaf42 RB	183
c977b98b	184	iter = pmcdev->map->ppfear0_offset;
0bdfaf42	185
c977b98b SP	186	for (index = 0; index < pmcdev->map->ppfear_buckets &&
c977b98b SP	187	index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
0bdfaf42 RB	188	pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
	189
	190	for (index = 0; map[index].name; index++)
	191	pmc_core_display_map(s, index, pf_regs[index / 8], map);
	192
	193	return 0;
	194	}
	195
	196	static int pmc_core_ppfear_sts_open(struct inode inode, struct file file)
	197	{
	198	return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
	199	}
	200
	201	static const struct file_operations pmc_core_ppfear_ops = {
	202	.open = pmc_core_ppfear_sts_open,
	203	.read = seq_read,
	204	.llseek = seq_lseek,
	205	.release = single_release,
	206	};
	207
173943b3 RB	208	/* This function should return link status, 0 means ready */
	209	static int pmc_core_mtpmc_link_status(void)
	210	{
	211	struct pmc_dev *pmcdev = &pmc;
	212	u32 value;
	213
	214	value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
4f24ecff	215	return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
173943b3 RB	216	}
	217
	218	static int pmc_core_send_msg(u32 *addr_xram)
	219	{
	220	struct pmc_dev *pmcdev = &pmc;
	221	u32 dest;
	222	int timeout;
	223
	224	for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
	225	if (pmc_core_mtpmc_link_status() == 0)
	226	break;
	227	msleep(5);
	228	}
	229
	230	if (timeout <= 0 && pmc_core_mtpmc_link_status())
	231	return -EBUSY;
	232
	233	dest = (*addr_xram & MTPMC_MASK) \| (1U << 1);
	234	pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
	235	return 0;
	236	}
	237
	238	static int pmc_core_mphy_pg_sts_show(struct seq_file s, void unused)
	239	{
	240	struct pmc_dev *pmcdev = s->private;
	241	const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
	242	u32 mphy_core_reg_low, mphy_core_reg_high;
	243	u32 val_low, val_high;
	244	int index, err = 0;
	245
	246	if (pmcdev->pmc_xram_read_bit) {
	247	seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
	248	return 0;
	249	}
	250
	251	mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
	252	mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
	253
	254	mutex_lock(&pmcdev->lock);
	255
	256	if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
	257	err = -EBUSY;
	258	goto out_unlock;
	259	}
	260
	261	msleep(10);
	262	val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
	263
	264	if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
	265	err = -EBUSY;
	266	goto out_unlock;
	267	}
	268
	269	msleep(10);
	270	val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
	271
	272	for (index = 0; map[index].name && index < 8; index++) {
	273	seq_printf(s, "%-32s\tState: %s\n",
	274	map[index].name,
	275	map[index].bit_mask & val_low ? "Not power gated" :
	276	"Power gated");
	277	}
	278
	279	for (index = 8; map[index].name; index++) {
280	seq_printf(s, "%-32s\tState: %s\n",
281	map[index].name,
282	map[index].bit_mask & val_high ? "Not power gated" :
283	"Power gated");
284	}
285
286	out_unlock:
287	mutex_unlock(&pmcdev->lock);
288	return err;
289	}
290
291	static int pmc_core_mphy_pg_sts_open(struct inode inode, struct file file)
292	{
293	return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
294	}
295
296	static const struct file_operations pmc_core_mphy_pg_ops = {
297	.open = pmc_core_mphy_pg_sts_open,
298	.read = seq_read,
299	.llseek = seq_lseek,
300	.release = single_release,
301	};
302
fe748227 RB	303	static int pmc_core_pll_show(struct seq_file s, void unused)
	304	{
	305	struct pmc_dev *pmcdev = s->private;
	306	const struct pmc_bit_map *map = pmcdev->map->pll_sts;
	307	u32 mphy_common_reg, val;
	308	int index, err = 0;
	309
	310	if (pmcdev->pmc_xram_read_bit) {
	311	seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
	312	return 0;
	313	}
	314
	315	mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
	316	mutex_lock(&pmcdev->lock);
	317
	318	if (pmc_core_send_msg(&mphy_common_reg) != 0) {
	319	err = -EBUSY;
	320	goto out_unlock;
	321	}
	322
	323	/* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
	324	msleep(10);
	325	val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
	326
	327	for (index = 0; map[index].name ; index++) {
	328	seq_printf(s, "%-32s\tState: %s\n",
	329	map[index].name,
	330	map[index].bit_mask & val ? "Active" : "Idle");
	331	}
	332
	333	out_unlock:
	334	mutex_unlock(&pmcdev->lock);
	335	return err;
	336	}
	337
	338	static int pmc_core_pll_open(struct inode inode, struct file file)
	339	{
	340	return single_open(file, pmc_core_pll_show, inode->i_private);
	341	}
	342
	343	static const struct file_operations pmc_core_pll_ops = {
	344	.open = pmc_core_pll_open,
	345	.read = seq_read,
	346	.llseek = seq_lseek,
	347	.release = single_release,
	348	};
	349
9c2ee199 RB	350	static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
	351	userbuf, size_t count, loff_t ppos)
	352	{
	353	struct pmc_dev *pmcdev = &pmc;
c977b98b	354	const struct pmc_reg_map *map = pmcdev->map;
9c2ee199 RB	355	u32 val, buf_size, fd;
	356	int err = 0;
	357
	358	buf_size = count < 64 ? count : 64;
	359	mutex_lock(&pmcdev->lock);
	360
	361	if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
	362	err = -EFAULT;
	363	goto out_unlock;
	364	}
	365
	366	if (val > NUM_IP_IGN_ALLOWED) {
	367	err = -EINVAL;
	368	goto out_unlock;
	369	}
	370
c977b98b	371	fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
9c2ee199	372	fd \|= (1U << val);
c977b98b	373	pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
9c2ee199 RB	374
	375	out_unlock:
	376	mutex_unlock(&pmcdev->lock);
	377	return err == 0 ? count : err;
	378	}
	379
	380	static int pmc_core_ltr_ignore_show(struct seq_file s, void unused)
	381	{
	382	return 0;
	383	}
	384
	385	static int pmc_core_ltr_ignore_open(struct inode inode, struct file file)
	386	{
	387	return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
	388	}
	389
	390	static const struct file_operations pmc_core_ltr_ignore_ops = {
	391	.open = pmc_core_ltr_ignore_open,
	392	.read = seq_read,
	393	.write = pmc_core_ltr_ignore_write,
	394	.llseek = seq_lseek,
	395	.release = single_release,
	396	};
	397
b740d2e9 RB	398	static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
	399	{
	400	debugfs_remove_recursive(pmcdev->dbgfs_dir);
	401	}
	402
	403	static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
	404	{
750e0f57	405	struct dentry *dir;
b740d2e9 RB	406
b740d2e9 RB	407	dir = debugfs_create_dir("pmc_core", NULL);
127595ed	408	if (!dir)
b740d2e9 RB	409	return -ENOMEM;
	410
	411	pmcdev->dbgfs_dir = dir;
b740d2e9	412
750e0f57 RB	413	debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
750e0f57 RB	414	&pmc_core_dev_state);
b740d2e9	415
750e0f57 RB	416	debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
750e0f57 RB	417	&pmc_core_ppfear_ops);
173943b3	418
750e0f57 RB	419	debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
750e0f57 RB	420	&pmc_core_ltr_ignore_ops);
9c2ee199	421
750e0f57 RB	422	if (pmcdev->map->pll_sts)
	423	debugfs_create_file("pll_status", 0444, dir, pmcdev,
	424	&pmc_core_pll_ops);
9c2ee199	425
750e0f57 RB	426	if (pmcdev->map->mphy_sts)
	427	debugfs_create_file("mphy_core_lanes_power_gating_status",
	428	0444, dir, pmcdev,
	429	&pmc_core_mphy_pg_ops);
0bdfaf42	430
fe748227	431	return 0;
0bdfaf42 RB	432	}
	433	#else
	434	static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
	435	{
	436	return 0;
	437	}
	438
	439	static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
	440	{
b740d2e9	441	}
0bdfaf42	442	#endif /* CONFIG_DEBUG_FS */
b740d2e9 RB	443
b740d2e9 RB	444	static const struct x86_cpu_id intel_pmc_core_ids[] = {
00f8b2fc RB	445	ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map),
	446	ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
	447	ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
	448	ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
b740d2e9 RB	449	{}
	450	};
	451
21ae4357 SP	452	MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
	453
	454	static int __init pmc_core_probe(void)
b740d2e9	455	{
b740d2e9 RB	456	struct pmc_dev *pmcdev = &pmc;
	457	const struct x86_cpu_id *cpu_id;
	458	int err;
	459
	460	cpu_id = x86_match_cpu(intel_pmc_core_ids);
21ae4357 SP	461	if (!cpu_id)
	462	return -ENODEV;
	463
	464	pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
	465	pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
	466	pmcdev->regbase = ioremap(pmcdev->base_addr,
	467	pmcdev->map->regmap_length);
	468	if (!pmcdev->regbase)
b740d2e9	469	return -ENOMEM;
b740d2e9	470
173943b3	471	mutex_init(&pmcdev->lock);
c977b98b	472	pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
173943b3	473
b740d2e9	474	err = pmc_core_dbgfs_register(pmcdev);
21ae4357 SP	475	if (err < 0) {
	476	pr_warn(" debugfs register failed.\n");
	477	iounmap(pmcdev->regbase);
	478	return err;
	479	}
b740d2e9	480
21ae4357	481	pr_info(" initialized\n");
b740d2e9 RB	482	return 0;
b740d2e9 RB	483	}
21ae4357	484	module_init(pmc_core_probe)
b740d2e9	485
21ae4357	486	static void __exit pmc_core_remove(void)
2854a0aa	487	{
21ae4357	488	struct pmc_dev *pmcdev = &pmc;
b740d2e9	489
21ae4357 SP	490	pmc_core_dbgfs_unregister(pmcdev);
	491	mutex_destroy(&pmcdev->lock);
	492	iounmap(pmcdev->regbase);
	493	}
	494	module_exit(pmc_core_remove)
2854a0aa SP	495
	496	MODULE_LICENSE("GPL v2");
	497	MODULE_DESCRIPTION("Intel PMC Core Driver");