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[linux-2.6-block.git] / drivers / platform / x86 / intel_ips.c
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aa7ffc01
JB		 1/*
2 * Copyright (c) 2009-2010 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
aa7ffc01
JB		 13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Authors:
17 * Jesse Barnes <jbarnes@virtuousgeek.org>
18 */
19
20/*
21 * Some Intel Ibex Peak based platforms support so-called "intelligent
22 * power sharing", which allows the CPU and GPU to cooperate to maximize
23 * performance within a given TDP (thermal design point). This driver
24 * performs the coordination between the CPU and GPU, monitors thermal and
25 * power statistics in the platform, and initializes power monitoring
26 * hardware. It also provides a few tunables to control behavior. Its
27 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled
28 * by tracking power and thermal budget; secondarily it can boost turbo
29 * performance by allocating more power or thermal budget to the CPU or GPU
30 * based on available headroom and activity.
31 *
049db626 32 * The basic algorithm is driven by a 5s moving average of temperature. If
aa7ffc01
JB		 33 * thermal headroom is available, the CPU and/or GPU power clamps may be
34 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger,
35 * we scale back the clamp. Aside from trigger events (when we're critically
36 * close or over our TDP) we don't adjust the clamps more than once every
37 * five seconds.
38 *
39 * The thermal device (device 31, function 6) has a set of registers that
40 * are updated by the ME firmware. The ME should also take the clamp values
41 * written to those registers and write them to the CPU, but we currently
42 * bypass that functionality and write the CPU MSR directly.
43 *
44 * UNSUPPORTED:
45 * - dual MCP configs
46 *
47 * TODO:
48 * - handle CPU hotplug
49 * - provide turbo enable/disable api
aa7ffc01
JB		 50 *
51 * Related documents:
52 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2
53 * - CDI 401376 - Ibex Peak EDS
54 * - ref 26037, 26641 - IPS BIOS spec
55 * - ref 26489 - Nehalem BIOS writer's guide
56 * - ref 26921 - Ibex Peak BIOS Specification
57 */
58
59#include <linux/debugfs.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
62#include <linux/kernel.h>
63#include <linux/kthread.h>
64#include <linux/module.h>
65#include <linux/pci.h>
66#include <linux/sched.h>
4f17722c 67#include <linux/sched/loadavg.h>
aa7ffc01
JB		 68#include <linux/seq_file.h>
69#include <linux/string.h>
70#include <linux/tick.h>
71#include <linux/timer.h>
88ca518b 72#include <linux/dmi.h>
aa7ffc01
JB		 73#include <drm/i915_drm.h>
74#include <asm/msr.h>
75#include <asm/processor.h>
63ee41d7 76#include "intel_ips.h"
aa7ffc01 77
2f8e2c87 78#include <linux/io-64-nonatomic-lo-hi.h>
797a796a 79
aa7ffc01
JB		 80#define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32
81
82/*
83 * Package level MSRs for monitor/control
84 */
85#define PLATFORM_INFO 0xce
86#define PLATFORM_TDP (1<<29)
87#define PLATFORM_RATIO (1<<28)
88
89#define IA32_MISC_ENABLE 0x1a0
90#define IA32_MISC_TURBO_EN (1ULL<<38)
91
92#define TURBO_POWER_CURRENT_LIMIT 0x1ac
93#define TURBO_TDC_OVR_EN (1UL<<31)
94#define TURBO_TDC_MASK (0x000000007fff0000UL)
95#define TURBO_TDC_SHIFT (16)
96#define TURBO_TDP_OVR_EN (1UL<<15)
97#define TURBO_TDP_MASK (0x0000000000003fffUL)
98
99/*
100 * Core/thread MSRs for monitoring
101 */
102#define IA32_PERF_CTL 0x199
103#define IA32_PERF_TURBO_DIS (1ULL<<32)
104
105/*
106 * Thermal PCI device regs
107 */
108#define THM_CFG_TBAR 0x10
109#define THM_CFG_TBAR_HI 0x14
110
111#define THM_TSIU 0x00
112#define THM_TSE 0x01
113#define TSE_EN 0xb8
114#define THM_TSS 0x02
115#define THM_TSTR 0x03
116#define THM_TSTTP 0x04
117#define THM_TSCO 0x08
118#define THM_TSES 0x0c
119#define THM_TSGPEN 0x0d
120#define TSGPEN_HOT_LOHI (1<<1)
121#define TSGPEN_CRIT_LOHI (1<<2)
122#define THM_TSPC 0x0e
123#define THM_PPEC 0x10
124#define THM_CTA 0x12
125#define THM_PTA 0x14
126#define PTA_SLOPE_MASK (0xff00)
127#define PTA_SLOPE_SHIFT 8
128#define PTA_OFFSET_MASK (0x00ff)
129#define THM_MGTA 0x16
130#define MGTA_SLOPE_MASK (0xff00)
131#define MGTA_SLOPE_SHIFT 8
132#define MGTA_OFFSET_MASK (0x00ff)
133#define THM_TRC 0x1a
134#define TRC_CORE2_EN (1<<15)
135#define TRC_THM_EN (1<<12)
136#define TRC_C6_WAR (1<<8)
137#define TRC_CORE1_EN (1<<7)
138#define TRC_CORE_PWR (1<<6)
139#define TRC_PCH_EN (1<<5)
140#define TRC_MCH_EN (1<<4)
141#define TRC_DIMM4 (1<<3)
142#define TRC_DIMM3 (1<<2)
143#define TRC_DIMM2 (1<<1)
144#define TRC_DIMM1 (1<<0)
145#define THM_TES 0x20
146#define THM_TEN 0x21
147#define TEN_UPDATE_EN 1
148#define THM_PSC 0x24
149#define PSC_NTG (1<<0) /* No GFX turbo support */
150#define PSC_NTPC (1<<1) /* No CPU turbo support */
151#define PSC_PP_DEF (0<<2) /* Perf policy up to driver */
152#define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */
153#define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */
154#define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */
155#define PSP_PBRT (1<<4) /* BIOS run time support */
156#define THM_CTV1 0x30
157#define CTV_TEMP_ERROR (1<<15)
158#define CTV_TEMP_MASK 0x3f
159#define CTV_
160#define THM_CTV2 0x32
161#define THM_CEC 0x34 /* undocumented power accumulator in joules */
162#define THM_AE 0x3f
163#define THM_HTS 0x50 /* 32 bits */
164#define HTS_PCPL_MASK (0x7fe00000)
165#define HTS_PCPL_SHIFT 21
166#define HTS_GPL_MASK (0x001ff000)
167#define HTS_GPL_SHIFT 12
168#define HTS_PP_MASK (0x00000c00)
169#define HTS_PP_SHIFT 10
170#define HTS_PP_DEF 0
171#define HTS_PP_PROC 1
172#define HTS_PP_BAL 2
173#define HTS_PP_GFX 3
174#define HTS_PCTD_DIS (1<<9)
175#define HTS_GTD_DIS (1<<8)
176#define HTS_PTL_MASK (0x000000fe)
177#define HTS_PTL_SHIFT 1
178#define HTS_NVV (1<<0)
179#define THM_HTSHI 0x54 /* 16 bits */
180#define HTS2_PPL_MASK (0x03ff)
181#define HTS2_PRST_MASK (0x3c00)
182#define HTS2_PRST_SHIFT 10
183#define HTS2_PRST_UNLOADED 0
184#define HTS2_PRST_RUNNING 1
185#define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */
186#define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */
187#define HTS2_PRST_TDISUSR 4 /* user disabled turbo */
188#define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */
189#define HTS2_PRST_TDISPM 6 /* power management disabled turbo */
190#define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */
191#define THM_PTL 0x56
192#define THM_MGTV 0x58
193#define TV_MASK 0x000000000000ff00
194#define TV_SHIFT 8
195#define THM_PTV 0x60
196#define PTV_MASK 0x00ff
197#define THM_MMGPC 0x64
198#define THM_MPPC 0x66
199#define THM_MPCPC 0x68
200#define THM_TSPIEN 0x82
201#define TSPIEN_AUX_LOHI (1<<0)
202#define TSPIEN_HOT_LOHI (1<<1)
203#define TSPIEN_CRIT_LOHI (1<<2)
204#define TSPIEN_AUX2_LOHI (1<<3)
205#define THM_TSLOCK 0x83
206#define THM_ATR 0x84
207#define THM_TOF 0x87
208#define THM_STS 0x98
209#define STS_PCPL_MASK (0x7fe00000)
210#define STS_PCPL_SHIFT 21
211#define STS_GPL_MASK (0x001ff000)
212#define STS_GPL_SHIFT 12
213#define STS_PP_MASK (0x00000c00)
214#define STS_PP_SHIFT 10
215#define STS_PP_DEF 0
216#define STS_PP_PROC 1
217#define STS_PP_BAL 2
218#define STS_PP_GFX 3
219#define STS_PCTD_DIS (1<<9)
220#define STS_GTD_DIS (1<<8)
221#define STS_PTL_MASK (0x000000fe)
222#define STS_PTL_SHIFT 1
223#define STS_NVV (1<<0)
224#define THM_SEC 0x9c
225#define SEC_ACK (1<<0)
226#define THM_TC3 0xa4
227#define THM_TC1 0xa8
228#define STS_PPL_MASK (0x0003ff00)
229#define STS_PPL_SHIFT 16
230#define THM_TC2 0xac
231#define THM_DTV 0xb0
232#define THM_ITV 0xd8
6230d18c 233#define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */
aa7ffc01
JB		 234#define ITV_ME_SEQNO_SHIFT (16)
235#define ITV_MCH_TEMP_MASK 0x0000ff00
236#define ITV_MCH_TEMP_SHIFT (8)
237#define ITV_PCH_TEMP_MASK 0x000000ff
238
239#define thm_readb(off) readb(ips->regmap + (off))
240#define thm_readw(off) readw(ips->regmap + (off))
241#define thm_readl(off) readl(ips->regmap + (off))
242#define thm_readq(off) readq(ips->regmap + (off))
243
244#define thm_writeb(off, val) writeb((val), ips->regmap + (off))
245#define thm_writew(off, val) writew((val), ips->regmap + (off))
246#define thm_writel(off, val) writel((val), ips->regmap + (off))
247
248static const int IPS_ADJUST_PERIOD = 5000; /* ms */
63ee41d7 249static bool late_i915_load = false;
aa7ffc01
JB		 250
251/* For initial average collection */
252static const int IPS_SAMPLE_PERIOD = 200; /* ms */
253static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */
254#define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)
255
256/* Per-SKU limits */
257struct ips_mcp_limits {
aa7ffc01
JB		 258 int mcp_power_limit; /* mW units */
259 int core_power_limit;
260 int mch_power_limit;
261 int core_temp_limit; /* degrees C */
262 int mch_temp_limit;
263};
264
265/* Max temps are -10 degrees C to avoid PROCHOT# */
266
cfa57fd9 267static struct ips_mcp_limits ips_sv_limits = {
aa7ffc01
JB		 268 .mcp_power_limit = 35000,
269 .core_power_limit = 29000,
270 .mch_power_limit = 20000,
271 .core_temp_limit = 95,
272 .mch_temp_limit = 90
273};
274
cfa57fd9 275static struct ips_mcp_limits ips_lv_limits = {
aa7ffc01
JB		 276 .mcp_power_limit = 25000,
277 .core_power_limit = 21000,
278 .mch_power_limit = 13000,
279 .core_temp_limit = 95,
280 .mch_temp_limit = 90
281};
282
cfa57fd9 283static struct ips_mcp_limits ips_ulv_limits = {
aa7ffc01
JB		 284 .mcp_power_limit = 18000,
285 .core_power_limit = 14000,
286 .mch_power_limit = 11000,
287 .core_temp_limit = 95,
288 .mch_temp_limit = 90
289};
290
291struct ips_driver {
d2fa170a 292 struct device *dev;
f5b33d94 293 void __iomem *regmap;
8b8bd6d2
AS		 294 int irq;
295
aa7ffc01
JB		 296 struct task_struct *monitor;
297 struct task_struct *adjust;
298 struct dentry *debug_root;
fbc15e30 299 struct timer_list timer;
aa7ffc01
JB		 300
301 /* Average CPU core temps (all averages in .01 degrees C for precision) */
302 u16 ctv1_avg_temp;
303 u16 ctv2_avg_temp;
304 /* GMCH average */
305 u16 mch_avg_temp;
306 /* Average for the CPU (both cores?) */
307 u16 mcp_avg_temp;
308 /* Average power consumption (in mW) */
309 u32 cpu_avg_power;
310 u32 mch_avg_power;
311
312 /* Offset values */
313 u16 cta_val;
314 u16 pta_val;
315 u16 mgta_val;
316
317 /* Maximums & prefs, protected by turbo status lock */
318 spinlock_t turbo_status_lock;
319 u16 mcp_temp_limit;
320 u16 mcp_power_limit;
321 u16 core_power_limit;
322 u16 mch_power_limit;
323 bool cpu_turbo_enabled;
324 bool __cpu_turbo_on;
325 bool gpu_turbo_enabled;
326 bool __gpu_turbo_on;
327 bool gpu_preferred;
328 bool poll_turbo_status;
329 bool second_cpu;
354aeeb1 330 bool turbo_toggle_allowed;
aa7ffc01
JB		 331 struct ips_mcp_limits *limits;
332
333 /* Optional MCH interfaces for if i915 is in use */
334 unsigned long (*read_mch_val)(void);
335 bool (*gpu_raise)(void);
336 bool (*gpu_lower)(void);
337 bool (*gpu_busy)(void);
338 bool (*gpu_turbo_disable)(void);
339
340 /* For restoration at unload */
341 u64 orig_turbo_limit;
342 u64 orig_turbo_ratios;
343};
344
63ee41d7
EA		 345static bool
346ips_gpu_turbo_enabled(struct ips_driver *ips);
347
aa7ffc01
JB		 348/**
349 * ips_cpu_busy - is CPU busy?
350 * @ips: IPS driver struct
351 *
352 * Check CPU for load to see whether we should increase its thermal budget.
353 *
354 * RETURNS:
355 * True if the CPU could use more power, false otherwise.
356 */
357static bool ips_cpu_busy(struct ips_driver *ips)
358{
359 if ((avenrun[0] >> FSHIFT) > 1)
360 return true;
361
362 return false;
363}
364
365/**
366 * ips_cpu_raise - raise CPU power clamp
367 * @ips: IPS driver struct
368 *
369 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for
370 * this platform.
371 *
372 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as
373 * long as we haven't hit the TDP limit for the SKU).
374 */
375static void ips_cpu_raise(struct ips_driver *ips)
376{
377 u64 turbo_override;
378 u16 cur_tdp_limit, new_tdp_limit;
379
380 if (!ips->cpu_turbo_enabled)
381 return;
382
383 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
384
385 cur_tdp_limit = turbo_override & TURBO_TDP_MASK;
386 new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */
387
388 /* Clamp to SKU TDP limit */
389 if (((new_tdp_limit * 10) / 8) > ips->core_power_limit)
390 new_tdp_limit = cur_tdp_limit;
391
392 thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8);
393
70fda70a 394 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN;
aa7ffc01
JB		 395 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
396
397 turbo_override &= ~TURBO_TDP_MASK;
398 turbo_override |= new_tdp_limit;
399
400 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
401}
402
403/**
404 * ips_cpu_lower - lower CPU power clamp
405 * @ips: IPS driver struct
406 *
407 * Lower CPU power clamp b %IPS_CPU_STEP if possible.
408 *
409 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going
410 * as low as the platform limits will allow (though we could go lower there
411 * wouldn't be much point).
412 */
413static void ips_cpu_lower(struct ips_driver *ips)
414{
415 u64 turbo_override;
416 u16 cur_limit, new_limit;
417
418 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
419
420 cur_limit = turbo_override & TURBO_TDP_MASK;
421 new_limit = cur_limit - 8; /* 1W decrease */
422
423 /* Clamp to SKU TDP limit */
d24a9da5 424 if (new_limit < (ips->orig_turbo_limit & TURBO_TDP_MASK))
aa7ffc01
JB		 425 new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK;
426
427 thm_writew(THM_MPCPC, (new_limit * 10) / 8);
428
70fda70a 429 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN;
aa7ffc01
JB		 430 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
431
432 turbo_override &= ~TURBO_TDP_MASK;
433 turbo_override |= new_limit;
434
435 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
436}
437
438/**
439 * do_enable_cpu_turbo - internal turbo enable function
440 * @data: unused
441 *
442 * Internal function for actually updating MSRs. When we enable/disable
443 * turbo, we need to do it on each CPU; this function is the one called
444 * by on_each_cpu() when needed.
445 */
446static void do_enable_cpu_turbo(void *data)
447{
448 u64 perf_ctl;
449
450 rdmsrl(IA32_PERF_CTL, perf_ctl);
451 if (perf_ctl & IA32_PERF_TURBO_DIS) {
452 perf_ctl &= ~IA32_PERF_TURBO_DIS;
453 wrmsrl(IA32_PERF_CTL, perf_ctl);
454 }
455}
456
457/**
458 * ips_enable_cpu_turbo - enable turbo mode on all CPUs
459 * @ips: IPS driver struct
460 *
461 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on
462 * all logical threads.
463 */
464static void ips_enable_cpu_turbo(struct ips_driver *ips)
465{
466 /* Already on, no need to mess with MSRs */
467 if (ips->__cpu_turbo_on)
468 return;
469
354aeeb1
JB		 470 if (ips->turbo_toggle_allowed)
471 on_each_cpu(do_enable_cpu_turbo, ips, 1);
aa7ffc01
JB		 472
473 ips->__cpu_turbo_on = true;
474}
475
476/**
477 * do_disable_cpu_turbo - internal turbo disable function
478 * @data: unused
479 *
480 * Internal function for actually updating MSRs. When we enable/disable
481 * turbo, we need to do it on each CPU; this function is the one called
482 * by on_each_cpu() when needed.
483 */
484static void do_disable_cpu_turbo(void *data)
485{
486 u64 perf_ctl;
487
488 rdmsrl(IA32_PERF_CTL, perf_ctl);
489 if (!(perf_ctl & IA32_PERF_TURBO_DIS)) {
490 perf_ctl |= IA32_PERF_TURBO_DIS;
491 wrmsrl(IA32_PERF_CTL, perf_ctl);
492 }
493}
494
495/**
496 * ips_disable_cpu_turbo - disable turbo mode on all CPUs
497 * @ips: IPS driver struct
498 *
499 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on
500 * all logical threads.
501 */
502static void ips_disable_cpu_turbo(struct ips_driver *ips)
503{
504 /* Already off, leave it */
505 if (!ips->__cpu_turbo_on)
506 return;
507
354aeeb1
JB		 508 if (ips->turbo_toggle_allowed)
509 on_each_cpu(do_disable_cpu_turbo, ips, 1);
aa7ffc01
JB		 510
511 ips->__cpu_turbo_on = false;
512}
513
514/**
515 * ips_gpu_busy - is GPU busy?
516 * @ips: IPS driver struct
517 *
518 * Check GPU for load to see whether we should increase its thermal budget.
519 * We need to call into the i915 driver in this case.
520 *
521 * RETURNS:
522 * True if the GPU could use more power, false otherwise.
523 */
524static bool ips_gpu_busy(struct ips_driver *ips)
525{
63ee41d7 526 if (!ips_gpu_turbo_enabled(ips))
0385e521
JB		 527 return false;
528
529 return ips->gpu_busy();
aa7ffc01
JB		 530}
531
532/**
533 * ips_gpu_raise - raise GPU power clamp
534 * @ips: IPS driver struct
535 *
536 * Raise the GPU frequency/power if possible. We need to call into the
537 * i915 driver in this case.
538 */
539static void ips_gpu_raise(struct ips_driver *ips)
540{
63ee41d7 541 if (!ips_gpu_turbo_enabled(ips))
aa7ffc01
JB		 542 return;
543
544 if (!ips->gpu_raise())
545 ips->gpu_turbo_enabled = false;
546
547 return;
548}
549
550/**
551 * ips_gpu_lower - lower GPU power clamp
552 * @ips: IPS driver struct
553 *
554 * Lower GPU frequency/power if possible. Need to call i915.
555 */
556static void ips_gpu_lower(struct ips_driver *ips)
557{
63ee41d7 558 if (!ips_gpu_turbo_enabled(ips))
aa7ffc01
JB		 559 return;
560
561 if (!ips->gpu_lower())
562 ips->gpu_turbo_enabled = false;
563
564 return;
565}
566
567/**
568 * ips_enable_gpu_turbo - notify the gfx driver turbo is available
569 * @ips: IPS driver struct
570 *
571 * Call into the graphics driver indicating that it can safely use
572 * turbo mode.
573 */
574static void ips_enable_gpu_turbo(struct ips_driver *ips)
575{
576 if (ips->__gpu_turbo_on)
577 return;
578 ips->__gpu_turbo_on = true;
579}
580
581/**
582 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode
583 * @ips: IPS driver struct
584 *
585 * Request that the graphics driver disable turbo mode.
586 */
587static void ips_disable_gpu_turbo(struct ips_driver *ips)
588{
589 /* Avoid calling i915 if turbo is already disabled */
590 if (!ips->__gpu_turbo_on)
591 return;
592
593 if (!ips->gpu_turbo_disable())
d2fa170a 594 dev_err(ips->dev, "failed to disable graphics turbo\n");
aa7ffc01
JB		 595 else
596 ips->__gpu_turbo_on = false;
597}
598
599/**
600 * mcp_exceeded - check whether we're outside our thermal & power limits
601 * @ips: IPS driver struct
602 *
603 * Check whether the MCP is over its thermal or power budget.
604 */
605static bool mcp_exceeded(struct ips_driver *ips)
606{
607 unsigned long flags;
608 bool ret = false;
a8c096ad
TG		 609 u32 temp_limit;
610 u32 avg_power;
aa7ffc01
JB		 611
612 spin_lock_irqsave(&ips->turbo_status_lock, flags);
a8c096ad
TG		 613
614 temp_limit = ips->mcp_temp_limit * 100;
c264c651 615 if (ips->mcp_avg_temp > temp_limit)
aa7ffc01 616 ret = true;
aa7ffc01 617
a8c096ad 618 avg_power = ips->cpu_avg_power + ips->mch_avg_power;
c264c651 619 if (avg_power > ips->mcp_power_limit)
a8c096ad 620 ret = true;
a8c096ad
TG		 621
622 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
aa7ffc01
JB		 623
624 return ret;
625}
626
627/**
628 * cpu_exceeded - check whether a CPU core is outside its limits
629 * @ips: IPS driver struct
630 * @cpu: CPU number to check
631 *
632 * Check a given CPU's average temp or power is over its limit.
633 */
634static bool cpu_exceeded(struct ips_driver *ips, int cpu)
635{
636 unsigned long flags;
637 int avg;
638 bool ret = false;
639
640 spin_lock_irqsave(&ips->turbo_status_lock, flags);
641 avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp;
642 if (avg > (ips->limits->core_temp_limit * 100))
643 ret = true;
0385e521 644 if (ips->cpu_avg_power > ips->core_power_limit * 100)
aa7ffc01
JB		 645 ret = true;
646 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
647
648 if (ret)
d2fa170a 649 dev_info(ips->dev, "CPU power or thermal limit exceeded\n");
aa7ffc01
JB		 650
651 return ret;
652}
653
654/**
655 * mch_exceeded - check whether the GPU is over budget
656 * @ips: IPS driver struct
657 *
658 * Check the MCH temp & power against their maximums.
659 */
660static bool mch_exceeded(struct ips_driver *ips)
661{
662 unsigned long flags;
663 bool ret = false;
664
665 spin_lock_irqsave(&ips->turbo_status_lock, flags);
666 if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100))
667 ret = true;
0385e521
JB		 668 if (ips->mch_avg_power > ips->mch_power_limit)
669 ret = true;
aa7ffc01
JB		 670 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
671
672 return ret;
673}
674
eceab272
JB		 675/**
676 * verify_limits - verify BIOS provided limits
677 * @ips: IPS structure
678 *
679 * BIOS can optionally provide non-default limits for power and temp. Check
680 * them here and use the defaults if the BIOS values are not provided or
681 * are otherwise unusable.
682 */
683static void verify_limits(struct ips_driver *ips)
684{
685 if (ips->mcp_power_limit < ips->limits->mcp_power_limit ||
686 ips->mcp_power_limit > 35000)
687 ips->mcp_power_limit = ips->limits->mcp_power_limit;
688
689 if (ips->mcp_temp_limit < ips->limits->core_temp_limit ||
690 ips->mcp_temp_limit < ips->limits->mch_temp_limit ||
691 ips->mcp_temp_limit > 150)
692 ips->mcp_temp_limit = min(ips->limits->core_temp_limit,
693 ips->limits->mch_temp_limit);
694}
695
aa7ffc01
JB		 696/**
697 * update_turbo_limits - get various limits & settings from regs
698 * @ips: IPS driver struct
699 *
700 * Update the IPS power & temp limits, along with turbo enable flags,
701 * based on latest register contents.
702 *
703 * Used at init time and for runtime BIOS support, which requires polling
704 * the regs for updates (as a result of AC->DC transition for example).
705 *
706 * LOCKING:
707 * Caller must hold turbo_status_lock (outside of init)
708 */
709static void update_turbo_limits(struct ips_driver *ips)
710{
711 u32 hts = thm_readl(THM_HTS);
712
713 ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS);
96f3823f
JB		 714 /*
715 * Disable turbo for now, until we can figure out why the power figures
716 * are wrong
717 */
718 ips->cpu_turbo_enabled = false;
719
070c0ee1
AW		 720 if (ips->gpu_busy)
721 ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS);
96f3823f 722
aa7ffc01
JB		 723 ips->core_power_limit = thm_readw(THM_MPCPC);
724 ips->mch_power_limit = thm_readw(THM_MMGPC);
725 ips->mcp_temp_limit = thm_readw(THM_PTL);
726 ips->mcp_power_limit = thm_readw(THM_MPPC);
727
eceab272 728 verify_limits(ips);
aa7ffc01
JB		 729 /* Ignore BIOS CPU vs GPU pref */
730}
731
732/**
733 * ips_adjust - adjust power clamp based on thermal state
734 * @data: ips driver structure
735 *
736 * Wake up every 5s or so and check whether we should adjust the power clamp.
737 * Check CPU and GPU load to determine which needs adjustment. There are
738 * several things to consider here:
739 * - do we need to adjust up or down?
740 * - is CPU busy?
741 * - is GPU busy?
742 * - is CPU in turbo?
743 * - is GPU in turbo?
744 * - is CPU or GPU preferred? (CPU is default)
745 *
746 * So, given the above, we do the following:
747 * - up (TDP available)
748 * - CPU not busy, GPU not busy - nothing
749 * - CPU busy, GPU not busy - adjust CPU up
750 * - CPU not busy, GPU busy - adjust GPU up
751 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from
752 * non-preferred unit if necessary
753 * - down (at TDP limit)
754 * - adjust both CPU and GPU down if possible
755 *
756 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu-
757cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing
758cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu-
759cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu-
760cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu-
761 *
762 */
763static int ips_adjust(void *data)
764{
765 struct ips_driver *ips = data;
766 unsigned long flags;
767
d2fa170a 768 dev_dbg(ips->dev, "starting ips-adjust thread\n");
aa7ffc01
JB		 769
770 /*
771 * Adjust CPU and GPU clamps every 5s if needed. Doing it more
772 * often isn't recommended due to ME interaction.
773 */
774 do {
775 bool cpu_busy = ips_cpu_busy(ips);
776 bool gpu_busy = ips_gpu_busy(ips);
777
778 spin_lock_irqsave(&ips->turbo_status_lock, flags);
779 if (ips->poll_turbo_status)
780 update_turbo_limits(ips);
781 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
782
783 /* Update turbo status if necessary */
784 if (ips->cpu_turbo_enabled)
785 ips_enable_cpu_turbo(ips);
786 else
787 ips_disable_cpu_turbo(ips);
788
789 if (ips->gpu_turbo_enabled)
790 ips_enable_gpu_turbo(ips);
791 else
792 ips_disable_gpu_turbo(ips);
793
794 /* We're outside our comfort zone, crank them down */
0385e521 795 if (mcp_exceeded(ips)) {
aa7ffc01
JB		 796 ips_cpu_lower(ips);
797 ips_gpu_lower(ips);
798 goto sleep;
799 }
800
801 if (!cpu_exceeded(ips, 0) && cpu_busy)
802 ips_cpu_raise(ips);
803 else
804 ips_cpu_lower(ips);
805
806 if (!mch_exceeded(ips) && gpu_busy)
807 ips_gpu_raise(ips);
808 else
809 ips_gpu_lower(ips);
810
811sleep:
812 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD));
813 } while (!kthread_should_stop());
814
d2fa170a 815 dev_dbg(ips->dev, "ips-adjust thread stopped\n");
aa7ffc01
JB		 816
817 return 0;
818}
819
820/*
821 * Helpers for reading out temp/power values and calculating their
822 * averages for the decision making and monitoring functions.
823 */
824
825static u16 calc_avg_temp(struct ips_driver *ips, u16 *array)
826{
827 u64 total = 0;
828 int i;
829 u16 avg;
830
831 for (i = 0; i < IPS_SAMPLE_COUNT; i++)
832 total += (u64)(array[i] * 100);
833
834 do_div(total, IPS_SAMPLE_COUNT);
835
836 avg = (u16)total;
837
838 return avg;
839}
840
841static u16 read_mgtv(struct ips_driver *ips)
842{
843 u16 ret;
844 u64 slope, offset;
845 u64 val;
846
847 val = thm_readq(THM_MGTV);
848 val = (val & TV_MASK) >> TV_SHIFT;
849
850 slope = offset = thm_readw(THM_MGTA);
851 slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT;
852 offset = offset & MGTA_OFFSET_MASK;
853
854 ret = ((val * slope + 0x40) >> 7) + offset;
855
0385e521 856 return 0; /* MCH temp reporting buggy */
aa7ffc01
JB		 857}
858
859static u16 read_ptv(struct ips_driver *ips)
860{
861 u16 val, slope, offset;
862
863 slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT;
864 offset = ips->pta_val & PTA_OFFSET_MASK;
865
866 val = thm_readw(THM_PTV) & PTV_MASK;
867
868 return val;
869}
870
871static u16 read_ctv(struct ips_driver *ips, int cpu)
872{
873 int reg = cpu ? THM_CTV2 : THM_CTV1;
874 u16 val;
875
876 val = thm_readw(reg);
877 if (!(val & CTV_TEMP_ERROR))
878 val = (val) >> 6; /* discard fractional component */
879 else
880 val = 0;
881
882 return val;
883}
884
885static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period)
886{
887 u32 val;
888 u32 ret;
889
890 /*
891 * CEC is in joules/65535. Take difference over time to
892 * get watts.
893 */
894 val = thm_readl(THM_CEC);
895
896 /* period is in ms and we want mW */
897 ret = (((val - *last) * 1000) / period);
898 ret = (ret * 1000) / 65535;
899 *last = val;
900
96f3823f 901 return 0;
aa7ffc01
JB		 902}
903
904static const u16 temp_decay_factor = 2;
905static u16 update_average_temp(u16 avg, u16 val)
906{
907 u16 ret;
908
909 /* Multiply by 100 for extra precision */
910 ret = (val * 100 / temp_decay_factor) +
911 (((temp_decay_factor - 1) * avg) / temp_decay_factor);
912 return ret;
913}
914
915static const u16 power_decay_factor = 2;
916static u16 update_average_power(u32 avg, u32 val)
917{
918 u32 ret;
919
920 ret = (val / power_decay_factor) +
921 (((power_decay_factor - 1) * avg) / power_decay_factor);
922
923 return ret;
924}
925
926static u32 calc_avg_power(struct ips_driver *ips, u32 *array)
927{
928 u64 total = 0;
929 u32 avg;
930 int i;
931
932 for (i = 0; i < IPS_SAMPLE_COUNT; i++)
933 total += array[i];
934
935 do_div(total, IPS_SAMPLE_COUNT);
936 avg = (u32)total;
937
938 return avg;
939}
940
fbc15e30 941static void monitor_timeout(struct timer_list *t)
aa7ffc01 942{
fbc15e30
KC		 943 struct ips_driver *ips = from_timer(ips, t, timer);
944 wake_up_process(ips->monitor);
aa7ffc01
JB		 945}
946
947/**
948 * ips_monitor - temp/power monitoring thread
949 * @data: ips driver structure
950 *
951 * This is the main function for the IPS driver. It monitors power and
952 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly.
953 *
954 * We keep a 5s moving average of power consumption and tempurature. Using
955 * that data, along with CPU vs GPU preference, we adjust the power clamps
956 * up or down.
957 */
958static int ips_monitor(void *data)
959{
960 struct ips_driver *ips = data;
aa7ffc01
JB		 961 unsigned long seqno_timestamp, expire, last_msecs, last_sample_period;
962 int i;
e9ec7f35
JS		 963 u32 *cpu_samples, *mchp_samples, old_cpu_power;
964 u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples;
aa7ffc01
JB		 965 u8 cur_seqno, last_seqno;
966
6396bb22
KC		 967 mcp_samples = kcalloc(IPS_SAMPLE_COUNT, sizeof(u16), GFP_KERNEL);
968 ctv1_samples = kcalloc(IPS_SAMPLE_COUNT, sizeof(u16), GFP_KERNEL);
969 ctv2_samples = kcalloc(IPS_SAMPLE_COUNT, sizeof(u16), GFP_KERNEL);
970 mch_samples = kcalloc(IPS_SAMPLE_COUNT, sizeof(u16), GFP_KERNEL);
971 cpu_samples = kcalloc(IPS_SAMPLE_COUNT, sizeof(u32), GFP_KERNEL);
972 mchp_samples = kcalloc(IPS_SAMPLE_COUNT, sizeof(u32), GFP_KERNEL);
e9ec7f35
JS		 973 if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples ||
974 !cpu_samples || !mchp_samples) {
d2fa170a 975 dev_err(ips->dev,
aa7ffc01
JB		 976 "failed to allocate sample array, ips disabled\n");
977 kfree(mcp_samples);
978 kfree(ctv1_samples);
979 kfree(ctv2_samples);
980 kfree(mch_samples);
981 kfree(cpu_samples);
e9ec7f35 982 kfree(mchp_samples);
aa7ffc01
JB		 983 return -ENOMEM;
984 }
985
986 last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
987 ITV_ME_SEQNO_SHIFT;
988 seqno_timestamp = get_jiffies_64();
989
c21eae4f 990 old_cpu_power = thm_readl(THM_CEC);
aa7ffc01
JB		 991 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
992
993 /* Collect an initial average */
994 for (i = 0; i < IPS_SAMPLE_COUNT; i++) {
995 u32 mchp, cpu_power;
996 u16 val;
997
998 mcp_samples[i] = read_ptv(ips);
999
1000 val = read_ctv(ips, 0);
1001 ctv1_samples[i] = val;
1002
1003 val = read_ctv(ips, 1);
1004 ctv2_samples[i] = val;
1005
1006 val = read_mgtv(ips);
1007 mch_samples[i] = val;
1008
1009 cpu_power = get_cpu_power(ips, &old_cpu_power,
1010 IPS_SAMPLE_PERIOD);
1011 cpu_samples[i] = cpu_power;
1012
1013 if (ips->read_mch_val) {
1014 mchp = ips->read_mch_val();
1015 mchp_samples[i] = mchp;
1016 }
1017
1018 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1019 if (kthread_should_stop())
1020 break;
1021 }
1022
1023 ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples);
1024 ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples);
1025 ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples);
1026 ips->mch_avg_temp = calc_avg_temp(ips, mch_samples);
1027 ips->cpu_avg_power = calc_avg_power(ips, cpu_samples);
1028 ips->mch_avg_power = calc_avg_power(ips, mchp_samples);
1029 kfree(mcp_samples);
1030 kfree(ctv1_samples);
1031 kfree(ctv2_samples);
1032 kfree(mch_samples);
1033 kfree(cpu_samples);
1034 kfree(mchp_samples);
1035
1036 /* Start the adjustment thread now that we have data */
1037 wake_up_process(ips->adjust);
1038
1039 /*
1040 * Ok, now we have an initial avg. From here on out, we track the
1041 * running avg using a decaying average calculation. This allows
1042 * us to reduce the sample frequency if the CPU and GPU are idle.
1043 */
1044 old_cpu_power = thm_readl(THM_CEC);
1045 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1046 last_sample_period = IPS_SAMPLE_PERIOD;
1047
fbc15e30 1048 timer_setup(&ips->timer, monitor_timeout, TIMER_DEFERRABLE);
aa7ffc01
JB		 1049 do {
1050 u32 cpu_val, mch_val;
1051 u16 val;
1052
1053 /* MCP itself */
1054 val = read_ptv(ips);
1055 ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val);
1056
1057 /* Processor 0 */
1058 val = read_ctv(ips, 0);
1059 ips->ctv1_avg_temp =
1060 update_average_temp(ips->ctv1_avg_temp, val);
1061 /* Power */
1062 cpu_val = get_cpu_power(ips, &old_cpu_power,
1063 last_sample_period);
1064 ips->cpu_avg_power =
1065 update_average_power(ips->cpu_avg_power, cpu_val);
1066
1067 if (ips->second_cpu) {
1068 /* Processor 1 */
1069 val = read_ctv(ips, 1);
1070 ips->ctv2_avg_temp =
1071 update_average_temp(ips->ctv2_avg_temp, val);
1072 }
1073
1074 /* MCH */
1075 val = read_mgtv(ips);
1076 ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val);
1077 /* Power */
1078 if (ips->read_mch_val) {
1079 mch_val = ips->read_mch_val();
1080 ips->mch_avg_power =
1081 update_average_power(ips->mch_avg_power,
1082 mch_val);
1083 }
1084
1085 /*
1086 * Make sure ME is updating thermal regs.
1087 * Note:
1088 * If it's been more than a second since the last update,
1089 * the ME is probably hung.
1090 */
1091 cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
1092 ITV_ME_SEQNO_SHIFT;
1093 if (cur_seqno == last_seqno &&
1094 time_after(jiffies, seqno_timestamp + HZ)) {
d2fa170a
AS		 1095 dev_warn(ips->dev,
1096 "ME failed to update for more than 1s, likely hung\n");
aa7ffc01
JB		 1097 } else {
1098 seqno_timestamp = get_jiffies_64();
1099 last_seqno = cur_seqno;
1100 }
1101
1102 last_msecs = jiffies_to_msecs(jiffies);
1103 expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD);
1104
a3424216 1105 __set_current_state(TASK_INTERRUPTIBLE);
fbc15e30 1106 mod_timer(&ips->timer, expire);
aa7ffc01
JB		 1107 schedule();
1108
1109 /* Calculate actual sample period for power averaging */
1110 last_sample_period = jiffies_to_msecs(jiffies) - last_msecs;
1111 if (!last_sample_period)
1112 last_sample_period = 1;
1113 } while (!kthread_should_stop());
1114
fbc15e30 1115 del_timer_sync(&ips->timer);
aa7ffc01 1116
d2fa170a 1117 dev_dbg(ips->dev, "ips-monitor thread stopped\n");
aa7ffc01
JB		 1118
1119 return 0;
1120}
1121
1122#if 0
1123#define THM_DUMPW(reg) \
1124 { \
1125 u16 val = thm_readw(reg); \
d2fa170a 1126 dev_dbg(ips->dev, #reg ": 0x%04x\n", val); \
aa7ffc01
JB		 1127 }
1128#define THM_DUMPL(reg) \
1129 { \
1130 u32 val = thm_readl(reg); \
d2fa170a 1131 dev_dbg(ips->dev, #reg ": 0x%08x\n", val); \
aa7ffc01
JB		 1132 }
1133#define THM_DUMPQ(reg) \
1134 { \
1135 u64 val = thm_readq(reg); \
d2fa170a 1136 dev_dbg(ips->dev, #reg ": 0x%016x\n", val); \
aa7ffc01
JB		 1137 }
1138
1139static void dump_thermal_info(struct ips_driver *ips)
1140{
1141 u16 ptl;
1142
1143 ptl = thm_readw(THM_PTL);
d2fa170a 1144 dev_dbg(ips->dev, "Processor temp limit: %d\n", ptl);
aa7ffc01
JB		 1145
1146 THM_DUMPW(THM_CTA);
1147 THM_DUMPW(THM_TRC);
1148 THM_DUMPW(THM_CTV1);
1149 THM_DUMPL(THM_STS);
1150 THM_DUMPW(THM_PTV);
1151 THM_DUMPQ(THM_MGTV);
1152}
1153#endif
1154
1155/**
1156 * ips_irq_handler - handle temperature triggers and other IPS events
1157 * @irq: irq number
1158 * @arg: unused
1159 *
1160 * Handle temperature limit trigger events, generally by lowering the clamps.
1161 * If we're at a critical limit, we clamp back to the lowest possible value
1162 * to prevent emergency shutdown.
1163 */
1164static irqreturn_t ips_irq_handler(int irq, void *arg)
1165{
1166 struct ips_driver *ips = arg;
1167 u8 tses = thm_readb(THM_TSES);
1168 u8 tes = thm_readb(THM_TES);
1169
1170 if (!tses && !tes)
1171 return IRQ_NONE;
1172
d2fa170a
AS		 1173 dev_info(ips->dev, "TSES: 0x%02x\n", tses);
1174 dev_info(ips->dev, "TES: 0x%02x\n", tes);
aa7ffc01
JB		 1175
1176 /* STS update from EC? */
1177 if (tes & 1) {
1178 u32 sts, tc1;
1179
1180 sts = thm_readl(THM_STS);
1181 tc1 = thm_readl(THM_TC1);
1182
1183 if (sts & STS_NVV) {
1184 spin_lock(&ips->turbo_status_lock);
1185 ips->core_power_limit = (sts & STS_PCPL_MASK) >>
1186 STS_PCPL_SHIFT;
1187 ips->mch_power_limit = (sts & STS_GPL_MASK) >>
1188 STS_GPL_SHIFT;
1189 /* ignore EC CPU vs GPU pref */
1190 ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS);
96f3823f
JB		 1191 /*
1192 * Disable turbo for now, until we can figure
1193 * out why the power figures are wrong
1194 */
1195 ips->cpu_turbo_enabled = false;
070c0ee1
AW		 1196 if (ips->gpu_busy)
1197 ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS);
aa7ffc01
JB		 1198 ips->mcp_temp_limit = (sts & STS_PTL_MASK) >>
1199 STS_PTL_SHIFT;
1200 ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >>
1201 STS_PPL_SHIFT;
eceab272 1202 verify_limits(ips);
aa7ffc01
JB		 1203 spin_unlock(&ips->turbo_status_lock);
1204
1205 thm_writeb(THM_SEC, SEC_ACK);
1206 }
1207 thm_writeb(THM_TES, tes);
1208 }
1209
1210 /* Thermal trip */
1211 if (tses) {
d2fa170a
AS		 1212 dev_warn(ips->dev, "thermal trip occurred, tses: 0x%04x\n",
1213 tses);
aa7ffc01
JB		 1214 thm_writeb(THM_TSES, tses);
1215 }
1216
1217 return IRQ_HANDLED;
1218}
1219
1220#ifndef CONFIG_DEBUG_FS
1221static void ips_debugfs_init(struct ips_driver *ips) { return; }
1222static void ips_debugfs_cleanup(struct ips_driver *ips) { return; }
1223#else
1224
1225/* Expose current state and limits in debugfs if possible */
1226
1227struct ips_debugfs_node {
1228 struct ips_driver *ips;
1229 char *name;
1230 int (*show)(struct seq_file *m, void *data);
1231};
1232
1233static int show_cpu_temp(struct seq_file *m, void *data)
1234{
1235 struct ips_driver *ips = m->private;
1236
1237 seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100,
1238 ips->ctv1_avg_temp % 100);
1239
1240 return 0;
1241}
1242
1243static int show_cpu_power(struct seq_file *m, void *data)
1244{
1245 struct ips_driver *ips = m->private;
1246
1247 seq_printf(m, "%dmW\n", ips->cpu_avg_power);
1248
1249 return 0;
1250}
1251
1252static int show_cpu_clamp(struct seq_file *m, void *data)
1253{
1254 u64 turbo_override;
1255 int tdp, tdc;
1256
1257 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1258
1259 tdp = (int)(turbo_override & TURBO_TDP_MASK);
1260 tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT);
1261
1262 /* Convert to .1W/A units */
1263 tdp = tdp * 10 / 8;
1264 tdc = tdc * 10 / 8;
1265
1266 /* Watts Amperes */
1267 seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10,
1268 tdc / 10, tdc % 10);
1269
1270 return 0;
1271}
1272
1273static int show_mch_temp(struct seq_file *m, void *data)
1274{
1275 struct ips_driver *ips = m->private;
1276
1277 seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100,
1278 ips->mch_avg_temp % 100);
1279
1280 return 0;
1281}
1282
1283static int show_mch_power(struct seq_file *m, void *data)
1284{
1285 struct ips_driver *ips = m->private;
1286
1287 seq_printf(m, "%dmW\n", ips->mch_avg_power);
1288
1289 return 0;
1290}
1291
1292static struct ips_debugfs_node ips_debug_files[] = {
1293 { NULL, "cpu_temp", show_cpu_temp },
1294 { NULL, "cpu_power", show_cpu_power },
1295 { NULL, "cpu_clamp", show_cpu_clamp },
1296 { NULL, "mch_temp", show_mch_temp },
1297 { NULL, "mch_power", show_mch_power },
1298};
1299
1300static int ips_debugfs_open(struct inode *inode, struct file *file)
1301{
1302 struct ips_debugfs_node *node = inode->i_private;
1303
1304 return single_open(file, node->show, node->ips);
1305}
1306
1307static const struct file_operations ips_debugfs_ops = {
1308 .owner = THIS_MODULE,
1309 .open = ips_debugfs_open,
1310 .read = seq_read,
1311 .llseek = seq_lseek,
1312 .release = single_release,
1313};
1314
1315static void ips_debugfs_cleanup(struct ips_driver *ips)
1316{
1317 if (ips->debug_root)
1318 debugfs_remove_recursive(ips->debug_root);
1319 return;
1320}
1321
1322static void ips_debugfs_init(struct ips_driver *ips)
1323{
1324 int i;
1325
1326 ips->debug_root = debugfs_create_dir("ips", NULL);
1327 if (!ips->debug_root) {
d2fa170a 1328 dev_err(ips->dev, "failed to create debugfs entries: %ld\n",
aa7ffc01
JB		 1329 PTR_ERR(ips->debug_root));
1330 return;
1331 }
1332
1333 for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) {
1334 struct dentry *ent;
1335 struct ips_debugfs_node *node = &ips_debug_files[i];
1336
1337 node->ips = ips;
1338 ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO,
1339 ips->debug_root, node,
1340 &ips_debugfs_ops);
1341 if (!ent) {
d2fa170a 1342 dev_err(ips->dev, "failed to create debug file: %ld\n",
aa7ffc01
JB		 1343 PTR_ERR(ent));
1344 goto err_cleanup;
1345 }
1346 }
1347
1348 return;
1349
1350err_cleanup:
1351 ips_debugfs_cleanup(ips);
1352 return;
1353}
1354#endif /* CONFIG_DEBUG_FS */
1355
1356/**
1357 * ips_detect_cpu - detect whether CPU supports IPS
1358 *
1359 * Walk our list and see if we're on a supported CPU. If we find one,
1360 * return the limits for it.
1361 */
1362static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
1363{
1364 u64 turbo_power, misc_en;
1365 struct ips_mcp_limits *limits = NULL;
1366 u16 tdp;
1367
1368 if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) {
d2fa170a 1369 dev_info(ips->dev, "Non-IPS CPU detected.\n");
b8cc799d 1370 return NULL;
aa7ffc01
JB		 1371 }
1372
1373 rdmsrl(IA32_MISC_ENABLE, misc_en);
1374 /*
1375 * If the turbo enable bit isn't set, we shouldn't try to enable/disable
1376 * turbo manually or we'll get an illegal MSR access, even though
1377 * turbo will still be available.
1378 */
354aeeb1
JB		 1379 if (misc_en & IA32_MISC_TURBO_EN)
1380 ips->turbo_toggle_allowed = true;
1381 else
1382 ips->turbo_toggle_allowed = false;
aa7ffc01
JB		 1383
1384 if (strstr(boot_cpu_data.x86_model_id, "CPU M"))
1385 limits = &ips_sv_limits;
1386 else if (strstr(boot_cpu_data.x86_model_id, "CPU L"))
1387 limits = &ips_lv_limits;
1388 else if (strstr(boot_cpu_data.x86_model_id, "CPU U"))
1389 limits = &ips_ulv_limits;
52d7ee55 1390 else {
d2fa170a 1391 dev_info(ips->dev, "No CPUID match found.\n");
b8cc799d 1392 return NULL;
52d7ee55 1393 }
aa7ffc01
JB		 1394
1395 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power);
1396 tdp = turbo_power & TURBO_TDP_MASK;
1397
1398 /* Sanity check TDP against CPU */
4fd07ac0 1399 if (limits->core_power_limit != (tdp / 8) * 1000) {
d2fa170a
AS		 1400 dev_info(ips->dev,
1401 "CPU TDP doesn't match expected value (found %d, expected %d)\n",
4fd07ac0
JB		 1402 tdp / 8, limits->core_power_limit / 1000);
1403 limits->core_power_limit = (tdp / 8) * 1000;
aa7ffc01
JB		 1404 }
1405
aa7ffc01
JB		 1406 return limits;
1407}
1408
1409/**
1410 * ips_get_i915_syms - try to get GPU control methods from i915 driver
1411 * @ips: IPS driver
1412 *
1413 * The i915 driver exports several interfaces to allow the IPS driver to
1414 * monitor and control graphics turbo mode. If we can find them, we can
1415 * enable graphics turbo, otherwise we must disable it to avoid exceeding
1416 * thermal and power limits in the MCP.
1417 */
1418static bool ips_get_i915_syms(struct ips_driver *ips)
1419{
1420 ips->read_mch_val = symbol_get(i915_read_mch_val);
1421 if (!ips->read_mch_val)
1422 goto out_err;
1423 ips->gpu_raise = symbol_get(i915_gpu_raise);
1424 if (!ips->gpu_raise)
1425 goto out_put_mch;
1426 ips->gpu_lower = symbol_get(i915_gpu_lower);
1427 if (!ips->gpu_lower)
1428 goto out_put_raise;
1429 ips->gpu_busy = symbol_get(i915_gpu_busy);
1430 if (!ips->gpu_busy)
1431 goto out_put_lower;
1432 ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable);
1433 if (!ips->gpu_turbo_disable)
1434 goto out_put_busy;
1435
1436 return true;
1437
1438out_put_busy:
fed522f7 1439 symbol_put(i915_gpu_busy);
aa7ffc01
JB		 1440out_put_lower:
1441 symbol_put(i915_gpu_lower);
1442out_put_raise:
1443 symbol_put(i915_gpu_raise);
1444out_put_mch:
1445 symbol_put(i915_read_mch_val);
1446out_err:
1447 return false;
1448}
1449
63ee41d7
EA		 1450static bool
1451ips_gpu_turbo_enabled(struct ips_driver *ips)
1452{
1453 if (!ips->gpu_busy && late_i915_load) {
1454 if (ips_get_i915_syms(ips)) {
d2fa170a 1455 dev_info(ips->dev,
63ee41d7
EA		 1456 "i915 driver attached, reenabling gpu turbo\n");
1457 ips->gpu_turbo_enabled = !(thm_readl(THM_HTS) & HTS_GTD_DIS);
1458 }
1459 }
1460
1461 return ips->gpu_turbo_enabled;
1462}
1463
1464void
7027d8b5 1465ips_link_to_i915_driver(void)
63ee41d7
EA		 1466{
1467 /* We can't cleanly get at the various ips_driver structs from
1468 * this caller (the i915 driver), so just set a flag saying
1469 * that it's time to try getting the symbols again.
1470 */
1471 late_i915_load = true;
1472}
1473EXPORT_SYMBOL_GPL(ips_link_to_i915_driver);
1474
9baa3c34 1475static const struct pci_device_id ips_id_table[] = {
512f4665 1476 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), },
aa7ffc01
JB		 1477 { 0, }
1478};
1479
1480MODULE_DEVICE_TABLE(pci, ips_id_table);
1481
88ca518b
TI		 1482static int ips_blacklist_callback(const struct dmi_system_id *id)
1483{
1484 pr_info("Blacklisted intel_ips for %s\n", id->ident);
1485 return 1;
1486}
1487
1488static const struct dmi_system_id ips_blacklist[] = {
1489 {
1490 .callback = ips_blacklist_callback,
1491 .ident = "HP ProBook",
1492 .matches = {
1493 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1494 DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook"),
1495 },
1496 },
1497 { } /* terminating entry */
1498};
1499
aa7ffc01
JB		 1500static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
1501{
1502 u64 platform_info;
1503 struct ips_driver *ips;
1504 u32 hts;
1505 int ret = 0;
1506 u16 htshi, trc, trc_required_mask;
1507 u8 tse;
1508
88ca518b
TI		 1509 if (dmi_check_system(ips_blacklist))
1510 return -ENODEV;
1511
f5b33d94 1512 ips = devm_kzalloc(&dev->dev, sizeof(*ips), GFP_KERNEL);
aa7ffc01
JB		 1513 if (!ips)
1514 return -ENOMEM;
1515
f5b33d94 1516 spin_lock_init(&ips->turbo_status_lock);
d2fa170a 1517 ips->dev = &dev->dev;
aa7ffc01
JB		 1518
1519 ips->limits = ips_detect_cpu(ips);
1520 if (!ips->limits) {
1521 dev_info(&dev->dev, "IPS not supported on this CPU\n");
f5b33d94 1522 return -ENXIO;
aa7ffc01
JB		 1523 }
1524
f5b33d94 1525 ret = pcim_enable_device(dev);
5629236b
KV		 1526 if (ret) {
1527 dev_err(&dev->dev, "can't enable PCI device, aborting\n");
f5b33d94 1528 return ret;
5629236b
KV		 1529 }
1530
f5b33d94 1531 ret = pcim_iomap_regions(dev, 1 << 0, pci_name(dev));
aa7ffc01 1532 if (ret) {
aa7ffc01 1533 dev_err(&dev->dev, "failed to map thermal regs, aborting\n");
f5b33d94 1534 return ret;
aa7ffc01 1535 }
f5b33d94
AS		 1536 ips->regmap = pcim_iomap_table(dev)[0];
1537
1538 pci_set_drvdata(dev, ips);
aa7ffc01
JB		 1539
1540 tse = thm_readb(THM_TSE);
1541 if (tse != TSE_EN) {
1542 dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse);
f5b33d94 1543 return -ENXIO;
aa7ffc01
JB		 1544 }
1545
1546 trc = thm_readw(THM_TRC);
1547 trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN;
1548 if ((trc & trc_required_mask) != trc_required_mask) {
1549 dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n");
f5b33d94 1550 return -ENXIO;
aa7ffc01
JB		 1551 }
1552
1553 if (trc & TRC_CORE2_EN)
1554 ips->second_cpu = true;
1555
aa7ffc01
JB		 1556 update_turbo_limits(ips);
1557 dev_dbg(&dev->dev, "max cpu power clamp: %dW\n",
1558 ips->mcp_power_limit / 10);
1559 dev_dbg(&dev->dev, "max core power clamp: %dW\n",
1560 ips->core_power_limit / 10);
1561 /* BIOS may update limits at runtime */
1562 if (thm_readl(THM_PSC) & PSP_PBRT)
1563 ips->poll_turbo_status = true;
1564
0385e521 1565 if (!ips_get_i915_syms(ips)) {
fc1a93bd 1566 dev_info(&dev->dev, "failed to get i915 symbols, graphics turbo disabled until i915 loads\n");
0385e521
JB		 1567 ips->gpu_turbo_enabled = false;
1568 } else {
1569 dev_dbg(&dev->dev, "graphics turbo enabled\n");
1570 ips->gpu_turbo_enabled = true;
1571 }
1572
aa7ffc01
JB		 1573 /*
1574 * Check PLATFORM_INFO MSR to make sure this chip is
1575 * turbo capable.
1576 */
1577 rdmsrl(PLATFORM_INFO, platform_info);
1578 if (!(platform_info & PLATFORM_TDP)) {
1579 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n");
f5b33d94 1580 return -ENODEV;
aa7ffc01
JB		 1581 }
1582
1583 /*
1584 * IRQ handler for ME interaction
1585 * Note: don't use MSI here as the PCH has bugs.
1586 */
8b8bd6d2
AS		 1587 ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
1588 if (ret < 0)
1589 return ret;
1590
1591 ips->irq = pci_irq_vector(dev, 0);
1592
1593 ret = request_irq(ips->irq, ips_irq_handler, IRQF_SHARED, "ips", ips);
aa7ffc01
JB		 1594 if (ret) {
1595 dev_err(&dev->dev, "request irq failed, aborting\n");
f5b33d94 1596 return ret;
aa7ffc01
JB		 1597 }
1598
1599 /* Enable aux, hot & critical interrupts */
1600 thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI |
1601 TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI);
1602 thm_writeb(THM_TEN, TEN_UPDATE_EN);
1603
1604 /* Collect adjustment values */
1605 ips->cta_val = thm_readw(THM_CTA);
1606 ips->pta_val = thm_readw(THM_PTA);
1607 ips->mgta_val = thm_readw(THM_MGTA);
1608
1609 /* Save turbo limits & ratios */
1610 rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1611
96f3823f
JB		 1612 ips_disable_cpu_turbo(ips);
1613 ips->cpu_turbo_enabled = false;
aa7ffc01 1614
a7abda8d 1615 /* Create thermal adjust thread */
1616 ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust");
1617 if (IS_ERR(ips->adjust)) {
aa7ffc01 1618 dev_err(&dev->dev,
a7abda8d 1619 "failed to create thermal adjust thread, aborting\n");
aa7ffc01
JB		 1620 ret = -ENOMEM;
1621 goto error_free_irq;
a7abda8d 1622
aa7ffc01
JB		 1623 }
1624
a7abda8d 1625 /*
1626 * Set up the work queue and monitor thread. The monitor thread
1627 * will wake up ips_adjust thread.
1628 */
1629 ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor");
1630 if (IS_ERR(ips->monitor)) {
aa7ffc01 1631 dev_err(&dev->dev,
a7abda8d 1632 "failed to create thermal monitor thread, aborting\n");
aa7ffc01
JB		 1633 ret = -ENOMEM;
1634 goto error_thread_cleanup;
1635 }
1636
1637 hts = (ips->core_power_limit << HTS_PCPL_SHIFT) |
1638 (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV;
1639 htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT;
1640
1641 thm_writew(THM_HTSHI, htshi);
1642 thm_writel(THM_HTS, hts);
1643
1644 ips_debugfs_init(ips);
1645
1646 dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n",
1647 ips->mcp_temp_limit);
1648 return ret;
1649
1650error_thread_cleanup:
a7abda8d 1651 kthread_stop(ips->adjust);
aa7ffc01 1652error_free_irq:
8b8bd6d2
AS		 1653 free_irq(ips->irq, ips);
1654 pci_free_irq_vectors(dev);
aa7ffc01
JB		 1655 return ret;
1656}
1657
1658static void ips_remove(struct pci_dev *dev)
1659{
1660 struct ips_driver *ips = pci_get_drvdata(dev);
1661 u64 turbo_override;
1662
1663 if (!ips)
1664 return;
1665
1666 ips_debugfs_cleanup(ips);
1667
1668 /* Release i915 driver */
1669 if (ips->read_mch_val)
1670 symbol_put(i915_read_mch_val);
1671 if (ips->gpu_raise)
1672 symbol_put(i915_gpu_raise);
1673 if (ips->gpu_lower)
1674 symbol_put(i915_gpu_lower);
1675 if (ips->gpu_busy)
1676 symbol_put(i915_gpu_busy);
1677 if (ips->gpu_turbo_disable)
1678 symbol_put(i915_gpu_turbo_disable);
1679
1680 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1681 turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN);
1682 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1683 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1684
8b8bd6d2
AS		 1685 free_irq(ips->irq, ips);
1686 pci_free_irq_vectors(dev);
aa7ffc01
JB		 1687 if (ips->adjust)
1688 kthread_stop(ips->adjust);
1689 if (ips->monitor)
1690 kthread_stop(ips->monitor);
aa7ffc01
JB		 1691 dev_dbg(&dev->dev, "IPS driver removed\n");
1692}
1693
aa7ffc01
JB		 1694static struct pci_driver ips_pci_driver = {
1695 .name = "intel ips",
1696 .id_table = ips_id_table,
1697 .probe = ips_probe,
1698 .remove = ips_remove,
aa7ffc01
JB		 1699};
1700
b5f4f9ef 1701module_pci_driver(ips_pci_driver);
aa7ffc01
JB		 1702
1703MODULE_LICENSE("GPL");
1704MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>");
1705MODULE_DESCRIPTION("Intelligent Power Sharing Driver");
Linux 6.x block layer and io_uring tree(s)