[linux-block.git] / drivers / platform / x86 / intel / pmc / lnl.c

// SPDX-License-Identifier: GPL-2.0
/*
 * This file contains platform specific structure definitions
 * and init function used by Lunar Lake PCH.
 *
 * Copyright (c) 2022, Intel Corporation.
 * All Rights Reserved.
 *
 */

#include <linux/cpu.h>
#include <linux/pci.h>

#include "core.h"

const struct pmc_bit_map lnl_ltr_show_map[] = {
	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
	{"SATA",		CNP_PMC_LTR_SATA},
	{"GIGABIT_ETHERNET",	CNP_PMC_LTR_GBE},
	{"XHCI",		CNP_PMC_LTR_XHCI},
	{"SOUTHPORT_F",		ADL_PMC_LTR_SPF},
	{"ME",			CNP_PMC_LTR_ME},
	/* EVA is Enterprise Value Add, doesn't really exist on PCH */
	{"SATA1",		CNP_PMC_LTR_EVA},
	{"SOUTHPORT_C",		CNP_PMC_LTR_SPC},
	{"HD_AUDIO",		CNP_PMC_LTR_AZ},
	{"CNV",			CNP_PMC_LTR_CNV},
	{"LPSS",		CNP_PMC_LTR_LPSS},
	{"SOUTHPORT_D",		CNP_PMC_LTR_SPD},
	{"SOUTHPORT_E",		CNP_PMC_LTR_SPE},
	{"SATA2",		CNP_PMC_LTR_CAM},
	{"ESPI",		CNP_PMC_LTR_ESPI},
	{"SCC",			CNP_PMC_LTR_SCC},
	{"ISH",			CNP_PMC_LTR_ISH},
	{"UFSX2",		CNP_PMC_LTR_UFSX2},
	{"EMMC",		CNP_PMC_LTR_EMMC},
	/*
	 * Check intel_pmc_core_ids[] users of cnp_reg_map for
	 * a list of core SoCs using this.
	 */
	{"WIGIG",		ICL_PMC_LTR_WIGIG},
	{"THC0",		TGL_PMC_LTR_THC0},
	{"THC1",		TGL_PMC_LTR_THC1},
	{"SOUTHPORT_G",		CNP_PMC_LTR_RESERVED},

	{"ESE",			MTL_PMC_LTR_ESE},
	{"IOE_PMC",		MTL_PMC_LTR_IOE_PMC},
	{"DMI3",		ARL_PMC_LTR_DMI3},
	{"OSSE",		LNL_PMC_LTR_OSSE},

	/* Below two cannot be used for LTR_IGNORE */
	{"CURRENT_PLATFORM",	CNP_PMC_LTR_CUR_PLT},
	{"AGGREGATED_SYSTEM",	CNP_PMC_LTR_CUR_ASLT},
	{}
};

const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
	{"PMC_PGD0_PG_STS",			BIT(0),		0},
	{"FUSE_OSSE_PGD0_PG_STS",		BIT(1),		0},
	{"ESPISPI_PGD0_PG_STS",			BIT(2),		0},
	{"XHCI_PGD0_PG_STS",			BIT(3),		1},
	{"SPA_PGD0_PG_STS",			BIT(4),		1},
	{"SPB_PGD0_PG_STS",			BIT(5),		1},
	{"SPR16B0_PGD0_PG_STS",			BIT(6),		0},
	{"GBE_PGD0_PG_STS",			BIT(7),		1},
	{"SBR8B7_PGD0_PG_STS",			BIT(8),		0},
	{"SBR8B6_PGD0_PG_STS",			BIT(9),		0},
	{"SBR16B1_PGD0_PG_STS",			BIT(10),	0},
	{"SBR8B8_PGD0_PG_STS",			BIT(11),	0},
	{"ESE_PGD3_PG_STS",			BIT(12),	1},
	{"D2D_DISP_PGD0_PG_STS",		BIT(13),	1},
	{"LPSS_PGD0_PG_STS",			BIT(14),	1},
	{"LPC_PGD0_PG_STS",			BIT(15),	0},
	{"SMB_PGD0_PG_STS",			BIT(16),	0},
	{"ISH_PGD0_PG_STS",			BIT(17),	0},
	{"SBR8B2_PGD0_PG_STS",			BIT(18),	0},
	{"NPK_PGD0_PG_STS",			BIT(19),	0},
	{"D2D_NOC_PGD0_PG_STS",			BIT(20),	0},
	{"SAFSS_PGD0_PG_STS",			BIT(21),	0},
	{"FUSE_PGD0_PG_STS",			BIT(22),	0},
	{"D2D_DISP_PGD1_PG_STS",		BIT(23),	1},
	{"MPFPW1_PGD0_PG_STS",			BIT(24),	0},
	{"XDCI_PGD0_PG_STS",			BIT(25),	1},
	{"EXI_PGD0_PG_STS",			BIT(26),	0},
	{"CSE_PGD0_PG_STS",			BIT(27),	1},
	{"KVMCC_PGD0_PG_STS",			BIT(28),	1},
	{"PMT_PGD0_PG_STS",			BIT(29),	1},
	{"CLINK_PGD0_PG_STS",			BIT(30),	1},
	{"PTIO_PGD0_PG_STS",			BIT(31),	1},
	{}
};

const struct pmc_bit_map lnl_power_gating_status_1_map[] = {
	{"USBR0_PGD0_PG_STS",			BIT(0),		1},
	{"SUSRAM_PGD0_PG_STS",			BIT(1),		1},
	{"SMT1_PGD0_PG_STS",			BIT(2),		1},
	{"U3FPW1_PGD0_PG_STS",			BIT(3),		0},
	{"SMS2_PGD0_PG_STS",			BIT(4),		1},
	{"SMS1_PGD0_PG_STS",			BIT(5),		1},
	{"CSMERTC_PGD0_PG_STS",			BIT(6),		0},
	{"CSMEPSF_PGD0_PG_STS",			BIT(7),		0},
	{"FIA_PG_PGD0_PG_STS",			BIT(8),		0},
	{"SBR16B4_PGD0_PG_STS",			BIT(9),		0},
	{"P2SB8B_PGD0_PG_STS",			BIT(10),	1},
	{"DBG_SBR_PGD0_PG_STS",			BIT(11),	0},
	{"SBR8B9_PGD0_PG_STS",			BIT(12),	0},
	{"OSSE_SMT1_PGD0_PG_STS",		BIT(13),	1},
	{"SBR8B10_PGD0_PG_STS",			BIT(14),	0},
	{"SBR16B3_PGD0_PG_STS",			BIT(15),	0},
	{"G5FPW1_PGD0_PG_STS",			BIT(16),	0},
	{"SBRG_PGD0_PG_STS",			BIT(17),	0},
	{"PSF4_PGD0_PG_STS",			BIT(18),	0},
	{"CNVI_PGD0_PG_STS",			BIT(19),	0},
	{"USFX2_PGD0_PG_STS",			BIT(20),	1},
	{"ENDBG_PGD0_PG_STS",			BIT(21),	0},
	{"FIACPCB_P5X4_PGD0_PG_STS",		BIT(22),	0},
	{"SBR8B3_PGD0_PG_STS",			BIT(23),	0},
	{"SBR8B0_PGD0_PG_STS",			BIT(24),	0},
	{"NPK_PGD1_PG_STS",			BIT(25),	0},
	{"OSSE_HOTHAM_PGD0_PG_STS",		BIT(26),	1},
	{"D2D_NOC_PGD2_PG_STS",			BIT(27),	1},
	{"SBR8B1_PGD0_PG_STS",			BIT(28),	0},
	{"PSF6_PGD0_PG_STS",			BIT(29),	0},
	{"PSF7_PGD0_PG_STS",			BIT(30),	0},
	{"FIA_U_PGD0_PG_STS",			BIT(31),	0},
	{}
};

const struct pmc_bit_map lnl_power_gating_status_2_map[] = {
	{"PSF8_PGD0_PG_STS",			BIT(0),		0},
	{"SBR16B2_PGD0_PG_STS",			BIT(1),		0},
	{"D2D_IPU_PGD0_PG_STS",			BIT(2),		1},
	{"FIACPCB_U_PGD0_PG_STS",		BIT(3),		0},
	{"TAM_PGD0_PG_STS",			BIT(4),		1},
	{"D2D_NOC_PGD1_PG_STS",			BIT(5),		1},
	{"TBTLSX_PGD0_PG_STS",			BIT(6),		1},
	{"THC0_PGD0_PG_STS",			BIT(7),		1},
	{"THC1_PGD0_PG_STS",			BIT(8),		1},
	{"PMC_PGD0_PG_STS",			BIT(9),		0},
	{"SBR8B5_PGD0_PG_STS",			BIT(10),	0},
	{"UFSPW1_PGD0_PG_STS",			BIT(11),	0},
	{"DBC_PGD0_PG_STS",			BIT(12),	0},
	{"TCSS_PGD0_PG_STS",			BIT(13),	0},
	{"FIA_P5X4_PGD0_PG_STS",		BIT(14),	0},
	{"DISP_PGA_PGD0_PG_STS",		BIT(15),	0},
	{"DISP_PSF_PGD0_PG_STS",		BIT(16),	0},
	{"PSF0_PGD0_PG_STS",			BIT(17),	0},
	{"P2SB16B_PGD0_PG_STS",			BIT(18),	1},
	{"ACE_PGD0_PG_STS",			BIT(19),	0},
	{"ACE_PGD1_PG_STS",			BIT(20),	0},
	{"ACE_PGD2_PG_STS",			BIT(21),	0},
	{"ACE_PGD3_PG_STS",			BIT(22),	0},
	{"ACE_PGD4_PG_STS",			BIT(23),	0},
	{"ACE_PGD5_PG_STS",			BIT(24),	0},
	{"ACE_PGD6_PG_STS",			BIT(25),	0},
	{"ACE_PGD7_PG_STS",			BIT(26),	0},
	{"ACE_PGD8_PG_STS",			BIT(27),	0},
	{"ACE_PGD9_PG_STS",			BIT(28),	0},
	{"ACE_PGD10_PG_STS",			BIT(29),	0},
	{"FIACPCB_PG_PGD0_PG_STS",		BIT(30),	0},
	{"OSSE_PGD0_PG_STS",			BIT(31),	1},
	{}
};

const struct pmc_bit_map lnl_d3_status_0_map[] = {
	{"LPSS_D3_STS",				BIT(3),		1},
	{"XDCI_D3_STS",				BIT(4),		1},
	{"XHCI_D3_STS",				BIT(5),		1},
	{"SPA_D3_STS",				BIT(12),	0},
	{"SPB_D3_STS",				BIT(13),	0},
	{"OSSE_D3_STS",				BIT(15),	0},
	{"ESPISPI_D3_STS",			BIT(18),	0},
	{"PSTH_D3_STS",				BIT(21),	0},
	{}
};

const struct pmc_bit_map lnl_d3_status_1_map[] = {
	{"OSSE_SMT1_D3_STS",			BIT(7),		0},
	{"GBE_D3_STS",				BIT(19),	0},
	{"ITSS_D3_STS",				BIT(23),	0},
	{"CNVI_D3_STS",				BIT(27),	0},
	{"UFSX2_D3_STS",			BIT(28),	1},
	{"OSSE_HOTHAM_D3_STS",			BIT(31),	0},
	{}
};

const struct pmc_bit_map lnl_d3_status_2_map[] = {
	{"ESE_D3_STS",				BIT(0),		0},
	{"CSMERTC_D3_STS",			BIT(1),		0},
	{"SUSRAM_D3_STS",			BIT(2),		0},
	{"CSE_D3_STS",				BIT(4),		0},
	{"KVMCC_D3_STS",			BIT(5),		0},
	{"USBR0_D3_STS",			BIT(6),		0},
	{"ISH_D3_STS",				BIT(7),		0},
	{"SMT1_D3_STS",				BIT(8),		0},
	{"SMT2_D3_STS",				BIT(9),		0},
	{"SMT3_D3_STS",				BIT(10),	0},
	{"OSSE_SMT2_D3_STS",			BIT(13),	0},
	{"CLINK_D3_STS",			BIT(14),	0},
	{"PTIO_D3_STS",				BIT(16),	0},
	{"PMT_D3_STS",				BIT(17),	0},
	{"SMS1_D3_STS",				BIT(18),	0},
	{"SMS2_D3_STS",				BIT(19),	0},
	{}
};

const struct pmc_bit_map lnl_d3_status_3_map[] = {
	{"THC0_D3_STS",				BIT(14),	1},
	{"THC1_D3_STS",				BIT(15),	1},
	{"OSSE_SMT3_D3_STS",			BIT(21),	0},
	{"ACE_D3_STS",				BIT(23),	0},
	{}
};

const struct pmc_bit_map lnl_vnn_req_status_0_map[] = {
	{"LPSS_VNN_REQ_STS",			BIT(3),		1},
	{"OSSE_VNN_REQ_STS",			BIT(15),	1},
	{"ESPISPI_VNN_REQ_STS",			BIT(18),	1},
	{}
};

const struct pmc_bit_map lnl_vnn_req_status_1_map[] = {
	{"NPK_VNN_REQ_STS",			BIT(4),		1},
	{"OSSE_SMT1_VNN_REQ_STS",		BIT(7),		1},
	{"DFXAGG_VNN_REQ_STS",			BIT(8),		0},
	{"EXI_VNN_REQ_STS",			BIT(9),		1},
	{"P2D_VNN_REQ_STS",			BIT(18),	1},
	{"GBE_VNN_REQ_STS",			BIT(19),	1},
	{"SMB_VNN_REQ_STS",			BIT(25),	1},
	{"LPC_VNN_REQ_STS",			BIT(26),	0},
	{}
};

const struct pmc_bit_map lnl_vnn_req_status_2_map[] = {
	{"eSE_VNN_REQ_STS",			BIT(0),		1},
	{"CSMERTC_VNN_REQ_STS",			BIT(1),		1},
	{"CSE_VNN_REQ_STS",			BIT(4),		1},
	{"ISH_VNN_REQ_STS",			BIT(7),		1},
	{"SMT1_VNN_REQ_STS",			BIT(8),		1},
	{"CLINK_VNN_REQ_STS",			BIT(14),	1},
	{"SMS1_VNN_REQ_STS",			BIT(18),	1},
	{"SMS2_VNN_REQ_STS",			BIT(19),	1},
	{"GPIOCOM4_VNN_REQ_STS",		BIT(20),	1},
	{"GPIOCOM3_VNN_REQ_STS",		BIT(21),	1},
	{"GPIOCOM2_VNN_REQ_STS",		BIT(22),	0},
	{"GPIOCOM1_VNN_REQ_STS",		BIT(23),	1},
	{"GPIOCOM0_VNN_REQ_STS",		BIT(24),	1},
	{}
};

const struct pmc_bit_map lnl_vnn_req_status_3_map[] = {
	{"DISP_SHIM_VNN_REQ_STS",		BIT(2),		0},
	{"DTS0_VNN_REQ_STS",			BIT(7),		0},
	{"GPIOCOM5_VNN_REQ_STS",		BIT(11),	2},
	{}
};

const struct pmc_bit_map lnl_vnn_misc_status_map[] = {
	{"CPU_C10_REQ_STS",			BIT(0),		0},
	{"TS_OFF_REQ_STS",			BIT(1),		0},
	{"PNDE_MET_REQ_STS",			BIT(2),		1},
	{"PCIE_DEEP_PM_REQ_STS",		BIT(3),		0},
	{"PMC_CLK_THROTTLE_EN_REQ_STS",		BIT(4),		0},
	{"NPK_VNNAON_REQ_STS",			BIT(5),		0},
	{"VNN_SOC_REQ_STS",			BIT(6),		1},
	{"ISH_VNNAON_REQ_STS",			BIT(7),		0},
	{"D2D_NOC_CFI_QACTIVE_REQ_STS",		BIT(8),		1},
	{"D2D_NOC_GPSB_QACTIVE_REQ_STS",	BIT(9),		1},
	{"D2D_NOC_IPU_QACTIVE_REQ_STS",		BIT(10),	1},
	{"PLT_GREATER_REQ_STS",			BIT(11),	1},
	{"PCIE_CLKREQ_REQ_STS",			BIT(12),	0},
	{"PMC_IDLE_FB_OCP_REQ_STS",		BIT(13),	0},
	{"PM_SYNC_STATES_REQ_STS",		BIT(14),	0},
	{"EA_REQ_STS",				BIT(15),	0},
	{"MPHY_CORE_OFF_REQ_STS",		BIT(16),	0},
	{"BRK_EV_EN_REQ_STS",			BIT(17),	0},
	{"AUTO_DEMO_EN_REQ_STS",		BIT(18),	0},
	{"ITSS_CLK_SRC_REQ_STS",		BIT(19),	1},
	{"LPC_CLK_SRC_REQ_STS",			BIT(20),	0},
	{"ARC_IDLE_REQ_STS",			BIT(21),	0},
	{"MPHY_SUS_REQ_STS",			BIT(22),	0},
	{"FIA_DEEP_PM_REQ_STS",			BIT(23),	0},
	{"UXD_CONNECTED_REQ_STS",		BIT(24),	1},
	{"ARC_INTERRUPT_WAKE_REQ_STS",		BIT(25),	0},
	{"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS",	BIT(26),	1},
	{"PRE_WAKE0_REQ_STS",			BIT(27),	1},
	{"PRE_WAKE1_REQ_STS",			BIT(28),	1},
	{"PRE_WAKE2_EN_REQ_STS",		BIT(29),	1},
	{"WOV_REQ_STS",				BIT(30),	0},
	{"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31",	BIT(31),	1},
	{}
};

const struct pmc_bit_map lnl_clocksource_status_map[] = {
	{"AON2_OFF_STS",			BIT(0),		0},
	{"AON3_OFF_STS",			BIT(1),		1},
	{"AON4_OFF_STS",			BIT(2),		1},
	{"AON5_OFF_STS",			BIT(3),		1},
	{"AON1_OFF_STS",			BIT(4),		0},
	{"MPFPW1_0_PLL_OFF_STS",		BIT(6),		1},
	{"USB3_PLL_OFF_STS",			BIT(8),		1},
	{"AON3_SPL_OFF_STS",			BIT(9),		1},
	{"G5FPW1_PLL_OFF_STS",			BIT(15),	1},
	{"XTAL_AGGR_OFF_STS",			BIT(17),	1},
	{"USB2_PLL_OFF_STS",			BIT(18),	0},
	{"SAF_PLL_OFF_STS",			BIT(19),	1},
	{"SE_TCSS_PLL_OFF_STS",			BIT(20),	1},
	{"DDI_PLL_OFF_STS",			BIT(21),	1},
	{"FILTER_PLL_OFF_STS",			BIT(22),	1},
	{"ACE_PLL_OFF_STS",			BIT(24),	0},
	{"FABRIC_PLL_OFF_STS",			BIT(25),	1},
	{"SOC_PLL_OFF_STS",			BIT(26),	1},
	{"REF_OFF_STS",				BIT(28),	1},
	{"IMG_OFF_STS",				BIT(29),	1},
	{"RTC_PLL_OFF_STS",			BIT(31),	0},
	{}
};

const struct pmc_bit_map lnl_signal_status_map[] = {
	{"LSX_Wake0_STS",			BIT(0),		0},
	{"LSX_Wake1_STS",			BIT(1),		0},
	{"LSX_Wake2_STS",			BIT(2),		0},
	{"LSX_Wake3_STS",			BIT(3),		0},
	{"LSX_Wake4_STS",			BIT(4),		0},
	{"LSX_Wake5_STS",			BIT(5),		0},
	{"LSX_Wake6_STS",			BIT(6),		0},
	{"LSX_Wake7_STS",			BIT(7),		0},
	{"LPSS_Wake0_STS",			BIT(8),		1},
	{"LPSS_Wake1_STS",			BIT(9),		1},
	{"Int_Timer_SS_Wake0_STS",		BIT(10),	1},
	{"Int_Timer_SS_Wake1_STS",		BIT(11),	1},
	{"Int_Timer_SS_Wake2_STS",		BIT(12),	1},
	{"Int_Timer_SS_Wake3_STS",		BIT(13),	1},
	{"Int_Timer_SS_Wake4_STS",		BIT(14),	1},
	{"Int_Timer_SS_Wake5_STS",		BIT(15),	1},
	{}
};

const struct pmc_bit_map lnl_rsc_status_map[] = {
	{"Memory",				0,		1},
	{"PSF0",				0,		1},
	{"PSF4",				0,		1},
	{"PSF6",				0,		1},
	{"PSF7",				0,		1},
	{"PSF8",				0,		1},
	{"SAF_CFI_LINK",			0,		1},
	{"SBR",					0,		1},
	{}
};

const struct pmc_bit_map *lnl_lpm_maps[] = {
	lnl_clocksource_status_map,
	lnl_power_gating_status_0_map,
	lnl_power_gating_status_1_map,
	lnl_power_gating_status_2_map,
	lnl_d3_status_0_map,
	lnl_d3_status_1_map,
	lnl_d3_status_2_map,
	lnl_d3_status_3_map,
	lnl_vnn_req_status_0_map,
	lnl_vnn_req_status_1_map,
	lnl_vnn_req_status_2_map,
	lnl_vnn_req_status_3_map,
	lnl_vnn_misc_status_map,
	lnl_signal_status_map,
	NULL
};

const struct pmc_bit_map *lnl_blk_maps[] = {
	lnl_power_gating_status_0_map,
	lnl_power_gating_status_1_map,
	lnl_power_gating_status_2_map,
	lnl_rsc_status_map,
	lnl_vnn_req_status_0_map,
	lnl_vnn_req_status_1_map,
	lnl_vnn_req_status_2_map,
	lnl_vnn_req_status_3_map,
	lnl_d3_status_0_map,
	lnl_d3_status_1_map,
	lnl_d3_status_2_map,
	lnl_d3_status_3_map,
	lnl_clocksource_status_map,
	lnl_vnn_misc_status_map,
	lnl_signal_status_map,
	NULL
};

const struct pmc_bit_map lnl_pfear_map[] = {
	{"PMC_0",			BIT(0)},
	{"FUSE_OSSE",			BIT(1)},
	{"ESPISPI",			BIT(2)},
	{"XHCI",			BIT(3)},
	{"SPA",				BIT(4)},
	{"SPB",				BIT(5)},
	{"SBR16B0",			BIT(6)},
	{"GBE",				BIT(7)},

	{"SBR8B7",			BIT(0)},
	{"SBR8B6",			BIT(1)},
	{"SBR16B1",			BIT(1)},
	{"SBR8B8",			BIT(2)},
	{"ESE",				BIT(3)},
	{"SBR8B10",			BIT(4)},
	{"D2D_DISP_0",			BIT(5)},
	{"LPSS",			BIT(6)},
	{"LPC",				BIT(7)},

	{"SMB",				BIT(0)},
	{"ISH",				BIT(1)},
	{"SBR8B2",			BIT(2)},
	{"NPK_0",			BIT(3)},
	{"D2D_NOC_0",			BIT(4)},
	{"SAFSS",			BIT(5)},
	{"FUSE",			BIT(6)},
	{"D2D_DISP_1",			BIT(7)},

	{"MPFPW1",			BIT(0)},
	{"XDCI",			BIT(1)},
	{"EXI",				BIT(2)},
	{"CSE",				BIT(3)},
	{"KVMCC",			BIT(4)},
	{"PMT",				BIT(5)},
	{"CLINK",			BIT(6)},
	{"PTIO",			BIT(7)},

	{"USBR",			BIT(0)},
	{"SUSRAM",			BIT(1)},
	{"SMT1",			BIT(2)},
	{"U3FPW1",			BIT(3)},
	{"SMS2",			BIT(4)},
	{"SMS1",			BIT(5)},
	{"CSMERTC",			BIT(6)},
	{"CSMEPSF",			BIT(7)},

	{"FIA_PG",			BIT(0)},
	{"SBR16B4",			BIT(1)},
	{"P2SB8B",			BIT(2)},
	{"DBG_SBR",			BIT(3)},
	{"SBR8B9",			BIT(4)},
	{"OSSE_SMT1",			BIT(5)},
	{"SBR8B10",			BIT(6)},
	{"SBR16B3",			BIT(7)},

	{"G5FPW1",			BIT(0)},
	{"SBRG",			BIT(1)},
	{"PSF4",			BIT(2)},
	{"CNVI",			BIT(3)},
	{"UFSX2",			BIT(4)},
	{"ENDBG",			BIT(5)},
	{"FIACPCB_P5X4",		BIT(6)},
	{"SBR8B3",			BIT(7)},

	{"SBR8B0",			BIT(0)},
	{"NPK_1",			BIT(1)},
	{"OSSE_HOTHAM",			BIT(2)},
	{"D2D_NOC_2",			BIT(3)},
	{"SBR8B1",			BIT(4)},
	{"PSF6",			BIT(5)},
	{"PSF7",			BIT(6)},
	{"FIA_U",			BIT(7)},

	{"PSF8",			BIT(0)},
	{"SBR16B2",			BIT(1)},
	{"D2D_IPU",			BIT(2)},
	{"FIACPCB_U",			BIT(3)},
	{"TAM",				BIT(4)},
	{"D2D_NOC_1",			BIT(5)},
	{"TBTLSX",			BIT(6)},
	{"THC0",			BIT(7)},

	{"THC1",			BIT(0)},
	{"PMC_1",			BIT(1)},
	{"SBR8B5",			BIT(2)},
	{"UFSPW1",			BIT(3)},
	{"DBC",				BIT(4)},
	{"TCSS",			BIT(5)},
	{"FIA_P5X4",			BIT(6)},
	{"DISP_PGA",			BIT(7)},

	{"DBG_PSF",			BIT(0)},
	{"PSF0",			BIT(1)},
	{"P2SB16B",			BIT(2)},
	{"ACE0",			BIT(3)},
	{"ACE1",			BIT(4)},
	{"ACE2",			BIT(5)},
	{"ACE3",			BIT(6)},
	{"ACE4",			BIT(7)},

	{"ACE5",			BIT(0)},
	{"ACE6",			BIT(1)},
	{"ACE7",			BIT(2)},
	{"ACE8",			BIT(3)},
	{"ACE9",			BIT(4)},
	{"ACE10",			BIT(5)},
	{"FIACPCB",			BIT(6)},
	{"OSSE",			BIT(7)},
	{}
};

const struct pmc_bit_map *ext_lnl_pfear_map[] = {
	lnl_pfear_map,
	NULL
};

const struct pmc_reg_map lnl_socm_reg_map = {
	.pfear_sts = ext_lnl_pfear_map,
	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
	.ltr_show_sts = lnl_ltr_show_map,
	.msr_sts = msr_map,
	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
	.regmap_length = LNL_PMC_MMIO_REG_LEN,
	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
	.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
	.lpm_num_maps = ADL_LPM_NUM_MAPS,
	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
	.etr3_offset = ETR3_OFFSET,
	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
	.lpm_en_offset = MTL_LPM_EN_OFFSET,
	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
	.lpm_sts = lnl_lpm_maps,
	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
	.s0ix_blocker_maps = lnl_blk_maps,
	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
};

#define LNL_NPU_PCI_DEV		0x643e
#define LNL_IPU_PCI_DEV		0x645d

/*
 * Set power state of select devices that do not have drivers to D3
 * so that they do not block Package C entry.
 */
static void lnl_d3_fixup(void)
{
	pmc_core_set_device_d3(LNL_IPU_PCI_DEV);
	pmc_core_set_device_d3(LNL_NPU_PCI_DEV);
}

static int lnl_resume(struct pmc_dev *pmcdev)
{
	lnl_d3_fixup();
	pmc_core_send_ltr_ignore(pmcdev, 3, 0);

	return pmc_core_resume_common(pmcdev);
}

int lnl_core_init(struct pmc_dev *pmcdev)
{
	int ret;
	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC];

	lnl_d3_fixup();

	pmcdev->suspend = cnl_suspend;
	pmcdev->resume = lnl_resume;

	pmc->map = &lnl_socm_reg_map;
	ret = get_primary_reg_base(pmc);
	if (ret)
		return ret;

	pmc_core_get_low_power_modes(pmcdev);

	return 0;
}
Commit	Line	Data
3748dfda RJ	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* This file contains platform specific structure definitions
f1f663eb	4	* and init function used by Lunar Lake PCH.
3748dfda RJ	5	*
	6	* Copyright (c) 2022, Intel Corporation.
	7	* All Rights Reserved.
	8	*
	9	*/
	10
	11	#include <linux/cpu.h>
	12	#include <linux/pci.h>
	13
	14	#include "core.h"
	15
3748dfda RJ	16	const struct pmc_bit_map lnl_ltr_show_map[] = {
	17	{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
	18	{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
	19	{"SATA", CNP_PMC_LTR_SATA},
	20	{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
	21	{"XHCI", CNP_PMC_LTR_XHCI},
	22	{"SOUTHPORT_F", ADL_PMC_LTR_SPF},
	23	{"ME", CNP_PMC_LTR_ME},
	24	/* EVA is Enterprise Value Add, doesn't really exist on PCH */
	25	{"SATA1", CNP_PMC_LTR_EVA},
	26	{"SOUTHPORT_C", CNP_PMC_LTR_SPC},
	27	{"HD_AUDIO", CNP_PMC_LTR_AZ},
	28	{"CNV", CNP_PMC_LTR_CNV},
	29	{"LPSS", CNP_PMC_LTR_LPSS},
	30	{"SOUTHPORT_D", CNP_PMC_LTR_SPD},
	31	{"SOUTHPORT_E", CNP_PMC_LTR_SPE},
	32	{"SATA2", CNP_PMC_LTR_CAM},
	33	{"ESPI", CNP_PMC_LTR_ESPI},
	34	{"SCC", CNP_PMC_LTR_SCC},
	35	{"ISH", CNP_PMC_LTR_ISH},
	36	{"UFSX2", CNP_PMC_LTR_UFSX2},
	37	{"EMMC", CNP_PMC_LTR_EMMC},
	38	/*
	39	* Check intel_pmc_core_ids[] users of cnp_reg_map for
	40	* a list of core SoCs using this.
	41	*/
	42	{"WIGIG", ICL_PMC_LTR_WIGIG},
	43	{"THC0", TGL_PMC_LTR_THC0},
	44	{"THC1", TGL_PMC_LTR_THC1},
	45	{"SOUTHPORT_G", CNP_PMC_LTR_RESERVED},
	46
	47	{"ESE", MTL_PMC_LTR_ESE},
	48	{"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
	49	{"DMI3", ARL_PMC_LTR_DMI3},
	50	{"OSSE", LNL_PMC_LTR_OSSE},
	51
	52	/* Below two cannot be used for LTR_IGNORE */
	53	{"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
	54	{"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
	55	{}
	56	};
	57
	58	const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
86cc9c70 XP	59	{"PMC_PGD0_PG_STS", BIT(0), 0},
	60	{"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0},
	61	{"ESPISPI_PGD0_PG_STS", BIT(2), 0},
	62	{"XHCI_PGD0_PG_STS", BIT(3), 1},
	63	{"SPA_PGD0_PG_STS", BIT(4), 1},
	64	{"SPB_PGD0_PG_STS", BIT(5), 1},
	65	{"SPR16B0_PGD0_PG_STS", BIT(6), 0},
	66	{"GBE_PGD0_PG_STS", BIT(7), 1},
	67	{"SBR8B7_PGD0_PG_STS", BIT(8), 0},
	68	{"SBR8B6_PGD0_PG_STS", BIT(9), 0},
	69	{"SBR16B1_PGD0_PG_STS", BIT(10), 0},
	70	{"SBR8B8_PGD0_PG_STS", BIT(11), 0},
	71	{"ESE_PGD3_PG_STS", BIT(12), 1},
	72	{"D2D_DISP_PGD0_PG_STS", BIT(13), 1},
	73	{"LPSS_PGD0_PG_STS", BIT(14), 1},
	74	{"LPC_PGD0_PG_STS", BIT(15), 0},
	75	{"SMB_PGD0_PG_STS", BIT(16), 0},
	76	{"ISH_PGD0_PG_STS", BIT(17), 0},
	77	{"SBR8B2_PGD0_PG_STS", BIT(18), 0},
	78	{"NPK_PGD0_PG_STS", BIT(19), 0},
	79	{"D2D_NOC_PGD0_PG_STS", BIT(20), 0},
	80	{"SAFSS_PGD0_PG_STS", BIT(21), 0},
	81	{"FUSE_PGD0_PG_STS", BIT(22), 0},
	82	{"D2D_DISP_PGD1_PG_STS", BIT(23), 1},
	83	{"MPFPW1_PGD0_PG_STS", BIT(24), 0},
	84	{"XDCI_PGD0_PG_STS", BIT(25), 1},
	85	{"EXI_PGD0_PG_STS", BIT(26), 0},
	86	{"CSE_PGD0_PG_STS", BIT(27), 1},
	87	{"KVMCC_PGD0_PG_STS", BIT(28), 1},
	88	{"PMT_PGD0_PG_STS", BIT(29), 1},
	89	{"CLINK_PGD0_PG_STS", BIT(30), 1},
	90	{"PTIO_PGD0_PG_STS", BIT(31), 1},
3748dfda RJ	91	{}
	92	};
	93
	94	const struct pmc_bit_map lnl_power_gating_status_1_map[] = {
86cc9c70 XP	95	{"USBR0_PGD0_PG_STS", BIT(0), 1},
	96	{"SUSRAM_PGD0_PG_STS", BIT(1), 1},
	97	{"SMT1_PGD0_PG_STS", BIT(2), 1},
	98	{"U3FPW1_PGD0_PG_STS", BIT(3), 0},
	99	{"SMS2_PGD0_PG_STS", BIT(4), 1},
	100	{"SMS1_PGD0_PG_STS", BIT(5), 1},
	101	{"CSMERTC_PGD0_PG_STS", BIT(6), 0},
	102	{"CSMEPSF_PGD0_PG_STS", BIT(7), 0},
	103	{"FIA_PG_PGD0_PG_STS", BIT(8), 0},
	104	{"SBR16B4_PGD0_PG_STS", BIT(9), 0},
	105	{"P2SB8B_PGD0_PG_STS", BIT(10), 1},
	106	{"DBG_SBR_PGD0_PG_STS", BIT(11), 0},
	107	{"SBR8B9_PGD0_PG_STS", BIT(12), 0},
	108	{"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1},
	109	{"SBR8B10_PGD0_PG_STS", BIT(14), 0},
	110	{"SBR16B3_PGD0_PG_STS", BIT(15), 0},
	111	{"G5FPW1_PGD0_PG_STS", BIT(16), 0},
	112	{"SBRG_PGD0_PG_STS", BIT(17), 0},
	113	{"PSF4_PGD0_PG_STS", BIT(18), 0},
	114	{"CNVI_PGD0_PG_STS", BIT(19), 0},
	115	{"USFX2_PGD0_PG_STS", BIT(20), 1},
	116	{"ENDBG_PGD0_PG_STS", BIT(21), 0},
	117	{"FIACPCB_P5X4_PGD0_PG_STS", BIT(22), 0},
	118	{"SBR8B3_PGD0_PG_STS", BIT(23), 0},
	119	{"SBR8B0_PGD0_PG_STS", BIT(24), 0},
	120	{"NPK_PGD1_PG_STS", BIT(25), 0},
	121	{"OSSE_HOTHAM_PGD0_PG_STS", BIT(26), 1},
	122	{"D2D_NOC_PGD2_PG_STS", BIT(27), 1},
	123	{"SBR8B1_PGD0_PG_STS", BIT(28), 0},
	124	{"PSF6_PGD0_PG_STS", BIT(29), 0},
	125	{"PSF7_PGD0_PG_STS", BIT(30), 0},
	126	{"FIA_U_PGD0_PG_STS", BIT(31), 0},
3748dfda RJ	127	{}
	128	};
	129
	130	const struct pmc_bit_map lnl_power_gating_status_2_map[] = {
86cc9c70 XP	131	{"PSF8_PGD0_PG_STS", BIT(0), 0},
	132	{"SBR16B2_PGD0_PG_STS", BIT(1), 0},
	133	{"D2D_IPU_PGD0_PG_STS", BIT(2), 1},
	134	{"FIACPCB_U_PGD0_PG_STS", BIT(3), 0},
	135	{"TAM_PGD0_PG_STS", BIT(4), 1},
	136	{"D2D_NOC_PGD1_PG_STS", BIT(5), 1},
	137	{"TBTLSX_PGD0_PG_STS", BIT(6), 1},
	138	{"THC0_PGD0_PG_STS", BIT(7), 1},
	139	{"THC1_PGD0_PG_STS", BIT(8), 1},
	140	{"PMC_PGD0_PG_STS", BIT(9), 0},
	141	{"SBR8B5_PGD0_PG_STS", BIT(10), 0},
	142	{"UFSPW1_PGD0_PG_STS", BIT(11), 0},
	143	{"DBC_PGD0_PG_STS", BIT(12), 0},
	144	{"TCSS_PGD0_PG_STS", BIT(13), 0},
	145	{"FIA_P5X4_PGD0_PG_STS", BIT(14), 0},
	146	{"DISP_PGA_PGD0_PG_STS", BIT(15), 0},
	147	{"DISP_PSF_PGD0_PG_STS", BIT(16), 0},
	148	{"PSF0_PGD0_PG_STS", BIT(17), 0},
	149	{"P2SB16B_PGD0_PG_STS", BIT(18), 1},
	150	{"ACE_PGD0_PG_STS", BIT(19), 0},
	151	{"ACE_PGD1_PG_STS", BIT(20), 0},
	152	{"ACE_PGD2_PG_STS", BIT(21), 0},
	153	{"ACE_PGD3_PG_STS", BIT(22), 0},
	154	{"ACE_PGD4_PG_STS", BIT(23), 0},
	155	{"ACE_PGD5_PG_STS", BIT(24), 0},
	156	{"ACE_PGD6_PG_STS", BIT(25), 0},
	157	{"ACE_PGD7_PG_STS", BIT(26), 0},
	158	{"ACE_PGD8_PG_STS", BIT(27), 0},
	159	{"ACE_PGD9_PG_STS", BIT(28), 0},
	160	{"ACE_PGD10_PG_STS", BIT(29), 0},
	161	{"FIACPCB_PG_PGD0_PG_STS", BIT(30), 0},
	162	{"OSSE_PGD0_PG_STS", BIT(31), 1},
3748dfda RJ	163	{}
	164	};
	165
	166	const struct pmc_bit_map lnl_d3_status_0_map[] = {
86cc9c70 XP	167	{"LPSS_D3_STS", BIT(3), 1},
	168	{"XDCI_D3_STS", BIT(4), 1},
	169	{"XHCI_D3_STS", BIT(5), 1},
	170	{"SPA_D3_STS", BIT(12), 0},
	171	{"SPB_D3_STS", BIT(13), 0},
	172	{"OSSE_D3_STS", BIT(15), 0},
	173	{"ESPISPI_D3_STS", BIT(18), 0},
	174	{"PSTH_D3_STS", BIT(21), 0},
3748dfda RJ	175	{}
	176	};
	177
	178	const struct pmc_bit_map lnl_d3_status_1_map[] = {
86cc9c70 XP	179	{"OSSE_SMT1_D3_STS", BIT(7), 0},
	180	{"GBE_D3_STS", BIT(19), 0},
	181	{"ITSS_D3_STS", BIT(23), 0},
	182	{"CNVI_D3_STS", BIT(27), 0},
	183	{"UFSX2_D3_STS", BIT(28), 1},
	184	{"OSSE_HOTHAM_D3_STS", BIT(31), 0},
3748dfda RJ	185	{}
	186	};
	187
	188	const struct pmc_bit_map lnl_d3_status_2_map[] = {
86cc9c70 XP	189	{"ESE_D3_STS", BIT(0), 0},
	190	{"CSMERTC_D3_STS", BIT(1), 0},
	191	{"SUSRAM_D3_STS", BIT(2), 0},
	192	{"CSE_D3_STS", BIT(4), 0},
	193	{"KVMCC_D3_STS", BIT(5), 0},
	194	{"USBR0_D3_STS", BIT(6), 0},
	195	{"ISH_D3_STS", BIT(7), 0},
	196	{"SMT1_D3_STS", BIT(8), 0},
	197	{"SMT2_D3_STS", BIT(9), 0},
	198	{"SMT3_D3_STS", BIT(10), 0},
	199	{"OSSE_SMT2_D3_STS", BIT(13), 0},
	200	{"CLINK_D3_STS", BIT(14), 0},
	201	{"PTIO_D3_STS", BIT(16), 0},
	202	{"PMT_D3_STS", BIT(17), 0},
	203	{"SMS1_D3_STS", BIT(18), 0},
	204	{"SMS2_D3_STS", BIT(19), 0},
3748dfda RJ	205	{}
	206	};
	207
	208	const struct pmc_bit_map lnl_d3_status_3_map[] = {
86cc9c70 XP	209	{"THC0_D3_STS", BIT(14), 1},
	210	{"THC1_D3_STS", BIT(15), 1},
	211	{"OSSE_SMT3_D3_STS", BIT(21), 0},
	212	{"ACE_D3_STS", BIT(23), 0},
3748dfda RJ	213	{}
	214	};
	215
	216	const struct pmc_bit_map lnl_vnn_req_status_0_map[] = {
86cc9c70 XP	217	{"LPSS_VNN_REQ_STS", BIT(3), 1},
	218	{"OSSE_VNN_REQ_STS", BIT(15), 1},
	219	{"ESPISPI_VNN_REQ_STS", BIT(18), 1},
3748dfda RJ	220	{}
	221	};
	222
	223	const struct pmc_bit_map lnl_vnn_req_status_1_map[] = {
86cc9c70 XP	224	{"NPK_VNN_REQ_STS", BIT(4), 1},
	225	{"OSSE_SMT1_VNN_REQ_STS", BIT(7), 1},
	226	{"DFXAGG_VNN_REQ_STS", BIT(8), 0},
	227	{"EXI_VNN_REQ_STS", BIT(9), 1},
	228	{"P2D_VNN_REQ_STS", BIT(18), 1},
	229	{"GBE_VNN_REQ_STS", BIT(19), 1},
	230	{"SMB_VNN_REQ_STS", BIT(25), 1},
	231	{"LPC_VNN_REQ_STS", BIT(26), 0},
3748dfda RJ	232	{}
	233	};
	234
	235	const struct pmc_bit_map lnl_vnn_req_status_2_map[] = {
86cc9c70 XP	236	{"eSE_VNN_REQ_STS", BIT(0), 1},
	237	{"CSMERTC_VNN_REQ_STS", BIT(1), 1},
	238	{"CSE_VNN_REQ_STS", BIT(4), 1},
	239	{"ISH_VNN_REQ_STS", BIT(7), 1},
	240	{"SMT1_VNN_REQ_STS", BIT(8), 1},
	241	{"CLINK_VNN_REQ_STS", BIT(14), 1},
	242	{"SMS1_VNN_REQ_STS", BIT(18), 1},
	243	{"SMS2_VNN_REQ_STS", BIT(19), 1},
	244	{"GPIOCOM4_VNN_REQ_STS", BIT(20), 1},
	245	{"GPIOCOM3_VNN_REQ_STS", BIT(21), 1},
	246	{"GPIOCOM2_VNN_REQ_STS", BIT(22), 0},
	247	{"GPIOCOM1_VNN_REQ_STS", BIT(23), 1},
	248	{"GPIOCOM0_VNN_REQ_STS", BIT(24), 1},
3748dfda RJ	249	{}
	250	};
	251
	252	const struct pmc_bit_map lnl_vnn_req_status_3_map[] = {
86cc9c70 XP	253	{"DISP_SHIM_VNN_REQ_STS", BIT(2), 0},
	254	{"DTS0_VNN_REQ_STS", BIT(7), 0},
	255	{"GPIOCOM5_VNN_REQ_STS", BIT(11), 2},
3748dfda RJ	256	{}
	257	};
	258
	259	const struct pmc_bit_map lnl_vnn_misc_status_map[] = {
86cc9c70 XP	260	{"CPU_C10_REQ_STS", BIT(0), 0},
	261	{"TS_OFF_REQ_STS", BIT(1), 0},
	262	{"PNDE_MET_REQ_STS", BIT(2), 1},
	263	{"PCIE_DEEP_PM_REQ_STS", BIT(3), 0},
	264	{"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4), 0},
	265	{"NPK_VNNAON_REQ_STS", BIT(5), 0},
	266	{"VNN_SOC_REQ_STS", BIT(6), 1},
	267	{"ISH_VNNAON_REQ_STS", BIT(7), 0},
	268	{"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1},
	269	{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1},
	270	{"D2D_NOC_IPU_QACTIVE_REQ_STS", BIT(10), 1},
	271	{"PLT_GREATER_REQ_STS", BIT(11), 1},
	272	{"PCIE_CLKREQ_REQ_STS", BIT(12), 0},
	273	{"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0},
	274	{"PM_SYNC_STATES_REQ_STS", BIT(14), 0},
	275	{"EA_REQ_STS", BIT(15), 0},
	276	{"MPHY_CORE_OFF_REQ_STS", BIT(16), 0},
	277	{"BRK_EV_EN_REQ_STS", BIT(17), 0},
	278	{"AUTO_DEMO_EN_REQ_STS", BIT(18), 0},
	279	{"ITSS_CLK_SRC_REQ_STS", BIT(19), 1},
	280	{"LPC_CLK_SRC_REQ_STS", BIT(20), 0},
	281	{"ARC_IDLE_REQ_STS", BIT(21), 0},
	282	{"MPHY_SUS_REQ_STS", BIT(22), 0},
	283	{"FIA_DEEP_PM_REQ_STS", BIT(23), 0},
	284	{"UXD_CONNECTED_REQ_STS", BIT(24), 1},
	285	{"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0},
	286	{"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1},
	287	{"PRE_WAKE0_REQ_STS", BIT(27), 1},
	288	{"PRE_WAKE1_REQ_STS", BIT(28), 1},
	289	{"PRE_WAKE2_EN_REQ_STS", BIT(29), 1},
	290	{"WOV_REQ_STS", BIT(30), 0},
	291	{"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31", BIT(31), 1},
3748dfda RJ	292	{}
	293	};
	294
	295	const struct pmc_bit_map lnl_clocksource_status_map[] = {
86cc9c70 XP	296	{"AON2_OFF_STS", BIT(0), 0},
	297	{"AON3_OFF_STS", BIT(1), 1},
	298	{"AON4_OFF_STS", BIT(2), 1},
	299	{"AON5_OFF_STS", BIT(3), 1},
	300	{"AON1_OFF_STS", BIT(4), 0},
	301	{"MPFPW1_0_PLL_OFF_STS", BIT(6), 1},
	302	{"USB3_PLL_OFF_STS", BIT(8), 1},
	303	{"AON3_SPL_OFF_STS", BIT(9), 1},
	304	{"G5FPW1_PLL_OFF_STS", BIT(15), 1},
	305	{"XTAL_AGGR_OFF_STS", BIT(17), 1},
	306	{"USB2_PLL_OFF_STS", BIT(18), 0},
	307	{"SAF_PLL_OFF_STS", BIT(19), 1},
	308	{"SE_TCSS_PLL_OFF_STS", BIT(20), 1},
	309	{"DDI_PLL_OFF_STS", BIT(21), 1},
	310	{"FILTER_PLL_OFF_STS", BIT(22), 1},
	311	{"ACE_PLL_OFF_STS", BIT(24), 0},
	312	{"FABRIC_PLL_OFF_STS", BIT(25), 1},
	313	{"SOC_PLL_OFF_STS", BIT(26), 1},
	314	{"REF_OFF_STS", BIT(28), 1},
	315	{"IMG_OFF_STS", BIT(29), 1},
	316	{"RTC_PLL_OFF_STS", BIT(31), 0},
3748dfda RJ	317	{}
	318	};
	319
4f3eec14	320	const struct pmc_bit_map lnl_signal_status_map[] = {
86cc9c70 XP	321	{"LSX_Wake0_STS", BIT(0), 0},
	322	{"LSX_Wake1_STS", BIT(1), 0},
	323	{"LSX_Wake2_STS", BIT(2), 0},
	324	{"LSX_Wake3_STS", BIT(3), 0},
	325	{"LSX_Wake4_STS", BIT(4), 0},
	326	{"LSX_Wake5_STS", BIT(5), 0},
	327	{"LSX_Wake6_STS", BIT(6), 0},
	328	{"LSX_Wake7_STS", BIT(7), 0},
	329	{"LPSS_Wake0_STS", BIT(8), 1},
	330	{"LPSS_Wake1_STS", BIT(9), 1},
	331	{"Int_Timer_SS_Wake0_STS", BIT(10), 1},
	332	{"Int_Timer_SS_Wake1_STS", BIT(11), 1},
	333	{"Int_Timer_SS_Wake2_STS", BIT(12), 1},
	334	{"Int_Timer_SS_Wake3_STS", BIT(13), 1},
	335	{"Int_Timer_SS_Wake4_STS", BIT(14), 1},
	336	{"Int_Timer_SS_Wake5_STS", BIT(15), 1},
	337	{}
	338	};
	339
	340	const struct pmc_bit_map lnl_rsc_status_map[] = {
	341	{"Memory", 0, 1},
	342	{"PSF0", 0, 1},
	343	{"PSF4", 0, 1},
	344	{"PSF6", 0, 1},
	345	{"PSF7", 0, 1},
	346	{"PSF8", 0, 1},
	347	{"SAF_CFI_LINK", 0, 1},
	348	{"SBR", 0, 1},
4f3eec14 XP	349	{}
	350	};
	351
3748dfda RJ	352	const struct pmc_bit_map *lnl_lpm_maps[] = {
	353	lnl_clocksource_status_map,
	354	lnl_power_gating_status_0_map,
	355	lnl_power_gating_status_1_map,
	356	lnl_power_gating_status_2_map,
	357	lnl_d3_status_0_map,
	358	lnl_d3_status_1_map,
	359	lnl_d3_status_2_map,
	360	lnl_d3_status_3_map,
	361	lnl_vnn_req_status_0_map,
	362	lnl_vnn_req_status_1_map,
	363	lnl_vnn_req_status_2_map,
	364	lnl_vnn_req_status_3_map,
	365	lnl_vnn_misc_status_map,
4f3eec14	366	lnl_signal_status_map,
3748dfda RJ	367	NULL
	368	};
	369
86cc9c70 XP	370	const struct pmc_bit_map *lnl_blk_maps[] = {
	371	lnl_power_gating_status_0_map,
	372	lnl_power_gating_status_1_map,
	373	lnl_power_gating_status_2_map,
	374	lnl_rsc_status_map,
	375	lnl_vnn_req_status_0_map,
	376	lnl_vnn_req_status_1_map,
	377	lnl_vnn_req_status_2_map,
	378	lnl_vnn_req_status_3_map,
	379	lnl_d3_status_0_map,
	380	lnl_d3_status_1_map,
	381	lnl_d3_status_2_map,
	382	lnl_d3_status_3_map,
	383	lnl_clocksource_status_map,
	384	lnl_vnn_misc_status_map,
	385	lnl_signal_status_map,
	386	NULL
	387	};
	388
3748dfda RJ	389	const struct pmc_bit_map lnl_pfear_map[] = {
	390	{"PMC_0", BIT(0)},
	391	{"FUSE_OSSE", BIT(1)},
	392	{"ESPISPI", BIT(2)},
	393	{"XHCI", BIT(3)},
	394	{"SPA", BIT(4)},
	395	{"SPB", BIT(5)},
	396	{"SBR16B0", BIT(6)},
	397	{"GBE", BIT(7)},
	398
	399	{"SBR8B7", BIT(0)},
	400	{"SBR8B6", BIT(1)},
	401	{"SBR16B1", BIT(1)},
	402	{"SBR8B8", BIT(2)},
	403	{"ESE", BIT(3)},
	404	{"SBR8B10", BIT(4)},
	405	{"D2D_DISP_0", BIT(5)},
	406	{"LPSS", BIT(6)},
	407	{"LPC", BIT(7)},
	408
	409	{"SMB", BIT(0)},
	410	{"ISH", BIT(1)},
	411	{"SBR8B2", BIT(2)},
	412	{"NPK_0", BIT(3)},
	413	{"D2D_NOC_0", BIT(4)},
	414	{"SAFSS", BIT(5)},
	415	{"FUSE", BIT(6)},
	416	{"D2D_DISP_1", BIT(7)},
	417
	418	{"MPFPW1", BIT(0)},
	419	{"XDCI", BIT(1)},
	420	{"EXI", BIT(2)},
	421	{"CSE", BIT(3)},
	422	{"KVMCC", BIT(4)},
	423	{"PMT", BIT(5)},
	424	{"CLINK", BIT(6)},
	425	{"PTIO", BIT(7)},
	426
	427	{"USBR", BIT(0)},
	428	{"SUSRAM", BIT(1)},
	429	{"SMT1", BIT(2)},
	430	{"U3FPW1", BIT(3)},
	431	{"SMS2", BIT(4)},
	432	{"SMS1", BIT(5)},
	433	{"CSMERTC", BIT(6)},
	434	{"CSMEPSF", BIT(7)},
	435
	436	{"FIA_PG", BIT(0)},
	437	{"SBR16B4", BIT(1)},
	438	{"P2SB8B", BIT(2)},
	439	{"DBG_SBR", BIT(3)},
	440	{"SBR8B9", BIT(4)},
	441	{"OSSE_SMT1", BIT(5)},
	442	{"SBR8B10", BIT(6)},
	443	{"SBR16B3", BIT(7)},
	444
	445	{"G5FPW1", BIT(0)},
	446	{"SBRG", BIT(1)},
	447	{"PSF4", BIT(2)},
	448	{"CNVI", BIT(3)},
	449	{"UFSX2", BIT(4)},
	450	{"ENDBG", BIT(5)},
	451	{"FIACPCB_P5X4", BIT(6)},
	452	{"SBR8B3", BIT(7)},
453
454	{"SBR8B0", BIT(0)},
455	{"NPK_1", BIT(1)},
456	{"OSSE_HOTHAM", BIT(2)},
457	{"D2D_NOC_2", BIT(3)},
458	{"SBR8B1", BIT(4)},
459	{"PSF6", BIT(5)},
460	{"PSF7", BIT(6)},
461	{"FIA_U", BIT(7)},
462
463	{"PSF8", BIT(0)},
464	{"SBR16B2", BIT(1)},
465	{"D2D_IPU", BIT(2)},
466	{"FIACPCB_U", BIT(3)},
467	{"TAM", BIT(4)},
468	{"D2D_NOC_1", BIT(5)},
469	{"TBTLSX", BIT(6)},
470	{"THC0", BIT(7)},
471
472	{"THC1", BIT(0)},
473	{"PMC_1", BIT(1)},
474	{"SBR8B5", BIT(2)},
475	{"UFSPW1", BIT(3)},
476	{"DBC", BIT(4)},
477	{"TCSS", BIT(5)},
478	{"FIA_P5X4", BIT(6)},
479	{"DISP_PGA", BIT(7)},
480
481	{"DBG_PSF", BIT(0)},
482	{"PSF0", BIT(1)},
483	{"P2SB16B", BIT(2)},
484	{"ACE0", BIT(3)},
485	{"ACE1", BIT(4)},
486	{"ACE2", BIT(5)},
487	{"ACE3", BIT(6)},
488	{"ACE4", BIT(7)},
489
490	{"ACE5", BIT(0)},
491	{"ACE6", BIT(1)},
492	{"ACE7", BIT(2)},
493	{"ACE8", BIT(3)},
494	{"ACE9", BIT(4)},
495	{"ACE10", BIT(5)},
496	{"FIACPCB", BIT(6)},
497	{"OSSE", BIT(7)},
498	{}
499	};
500
501	const struct pmc_bit_map *ext_lnl_pfear_map[] = {
502	lnl_pfear_map,
503	NULL
504	};
505
506	const struct pmc_reg_map lnl_socm_reg_map = {
507	.pfear_sts = ext_lnl_pfear_map,
508	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
509	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
510	.ltr_show_sts = lnl_ltr_show_map,
511	.msr_sts = msr_map,
512	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
513	.regmap_length = LNL_PMC_MMIO_REG_LEN,
514	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
515	.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
516	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
517	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
518	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
519	.lpm_num_maps = ADL_LPM_NUM_MAPS,
520	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
521	.etr3_offset = ETR3_OFFSET,
522	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
523	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
524	.lpm_en_offset = MTL_LPM_EN_OFFSET,
525	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
526	.lpm_sts = lnl_lpm_maps,
527	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
528	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
86cc9c70 XP	529	.s0ix_blocker_maps = lnl_blk_maps,
86cc9c70 XP	530	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
3748dfda RJ	531	};
	532
	533	#define LNL_NPU_PCI_DEV 0x643e
	534	#define LNL_IPU_PCI_DEV 0x645d
	535
	536	/*
	537	* Set power state of select devices that do not have drivers to D3
	538	* so that they do not block Package C entry.
	539	*/
	540	static void lnl_d3_fixup(void)
	541	{
	542	pmc_core_set_device_d3(LNL_IPU_PCI_DEV);
	543	pmc_core_set_device_d3(LNL_NPU_PCI_DEV);
	544	}
	545
	546	static int lnl_resume(struct pmc_dev *pmcdev)
	547	{
	548	lnl_d3_fixup();
6f9fac55 DB	549	pmc_core_send_ltr_ignore(pmcdev, 3, 0);
6f9fac55 DB	550
3748dfda RJ	551	return pmc_core_resume_common(pmcdev);
	552	}
	553
	554	int lnl_core_init(struct pmc_dev *pmcdev)
	555	{
	556	int ret;
3748dfda RJ	557	struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC];
	558
	559	lnl_d3_fixup();
	560
6f9fac55	561	pmcdev->suspend = cnl_suspend;
3748dfda	562	pmcdev->resume = lnl_resume;
3748dfda	563
e6ba4acd DB	564	pmc->map = &lnl_socm_reg_map;
	565	ret = get_primary_reg_base(pmc);
	566	if (ret)
	567	return ret;
3748dfda	568
e6ba4acd	569	pmc_core_get_low_power_modes(pmcdev);
3748dfda RJ	570
	571	return 0;
	572	}