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platform/x86: amd-pmc: Output error codes in messages
[linux-block.git] / drivers / platform / x86 / amd-pmc.c
CommitLineData
156ec473
SS		 1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/acpi.h>
14#include <linux/bitfield.h>
15#include <linux/bits.h>
16#include <linux/debugfs.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
59348401 20#include <linux/limits.h>
156ec473
SS		 21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/platform_device.h>
32370191 24#include <linux/pm_qos.h>
59348401 25#include <linux/rtc.h>
156ec473
SS		 26#include <linux/suspend.h>
27#include <linux/seq_file.h>
28#include <linux/uaccess.h>
29
30/* SMU communication registers */
31#define AMD_PMC_REGISTER_MESSAGE 0x538
32#define AMD_PMC_REGISTER_RESPONSE 0x980
33#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
34
f6045de1
SG		 35/* PMC Scratch Registers */
36#define AMD_PMC_SCRATCH_REG_CZN 0x94
37#define AMD_PMC_SCRATCH_REG_YC 0xD14
38
426c0ff2
SG		 39/* STB Registers */
40#define AMD_PMC_STB_INDEX_ADDRESS 0xF8
41#define AMD_PMC_STB_INDEX_DATA 0xFC
42#define AMD_PMC_STB_PMI_0 0x03E30600
43#define AMD_PMC_STB_PREDEF 0xC6000001
44
3d7d407d
SG		 45/* STB S2D(Spill to DRAM) has different message port offset */
46#define STB_SPILL_TO_DRAM 0xBE
47#define AMD_S2D_REGISTER_MESSAGE 0xA20
48#define AMD_S2D_REGISTER_RESPONSE 0xA80
49#define AMD_S2D_REGISTER_ARGUMENT 0xA88
50
51/* STB Spill to DRAM Parameters */
52#define S2D_TELEMETRY_BYTES_MAX 0x100000
53#define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
54
156ec473
SS		 55/* Base address of SMU for mapping physical address to virtual address */
56#define AMD_PMC_SMU_INDEX_ADDRESS 0xB8
57#define AMD_PMC_SMU_INDEX_DATA 0xBC
58#define AMD_PMC_MAPPING_SIZE 0x01000
59#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
60#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
61#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
62#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
63#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
64
65/* SMU Response Codes */
66#define AMD_PMC_RESULT_OK 0x01
67#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
68#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
69#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
70#define AMD_PMC_RESULT_FAILED 0xFF
71
b9a4fa69
SS		 72/* FCH SSC Registers */
73#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
74#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
75#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
76#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
77#define FCH_SSC_MAPPING_SIZE 0x800
78#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
79#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
80
76620567
SS		 81/* SMU Message Definations */
82#define SMU_MSG_GETSMUVERSION 0x02
83#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
84#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
85#define SMU_MSG_LOG_START 0x06
86#define SMU_MSG_LOG_RESET 0x07
87#define SMU_MSG_LOG_DUMP_DATA 0x08
88#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
156ec473
SS		 89/* List of supported CPU ids */
90#define AMD_CPU_ID_RV 0x15D0
91#define AMD_CPU_ID_RN 0x1630
92#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
93#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
83cbaf14 94#define AMD_CPU_ID_YC 0x14B5
156ec473 95
a602f511 96#define PMC_MSG_DELAY_MIN_US 50
3c3c8e88 97#define RESPONSE_REGISTER_LOOP_MAX 20000
156ec473 98
32370191
ML		 99/* QoS request for letting CPUs in idle states, but not the deepest */
100#define AMD_PMC_MAX_IDLE_STATE_LATENCY 3
101
76620567
SS		 102#define SOC_SUBSYSTEM_IP_MAX 12
103#define DELAY_MIN_US 2000
104#define DELAY_MAX_US 3000
426c0ff2 105#define FIFO_SIZE 4096
156ec473
SS		 106enum amd_pmc_def {
107 MSG_TEST = 0x01,
108 MSG_OS_HINT_PCO,
109 MSG_OS_HINT_RN,
110};
111
3d7d407d
SG		 112enum s2d_arg {
113 S2D_TELEMETRY_SIZE = 0x01,
114 S2D_PHYS_ADDR_LOW,
115 S2D_PHYS_ADDR_HIGH,
116};
117
76620567
SS		 118struct amd_pmc_bit_map {
119 const char *name;
120 u32 bit_mask;
121};
122
123static const struct amd_pmc_bit_map soc15_ip_blk[] = {
124 {"DISPLAY", BIT(0)},
125 {"CPU", BIT(1)},
126 {"GFX", BIT(2)},
127 {"VDD", BIT(3)},
128 {"ACP", BIT(4)},
129 {"VCN", BIT(5)},
130 {"ISP", BIT(6)},
131 {"NBIO", BIT(7)},
132 {"DF", BIT(8)},
133 {"USB0", BIT(9)},
134 {"USB1", BIT(10)},
135 {"LAPIC", BIT(11)},
136 {}
137};
138
156ec473
SS		 139struct amd_pmc_dev {
140 void __iomem *regbase;
76620567 141 void __iomem *smu_virt_addr;
3d7d407d 142 void __iomem *stb_virt_addr;
b9a4fa69 143 void __iomem *fch_virt_addr;
3d7d407d 144 bool msg_port;
156ec473
SS		 145 u32 base_addr;
146 u32 cpu_id;
76620567 147 u32 active_ips;
f6045de1 148/* SMU version information */
b8fb0d9b
ML		 149 u8 smu_program;
150 u8 major;
151 u8 minor;
152 u8 rev;
156ec473 153 struct device *dev;
6a5a14b1 154 struct pci_dev *rdev;
95e1b60f 155 struct mutex lock; /* generic mutex lock */
32370191 156 struct pm_qos_request amd_pmc_pm_qos_req;
156ec473
SS		 157#if IS_ENABLED(CONFIG_DEBUG_FS)
158 struct dentry *dbgfs_dir;
159#endif /* CONFIG_DEBUG_FS */
160};
161
426c0ff2
SG		 162static bool enable_stb;
163module_param(enable_stb, bool, 0644);
164MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
165
156ec473 166static struct amd_pmc_dev pmc;
4c9dbf86 167static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
426c0ff2
SG		 168static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
169static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
156ec473
SS		 170
171static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
172{
173 return ioread32(dev->regbase + reg_offset);
174}
175
176static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
177{
178 iowrite32(val, dev->regbase + reg_offset);
179}
180
76620567
SS		 181struct smu_metrics {
182 u32 table_version;
183 u32 hint_count;
9cfe0202 184 u32 s0i3_last_entry_status;
76620567
SS		 185 u32 timein_s0i2;
186 u64 timeentering_s0i3_lastcapture;
187 u64 timeentering_s0i3_totaltime;
188 u64 timeto_resume_to_os_lastcapture;
189 u64 timeto_resume_to_os_totaltime;
190 u64 timein_s0i3_lastcapture;
191 u64 timein_s0i3_totaltime;
192 u64 timein_swdrips_lastcapture;
193 u64 timein_swdrips_totaltime;
194 u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
195 u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
196} __packed;
197
40635cd3
HG		 198static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
199{
200 int rc;
201 u32 val;
202
203 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
204 if (rc)
205 return rc;
206
b8fb0d9b
ML		 207 dev->smu_program = (val >> 24) & GENMASK(7, 0);
208 dev->major = (val >> 16) & GENMASK(7, 0);
40635cd3
HG		 209 dev->minor = (val >> 8) & GENMASK(7, 0);
210 dev->rev = (val >> 0) & GENMASK(7, 0);
211
b8fb0d9b
ML		 212 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
213 dev->smu_program, dev->major, dev->minor, dev->rev);
40635cd3
HG		 214
215 return 0;
216}
217
426c0ff2
SG		 218static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
219{
220 struct amd_pmc_dev *dev = filp->f_inode->i_private;
221 u32 size = FIFO_SIZE * sizeof(u32);
222 u32 *buf;
223 int rc;
224
225 buf = kzalloc(size, GFP_KERNEL);
226 if (!buf)
227 return -ENOMEM;
228
229 rc = amd_pmc_read_stb(dev, buf);
230 if (rc) {
231 kfree(buf);
232 return rc;
233 }
234
235 filp->private_data = buf;
236 return rc;
237}
238
239static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
240 loff_t *pos)
241{
242 if (!filp->private_data)
243 return -EINVAL;
244
245 return simple_read_from_buffer(buf, size, pos, filp->private_data,
246 FIFO_SIZE * sizeof(u32));
247}
248
249static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
250{
251 kfree(filp->private_data);
252 return 0;
253}
254
f7086daa 255static const struct file_operations amd_pmc_stb_debugfs_fops = {
426c0ff2
SG		 256 .owner = THIS_MODULE,
257 .open = amd_pmc_stb_debugfs_open,
258 .read = amd_pmc_stb_debugfs_read,
259 .release = amd_pmc_stb_debugfs_release,
260};
261
3d7d407d
SG		 262static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
263{
264 struct amd_pmc_dev *dev = filp->f_inode->i_private;
265 u32 *buf;
266
267 buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
268 if (!buf)
269 return -ENOMEM;
270
271 memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
272 filp->private_data = buf;
273
274 return 0;
275}
276
277static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
278 loff_t *pos)
279{
280 if (!filp->private_data)
281 return -EINVAL;
282
283 return simple_read_from_buffer(buf, size, pos, filp->private_data,
284 S2D_TELEMETRY_BYTES_MAX);
285}
286
287static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
288{
289 kfree(filp->private_data);
290 return 0;
291}
292
293static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
294 .owner = THIS_MODULE,
295 .open = amd_pmc_stb_debugfs_open_v2,
296 .read = amd_pmc_stb_debugfs_read_v2,
297 .release = amd_pmc_stb_debugfs_release_v2,
298};
299
40635cd3
HG		 300static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
301 struct seq_file *s)
302{
303 u32 val;
304
305 switch (pdev->cpu_id) {
306 case AMD_CPU_ID_CZN:
307 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
308 break;
309 case AMD_CPU_ID_YC:
310 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
311 break;
312 default:
313 return -EINVAL;
314 }
315
316 if (dev)
317 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
318
319 if (s)
320 seq_printf(s, "SMU idlemask : 0x%x\n", val);
321
322 return 0;
323}
324
854abe25
ML		 325static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
326{
327 if (pdev->cpu_id == AMD_CPU_ID_PCO)
328 return -ENODEV;
329 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
330 return 0;
331}
332
333static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
334{
335 struct smu_metrics table;
336
337 if (get_metrics_table(pdev, &table))
338 return;
339
340 if (!table.s0i3_last_entry_status)
341 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
342 else
343 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
344 table.timein_s0i3_lastcapture);
345}
346
5b569302 347#ifdef CONFIG_DEBUG_FS
156ec473
SS		 348static int smu_fw_info_show(struct seq_file *s, void *unused)
349{
76620567
SS		 350 struct amd_pmc_dev *dev = s->private;
351 struct smu_metrics table;
352 int idx;
353
854abe25 354 if (get_metrics_table(dev, &table))
76620567
SS		 355 return -EINVAL;
356
76620567
SS		 357 seq_puts(s, "\n=== SMU Statistics ===\n");
358 seq_printf(s, "Table Version: %d\n", table.table_version);
359 seq_printf(s, "Hint Count: %d\n", table.hint_count);
9cfe0202
SG		 360 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
361 "Unknown/Fail");
76620567
SS		 362 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
363 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
7dbcaf74
SG		 364 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
365 table.timeto_resume_to_os_lastcapture);
76620567
SS		 366
367 seq_puts(s, "\n=== Active time (in us) ===\n");
368 for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
369 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
370 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
371 table.timecondition_notmet_lastcapture[idx]);
372 }
373
156ec473
SS		 374 return 0;
375}
376DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
377
b9a4fa69
SS		 378static int s0ix_stats_show(struct seq_file *s, void *unused)
379{
380 struct amd_pmc_dev *dev = s->private;
381 u64 entry_time, exit_time, residency;
382
383 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
384 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
385
386 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
387 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
388
389 /* It's in 48MHz. We need to convert it */
7f5231b1
SS		 390 residency = exit_time - entry_time;
391 do_div(residency, 48);
b9a4fa69
SS		 392
393 seq_puts(s, "=== S0ix statistics ===\n");
394 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
395 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
396 seq_printf(s, "Residency Time: %lld\n", residency);
397
398 return 0;
399}
400DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
401
f6045de1
SG		 402static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
403{
404 struct amd_pmc_dev *dev = s->private;
405 int rc;
406
407 if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
408 rc = amd_pmc_idlemask_read(dev, NULL, s);
409 if (rc)
410 return rc;
411 } else {
412 seq_puts(s, "Unsupported SMU version for Idlemask\n");
413 }
414
415 return 0;
416}
417DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
418
156ec473
SS		 419static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
420{
421 debugfs_remove_recursive(dev->dbgfs_dir);
422}
423
424static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
425{
426 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
427 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
428 &smu_fw_info_fops);
b9a4fa69
SS		 429 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
430 &s0ix_stats_fops);
f6045de1
SG		 431 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
432 &amd_pmc_idlemask_fops);
426c0ff2 433 /* Enable STB only when the module_param is set */
3d7d407d
SG		 434 if (enable_stb) {
435 if (dev->cpu_id == AMD_CPU_ID_YC)
436 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
437 &amd_pmc_stb_debugfs_fops_v2);
438 else
439 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
440 &amd_pmc_stb_debugfs_fops);
441 }
156ec473
SS		 442}
443#else
444static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
445{
446}
447
448static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
449{
450}
451#endif /* CONFIG_DEBUG_FS */
452
76620567
SS		 453static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
454{
455 u32 phys_addr_low, phys_addr_hi;
456 u64 smu_phys_addr;
457
458 if (dev->cpu_id == AMD_CPU_ID_PCO)
459 return -EINVAL;
460
461 /* Get Active devices list from SMU */
462 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
463
464 /* Get dram address */
465 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
466 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
467 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
468
469 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
470 if (!dev->smu_virt_addr)
471 return -ENOMEM;
472
473 /* Start the logging */
474 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
475
476 return 0;
477}
478
156ec473
SS		 479static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
480{
3d7d407d
SG		 481 u32 value, message, argument, response;
482
483 if (dev->msg_port) {
484 message = AMD_S2D_REGISTER_MESSAGE;
485 argument = AMD_S2D_REGISTER_ARGUMENT;
486 response = AMD_S2D_REGISTER_RESPONSE;
487 } else {
488 message = AMD_PMC_REGISTER_MESSAGE;
489 argument = AMD_PMC_REGISTER_ARGUMENT;
490 response = AMD_PMC_REGISTER_RESPONSE;
491 }
156ec473 492
3d7d407d 493 value = amd_pmc_reg_read(dev, response);
156ec473
SS		 494 dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
495
3d7d407d 496 value = amd_pmc_reg_read(dev, argument);
156ec473
SS		 497 dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
498
3d7d407d 499 value = amd_pmc_reg_read(dev, message);
156ec473
SS		 500 dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
501}
502
4c9dbf86 503static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
156ec473
SS		 504{
505 int rc;
3d7d407d 506 u32 val, message, argument, response;
156ec473 507
95e1b60f 508 mutex_lock(&dev->lock);
3d7d407d
SG		 509
510 if (dev->msg_port) {
511 message = AMD_S2D_REGISTER_MESSAGE;
512 argument = AMD_S2D_REGISTER_ARGUMENT;
513 response = AMD_S2D_REGISTER_RESPONSE;
514 } else {
515 message = AMD_PMC_REGISTER_MESSAGE;
516 argument = AMD_PMC_REGISTER_ARGUMENT;
517 response = AMD_PMC_REGISTER_RESPONSE;
518 }
519
156ec473 520 /* Wait until we get a valid response */
3d7d407d 521 rc = readx_poll_timeout(ioread32, dev->regbase + response,
95e1b60f 522 val, val != 0, PMC_MSG_DELAY_MIN_US,
156ec473
SS		 523 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
524 if (rc) {
525 dev_err(dev->dev, "failed to talk to SMU\n");
95edbbf7 526 goto out_unlock;
156ec473
SS		 527 }
528
529 /* Write zero to response register */
3d7d407d 530 amd_pmc_reg_write(dev, response, 0);
156ec473
SS		 531
532 /* Write argument into response register */
3d7d407d 533 amd_pmc_reg_write(dev, argument, arg);
156ec473
SS		 534
535 /* Write message ID to message ID register */
3d7d407d 536 amd_pmc_reg_write(dev, message, msg);
76620567 537
95e1b60f 538 /* Wait until we get a valid response */
3d7d407d 539 rc = readx_poll_timeout(ioread32, dev->regbase + response,
95e1b60f
SS		 540 val, val != 0, PMC_MSG_DELAY_MIN_US,
541 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
542 if (rc) {
543 dev_err(dev->dev, "SMU response timed out\n");
544 goto out_unlock;
545 }
546
547 switch (val) {
548 case AMD_PMC_RESULT_OK:
76620567
SS		 549 if (ret) {
550 /* PMFW may take longer time to return back the data */
551 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
3d7d407d 552 *data = amd_pmc_reg_read(dev, argument);
76620567 553 }
95e1b60f
SS		 554 break;
555 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
556 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
557 rc = -EBUSY;
558 goto out_unlock;
559 case AMD_PMC_RESULT_CMD_UNKNOWN:
560 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
561 rc = -EINVAL;
562 goto out_unlock;
563 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
564 case AMD_PMC_RESULT_FAILED:
565 default:
566 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
567 rc = -EIO;
568 goto out_unlock;
569 }
570
571out_unlock:
572 mutex_unlock(&dev->lock);
162b937a 573 amd_pmc_dump_registers(dev);
95e1b60f 574 return rc;
156ec473
SS		 575}
576
76620567
SS		 577static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
578{
579 switch (dev->cpu_id) {
580 case AMD_CPU_ID_PCO:
581 return MSG_OS_HINT_PCO;
582 case AMD_CPU_ID_RN:
83cbaf14 583 case AMD_CPU_ID_YC:
76620567
SS		 584 return MSG_OS_HINT_RN;
585 }
586 return -EINVAL;
587}
588
59348401
ML		 589static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
590{
591 struct rtc_device *rtc_device;
592 time64_t then, now, duration;
593 struct rtc_wkalrm alarm;
594 struct rtc_time tm;
595 int rc;
596
597 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
598 return 0;
599
2978891a 600 rtc_device = rtc_class_open("rtc0");
59348401
ML		 601 if (!rtc_device)
602 return 0;
603 rc = rtc_read_alarm(rtc_device, &alarm);
604 if (rc)
605 return rc;
606 if (!alarm.enabled) {
607 dev_dbg(pdev->dev, "alarm not enabled\n");
608 return 0;
609 }
59348401
ML		 610 rc = rtc_read_time(rtc_device, &tm);
611 if (rc)
612 return rc;
613 then = rtc_tm_to_time64(&alarm.time);
614 now = rtc_tm_to_time64(&tm);
615 duration = then-now;
616
617 /* in the past */
618 if (then < now)
619 return 0;
620
621 /* will be stored in upper 16 bits of s0i3 hint argument,
622 * so timer wakeup from s0i3 is limited to ~18 hours or less
623 */
624 if (duration <= 4 || duration > U16_MAX)
625 return -EINVAL;
626
627 *arg |= (duration << 16);
628 rc = rtc_alarm_irq_enable(rtc_device, 0);
16a035a3 629 dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
59348401 630
32370191
ML		 631 /*
632 * Prevent CPUs from getting into deep idle states while sending OS_HINT
633 * which is otherwise generally safe to send when at least one of the CPUs
634 * is not in deep idle states.
635 */
636 cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req, AMD_PMC_MAX_IDLE_STATE_LATENCY);
637 wake_up_all_idle_cpus();
638
59348401
ML		 639 return rc;
640}
641
b1f66033 642static void amd_pmc_s2idle_prepare(void)
156ec473 643{
b1f66033 644 struct amd_pmc_dev *pdev = &pmc;
156ec473 645 int rc;
76620567 646 u8 msg;
59348401 647 u32 arg = 1;
156ec473 648
76620567
SS		 649 /* Reset and Start SMU logging - to monitor the s0i3 stats */
650 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
651 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
652
59348401
ML		 653 /* Activate CZN specific RTC functionality */
654 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
655 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
23f5f700
ML		 656 if (rc) {
657 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
32370191 658 goto fail;
23f5f700 659 }
59348401
ML		 660 }
661
f6045de1 662 /* Dump the IdleMask before we send hint to SMU */
b1f66033 663 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
76620567 664 msg = amd_pmc_get_os_hint(pdev);
59348401 665 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
32370191 666 if (rc) {
23f5f700 667 dev_err(pdev->dev, "suspend failed: %d\n", rc);
32370191
ML		 668 goto fail;
669 }
156ec473 670
426c0ff2
SG		 671 if (enable_stb)
672 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);
32370191 673 if (rc) {
23f5f700 674 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
32370191 675 goto fail;
426c0ff2 676 }
b1f66033 677 return;
32370191
ML		 678fail:
679 if (pdev->cpu_id == AMD_CPU_ID_CZN)
680 cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req,
681 PM_QOS_DEFAULT_VALUE);
156ec473
SS		 682}
683
b1f66033 684static void amd_pmc_s2idle_restore(void)
156ec473 685{
b1f66033 686 struct amd_pmc_dev *pdev = &pmc;
156ec473 687 int rc;
76620567 688 u8 msg;
156ec473 689
76620567
SS		 690 msg = amd_pmc_get_os_hint(pdev);
691 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
156ec473 692 if (rc)
23f5f700 693 dev_err(pdev->dev, "resume failed: %d\n", rc);
156ec473 694
9c93f8f4
SG		 695 /* Let SMU know that we are looking for stats */
696 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
697
f6045de1 698 /* Dump the IdleMask to see the blockers */
b1f66033 699 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
f6045de1 700
426c0ff2
SG		 701 /* Write data incremented by 1 to distinguish in stb_read */
702 if (enable_stb)
703 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);
32370191 704 if (rc)
23f5f700 705 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
426c0ff2 706
32370191
ML		 707 /* Restore the QoS request back to defaults if it was set */
708 if (pdev->cpu_id == AMD_CPU_ID_CZN)
709 cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req,
710 PM_QOS_DEFAULT_VALUE);
711
854abe25
ML		 712 /* Notify on failed entry */
713 amd_pmc_validate_deepest(pdev);
156ec473
SS		 714}
715
b1f66033
ML		 716static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
717 .prepare = amd_pmc_s2idle_prepare,
718 .restore = amd_pmc_s2idle_restore,
156ec473
SS		 719};
720
721static const struct pci_device_id pmc_pci_ids[] = {
83cbaf14 722 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
156ec473
SS		 723 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
724 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
725 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
726 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
727 { }
728};
729
3d7d407d
SG		 730static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
731{
d713b8d2 732 u32 phys_addr_low, phys_addr_hi;
3d7d407d 733 u64 stb_phys_addr;
d713b8d2 734 u32 size = 0;
3d7d407d
SG		 735
736 /* Spill to DRAM feature uses separate SMU message port */
737 dev->msg_port = 1;
738
739 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
740 if (size != S2D_TELEMETRY_BYTES_MAX)
741 return -EIO;
742
743 /* Get STB DRAM address */
744 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
745 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
746
747 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
748
749 /* Clear msg_port for other SMU operation */
750 dev->msg_port = 0;
751
752 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
753 if (!dev->stb_virt_addr)
754 return -ENOMEM;
755
756 return 0;
757}
758
426c0ff2
SG		 759static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
760{
761 int err;
762
763 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
764 if (err) {
765 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
766 AMD_PMC_STB_INDEX_ADDRESS);
767 return pcibios_err_to_errno(err);
768 }
769
770 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
771 if (err) {
772 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
773 AMD_PMC_STB_INDEX_DATA);
774 return pcibios_err_to_errno(err);
775 }
776
777 return 0;
778}
779
780static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
781{
782 int i, err;
783
784 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
785 if (err) {
786 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
787 AMD_PMC_STB_INDEX_ADDRESS);
788 return pcibios_err_to_errno(err);
789 }
790
791 for (i = 0; i < FIFO_SIZE; i++) {
792 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
793 if (err) {
794 dev_err(dev->dev, "error reading data from stb: 0x%X\n",
795 AMD_PMC_STB_INDEX_DATA);
796 return pcibios_err_to_errno(err);
797 }
798 }
799
800 return 0;
801}
802
156ec473
SS		 803static int amd_pmc_probe(struct platform_device *pdev)
804{
805 struct amd_pmc_dev *dev = &pmc;
806 struct pci_dev *rdev;
76620567 807 u32 base_addr_lo, base_addr_hi;
b9a4fa69 808 u64 base_addr, fch_phys_addr;
156ec473
SS		 809 int err;
810 u32 val;
811
812 dev->dev = &pdev->dev;
813
814 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
745ed17a 815 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
6a5a14b1
SG		 816 err = -ENODEV;
817 goto err_pci_dev_put;
745ed17a 818 }
156ec473
SS		 819
820 dev->cpu_id = rdev->device;
6a5a14b1 821 dev->rdev = rdev;
156ec473
SS		 822 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
823 if (err) {
824 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
6a5a14b1
SG		 825 err = pcibios_err_to_errno(err);
826 goto err_pci_dev_put;
156ec473
SS		 827 }
828
829 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
745ed17a 830 if (err) {
6a5a14b1
SG		 831 err = pcibios_err_to_errno(err);
832 goto err_pci_dev_put;
745ed17a 833 }
156ec473
SS		 834
835 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
836
837 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
838 if (err) {
839 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
6a5a14b1
SG		 840 err = pcibios_err_to_errno(err);
841 goto err_pci_dev_put;
156ec473
SS		 842 }
843
844 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
745ed17a 845 if (err) {
6a5a14b1
SG		 846 err = pcibios_err_to_errno(err);
847 goto err_pci_dev_put;
745ed17a 848 }
156ec473
SS		 849
850 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
156ec473
SS		 851 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
852
156ec473
SS		 853 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
854 AMD_PMC_MAPPING_SIZE);
6a5a14b1
SG		 855 if (!dev->regbase) {
856 err = -ENOMEM;
857 goto err_pci_dev_put;
858 }
156ec473 859
95e1b60f 860 mutex_init(&dev->lock);
76620567 861
b9a4fa69
SS		 862 /* Use FCH registers to get the S0ix stats */
863 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
864 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
865 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
866 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
6a5a14b1
SG		 867 if (!dev->fch_virt_addr) {
868 err = -ENOMEM;
869 goto err_pci_dev_put;
870 }
b9a4fa69 871
76620567
SS		 872 /* Use SMU to get the s0i3 debug stats */
873 err = amd_pmc_setup_smu_logging(dev);
874 if (err)
875 dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
876
3d7d407d
SG		 877 if (enable_stb && dev->cpu_id == AMD_CPU_ID_YC) {
878 err = amd_pmc_s2d_init(dev);
879 if (err)
880 return err;
881 }
882
f6045de1 883 amd_pmc_get_smu_version(dev);
156ec473 884 platform_set_drvdata(pdev, dev);
b1f66033
ML		 885 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
886 if (err)
887 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
888
156ec473 889 amd_pmc_dbgfs_register(dev);
32370191 890 cpu_latency_qos_add_request(&dev->amd_pmc_pm_qos_req, PM_QOS_DEFAULT_VALUE);
156ec473 891 return 0;
6a5a14b1
SG		 892
893err_pci_dev_put:
894 pci_dev_put(rdev);
895 return err;
156ec473
SS		 896}
897
898static int amd_pmc_remove(struct platform_device *pdev)
899{
900 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
901
b1f66033 902 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
156ec473 903 amd_pmc_dbgfs_unregister(dev);
6a5a14b1 904 pci_dev_put(dev->rdev);
95e1b60f 905 mutex_destroy(&dev->lock);
156ec473
SS		 906 return 0;
907}
908
909static const struct acpi_device_id amd_pmc_acpi_ids[] = {
910 {"AMDI0005", 0},
9422584a 911 {"AMDI0006", 0},
83cbaf14 912 {"AMDI0007", 0},
156ec473 913 {"AMD0004", 0},
432cce21 914 {"AMD0005", 0},
156ec473
SS		 915 { }
916};
917MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
918
919static struct platform_driver amd_pmc_driver = {
920 .driver = {
921 .name = "amd_pmc",
922 .acpi_match_table = amd_pmc_acpi_ids,
156ec473
SS		 923 },
924 .probe = amd_pmc_probe,
925 .remove = amd_pmc_remove,
926};
927module_platform_driver(amd_pmc_driver);
928
929MODULE_LICENSE("GPL v2");
930MODULE_DESCRIPTION("AMD PMC Driver");
Linux 6.x block layer and io_uring tree(s)