Commit | Line | Data |
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0e37f88d MR |
1 | /* |
2 | * Allwinner A1X SoCs pinctrl driver. | |
3 | * | |
4 | * Copyright (C) 2012 Maxime Ripard | |
5 | * | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/io.h> | |
950707c0 | 14 | #include <linux/clk.h> |
88057d6e | 15 | #include <linux/gpio/driver.h> |
a59c99d9 | 16 | #include <linux/interrupt.h> |
60242db1 | 17 | #include <linux/irqdomain.h> |
905a5117 | 18 | #include <linux/irqchip/chained_irq.h> |
bcc76199 | 19 | #include <linux/export.h> |
0e37f88d | 20 | #include <linux/of.h> |
10e3a88b | 21 | #include <linux/of_clk.h> |
0e37f88d MR |
22 | #include <linux/of_address.h> |
23 | #include <linux/of_device.h> | |
60242db1 | 24 | #include <linux/of_irq.h> |
0e37f88d MR |
25 | #include <linux/pinctrl/consumer.h> |
26 | #include <linux/pinctrl/machine.h> | |
27 | #include <linux/pinctrl/pinctrl.h> | |
28 | #include <linux/pinctrl/pinconf-generic.h> | |
29 | #include <linux/pinctrl/pinmux.h> | |
9a2a566a | 30 | #include <linux/regulator/consumer.h> |
0e37f88d MR |
31 | #include <linux/platform_device.h> |
32 | #include <linux/slab.h> | |
33 | ||
42676fa4 MR |
34 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
35 | ||
5f910777 | 36 | #include "../core.h" |
0e37f88d | 37 | #include "pinctrl-sunxi.h" |
eaa3d848 | 38 | |
f4c51c10 HG |
39 | static struct irq_chip sunxi_pinctrl_edge_irq_chip; |
40 | static struct irq_chip sunxi_pinctrl_level_irq_chip; | |
41 | ||
0e37f88d MR |
42 | static struct sunxi_pinctrl_group * |
43 | sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) | |
44 | { | |
45 | int i; | |
46 | ||
47 | for (i = 0; i < pctl->ngroups; i++) { | |
48 | struct sunxi_pinctrl_group *grp = pctl->groups + i; | |
49 | ||
50 | if (!strcmp(grp->name, group)) | |
51 | return grp; | |
52 | } | |
53 | ||
54 | return NULL; | |
55 | } | |
56 | ||
57 | static struct sunxi_pinctrl_function * | |
58 | sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, | |
59 | const char *name) | |
60 | { | |
61 | struct sunxi_pinctrl_function *func = pctl->functions; | |
62 | int i; | |
63 | ||
64 | for (i = 0; i < pctl->nfunctions; i++) { | |
65 | if (!func[i].name) | |
66 | break; | |
67 | ||
68 | if (!strcmp(func[i].name, name)) | |
69 | return func + i; | |
70 | } | |
71 | ||
72 | return NULL; | |
73 | } | |
74 | ||
75 | static struct sunxi_desc_function * | |
76 | sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, | |
77 | const char *pin_name, | |
78 | const char *func_name) | |
79 | { | |
80 | int i; | |
81 | ||
82 | for (i = 0; i < pctl->desc->npins; i++) { | |
83 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
84 | ||
85 | if (!strcmp(pin->pin.name, pin_name)) { | |
86 | struct sunxi_desc_function *func = pin->functions; | |
87 | ||
88 | while (func->name) { | |
32e21f08 | 89 | if (!strcmp(func->name, func_name) && |
90 | (!func->variant || | |
91 | func->variant & pctl->variant)) | |
0e37f88d MR |
92 | return func; |
93 | ||
94 | func++; | |
95 | } | |
96 | } | |
97 | } | |
98 | ||
99 | return NULL; | |
100 | } | |
101 | ||
814d4f2e MR |
102 | static struct sunxi_desc_function * |
103 | sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, | |
104 | const u16 pin_num, | |
105 | const char *func_name) | |
106 | { | |
107 | int i; | |
108 | ||
109 | for (i = 0; i < pctl->desc->npins; i++) { | |
110 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
111 | ||
112 | if (pin->pin.number == pin_num) { | |
113 | struct sunxi_desc_function *func = pin->functions; | |
114 | ||
115 | while (func->name) { | |
116 | if (!strcmp(func->name, func_name)) | |
117 | return func; | |
118 | ||
119 | func++; | |
120 | } | |
121 | } | |
122 | } | |
123 | ||
124 | return NULL; | |
125 | } | |
126 | ||
0e37f88d MR |
127 | static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) |
128 | { | |
129 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
130 | ||
131 | return pctl->ngroups; | |
132 | } | |
133 | ||
134 | static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
135 | unsigned group) | |
136 | { | |
137 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
138 | ||
139 | return pctl->groups[group].name; | |
140 | } | |
141 | ||
142 | static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
143 | unsigned group, | |
144 | const unsigned **pins, | |
145 | unsigned *num_pins) | |
146 | { | |
147 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
148 | ||
149 | *pins = (unsigned *)&pctl->groups[group].pin; | |
150 | *num_pins = 1; | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
f233dbca MR |
155 | static bool sunxi_pctrl_has_bias_prop(struct device_node *node) |
156 | { | |
cefbf1a1 MR |
157 | return of_find_property(node, "bias-pull-up", NULL) || |
158 | of_find_property(node, "bias-pull-down", NULL) || | |
159 | of_find_property(node, "bias-disable", NULL) || | |
160 | of_find_property(node, "allwinner,pull", NULL); | |
f233dbca MR |
161 | } |
162 | ||
163 | static bool sunxi_pctrl_has_drive_prop(struct device_node *node) | |
164 | { | |
cefbf1a1 MR |
165 | return of_find_property(node, "drive-strength", NULL) || |
166 | of_find_property(node, "allwinner,drive", NULL); | |
f233dbca MR |
167 | } |
168 | ||
169 | static int sunxi_pctrl_parse_bias_prop(struct device_node *node) | |
170 | { | |
171 | u32 val; | |
172 | ||
cefbf1a1 MR |
173 | /* Try the new style binding */ |
174 | if (of_find_property(node, "bias-pull-up", NULL)) | |
175 | return PIN_CONFIG_BIAS_PULL_UP; | |
176 | ||
177 | if (of_find_property(node, "bias-pull-down", NULL)) | |
178 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
179 | ||
180 | if (of_find_property(node, "bias-disable", NULL)) | |
181 | return PIN_CONFIG_BIAS_DISABLE; | |
182 | ||
183 | /* And fall back to the old binding */ | |
f233dbca MR |
184 | if (of_property_read_u32(node, "allwinner,pull", &val)) |
185 | return -EINVAL; | |
186 | ||
187 | switch (val) { | |
07fe64ba MR |
188 | case SUN4I_PINCTRL_NO_PULL: |
189 | return PIN_CONFIG_BIAS_DISABLE; | |
42676fa4 | 190 | case SUN4I_PINCTRL_PULL_UP: |
f233dbca | 191 | return PIN_CONFIG_BIAS_PULL_UP; |
42676fa4 | 192 | case SUN4I_PINCTRL_PULL_DOWN: |
f233dbca MR |
193 | return PIN_CONFIG_BIAS_PULL_DOWN; |
194 | } | |
195 | ||
196 | return -EINVAL; | |
197 | } | |
198 | ||
199 | static int sunxi_pctrl_parse_drive_prop(struct device_node *node) | |
200 | { | |
201 | u32 val; | |
202 | ||
cefbf1a1 MR |
203 | /* Try the new style binding */ |
204 | if (!of_property_read_u32(node, "drive-strength", &val)) { | |
205 | /* We can't go below 10mA ... */ | |
206 | if (val < 10) | |
207 | return -EINVAL; | |
208 | ||
209 | /* ... and only up to 40 mA ... */ | |
210 | if (val > 40) | |
211 | val = 40; | |
212 | ||
213 | /* by steps of 10 mA */ | |
214 | return rounddown(val, 10); | |
215 | } | |
216 | ||
217 | /* And then fall back to the old binding */ | |
f233dbca MR |
218 | if (of_property_read_u32(node, "allwinner,drive", &val)) |
219 | return -EINVAL; | |
220 | ||
221 | return (val + 1) * 10; | |
222 | } | |
223 | ||
224 | static const char *sunxi_pctrl_parse_function_prop(struct device_node *node) | |
225 | { | |
226 | const char *function; | |
227 | int ret; | |
228 | ||
cefbf1a1 MR |
229 | /* Try the generic binding */ |
230 | ret = of_property_read_string(node, "function", &function); | |
231 | if (!ret) | |
232 | return function; | |
233 | ||
234 | /* And fall back to our legacy one */ | |
f233dbca MR |
235 | ret = of_property_read_string(node, "allwinner,function", &function); |
236 | if (!ret) | |
237 | return function; | |
238 | ||
239 | return NULL; | |
240 | } | |
241 | ||
242 | static const char *sunxi_pctrl_find_pins_prop(struct device_node *node, | |
243 | int *npins) | |
244 | { | |
245 | int count; | |
246 | ||
cefbf1a1 MR |
247 | /* Try the generic binding */ |
248 | count = of_property_count_strings(node, "pins"); | |
249 | if (count > 0) { | |
250 | *npins = count; | |
251 | return "pins"; | |
252 | } | |
253 | ||
254 | /* And fall back to our legacy one */ | |
f233dbca MR |
255 | count = of_property_count_strings(node, "allwinner,pins"); |
256 | if (count > 0) { | |
257 | *npins = count; | |
258 | return "allwinner,pins"; | |
259 | } | |
260 | ||
261 | return NULL; | |
262 | } | |
263 | ||
264 | static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node, | |
265 | unsigned int *len) | |
266 | { | |
267 | unsigned long *pinconfig; | |
268 | unsigned int configlen = 0, idx = 0; | |
e11dee2e | 269 | int ret; |
f233dbca MR |
270 | |
271 | if (sunxi_pctrl_has_drive_prop(node)) | |
272 | configlen++; | |
273 | if (sunxi_pctrl_has_bias_prop(node)) | |
274 | configlen++; | |
275 | ||
e11dee2e MR |
276 | /* |
277 | * If we don't have any configuration, bail out | |
278 | */ | |
279 | if (!configlen) | |
280 | return NULL; | |
281 | ||
6396bb22 | 282 | pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL); |
f233dbca | 283 | if (!pinconfig) |
e11dee2e | 284 | return ERR_PTR(-ENOMEM); |
f233dbca MR |
285 | |
286 | if (sunxi_pctrl_has_drive_prop(node)) { | |
287 | int drive = sunxi_pctrl_parse_drive_prop(node); | |
e11dee2e MR |
288 | if (drive < 0) { |
289 | ret = drive; | |
f233dbca | 290 | goto err_free; |
e11dee2e | 291 | } |
f233dbca MR |
292 | |
293 | pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, | |
294 | drive); | |
295 | } | |
296 | ||
297 | if (sunxi_pctrl_has_bias_prop(node)) { | |
298 | int pull = sunxi_pctrl_parse_bias_prop(node); | |
223dba00 | 299 | int arg = 0; |
e11dee2e MR |
300 | if (pull < 0) { |
301 | ret = pull; | |
f233dbca | 302 | goto err_free; |
e11dee2e | 303 | } |
f233dbca | 304 | |
223dba00 CYT |
305 | if (pull != PIN_CONFIG_BIAS_DISABLE) |
306 | arg = 1; /* hardware uses weak pull resistors */ | |
307 | ||
308 | pinconfig[idx++] = pinconf_to_config_packed(pull, arg); | |
f233dbca MR |
309 | } |
310 | ||
311 | ||
312 | *len = configlen; | |
313 | return pinconfig; | |
314 | ||
315 | err_free: | |
316 | kfree(pinconfig); | |
e11dee2e | 317 | return ERR_PTR(ret); |
f233dbca MR |
318 | } |
319 | ||
0e37f88d MR |
320 | static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
321 | struct device_node *node, | |
322 | struct pinctrl_map **map, | |
323 | unsigned *num_maps) | |
324 | { | |
325 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
326 | unsigned long *pinconfig; | |
327 | struct property *prop; | |
f233dbca | 328 | const char *function, *pin_prop; |
0e37f88d | 329 | const char *group; |
f233dbca | 330 | int ret, npins, nmaps, configlen = 0, i = 0; |
0e37f88d MR |
331 | |
332 | *map = NULL; | |
333 | *num_maps = 0; | |
334 | ||
f233dbca MR |
335 | function = sunxi_pctrl_parse_function_prop(node); |
336 | if (!function) { | |
94f4e54c RH |
337 | dev_err(pctl->dev, "missing function property in node %pOFn\n", |
338 | node); | |
0e37f88d MR |
339 | return -EINVAL; |
340 | } | |
341 | ||
f233dbca MR |
342 | pin_prop = sunxi_pctrl_find_pins_prop(node, &npins); |
343 | if (!pin_prop) { | |
94f4e54c RH |
344 | dev_err(pctl->dev, "missing pins property in node %pOFn\n", |
345 | node); | |
0e37f88d MR |
346 | return -EINVAL; |
347 | } | |
348 | ||
f233dbca MR |
349 | /* |
350 | * We have two maps for each pin: one for the function, one | |
e11dee2e MR |
351 | * for the configuration (bias, strength, etc). |
352 | * | |
353 | * We might be slightly overshooting, since we might not have | |
354 | * any configuration. | |
f233dbca MR |
355 | */ |
356 | nmaps = npins * 2; | |
6da2ec56 | 357 | *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL); |
3efa921d | 358 | if (!*map) |
0e37f88d MR |
359 | return -ENOMEM; |
360 | ||
f233dbca | 361 | pinconfig = sunxi_pctrl_build_pin_config(node, &configlen); |
e11dee2e MR |
362 | if (IS_ERR(pinconfig)) { |
363 | ret = PTR_ERR(pinconfig); | |
f233dbca MR |
364 | goto err_free_map; |
365 | } | |
366 | ||
367 | of_property_for_each_string(node, pin_prop, prop, group) { | |
0e37f88d MR |
368 | struct sunxi_pinctrl_group *grp = |
369 | sunxi_pinctrl_find_group_by_name(pctl, group); | |
0e37f88d MR |
370 | |
371 | if (!grp) { | |
372 | dev_err(pctl->dev, "unknown pin %s", group); | |
373 | continue; | |
374 | } | |
375 | ||
376 | if (!sunxi_pinctrl_desc_find_function_by_name(pctl, | |
377 | grp->name, | |
378 | function)) { | |
379 | dev_err(pctl->dev, "unsupported function %s on pin %s", | |
380 | function, group); | |
381 | continue; | |
382 | } | |
383 | ||
384 | (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; | |
385 | (*map)[i].data.mux.group = group; | |
386 | (*map)[i].data.mux.function = function; | |
387 | ||
388 | i++; | |
389 | ||
e11dee2e MR |
390 | if (pinconfig) { |
391 | (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
392 | (*map)[i].data.configs.group_or_pin = group; | |
393 | (*map)[i].data.configs.configs = pinconfig; | |
394 | (*map)[i].data.configs.num_configs = configlen; | |
395 | i++; | |
396 | } | |
0e37f88d MR |
397 | } |
398 | ||
e11dee2e MR |
399 | *num_maps = i; |
400 | ||
401 | /* | |
402 | * We know have the number of maps we need, we can resize our | |
403 | * map array | |
404 | */ | |
405 | *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); | |
b3cde198 | 406 | if (!*map) |
e11dee2e | 407 | return -ENOMEM; |
0e37f88d MR |
408 | |
409 | return 0; | |
f233dbca MR |
410 | |
411 | err_free_map: | |
b3cde198 DC |
412 | kfree(*map); |
413 | *map = NULL; | |
f233dbca | 414 | return ret; |
0e37f88d MR |
415 | } |
416 | ||
417 | static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, | |
418 | struct pinctrl_map *map, | |
419 | unsigned num_maps) | |
420 | { | |
88f01a1b CYT |
421 | int i; |
422 | ||
423 | /* pin config is never in the first map */ | |
424 | for (i = 1; i < num_maps; i++) { | |
425 | if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP) | |
426 | continue; | |
427 | ||
428 | /* | |
429 | * All the maps share the same pin config, | |
430 | * free only the first one we find. | |
431 | */ | |
432 | kfree(map[i].data.configs.configs); | |
433 | break; | |
434 | } | |
435 | ||
0e37f88d MR |
436 | kfree(map); |
437 | } | |
438 | ||
022ab148 | 439 | static const struct pinctrl_ops sunxi_pctrl_ops = { |
0e37f88d MR |
440 | .dt_node_to_map = sunxi_pctrl_dt_node_to_map, |
441 | .dt_free_map = sunxi_pctrl_dt_free_map, | |
442 | .get_groups_count = sunxi_pctrl_get_groups_count, | |
443 | .get_group_name = sunxi_pctrl_get_group_name, | |
444 | .get_group_pins = sunxi_pctrl_get_group_pins, | |
445 | }; | |
446 | ||
c5fda170 CYT |
447 | static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, |
448 | u32 *offset, u32 *shift, u32 *mask) | |
449 | { | |
450 | switch (param) { | |
451 | case PIN_CONFIG_DRIVE_STRENGTH: | |
452 | *offset = sunxi_dlevel_reg(pin); | |
453 | *shift = sunxi_dlevel_offset(pin); | |
454 | *mask = DLEVEL_PINS_MASK; | |
455 | break; | |
456 | ||
457 | case PIN_CONFIG_BIAS_PULL_UP: | |
458 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
459 | case PIN_CONFIG_BIAS_DISABLE: | |
460 | *offset = sunxi_pull_reg(pin); | |
461 | *shift = sunxi_pull_offset(pin); | |
462 | *mask = PULL_PINS_MASK; | |
463 | break; | |
464 | ||
465 | default: | |
466 | return -ENOTSUPP; | |
467 | } | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
472 | static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, | |
473 | unsigned long *config) | |
474 | { | |
475 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
476 | enum pin_config_param param = pinconf_to_config_param(*config); | |
477 | u32 offset, shift, mask, val; | |
478 | u16 arg; | |
479 | int ret; | |
480 | ||
481 | pin -= pctl->desc->pin_base; | |
482 | ||
483 | ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); | |
484 | if (ret < 0) | |
485 | return ret; | |
486 | ||
487 | val = (readl(pctl->membase + offset) >> shift) & mask; | |
488 | ||
489 | switch (pinconf_to_config_param(*config)) { | |
490 | case PIN_CONFIG_DRIVE_STRENGTH: | |
491 | arg = (val + 1) * 10; | |
492 | break; | |
493 | ||
494 | case PIN_CONFIG_BIAS_PULL_UP: | |
495 | if (val != SUN4I_PINCTRL_PULL_UP) | |
496 | return -EINVAL; | |
497 | arg = 1; /* hardware is weak pull-up */ | |
498 | break; | |
499 | ||
500 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
501 | if (val != SUN4I_PINCTRL_PULL_DOWN) | |
502 | return -EINVAL; | |
503 | arg = 1; /* hardware is weak pull-down */ | |
504 | break; | |
505 | ||
506 | case PIN_CONFIG_BIAS_DISABLE: | |
507 | if (val != SUN4I_PINCTRL_NO_PULL) | |
508 | return -EINVAL; | |
509 | arg = 0; | |
510 | break; | |
511 | ||
512 | default: | |
513 | /* sunxi_pconf_reg should catch anything unsupported */ | |
514 | WARN_ON(1); | |
515 | return -ENOTSUPP; | |
516 | } | |
517 | ||
518 | *config = pinconf_to_config_packed(param, arg); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
0e37f88d MR |
523 | static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, |
524 | unsigned group, | |
525 | unsigned long *config) | |
526 | { | |
527 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
c5fda170 | 528 | struct sunxi_pinctrl_group *g = &pctl->groups[group]; |
0e37f88d | 529 | |
c5fda170 CYT |
530 | /* We only support 1 pin per group. Chain it to the pin callback */ |
531 | return sunxi_pconf_get(pctldev, g->pin, config); | |
0e37f88d MR |
532 | } |
533 | ||
90be64e2 MR |
534 | static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, |
535 | unsigned long *configs, unsigned num_configs) | |
0e37f88d MR |
536 | { |
537 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
03b054e9 | 538 | int i; |
0e37f88d | 539 | |
03b054e9 | 540 | for (i = 0; i < num_configs; i++) { |
51814827 CYT |
541 | enum pin_config_param param; |
542 | unsigned long flags; | |
543 | u32 offset, shift, mask, reg; | |
58957d2e | 544 | u32 arg, val; |
51814827 CYT |
545 | int ret; |
546 | ||
547 | param = pinconf_to_config_param(configs[i]); | |
548 | arg = pinconf_to_config_argument(configs[i]); | |
549 | ||
550 | ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); | |
551 | if (ret < 0) | |
552 | return ret; | |
553 | ||
554 | switch (param) { | |
03b054e9 | 555 | case PIN_CONFIG_DRIVE_STRENGTH: |
51814827 | 556 | if (arg < 10 || arg > 40) |
03b054e9 SY |
557 | return -EINVAL; |
558 | /* | |
559 | * We convert from mA to what the register expects: | |
560 | * 0: 10mA | |
561 | * 1: 20mA | |
562 | * 2: 30mA | |
563 | * 3: 40mA | |
564 | */ | |
51814827 | 565 | val = arg / 10 - 1; |
03b054e9 | 566 | break; |
07fe64ba | 567 | case PIN_CONFIG_BIAS_DISABLE: |
ac059e2a PL |
568 | val = 0; |
569 | break; | |
03b054e9 | 570 | case PIN_CONFIG_BIAS_PULL_UP: |
51814827 CYT |
571 | if (arg == 0) |
572 | return -EINVAL; | |
573 | val = 1; | |
03b054e9 SY |
574 | break; |
575 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
51814827 CYT |
576 | if (arg == 0) |
577 | return -EINVAL; | |
578 | val = 2; | |
03b054e9 SY |
579 | break; |
580 | default: | |
51814827 CYT |
581 | /* sunxi_pconf_reg should catch anything unsupported */ |
582 | WARN_ON(1); | |
583 | return -ENOTSUPP; | |
03b054e9 | 584 | } |
0e37f88d | 585 | |
f658ed36 | 586 | raw_spin_lock_irqsave(&pctl->lock, flags); |
51814827 CYT |
587 | reg = readl(pctl->membase + offset); |
588 | reg &= ~(mask << shift); | |
589 | writel(reg | val << shift, pctl->membase + offset); | |
f658ed36 | 590 | raw_spin_unlock_irqrestore(&pctl->lock, flags); |
51814827 | 591 | } /* for each config */ |
0e37f88d MR |
592 | |
593 | return 0; | |
594 | } | |
595 | ||
90be64e2 MR |
596 | static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, |
597 | unsigned long *configs, unsigned num_configs) | |
598 | { | |
599 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
600 | struct sunxi_pinctrl_group *g = &pctl->groups[group]; | |
601 | ||
602 | /* We only support 1 pin per group. Chain it to the pin callback */ | |
603 | return sunxi_pconf_set(pctldev, g->pin, configs, num_configs); | |
604 | } | |
605 | ||
022ab148 | 606 | static const struct pinconf_ops sunxi_pconf_ops = { |
c5fda170 CYT |
607 | .is_generic = true, |
608 | .pin_config_get = sunxi_pconf_get, | |
90be64e2 | 609 | .pin_config_set = sunxi_pconf_set, |
0e37f88d MR |
610 | .pin_config_group_get = sunxi_pconf_group_get, |
611 | .pin_config_group_set = sunxi_pconf_group_set, | |
612 | }; | |
613 | ||
402bfb3c CYT |
614 | static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, |
615 | unsigned pin, | |
616 | struct regulator *supply) | |
617 | { | |
cc62383f OJ |
618 | unsigned short bank = pin / PINS_PER_BANK; |
619 | unsigned long flags; | |
402bfb3c CYT |
620 | u32 val, reg; |
621 | int uV; | |
622 | ||
f7275345 | 623 | if (!pctl->desc->io_bias_cfg_variant) |
402bfb3c CYT |
624 | return 0; |
625 | ||
626 | uV = regulator_get_voltage(supply); | |
627 | if (uV < 0) | |
628 | return uV; | |
629 | ||
630 | /* Might be dummy regulator with no voltage set */ | |
631 | if (uV == 0) | |
632 | return 0; | |
633 | ||
f7275345 OJ |
634 | switch (pctl->desc->io_bias_cfg_variant) { |
635 | case BIAS_VOLTAGE_GRP_CONFIG: | |
636 | /* | |
637 | * Configured value must be equal or greater to actual | |
638 | * voltage. | |
639 | */ | |
640 | if (uV <= 1800000) | |
641 | val = 0x0; /* 1.8V */ | |
642 | else if (uV <= 2500000) | |
643 | val = 0x6; /* 2.5V */ | |
644 | else if (uV <= 2800000) | |
645 | val = 0x9; /* 2.8V */ | |
646 | else if (uV <= 3000000) | |
647 | val = 0xA; /* 3.0V */ | |
648 | else | |
649 | val = 0xD; /* 3.3V */ | |
650 | ||
651 | pin -= pctl->desc->pin_base; | |
652 | ||
653 | reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); | |
654 | reg &= ~IO_BIAS_MASK; | |
655 | writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); | |
656 | return 0; | |
cc62383f OJ |
657 | case BIAS_VOLTAGE_PIO_POW_MODE_SEL: |
658 | val = uV <= 1800000 ? 1 : 0; | |
659 | ||
660 | raw_spin_lock_irqsave(&pctl->lock, flags); | |
661 | reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); | |
662 | reg &= ~(1 << bank); | |
663 | writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); | |
664 | raw_spin_unlock_irqrestore(&pctl->lock, flags); | |
665 | return 0; | |
f7275345 OJ |
666 | default: |
667 | return -EINVAL; | |
668 | } | |
402bfb3c CYT |
669 | } |
670 | ||
0e37f88d MR |
671 | static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
672 | { | |
673 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
674 | ||
675 | return pctl->nfunctions; | |
676 | } | |
677 | ||
678 | static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
679 | unsigned function) | |
680 | { | |
681 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
682 | ||
683 | return pctl->functions[function].name; | |
684 | } | |
685 | ||
686 | static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
687 | unsigned function, | |
688 | const char * const **groups, | |
689 | unsigned * const num_groups) | |
690 | { | |
691 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
692 | ||
693 | *groups = pctl->functions[function].groups; | |
694 | *num_groups = pctl->functions[function].ngroups; | |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
699 | static void sunxi_pmx_set(struct pinctrl_dev *pctldev, | |
700 | unsigned pin, | |
701 | u8 config) | |
702 | { | |
703 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1bee963d MR |
704 | unsigned long flags; |
705 | u32 val, mask; | |
706 | ||
f658ed36 | 707 | raw_spin_lock_irqsave(&pctl->lock, flags); |
0e37f88d | 708 | |
b4575c69 | 709 | pin -= pctl->desc->pin_base; |
1bee963d MR |
710 | val = readl(pctl->membase + sunxi_mux_reg(pin)); |
711 | mask = MUX_PINS_MASK << sunxi_mux_offset(pin); | |
0e37f88d MR |
712 | writel((val & ~mask) | config << sunxi_mux_offset(pin), |
713 | pctl->membase + sunxi_mux_reg(pin)); | |
1bee963d | 714 | |
f658ed36 | 715 | raw_spin_unlock_irqrestore(&pctl->lock, flags); |
0e37f88d MR |
716 | } |
717 | ||
03e9f0ca LW |
718 | static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, |
719 | unsigned function, | |
720 | unsigned group) | |
0e37f88d MR |
721 | { |
722 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
723 | struct sunxi_pinctrl_group *g = pctl->groups + group; | |
724 | struct sunxi_pinctrl_function *func = pctl->functions + function; | |
725 | struct sunxi_desc_function *desc = | |
726 | sunxi_pinctrl_desc_find_function_by_name(pctl, | |
727 | g->name, | |
728 | func->name); | |
729 | ||
730 | if (!desc) | |
731 | return -EINVAL; | |
732 | ||
733 | sunxi_pmx_set(pctldev, g->pin, desc->muxval); | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
08e9e614 MR |
738 | static int |
739 | sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
740 | struct pinctrl_gpio_range *range, | |
741 | unsigned offset, | |
742 | bool input) | |
743 | { | |
744 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
745 | struct sunxi_desc_function *desc; | |
08e9e614 | 746 | const char *func; |
08e9e614 MR |
747 | |
748 | if (input) | |
749 | func = "gpio_in"; | |
750 | else | |
751 | func = "gpio_out"; | |
752 | ||
814d4f2e MR |
753 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); |
754 | if (!desc) | |
755 | return -EINVAL; | |
08e9e614 MR |
756 | |
757 | sunxi_pmx_set(pctldev, offset, desc->muxval); | |
758 | ||
814d4f2e | 759 | return 0; |
08e9e614 MR |
760 | } |
761 | ||
9a2a566a MR |
762 | static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) |
763 | { | |
764 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
765 | unsigned short bank = offset / PINS_PER_BANK; | |
ca443844 CYT |
766 | unsigned short bank_offset = bank - pctl->desc->pin_base / |
767 | PINS_PER_BANK; | |
768 | struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; | |
dc144558 CYT |
769 | struct regulator *reg = s_reg->regulator; |
770 | char supply[16]; | |
9a2a566a MR |
771 | int ret; |
772 | ||
dc144558 | 773 | if (reg) { |
9a2a566a | 774 | refcount_inc(&s_reg->refcount); |
dc144558 CYT |
775 | return 0; |
776 | } | |
777 | ||
778 | snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); | |
779 | reg = regulator_get(pctl->dev, supply); | |
780 | if (IS_ERR(reg)) { | |
781 | dev_err(pctl->dev, "Couldn't get bank P%c regulator\n", | |
782 | 'A' + bank); | |
783 | return PTR_ERR(reg); | |
9a2a566a MR |
784 | } |
785 | ||
786 | ret = regulator_enable(reg); | |
787 | if (ret) { | |
788 | dev_err(pctl->dev, | |
789 | "Couldn't enable bank P%c regulator\n", 'A' + bank); | |
790 | goto out; | |
791 | } | |
792 | ||
402bfb3c CYT |
793 | sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg); |
794 | ||
dc144558 CYT |
795 | s_reg->regulator = reg; |
796 | refcount_set(&s_reg->refcount, 1); | |
797 | ||
9a2a566a MR |
798 | return 0; |
799 | ||
800 | out: | |
dc144558 | 801 | regulator_put(s_reg->regulator); |
9a2a566a MR |
802 | |
803 | return ret; | |
804 | } | |
805 | ||
806 | static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset) | |
807 | { | |
808 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
809 | unsigned short bank = offset / PINS_PER_BANK; | |
ca443844 CYT |
810 | unsigned short bank_offset = bank - pctl->desc->pin_base / |
811 | PINS_PER_BANK; | |
812 | struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; | |
9a2a566a MR |
813 | |
814 | if (!refcount_dec_and_test(&s_reg->refcount)) | |
815 | return 0; | |
816 | ||
817 | regulator_disable(s_reg->regulator); | |
818 | regulator_put(s_reg->regulator); | |
819 | s_reg->regulator = NULL; | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
022ab148 | 824 | static const struct pinmux_ops sunxi_pmx_ops = { |
0e37f88d MR |
825 | .get_functions_count = sunxi_pmx_get_funcs_cnt, |
826 | .get_function_name = sunxi_pmx_get_func_name, | |
827 | .get_function_groups = sunxi_pmx_get_func_groups, | |
03e9f0ca | 828 | .set_mux = sunxi_pmx_set_mux, |
08e9e614 | 829 | .gpio_set_direction = sunxi_pmx_gpio_set_direction, |
9a2a566a MR |
830 | .request = sunxi_pmx_request, |
831 | .free = sunxi_pmx_free, | |
13960072 | 832 | .strict = true, |
0e37f88d MR |
833 | }; |
834 | ||
08e9e614 MR |
835 | static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, |
836 | unsigned offset) | |
837 | { | |
838 | return pinctrl_gpio_direction_input(chip->base + offset); | |
839 | } | |
840 | ||
841 | static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) | |
842 | { | |
88057d6e | 843 | struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); |
08e9e614 MR |
844 | u32 reg = sunxi_data_reg(offset); |
845 | u8 index = sunxi_data_offset(offset); | |
6cee3821 LW |
846 | bool set_mux = pctl->desc->irq_read_needs_mux && |
847 | gpiochip_line_is_irq(chip, offset); | |
be2d107f | 848 | u32 pin = offset + chip->base; |
ef6d24cc HG |
849 | u32 val; |
850 | ||
851 | if (set_mux) | |
be2d107f | 852 | sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); |
ef6d24cc HG |
853 | |
854 | val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; | |
855 | ||
856 | if (set_mux) | |
be2d107f | 857 | sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); |
08e9e614 | 858 | |
39e24ac3 | 859 | return !!val; |
08e9e614 MR |
860 | } |
861 | ||
08e9e614 MR |
862 | static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, |
863 | unsigned offset, int value) | |
864 | { | |
88057d6e | 865 | struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); |
08e9e614 MR |
866 | u32 reg = sunxi_data_reg(offset); |
867 | u8 index = sunxi_data_offset(offset); | |
1bee963d MR |
868 | unsigned long flags; |
869 | u32 regval; | |
870 | ||
f658ed36 | 871 | raw_spin_lock_irqsave(&pctl->lock, flags); |
1bee963d MR |
872 | |
873 | regval = readl(pctl->membase + reg); | |
08e9e614 | 874 | |
df7b34f4 MR |
875 | if (value) |
876 | regval |= BIT(index); | |
877 | else | |
878 | regval &= ~(BIT(index)); | |
08e9e614 | 879 | |
df7b34f4 | 880 | writel(regval, pctl->membase + reg); |
1bee963d | 881 | |
f658ed36 | 882 | raw_spin_unlock_irqrestore(&pctl->lock, flags); |
08e9e614 MR |
883 | } |
884 | ||
fa8cf57c CYT |
885 | static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, |
886 | unsigned offset, int value) | |
887 | { | |
888 | sunxi_pinctrl_gpio_set(chip, offset, value); | |
889 | return pinctrl_gpio_direction_output(chip->base + offset); | |
890 | } | |
891 | ||
a0d72094 MR |
892 | static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, |
893 | const struct of_phandle_args *gpiospec, | |
894 | u32 *flags) | |
895 | { | |
896 | int pin, base; | |
897 | ||
898 | base = PINS_PER_BANK * gpiospec->args[0]; | |
899 | pin = base + gpiospec->args[1]; | |
900 | ||
343f1327 | 901 | if (pin > gc->ngpio) |
a0d72094 MR |
902 | return -EINVAL; |
903 | ||
904 | if (flags) | |
905 | *flags = gpiospec->args[2]; | |
906 | ||
907 | return pin; | |
908 | } | |
909 | ||
60242db1 MR |
910 | static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
911 | { | |
88057d6e | 912 | struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); |
60242db1 | 913 | struct sunxi_desc_function *desc; |
343f1327 | 914 | unsigned pinnum = pctl->desc->pin_base + offset; |
0d3bafac | 915 | unsigned irqnum; |
60242db1 | 916 | |
c9e3b2d8 | 917 | if (offset >= chip->ngpio) |
60242db1 MR |
918 | return -ENXIO; |
919 | ||
343f1327 | 920 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); |
60242db1 MR |
921 | if (!desc) |
922 | return -EINVAL; | |
923 | ||
0d3bafac CYT |
924 | irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; |
925 | ||
58383c78 | 926 | dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", |
0d3bafac | 927 | chip->label, offset + chip->base, irqnum); |
60242db1 | 928 | |
0d3bafac | 929 | return irq_find_mapping(pctl->domain, irqnum); |
60242db1 MR |
930 | } |
931 | ||
fea6d8ef HG |
932 | static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) |
933 | { | |
934 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
935 | struct sunxi_desc_function *func; | |
f83549d6 | 936 | int ret; |
fea6d8ef HG |
937 | |
938 | func = sunxi_pinctrl_desc_find_function_by_pin(pctl, | |
939 | pctl->irq_array[d->hwirq], "irq"); | |
940 | if (!func) | |
941 | return -EINVAL; | |
942 | ||
e3a2e878 | 943 | ret = gpiochip_lock_as_irq(pctl->chip, |
343f1327 | 944 | pctl->irq_array[d->hwirq] - pctl->desc->pin_base); |
f83549d6 CYT |
945 | if (ret) { |
946 | dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", | |
947 | irqd_to_hwirq(d)); | |
948 | return ret; | |
949 | } | |
950 | ||
fea6d8ef HG |
951 | /* Change muxing to INT mode */ |
952 | sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); | |
08e9e614 | 953 | |
fea6d8ef HG |
954 | return 0; |
955 | } | |
08e9e614 | 956 | |
f83549d6 CYT |
957 | static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) |
958 | { | |
959 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
960 | ||
e3a2e878 AC |
961 | gpiochip_unlock_as_irq(pctl->chip, |
962 | pctl->irq_array[d->hwirq] - pctl->desc->pin_base); | |
f83549d6 CYT |
963 | } |
964 | ||
f4c51c10 | 965 | static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) |
60242db1 MR |
966 | { |
967 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
4b0d6c5a | 968 | u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); |
60242db1 | 969 | u8 index = sunxi_irq_cfg_offset(d->hwirq); |
1bee963d | 970 | unsigned long flags; |
2aaaddff | 971 | u32 regval; |
60242db1 MR |
972 | u8 mode; |
973 | ||
974 | switch (type) { | |
975 | case IRQ_TYPE_EDGE_RISING: | |
976 | mode = IRQ_EDGE_RISING; | |
977 | break; | |
978 | case IRQ_TYPE_EDGE_FALLING: | |
979 | mode = IRQ_EDGE_FALLING; | |
980 | break; | |
981 | case IRQ_TYPE_EDGE_BOTH: | |
982 | mode = IRQ_EDGE_BOTH; | |
983 | break; | |
984 | case IRQ_TYPE_LEVEL_HIGH: | |
985 | mode = IRQ_LEVEL_HIGH; | |
986 | break; | |
987 | case IRQ_TYPE_LEVEL_LOW: | |
988 | mode = IRQ_LEVEL_LOW; | |
989 | break; | |
990 | default: | |
991 | return -EINVAL; | |
992 | } | |
993 | ||
f658ed36 | 994 | raw_spin_lock_irqsave(&pctl->lock, flags); |
1bee963d | 995 | |
a0d6de9b | 996 | if (type & IRQ_TYPE_LEVEL_MASK) |
b9a5ec33 TG |
997 | irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, |
998 | handle_fasteoi_irq, NULL); | |
a0d6de9b | 999 | else |
b9a5ec33 TG |
1000 | irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, |
1001 | handle_edge_irq, NULL); | |
a0d6de9b | 1002 | |
2aaaddff | 1003 | regval = readl(pctl->membase + reg); |
d82f9401 | 1004 | regval &= ~(IRQ_CFG_IRQ_MASK << index); |
2aaaddff | 1005 | writel(regval | (mode << index), pctl->membase + reg); |
60242db1 | 1006 | |
f658ed36 | 1007 | raw_spin_unlock_irqrestore(&pctl->lock, flags); |
60242db1 MR |
1008 | |
1009 | return 0; | |
1010 | } | |
1011 | ||
645ec714 | 1012 | static void sunxi_pinctrl_irq_ack(struct irq_data *d) |
60242db1 MR |
1013 | { |
1014 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
4b0d6c5a | 1015 | u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); |
60242db1 | 1016 | u8 status_idx = sunxi_irq_status_offset(d->hwirq); |
60242db1 MR |
1017 | |
1018 | /* Clear the IRQ */ | |
1019 | writel(1 << status_idx, pctl->membase + status_reg); | |
1020 | } | |
1021 | ||
1022 | static void sunxi_pinctrl_irq_mask(struct irq_data *d) | |
1023 | { | |
1024 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
4b0d6c5a | 1025 | u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); |
60242db1 | 1026 | u8 idx = sunxi_irq_ctrl_offset(d->hwirq); |
1bee963d | 1027 | unsigned long flags; |
60242db1 MR |
1028 | u32 val; |
1029 | ||
f658ed36 | 1030 | raw_spin_lock_irqsave(&pctl->lock, flags); |
1bee963d | 1031 | |
60242db1 MR |
1032 | /* Mask the IRQ */ |
1033 | val = readl(pctl->membase + reg); | |
1034 | writel(val & ~(1 << idx), pctl->membase + reg); | |
1bee963d | 1035 | |
f658ed36 | 1036 | raw_spin_unlock_irqrestore(&pctl->lock, flags); |
60242db1 MR |
1037 | } |
1038 | ||
1039 | static void sunxi_pinctrl_irq_unmask(struct irq_data *d) | |
1040 | { | |
1041 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
4b0d6c5a | 1042 | u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); |
60242db1 | 1043 | u8 idx = sunxi_irq_ctrl_offset(d->hwirq); |
1bee963d | 1044 | unsigned long flags; |
60242db1 MR |
1045 | u32 val; |
1046 | ||
f658ed36 | 1047 | raw_spin_lock_irqsave(&pctl->lock, flags); |
1bee963d | 1048 | |
60242db1 MR |
1049 | /* Unmask the IRQ */ |
1050 | val = readl(pctl->membase + reg); | |
1051 | writel(val | (1 << idx), pctl->membase + reg); | |
1bee963d | 1052 | |
f658ed36 | 1053 | raw_spin_unlock_irqrestore(&pctl->lock, flags); |
60242db1 MR |
1054 | } |
1055 | ||
d61e23e5 HG |
1056 | static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) |
1057 | { | |
1058 | sunxi_pinctrl_irq_ack(d); | |
1059 | sunxi_pinctrl_irq_unmask(d); | |
1060 | } | |
1061 | ||
a59c99d9 SH |
1062 | static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on) |
1063 | { | |
1064 | struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
1065 | u8 bank = d->hwirq / IRQ_PER_BANK; | |
1066 | ||
1067 | return irq_set_irq_wake(pctl->irq[bank], on); | |
1068 | } | |
1069 | ||
f4c51c10 | 1070 | static struct irq_chip sunxi_pinctrl_edge_irq_chip = { |
fb5b7788 | 1071 | .name = "sunxi_pio_edge", |
645ec714 | 1072 | .irq_ack = sunxi_pinctrl_irq_ack, |
60242db1 | 1073 | .irq_mask = sunxi_pinctrl_irq_mask, |
60242db1 | 1074 | .irq_unmask = sunxi_pinctrl_irq_unmask, |
fea6d8ef | 1075 | .irq_request_resources = sunxi_pinctrl_irq_request_resources, |
f83549d6 | 1076 | .irq_release_resources = sunxi_pinctrl_irq_release_resources, |
60242db1 | 1077 | .irq_set_type = sunxi_pinctrl_irq_set_type, |
a59c99d9 | 1078 | .irq_set_wake = sunxi_pinctrl_irq_set_wake, |
8587b21c | 1079 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
60242db1 MR |
1080 | }; |
1081 | ||
f4c51c10 | 1082 | static struct irq_chip sunxi_pinctrl_level_irq_chip = { |
fb5b7788 | 1083 | .name = "sunxi_pio_level", |
f4c51c10 | 1084 | .irq_eoi = sunxi_pinctrl_irq_ack, |
60242db1 | 1085 | .irq_mask = sunxi_pinctrl_irq_mask, |
60242db1 | 1086 | .irq_unmask = sunxi_pinctrl_irq_unmask, |
d61e23e5 HG |
1087 | /* Define irq_enable / disable to avoid spurious irqs for drivers |
1088 | * using these to suppress irqs while they clear the irq source */ | |
1089 | .irq_enable = sunxi_pinctrl_irq_ack_unmask, | |
1090 | .irq_disable = sunxi_pinctrl_irq_mask, | |
f4c51c10 | 1091 | .irq_request_resources = sunxi_pinctrl_irq_request_resources, |
f83549d6 | 1092 | .irq_release_resources = sunxi_pinctrl_irq_release_resources, |
60242db1 | 1093 | .irq_set_type = sunxi_pinctrl_irq_set_type, |
a59c99d9 SH |
1094 | .irq_set_wake = sunxi_pinctrl_irq_set_wake, |
1095 | .flags = IRQCHIP_EOI_THREADED | | |
8587b21c | 1096 | IRQCHIP_MASK_ON_SUSPEND | |
f4c51c10 | 1097 | IRQCHIP_EOI_IF_HANDLED, |
60242db1 MR |
1098 | }; |
1099 | ||
d8323c6b MR |
1100 | static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, |
1101 | struct device_node *node, | |
1102 | const u32 *intspec, | |
1103 | unsigned int intsize, | |
1104 | unsigned long *out_hwirq, | |
1105 | unsigned int *out_type) | |
1106 | { | |
8297992c | 1107 | struct sunxi_pinctrl *pctl = d->host_data; |
d8323c6b MR |
1108 | struct sunxi_desc_function *desc; |
1109 | int pin, base; | |
1110 | ||
1111 | if (intsize < 3) | |
1112 | return -EINVAL; | |
1113 | ||
1114 | base = PINS_PER_BANK * intspec[0]; | |
8297992c | 1115 | pin = pctl->desc->pin_base + base + intspec[1]; |
d8323c6b | 1116 | |
8297992c | 1117 | desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); |
d8323c6b MR |
1118 | if (!desc) |
1119 | return -EINVAL; | |
1120 | ||
1121 | *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; | |
1122 | *out_type = intspec[2]; | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
2421dfd6 | 1127 | static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { |
d8323c6b MR |
1128 | .xlate = sunxi_pinctrl_irq_of_xlate, |
1129 | }; | |
1130 | ||
bd0b9ac4 | 1131 | static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) |
60242db1 | 1132 | { |
eeef97b1 | 1133 | unsigned int irq = irq_desc_get_irq(desc); |
5663bb27 JL |
1134 | struct irq_chip *chip = irq_desc_get_chip(desc); |
1135 | struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); | |
aebdc8ab MR |
1136 | unsigned long bank, reg, val; |
1137 | ||
1138 | for (bank = 0; bank < pctl->desc->irq_banks; bank++) | |
1139 | if (irq == pctl->irq[bank]) | |
1140 | break; | |
1141 | ||
fd5198dd | 1142 | WARN_ON(bank == pctl->desc->irq_banks); |
60242db1 | 1143 | |
a1158e36 YL |
1144 | chained_irq_enter(chip, desc); |
1145 | ||
4b0d6c5a | 1146 | reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); |
aebdc8ab | 1147 | val = readl(pctl->membase + reg); |
60242db1 | 1148 | |
aebdc8ab | 1149 | if (val) { |
60242db1 MR |
1150 | int irqoffset; |
1151 | ||
a9cb09b7 MZ |
1152 | for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) |
1153 | generic_handle_domain_irq(pctl->domain, | |
1154 | bank * IRQ_PER_BANK + irqoffset); | |
60242db1 | 1155 | } |
a1158e36 YL |
1156 | |
1157 | chained_irq_exit(chip, desc); | |
60242db1 MR |
1158 | } |
1159 | ||
0e37f88d MR |
1160 | static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, |
1161 | const char *name) | |
1162 | { | |
1163 | struct sunxi_pinctrl_function *func = pctl->functions; | |
1164 | ||
1165 | while (func->name) { | |
1166 | /* function already there */ | |
1167 | if (strcmp(func->name, name) == 0) { | |
1168 | func->ngroups++; | |
1169 | return -EEXIST; | |
1170 | } | |
1171 | func++; | |
1172 | } | |
1173 | ||
1174 | func->name = name; | |
1175 | func->ngroups = 1; | |
1176 | ||
1177 | pctl->nfunctions++; | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | static int sunxi_pinctrl_build_state(struct platform_device *pdev) | |
1183 | { | |
1184 | struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); | |
a93a676b | 1185 | void *ptr; |
0e37f88d MR |
1186 | int i; |
1187 | ||
578db85f MR |
1188 | /* |
1189 | * Allocate groups | |
1190 | * | |
1191 | * We assume that the number of groups is the number of pins | |
1192 | * given in the data array. | |
0e37f88d | 1193 | |
578db85f MR |
1194 | * This will not always be true, since some pins might not be |
1195 | * available in the current variant, but fortunately for us, | |
1196 | * this means that the number of pins is the maximum group | |
1197 | * number we will ever see. | |
1198 | */ | |
a86854d0 KC |
1199 | pctl->groups = devm_kcalloc(&pdev->dev, |
1200 | pctl->desc->npins, sizeof(*pctl->groups), | |
0e37f88d MR |
1201 | GFP_KERNEL); |
1202 | if (!pctl->groups) | |
1203 | return -ENOMEM; | |
1204 | ||
1205 | for (i = 0; i < pctl->desc->npins; i++) { | |
1206 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
578db85f MR |
1207 | struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; |
1208 | ||
1209 | if (pin->variant && !(pctl->variant & pin->variant)) | |
1210 | continue; | |
0e37f88d MR |
1211 | |
1212 | group->name = pin->pin.name; | |
1213 | group->pin = pin->pin.number; | |
578db85f MR |
1214 | |
1215 | /* And now we count the actual number of pins / groups */ | |
1216 | pctl->ngroups++; | |
0e37f88d MR |
1217 | } |
1218 | ||
1219 | /* | |
1220 | * We suppose that we won't have any more functions than pins, | |
1221 | * we'll reallocate that later anyway | |
1222 | */ | |
a4925311 Y |
1223 | pctl->functions = kcalloc(pctl->ngroups, |
1224 | sizeof(*pctl->functions), | |
1225 | GFP_KERNEL); | |
0e37f88d MR |
1226 | if (!pctl->functions) |
1227 | return -ENOMEM; | |
1228 | ||
1229 | /* Count functions and their associated groups */ | |
1230 | for (i = 0; i < pctl->desc->npins; i++) { | |
1231 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
578db85f MR |
1232 | struct sunxi_desc_function *func; |
1233 | ||
1234 | if (pin->variant && !(pctl->variant & pin->variant)) | |
1235 | continue; | |
1236 | ||
1237 | for (func = pin->functions; func->name; func++) { | |
1238 | if (func->variant && !(pctl->variant & func->variant)) | |
1239 | continue; | |
0e37f88d | 1240 | |
d54e9a28 | 1241 | /* Create interrupt mapping while we're at it */ |
aebdc8ab MR |
1242 | if (!strcmp(func->name, "irq")) { |
1243 | int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; | |
1244 | pctl->irq_array[irqnum] = pin->pin.number; | |
1245 | } | |
1246 | ||
0e37f88d | 1247 | sunxi_pinctrl_add_function(pctl, func->name); |
0e37f88d MR |
1248 | } |
1249 | } | |
1250 | ||
578db85f | 1251 | /* And now allocated and fill the array for real */ |
a93a676b CJ |
1252 | ptr = krealloc(pctl->functions, |
1253 | pctl->nfunctions * sizeof(*pctl->functions), | |
1254 | GFP_KERNEL); | |
1255 | if (!ptr) { | |
578db85f | 1256 | kfree(pctl->functions); |
a93a676b | 1257 | pctl->functions = NULL; |
578db85f MR |
1258 | return -ENOMEM; |
1259 | } | |
a93a676b | 1260 | pctl->functions = ptr; |
0e37f88d MR |
1261 | |
1262 | for (i = 0; i < pctl->desc->npins; i++) { | |
1263 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
578db85f | 1264 | struct sunxi_desc_function *func; |
0e37f88d | 1265 | |
578db85f MR |
1266 | if (pin->variant && !(pctl->variant & pin->variant)) |
1267 | continue; | |
1268 | ||
1269 | for (func = pin->functions; func->name; func++) { | |
0e37f88d MR |
1270 | struct sunxi_pinctrl_function *func_item; |
1271 | const char **func_grp; | |
1272 | ||
578db85f MR |
1273 | if (func->variant && !(pctl->variant & func->variant)) |
1274 | continue; | |
1275 | ||
0e37f88d MR |
1276 | func_item = sunxi_pinctrl_find_function_by_name(pctl, |
1277 | func->name); | |
a4925311 Y |
1278 | if (!func_item) { |
1279 | kfree(pctl->functions); | |
0e37f88d | 1280 | return -EINVAL; |
a4925311 | 1281 | } |
0e37f88d MR |
1282 | |
1283 | if (!func_item->groups) { | |
1284 | func_item->groups = | |
a86854d0 KC |
1285 | devm_kcalloc(&pdev->dev, |
1286 | func_item->ngroups, | |
1287 | sizeof(*func_item->groups), | |
0e37f88d | 1288 | GFP_KERNEL); |
a4925311 Y |
1289 | if (!func_item->groups) { |
1290 | kfree(pctl->functions); | |
0e37f88d | 1291 | return -ENOMEM; |
a4925311 | 1292 | } |
0e37f88d MR |
1293 | } |
1294 | ||
1295 | func_grp = func_item->groups; | |
1296 | while (*func_grp) | |
1297 | func_grp++; | |
1298 | ||
1299 | *func_grp = pin->pin.name; | |
0e37f88d MR |
1300 | } |
1301 | } | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
7c926492 MR |
1306 | static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff) |
1307 | { | |
1308 | unsigned long clock = clk_get_rate(clk); | |
d8a22212 | 1309 | unsigned int best_diff, best_div; |
7c926492 MR |
1310 | int i; |
1311 | ||
d8a22212 AB |
1312 | best_diff = abs(freq - clock); |
1313 | best_div = 0; | |
1314 | ||
1315 | for (i = 1; i < 8; i++) { | |
7c926492 MR |
1316 | int cur_diff = abs(freq - (clock >> i)); |
1317 | ||
1318 | if (cur_diff < best_diff) { | |
1319 | best_diff = cur_diff; | |
1320 | best_div = i; | |
1321 | } | |
1322 | } | |
1323 | ||
1324 | *diff = best_diff; | |
1325 | return best_div; | |
1326 | } | |
1327 | ||
1328 | static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, | |
1329 | struct device_node *node) | |
1330 | { | |
1331 | unsigned int hosc_diff, losc_diff; | |
1332 | unsigned int hosc_div, losc_div; | |
1333 | struct clk *hosc, *losc; | |
1334 | u8 div, src; | |
1335 | int i, ret; | |
1336 | ||
1337 | /* Deal with old DTs that didn't have the oscillators */ | |
470b73a3 | 1338 | if (of_clk_get_parent_count(node) != 3) |
7c926492 MR |
1339 | return 0; |
1340 | ||
1341 | /* If we don't have any setup, bail out */ | |
1342 | if (!of_find_property(node, "input-debounce", NULL)) | |
1343 | return 0; | |
1344 | ||
1345 | losc = devm_clk_get(pctl->dev, "losc"); | |
1346 | if (IS_ERR(losc)) | |
1347 | return PTR_ERR(losc); | |
1348 | ||
1349 | hosc = devm_clk_get(pctl->dev, "hosc"); | |
1350 | if (IS_ERR(hosc)) | |
1351 | return PTR_ERR(hosc); | |
1352 | ||
1353 | for (i = 0; i < pctl->desc->irq_banks; i++) { | |
1354 | unsigned long debounce_freq; | |
1355 | u32 debounce; | |
1356 | ||
1357 | ret = of_property_read_u32_index(node, "input-debounce", | |
1358 | i, &debounce); | |
1359 | if (ret) | |
1360 | return ret; | |
1361 | ||
1362 | if (!debounce) | |
1363 | continue; | |
1364 | ||
1365 | debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce); | |
1366 | losc_div = sunxi_pinctrl_get_debounce_div(losc, | |
1367 | debounce_freq, | |
1368 | &losc_diff); | |
1369 | ||
1370 | hosc_div = sunxi_pinctrl_get_debounce_div(hosc, | |
1371 | debounce_freq, | |
1372 | &hosc_diff); | |
1373 | ||
1374 | if (hosc_diff < losc_diff) { | |
1375 | div = hosc_div; | |
1376 | src = 1; | |
1377 | } else { | |
1378 | div = losc_div; | |
1379 | src = 0; | |
1380 | } | |
1381 | ||
1382 | writel(src | div << 4, | |
1383 | pctl->membase + | |
4b0d6c5a | 1384 | sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); |
7c926492 MR |
1385 | } |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
578db85f MR |
1390 | int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, |
1391 | const struct sunxi_pinctrl_desc *desc, | |
1392 | unsigned long variant) | |
0e37f88d MR |
1393 | { |
1394 | struct device_node *node = pdev->dev.of_node; | |
ba6764d5 | 1395 | struct pinctrl_desc *pctrl_desc; |
0e37f88d MR |
1396 | struct pinctrl_pin_desc *pins; |
1397 | struct sunxi_pinctrl *pctl; | |
aae842a3 | 1398 | struct pinmux_ops *pmxops; |
578db85f | 1399 | int i, ret, last_pin, pin_idx; |
950707c0 | 1400 | struct clk *clk; |
0e37f88d MR |
1401 | |
1402 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); | |
1403 | if (!pctl) | |
1404 | return -ENOMEM; | |
1405 | platform_set_drvdata(pdev, pctl); | |
1406 | ||
f658ed36 | 1407 | raw_spin_lock_init(&pctl->lock); |
1bee963d | 1408 | |
4b024225 | 1409 | pctl->membase = devm_platform_ioremap_resource(pdev, 0); |
4409cafc MR |
1410 | if (IS_ERR(pctl->membase)) |
1411 | return PTR_ERR(pctl->membase); | |
0e37f88d | 1412 | |
ba6764d5 | 1413 | pctl->dev = &pdev->dev; |
2284ba6b | 1414 | pctl->desc = desc; |
578db85f | 1415 | pctl->variant = variant; |
0e37f88d | 1416 | |
aebdc8ab MR |
1417 | pctl->irq_array = devm_kcalloc(&pdev->dev, |
1418 | IRQ_PER_BANK * pctl->desc->irq_banks, | |
1419 | sizeof(*pctl->irq_array), | |
1420 | GFP_KERNEL); | |
1421 | if (!pctl->irq_array) | |
1422 | return -ENOMEM; | |
1423 | ||
0e37f88d MR |
1424 | ret = sunxi_pinctrl_build_state(pdev); |
1425 | if (ret) { | |
1426 | dev_err(&pdev->dev, "dt probe failed: %d\n", ret); | |
1427 | return ret; | |
1428 | } | |
1429 | ||
a86854d0 KC |
1430 | pins = devm_kcalloc(&pdev->dev, |
1431 | pctl->desc->npins, sizeof(*pins), | |
0e37f88d MR |
1432 | GFP_KERNEL); |
1433 | if (!pins) | |
1434 | return -ENOMEM; | |
1435 | ||
578db85f MR |
1436 | for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { |
1437 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
1438 | ||
1439 | if (pin->variant && !(pctl->variant & pin->variant)) | |
1440 | continue; | |
1441 | ||
1442 | pins[pin_idx++] = pin->pin; | |
1443 | } | |
0e37f88d | 1444 | |
ba6764d5 MR |
1445 | pctrl_desc = devm_kzalloc(&pdev->dev, |
1446 | sizeof(*pctrl_desc), | |
1447 | GFP_KERNEL); | |
1448 | if (!pctrl_desc) | |
1449 | return -ENOMEM; | |
1450 | ||
1451 | pctrl_desc->name = dev_name(&pdev->dev); | |
1452 | pctrl_desc->owner = THIS_MODULE; | |
1453 | pctrl_desc->pins = pins; | |
578db85f | 1454 | pctrl_desc->npins = pctl->ngroups; |
ba6764d5 MR |
1455 | pctrl_desc->confops = &sunxi_pconf_ops; |
1456 | pctrl_desc->pctlops = &sunxi_pctrl_ops; | |
aae842a3 MR |
1457 | |
1458 | pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops), | |
1459 | GFP_KERNEL); | |
1460 | if (!pmxops) | |
1461 | return -ENOMEM; | |
1462 | ||
1463 | if (desc->disable_strict_mode) | |
1464 | pmxops->strict = false; | |
1465 | ||
1466 | pctrl_desc->pmxops = pmxops; | |
ba6764d5 | 1467 | |
45078ea0 | 1468 | pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); |
323de9ef | 1469 | if (IS_ERR(pctl->pctl_dev)) { |
0e37f88d | 1470 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); |
323de9ef | 1471 | return PTR_ERR(pctl->pctl_dev); |
0e37f88d MR |
1472 | } |
1473 | ||
08e9e614 | 1474 | pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); |
45078ea0 LD |
1475 | if (!pctl->chip) |
1476 | return -ENOMEM; | |
08e9e614 MR |
1477 | |
1478 | last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; | |
d83c82ce | 1479 | pctl->chip->owner = THIS_MODULE; |
fb7dea60 MR |
1480 | pctl->chip->request = gpiochip_generic_request; |
1481 | pctl->chip->free = gpiochip_generic_free; | |
04ed8c0c | 1482 | pctl->chip->set_config = gpiochip_generic_config; |
fb7dea60 MR |
1483 | pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input; |
1484 | pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output; | |
1485 | pctl->chip->get = sunxi_pinctrl_gpio_get; | |
1486 | pctl->chip->set = sunxi_pinctrl_gpio_set; | |
1487 | pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate; | |
1488 | pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq; | |
1489 | pctl->chip->of_gpio_n_cells = 3; | |
1490 | pctl->chip->can_sleep = false; | |
d83c82ce BB |
1491 | pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - |
1492 | pctl->desc->pin_base; | |
08e9e614 | 1493 | pctl->chip->label = dev_name(&pdev->dev); |
58383c78 | 1494 | pctl->chip->parent = &pdev->dev; |
d83c82ce | 1495 | pctl->chip->base = pctl->desc->pin_base; |
08e9e614 | 1496 | |
88057d6e | 1497 | ret = gpiochip_add_data(pctl->chip, pctl); |
08e9e614 | 1498 | if (ret) |
45078ea0 | 1499 | return ret; |
08e9e614 MR |
1500 | |
1501 | for (i = 0; i < pctl->desc->npins; i++) { | |
1502 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
1503 | ||
1504 | ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), | |
343f1327 | 1505 | pin->pin.number - pctl->desc->pin_base, |
08e9e614 MR |
1506 | pin->pin.number, 1); |
1507 | if (ret) | |
1508 | goto gpiochip_error; | |
1509 | } | |
1510 | ||
10e3a88b | 1511 | ret = of_clk_get_parent_count(node); |
a34ea4b4 | 1512 | clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb"); |
d72f88a4 WY |
1513 | if (IS_ERR(clk)) { |
1514 | ret = PTR_ERR(clk); | |
950707c0 | 1515 | goto gpiochip_error; |
d72f88a4 | 1516 | } |
950707c0 | 1517 | |
6415093f BB |
1518 | ret = clk_prepare_enable(clk); |
1519 | if (ret) | |
1520 | goto gpiochip_error; | |
950707c0 | 1521 | |
aebdc8ab MR |
1522 | pctl->irq = devm_kcalloc(&pdev->dev, |
1523 | pctl->desc->irq_banks, | |
1524 | sizeof(*pctl->irq), | |
1525 | GFP_KERNEL); | |
60242db1 | 1526 | if (!pctl->irq) { |
aebdc8ab | 1527 | ret = -ENOMEM; |
dc969106 | 1528 | goto clk_error; |
60242db1 MR |
1529 | } |
1530 | ||
aebdc8ab MR |
1531 | for (i = 0; i < pctl->desc->irq_banks; i++) { |
1532 | pctl->irq[i] = platform_get_irq(pdev, i); | |
1533 | if (pctl->irq[i] < 0) { | |
1534 | ret = pctl->irq[i]; | |
1535 | goto clk_error; | |
1536 | } | |
1537 | } | |
1538 | ||
1539 | pctl->domain = irq_domain_add_linear(node, | |
1540 | pctl->desc->irq_banks * IRQ_PER_BANK, | |
d8323c6b MR |
1541 | &sunxi_pinctrl_irq_domain_ops, |
1542 | pctl); | |
60242db1 MR |
1543 | if (!pctl->domain) { |
1544 | dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); | |
1545 | ret = -ENOMEM; | |
dc969106 | 1546 | goto clk_error; |
60242db1 MR |
1547 | } |
1548 | ||
aebdc8ab | 1549 | for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { |
60242db1 MR |
1550 | int irqno = irq_create_mapping(pctl->domain, i); |
1551 | ||
f4c51c10 HG |
1552 | irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, |
1553 | handle_edge_irq); | |
60242db1 | 1554 | irq_set_chip_data(irqno, pctl); |
5c99c0ff | 1555 | } |
60242db1 | 1556 | |
aebdc8ab | 1557 | for (i = 0; i < pctl->desc->irq_banks; i++) { |
f4c51c10 | 1558 | /* Mask and clear all IRQs before registering a handler */ |
4b0d6c5a IZ |
1559 | writel(0, pctl->membase + |
1560 | sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); | |
f4c51c10 | 1561 | writel(0xffffffff, |
4b0d6c5a IZ |
1562 | pctl->membase + |
1563 | sunxi_irq_status_reg_from_bank(pctl->desc, i)); | |
f4c51c10 | 1564 | |
ef80e87d TG |
1565 | irq_set_chained_handler_and_data(pctl->irq[i], |
1566 | sunxi_pinctrl_irq_handler, | |
1567 | pctl); | |
aebdc8ab | 1568 | } |
60242db1 | 1569 | |
7c926492 MR |
1570 | sunxi_pinctrl_setup_debounce(pctl, node); |
1571 | ||
08e9e614 | 1572 | dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); |
0e37f88d MR |
1573 | |
1574 | return 0; | |
08e9e614 | 1575 | |
e2bddc6a BB |
1576 | clk_error: |
1577 | clk_disable_unprepare(clk); | |
08e9e614 | 1578 | gpiochip_error: |
b4e7c55d | 1579 | gpiochip_remove(pctl->chip); |
08e9e614 | 1580 | return ret; |
0e37f88d | 1581 | } |