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[linux-2.6-block.git] / drivers / pinctrl / sprd / pinctrl-sprd.c
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1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
41d32cfc
BW		 2/*
3 * Spreadtrum pin controller driver
4 * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
41d32cfc
BW		 5 */
6
7#include <linux/debugfs.h>
8#include <linux/err.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
82a045ab
AS		 16#include <linux/seq_file.h>
17#include <linux/slab.h>
18
19#include <linux/pinctrl/consumer.h>
41d32cfc 20#include <linux/pinctrl/machine.h>
41d32cfc 21#include <linux/pinctrl/pinconf-generic.h>
82a045ab 22#include <linux/pinctrl/pinconf.h>
41d32cfc
BW		 23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
41d32cfc
BW		 25
26#include "../core.h"
27#include "../pinmux.h"
28#include "../pinconf.h"
29#include "../pinctrl-utils.h"
30#include "pinctrl-sprd.h"
31
32#define PINCTRL_BIT_MASK(width) (~(~0UL << (width)))
33#define PINCTRL_REG_OFFSET 0x20
34#define PINCTRL_REG_MISC_OFFSET 0x4020
35#define PINCTRL_REG_LEN 0x4
36
37#define PIN_FUNC_MASK (BIT(4) | BIT(5))
38#define PIN_FUNC_SEL_1 ~PIN_FUNC_MASK
39#define PIN_FUNC_SEL_2 BIT(4)
40#define PIN_FUNC_SEL_3 BIT(5)
41#define PIN_FUNC_SEL_4 PIN_FUNC_MASK
42
43#define AP_SLEEP_MODE BIT(13)
44#define PUBCP_SLEEP_MODE BIT(14)
45#define TGLDSP_SLEEP_MODE BIT(15)
46#define AGDSP_SLEEP_MODE BIT(16)
e543b3f5
BC		 47#define CM4_SLEEP_MODE BIT(17)
48#define SLEEP_MODE_MASK GENMASK(5, 0)
41d32cfc
BW		 49#define SLEEP_MODE_SHIFT 13
50
51#define SLEEP_INPUT BIT(1)
52#define SLEEP_INPUT_MASK 0x1
53#define SLEEP_INPUT_SHIFT 1
54
55#define SLEEP_OUTPUT BIT(0)
56#define SLEEP_OUTPUT_MASK 0x1
57#define SLEEP_OUTPUT_SHIFT 0
58
59#define DRIVE_STRENGTH_MASK GENMASK(3, 0)
60#define DRIVE_STRENGTH_SHIFT 19
61
62#define SLEEP_PULL_DOWN BIT(2)
63#define SLEEP_PULL_DOWN_MASK 0x1
64#define SLEEP_PULL_DOWN_SHIFT 2
65
66#define PULL_DOWN BIT(6)
67#define PULL_DOWN_MASK 0x1
68#define PULL_DOWN_SHIFT 6
69
70#define SLEEP_PULL_UP BIT(3)
71#define SLEEP_PULL_UP_MASK 0x1
72#define SLEEP_PULL_UP_SHIFT 3
73
94873f6b
BW		 74#define PULL_UP_4_7K (BIT(12) | BIT(7))
75#define PULL_UP_20K BIT(7)
41d32cfc
BW		 76#define PULL_UP_MASK 0x21
77#define PULL_UP_SHIFT 7
78
79#define INPUT_SCHMITT BIT(11)
80#define INPUT_SCHMITT_MASK 0x1
81#define INPUT_SCHMITT_SHIFT 11
82
83enum pin_sleep_mode {
84 AP_SLEEP = BIT(0),
85 PUBCP_SLEEP = BIT(1),
86 TGLDSP_SLEEP = BIT(2),
87 AGDSP_SLEEP = BIT(3),
e543b3f5 88 CM4_SLEEP = BIT(4),
41d32cfc
BW		 89};
90
91enum pin_func_sel {
92 PIN_FUNC_1,
93 PIN_FUNC_2,
94 PIN_FUNC_3,
95 PIN_FUNC_4,
96 PIN_FUNC_MAX,
97};
98
99/**
100 * struct sprd_pin: represent one pin's description
101 * @name: pin name
102 * @number: pin number
103 * @type: pin type, can be GLOBAL_CTRL_PIN/COMMON_PIN/MISC_PIN
104 * @reg: pin register address
105 * @bit_offset: bit offset in pin register
106 * @bit_width: bit width in pin register
107 */
108struct sprd_pin {
109 const char *name;
110 unsigned int number;
111 enum pin_type type;
112 unsigned long reg;
113 unsigned long bit_offset;
114 unsigned long bit_width;
115};
116
117/**
118 * struct sprd_pin_group: represent one group's description
119 * @name: group name
120 * @npins: pin numbers of this group
121 * @pins: pointer to pins array
122 */
123struct sprd_pin_group {
124 const char *name;
125 unsigned int npins;
126 unsigned int *pins;
127};
128
129/**
130 * struct sprd_pinctrl_soc_info: represent the SoC's pins description
131 * @groups: pointer to groups of pins
132 * @ngroups: group numbers of the whole SoC
133 * @pins: pointer to pins description
134 * @npins: pin numbers of the whole SoC
135 * @grp_names: pointer to group names array
136 */
137struct sprd_pinctrl_soc_info {
138 struct sprd_pin_group *groups;
139 unsigned int ngroups;
140 struct sprd_pin *pins;
141 unsigned int npins;
142 const char **grp_names;
143};
144
145/**
146 * struct sprd_pinctrl: represent the pin controller device
147 * @dev: pointer to the device structure
148 * @pctl: pointer to the pinctrl handle
149 * @base: base address of the controller
150 * @info: pointer to SoC's pins description information
151 */
152struct sprd_pinctrl {
153 struct device *dev;
154 struct pinctrl_dev *pctl;
155 void __iomem *base;
156 struct sprd_pinctrl_soc_info *info;
157};
158
957063c9
NC		 159#define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
160#define SPRD_PIN_CONFIG_SLEEP_MODE (PIN_CONFIG_END + 2)
41d32cfc
BW		 161
162static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl,
163 const char *name)
164{
165 struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
166 int i;
167
168 for (i = 0; i < info->npins; i++) {
169 if (!strcmp(info->pins[i].name, name))
170 return info->pins[i].number;
171 }
172
173 return -ENODEV;
174}
175
176static struct sprd_pin *
177sprd_pinctrl_get_pin_by_id(struct sprd_pinctrl *sprd_pctl, unsigned int id)
178{
179 struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
180 struct sprd_pin *pin = NULL;
181 int i;
182
183 for (i = 0; i < info->npins; i++) {
184 if (info->pins[i].number == id) {
185 pin = &info->pins[i];
186 break;
187 }
188 }
189
190 return pin;
191}
192
193static const struct sprd_pin_group *
194sprd_pinctrl_find_group_by_name(struct sprd_pinctrl *sprd_pctl,
195 const char *name)
196{
197 struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
198 const struct sprd_pin_group *grp = NULL;
199 int i;
200
201 for (i = 0; i < info->ngroups; i++) {
202 if (!strcmp(info->groups[i].name, name)) {
203 grp = &info->groups[i];
204 break;
205 }
206 }
207
208 return grp;
209}
210
211static int sprd_pctrl_group_count(struct pinctrl_dev *pctldev)
212{
213 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
214 struct sprd_pinctrl_soc_info *info = pctl->info;
215
216 return info->ngroups;
217}
218
219static const char *sprd_pctrl_group_name(struct pinctrl_dev *pctldev,
220 unsigned int selector)
221{
222 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
223 struct sprd_pinctrl_soc_info *info = pctl->info;
224
225 return info->groups[selector].name;
226}
227
228static int sprd_pctrl_group_pins(struct pinctrl_dev *pctldev,
229 unsigned int selector,
230 const unsigned int **pins,
231 unsigned int *npins)
232{
233 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
234 struct sprd_pinctrl_soc_info *info = pctl->info;
235
236 if (selector >= info->ngroups)
237 return -EINVAL;
238
239 *pins = info->groups[selector].pins;
240 *npins = info->groups[selector].npins;
241
242 return 0;
243}
244
245static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev,
246 struct device_node *np,
247 struct pinctrl_map **map,
248 unsigned int *num_maps)
249{
250 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
251 const struct sprd_pin_group *grp;
252 unsigned long *configs = NULL;
253 unsigned int num_configs = 0;
254 unsigned int reserved_maps = 0;
255 unsigned int reserve = 0;
256 const char *function;
257 enum pinctrl_map_type type;
258 int ret;
259
260 grp = sprd_pinctrl_find_group_by_name(pctl, np->name);
261 if (!grp) {
262 dev_err(pctl->dev, "unable to find group for node %s\n",
263 of_node_full_name(np));
264 return -EINVAL;
265 }
266
267 ret = of_property_count_strings(np, "pins");
268 if (ret < 0)
269 return ret;
270
271 if (ret == 1)
272 type = PIN_MAP_TYPE_CONFIGS_PIN;
273 else
274 type = PIN_MAP_TYPE_CONFIGS_GROUP;
275
276 ret = of_property_read_string(np, "function", &function);
277 if (ret < 0) {
278 if (ret != -EINVAL)
279 dev_err(pctl->dev,
280 "%s: could not parse property function\n",
281 of_node_full_name(np));
282 function = NULL;
283 }
284
285 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
286 &num_configs);
287 if (ret < 0) {
288 dev_err(pctl->dev, "%s: could not parse node property\n",
289 of_node_full_name(np));
290 return ret;
291 }
292
293 *map = NULL;
294 *num_maps = 0;
295
296 if (function != NULL)
297 reserve++;
298 if (num_configs)
299 reserve++;
300
301 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
302 num_maps, reserve);
303 if (ret < 0)
304 goto out;
305
306 if (function) {
307 ret = pinctrl_utils_add_map_mux(pctldev, map,
308 &reserved_maps, num_maps,
309 grp->name, function);
310 if (ret < 0)
311 goto out;
312 }
313
314 if (num_configs) {
315 const char *group_or_pin;
316 unsigned int pin_id;
317
318 if (type == PIN_MAP_TYPE_CONFIGS_PIN) {
319 pin_id = grp->pins[0];
320 group_or_pin = pin_get_name(pctldev, pin_id);
321 } else {
322 group_or_pin = grp->name;
323 }
324
325 ret = pinctrl_utils_add_map_configs(pctldev, map,
326 &reserved_maps, num_maps,
327 group_or_pin, configs,
328 num_configs, type);
329 }
330
331out:
332 kfree(configs);
333 return ret;
334}
335
336static void sprd_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
337 unsigned int offset)
338{
339 seq_printf(s, "%s", dev_name(pctldev->dev));
340}
341
342static const struct pinctrl_ops sprd_pctrl_ops = {
343 .get_groups_count = sprd_pctrl_group_count,
344 .get_group_name = sprd_pctrl_group_name,
345 .get_group_pins = sprd_pctrl_group_pins,
346 .pin_dbg_show = sprd_pctrl_dbg_show,
347 .dt_node_to_map = sprd_dt_node_to_map,
348 .dt_free_map = pinctrl_utils_free_map,
349};
350
045b5792 351static int sprd_pmx_get_function_count(struct pinctrl_dev *pctldev)
41d32cfc
BW		 352{
353 return PIN_FUNC_MAX;
354}
355
045b5792
CIK		 356static const char *sprd_pmx_get_function_name(struct pinctrl_dev *pctldev,
357 unsigned int selector)
41d32cfc
BW		 358{
359 switch (selector) {
360 case PIN_FUNC_1:
361 return "func1";
362 case PIN_FUNC_2:
363 return "func2";
364 case PIN_FUNC_3:
365 return "func3";
366 case PIN_FUNC_4:
367 return "func4";
368 default:
369 return "null";
370 }
371}
372
045b5792
CIK		 373static int sprd_pmx_get_function_groups(struct pinctrl_dev *pctldev,
374 unsigned int selector,
375 const char * const **groups,
376 unsigned int * const num_groups)
41d32cfc
BW		 377{
378 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
379 struct sprd_pinctrl_soc_info *info = pctl->info;
380
381 *groups = info->grp_names;
382 *num_groups = info->ngroups;
383
384 return 0;
385}
386
387static int sprd_pmx_set_mux(struct pinctrl_dev *pctldev,
388 unsigned int func_selector,
389 unsigned int group_selector)
390{
391 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
392 struct sprd_pinctrl_soc_info *info = pctl->info;
393 struct sprd_pin_group *grp = &info->groups[group_selector];
394 unsigned int i, grp_pins = grp->npins;
395 unsigned long reg;
396 unsigned int val = 0;
397
4ce504c4 398 if (group_selector >= info->ngroups)
41d32cfc
BW		 399 return -EINVAL;
400
401 switch (func_selector) {
402 case PIN_FUNC_1:
403 val &= PIN_FUNC_SEL_1;
404 break;
405 case PIN_FUNC_2:
406 val |= PIN_FUNC_SEL_2;
407 break;
408 case PIN_FUNC_3:
409 val |= PIN_FUNC_SEL_3;
410 break;
411 case PIN_FUNC_4:
412 val |= PIN_FUNC_SEL_4;
413 break;
414 default:
415 break;
416 }
417
418 for (i = 0; i < grp_pins; i++) {
419 unsigned int pin_id = grp->pins[i];
420 struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
421
422 if (!pin || pin->type != COMMON_PIN)
423 continue;
424
425 reg = readl((void __iomem *)pin->reg);
426 reg &= ~PIN_FUNC_MASK;
427 reg |= val;
428 writel(reg, (void __iomem *)pin->reg);
429 }
430
431 return 0;
432}
433
434static const struct pinmux_ops sprd_pmx_ops = {
435 .get_functions_count = sprd_pmx_get_function_count,
436 .get_function_name = sprd_pmx_get_function_name,
437 .get_function_groups = sprd_pmx_get_function_groups,
438 .set_mux = sprd_pmx_set_mux,
439};
440
441static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
442 unsigned long *config)
443{
444 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
445 struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
446 unsigned int param = pinconf_to_config_param(*config);
447 unsigned int reg, arg;
448
449 if (!pin)
450 return -EINVAL;
451
452 if (pin->type == GLOBAL_CTRL_PIN) {
453 reg = (readl((void __iomem *)pin->reg) >>
454 pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
455 } else {
456 reg = readl((void __iomem *)pin->reg);
457 }
458
459 if (pin->type == GLOBAL_CTRL_PIN &&
460 param == SPRD_PIN_CONFIG_CONTROL) {
461 arg = reg;
2f22e202 462 } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
41d32cfc
BW		 463 switch (param) {
464 case SPRD_PIN_CONFIG_SLEEP_MODE:
465 arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK;
466 break;
467 case PIN_CONFIG_INPUT_ENABLE:
468 arg = (reg >> SLEEP_INPUT_SHIFT) & SLEEP_INPUT_MASK;
469 break;
bb0f472f 470 case PIN_CONFIG_OUTPUT_ENABLE:
41d32cfc
BW		 471 arg = reg & SLEEP_OUTPUT_MASK;
472 break;
1592c4b9
LX		 473 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
474 if ((reg & SLEEP_OUTPUT) || (reg & SLEEP_INPUT))
475 return -EINVAL;
476
477 arg = 1;
478 break;
41d32cfc
BW		 479 case PIN_CONFIG_DRIVE_STRENGTH:
480 arg = (reg >> DRIVE_STRENGTH_SHIFT) &
481 DRIVE_STRENGTH_MASK;
482 break;
483 case PIN_CONFIG_BIAS_PULL_DOWN:
484 /* combine sleep pull down and pull down config */
485 arg = ((reg >> SLEEP_PULL_DOWN_SHIFT) &
486 SLEEP_PULL_DOWN_MASK) << 16;
487 arg |= (reg >> PULL_DOWN_SHIFT) & PULL_DOWN_MASK;
488 break;
489 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
490 arg = (reg >> INPUT_SCHMITT_SHIFT) & INPUT_SCHMITT_MASK;
491 break;
492 case PIN_CONFIG_BIAS_PULL_UP:
493 /* combine sleep pull up and pull up config */
494 arg = ((reg >> SLEEP_PULL_UP_SHIFT) &
495 SLEEP_PULL_UP_MASK) << 16;
496 arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK;
497 break;
f8b05fe4
BW		 498 case PIN_CONFIG_BIAS_DISABLE:
499 if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
500 (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
501 return -EINVAL;
502
503 arg = 1;
504 break;
41d32cfc
BW		 505 case PIN_CONFIG_SLEEP_HARDWARE_STATE:
506 arg = 0;
507 break;
508 default:
509 return -ENOTSUPP;
510 }
511 } else {
512 return -ENOTSUPP;
513 }
514
515 *config = pinconf_to_config_packed(param, arg);
516 return 0;
517}
518
519static unsigned int sprd_pinconf_drive(unsigned int mA)
520{
521 unsigned int val = 0;
522
523 switch (mA) {
524 case 2:
525 break;
526 case 4:
527 val |= BIT(19);
528 break;
529 case 6:
530 val |= BIT(20);
531 break;
532 case 8:
533 val |= BIT(19) | BIT(20);
534 break;
535 case 10:
536 val |= BIT(21);
537 break;
538 case 12:
539 val |= BIT(21) | BIT(19);
540 break;
541 case 14:
542 val |= BIT(21) | BIT(20);
543 break;
544 case 16:
545 val |= BIT(19) | BIT(20) | BIT(21);
546 break;
547 case 20:
548 val |= BIT(22);
549 break;
550 case 21:
551 val |= BIT(22) | BIT(19);
552 break;
553 case 24:
554 val |= BIT(22) | BIT(20);
555 break;
556 case 25:
557 val |= BIT(22) | BIT(20) | BIT(19);
558 break;
559 case 27:
560 val |= BIT(22) | BIT(21);
561 break;
562 case 29:
563 val |= BIT(22) | BIT(21) | BIT(19);
564 break;
565 case 31:
566 val |= BIT(22) | BIT(21) | BIT(20);
567 break;
568 case 33:
569 val |= BIT(22) | BIT(21) | BIT(20) | BIT(19);
570 break;
571 default:
572 break;
573 }
574
575 return val;
576}
577
578static bool sprd_pinctrl_check_sleep_config(unsigned long *configs,
579 unsigned int num_configs)
580{
581 unsigned int param;
582 int i;
583
584 for (i = 0; i < num_configs; i++) {
585 param = pinconf_to_config_param(configs[i]);
586 if (param == PIN_CONFIG_SLEEP_HARDWARE_STATE)
587 return true;
588 }
589
590 return false;
591}
592
593static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
594 unsigned long *configs, unsigned int num_configs)
595{
596 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
597 struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
598 bool is_sleep_config;
599 unsigned long reg;
600 int i;
601
602 if (!pin)
603 return -EINVAL;
604
605 is_sleep_config = sprd_pinctrl_check_sleep_config(configs, num_configs);
606
607 for (i = 0; i < num_configs; i++) {
608 unsigned int param, arg, shift, mask, val;
609
610 param = pinconf_to_config_param(configs[i]);
611 arg = pinconf_to_config_argument(configs[i]);
612
613 val = 0;
614 shift = 0;
615 mask = 0;
616 if (pin->type == GLOBAL_CTRL_PIN &&
617 param == SPRD_PIN_CONFIG_CONTROL) {
618 val = arg;
2f22e202 619 } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
41d32cfc
BW		 620 switch (param) {
621 case SPRD_PIN_CONFIG_SLEEP_MODE:
622 if (arg & AP_SLEEP)
623 val |= AP_SLEEP_MODE;
624 if (arg & PUBCP_SLEEP)
625 val |= PUBCP_SLEEP_MODE;
626 if (arg & TGLDSP_SLEEP)
627 val |= TGLDSP_SLEEP_MODE;
628 if (arg & AGDSP_SLEEP)
629 val |= AGDSP_SLEEP_MODE;
e543b3f5
BC		 630 if (arg & CM4_SLEEP)
631 val |= CM4_SLEEP_MODE;
41d32cfc
BW		 632
633 mask = SLEEP_MODE_MASK;
634 shift = SLEEP_MODE_SHIFT;
635 break;
636 case PIN_CONFIG_INPUT_ENABLE:
637 if (is_sleep_config == true) {
638 if (arg > 0)
639 val |= SLEEP_INPUT;
640 else
641 val &= ~SLEEP_INPUT;
642
643 mask = SLEEP_INPUT_MASK;
644 shift = SLEEP_INPUT_SHIFT;
645 }
646 break;
bb0f472f 647 case PIN_CONFIG_OUTPUT_ENABLE:
41d32cfc 648 if (is_sleep_config == true) {
bb0f472f
LX		 649 if (arg > 0)
650 val |= SLEEP_OUTPUT;
651 else
652 val &= ~SLEEP_OUTPUT;
653
41d32cfc
BW		 654 mask = SLEEP_OUTPUT_MASK;
655 shift = SLEEP_OUTPUT_SHIFT;
656 }
657 break;
1592c4b9
LX		 658 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
659 if (is_sleep_config == true) {
660 val = shift = 0;
661 mask = SLEEP_OUTPUT | SLEEP_INPUT;
662 }
663 break;
41d32cfc
BW		 664 case PIN_CONFIG_DRIVE_STRENGTH:
665 if (arg < 2 || arg > 60)
666 return -EINVAL;
667
668 val = sprd_pinconf_drive(arg);
669 mask = DRIVE_STRENGTH_MASK;
670 shift = DRIVE_STRENGTH_SHIFT;
671 break;
672 case PIN_CONFIG_BIAS_PULL_DOWN:
673 if (is_sleep_config == true) {
674 val |= SLEEP_PULL_DOWN;
675 mask = SLEEP_PULL_DOWN_MASK;
676 shift = SLEEP_PULL_DOWN_SHIFT;
677 } else {
678 val |= PULL_DOWN;
679 mask = PULL_DOWN_MASK;
680 shift = PULL_DOWN_SHIFT;
681 }
682 break;
683 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
684 if (arg > 0)
685 val |= INPUT_SCHMITT;
686 else
687 val &= ~INPUT_SCHMITT;
688
689 mask = INPUT_SCHMITT_MASK;
690 shift = INPUT_SCHMITT_SHIFT;
691 break;
692 case PIN_CONFIG_BIAS_PULL_UP:
60c456e0 693 if (is_sleep_config) {
41d32cfc
BW		 694 val |= SLEEP_PULL_UP;
695 mask = SLEEP_PULL_UP_MASK;
696 shift = SLEEP_PULL_UP_SHIFT;
697 } else {
698 if (arg == 20000)
699 val |= PULL_UP_20K;
700 else if (arg == 4700)
701 val |= PULL_UP_4_7K;
702
703 mask = PULL_UP_MASK;
704 shift = PULL_UP_SHIFT;
705 }
706 break;
f8b05fe4
BW		 707 case PIN_CONFIG_BIAS_DISABLE:
708 if (is_sleep_config == true) {
709 val = shift = 0;
710 mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP;
711 } else {
712 val = shift = 0;
713 mask = PULL_DOWN | PULL_UP_20K |
714 PULL_UP_4_7K;
715 }
716 break;
41d32cfc
BW		 717 case PIN_CONFIG_SLEEP_HARDWARE_STATE:
718 continue;
719 default:
720 return -ENOTSUPP;
721 }
722 } else {
723 return -ENOTSUPP;
724 }
725
726 if (pin->type == GLOBAL_CTRL_PIN) {
727 reg = readl((void __iomem *)pin->reg);
728 reg &= ~(PINCTRL_BIT_MASK(pin->bit_width)
729 << pin->bit_offset);
730 reg |= (val & PINCTRL_BIT_MASK(pin->bit_width))
731 << pin->bit_offset;
732 writel(reg, (void __iomem *)pin->reg);
733 } else {
734 reg = readl((void __iomem *)pin->reg);
735 reg &= ~(mask << shift);
736 reg |= val;
737 writel(reg, (void __iomem *)pin->reg);
738 }
739 }
740
741 return 0;
742}
743
744static int sprd_pinconf_group_get(struct pinctrl_dev *pctldev,
745 unsigned int selector, unsigned long *config)
746{
747 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
748 struct sprd_pinctrl_soc_info *info = pctl->info;
749 struct sprd_pin_group *grp;
750 unsigned int pin_id;
751
4ce504c4 752 if (selector >= info->ngroups)
41d32cfc
BW		 753 return -EINVAL;
754
755 grp = &info->groups[selector];
756 pin_id = grp->pins[0];
757
758 return sprd_pinconf_get(pctldev, pin_id, config);
759}
760
761static int sprd_pinconf_group_set(struct pinctrl_dev *pctldev,
762 unsigned int selector,
763 unsigned long *configs,
764 unsigned int num_configs)
765{
766 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
767 struct sprd_pinctrl_soc_info *info = pctl->info;
768 struct sprd_pin_group *grp;
769 int ret, i;
770
4ce504c4 771 if (selector >= info->ngroups)
41d32cfc
BW		 772 return -EINVAL;
773
774 grp = &info->groups[selector];
775
776 for (i = 0; i < grp->npins; i++) {
777 unsigned int pin_id = grp->pins[i];
778
779 ret = sprd_pinconf_set(pctldev, pin_id, configs, num_configs);
780 if (ret)
781 return ret;
782 }
783
784 return 0;
785}
786
787static int sprd_pinconf_get_config(struct pinctrl_dev *pctldev,
788 unsigned int pin_id,
789 unsigned long *config)
790{
791 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
792 struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
793
794 if (!pin)
795 return -EINVAL;
796
797 if (pin->type == GLOBAL_CTRL_PIN) {
798 *config = (readl((void __iomem *)pin->reg) >>
799 pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
800 } else {
801 *config = readl((void __iomem *)pin->reg);
802 }
803
804 return 0;
805}
806
807static void sprd_pinconf_dbg_show(struct pinctrl_dev *pctldev,
808 struct seq_file *s, unsigned int pin_id)
809{
810 unsigned long config;
811 int ret;
812
813 ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
814 if (ret)
815 return;
816
817 seq_printf(s, "0x%lx", config);
818}
819
820static void sprd_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
821 struct seq_file *s,
822 unsigned int selector)
823{
824 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
825 struct sprd_pinctrl_soc_info *info = pctl->info;
826 struct sprd_pin_group *grp;
827 unsigned long config;
828 const char *name;
829 int i, ret;
830
4ce504c4 831 if (selector >= info->ngroups)
41d32cfc
BW		 832 return;
833
834 grp = &info->groups[selector];
835
9d2fc7c3 836 seq_putc(s, '\n');
41d32cfc
BW		 837 for (i = 0; i < grp->npins; i++, config++) {
838 unsigned int pin_id = grp->pins[i];
839
840 name = pin_get_name(pctldev, pin_id);
841 ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
842 if (ret)
843 return;
844
845 seq_printf(s, "%s: 0x%lx ", name, config);
846 }
847}
848
849static const struct pinconf_ops sprd_pinconf_ops = {
850 .is_generic = true,
851 .pin_config_get = sprd_pinconf_get,
852 .pin_config_set = sprd_pinconf_set,
853 .pin_config_group_get = sprd_pinconf_group_get,
854 .pin_config_group_set = sprd_pinconf_group_set,
855 .pin_config_dbg_show = sprd_pinconf_dbg_show,
856 .pin_config_group_dbg_show = sprd_pinconf_group_dbg_show,
857};
858
859static const struct pinconf_generic_params sprd_dt_params[] = {
860 {"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0},
861 {"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0},
862};
863
864#ifdef CONFIG_DEBUG_FS
865static const struct pin_config_item sprd_conf_items[] = {
866 PCONFDUMP(SPRD_PIN_CONFIG_CONTROL, "global control", NULL, true),
867 PCONFDUMP(SPRD_PIN_CONFIG_SLEEP_MODE, "sleep mode", NULL, true),
868};
869#endif
870
871static struct pinctrl_desc sprd_pinctrl_desc = {
872 .pctlops = &sprd_pctrl_ops,
873 .pmxops = &sprd_pmx_ops,
874 .confops = &sprd_pinconf_ops,
875 .num_custom_params = ARRAY_SIZE(sprd_dt_params),
876 .custom_params = sprd_dt_params,
877#ifdef CONFIG_DEBUG_FS
878 .custom_conf_items = sprd_conf_items,
879#endif
880 .owner = THIS_MODULE,
881};
882
883static int sprd_pinctrl_parse_groups(struct device_node *np,
884 struct sprd_pinctrl *sprd_pctl,
885 struct sprd_pin_group *grp)
886{
887 struct property *prop;
888 const char *pin_name;
889 int ret, i = 0;
890
891 ret = of_property_count_strings(np, "pins");
892 if (ret < 0)
893 return ret;
894
895 grp->name = np->name;
896 grp->npins = ret;
a86854d0
KC		 897 grp->pins = devm_kcalloc(sprd_pctl->dev,
898 grp->npins, sizeof(unsigned int),
899 GFP_KERNEL);
41d32cfc
BW		 900 if (!grp->pins)
901 return -ENOMEM;
902
903 of_property_for_each_string(np, "pins", prop, pin_name) {
904 ret = sprd_pinctrl_get_id_by_name(sprd_pctl, pin_name);
905 if (ret >= 0)
906 grp->pins[i++] = ret;
907 }
908
909 for (i = 0; i < grp->npins; i++) {
910 dev_dbg(sprd_pctl->dev,
911 "Group[%s] contains [%d] pins: id = %d\n",
912 grp->name, grp->npins, grp->pins[i]);
913 }
914
915 return 0;
916}
917
918static unsigned int sprd_pinctrl_get_groups(struct device_node *np)
919{
920 struct device_node *child;
921 unsigned int group_cnt, cnt;
922
923 group_cnt = of_get_child_count(np);
924
925 for_each_child_of_node(np, child) {
926 cnt = of_get_child_count(child);
927 if (cnt > 0)
928 group_cnt += cnt;
929 }
930
931 return group_cnt;
932}
933
934static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
935{
936 struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
937 struct device_node *np = sprd_pctl->dev->of_node;
938 struct device_node *child, *sub_child;
939 struct sprd_pin_group *grp;
940 const char **temp;
941 int ret;
942
943 if (!np)
944 return -ENODEV;
945
946 info->ngroups = sprd_pinctrl_get_groups(np);
947 if (!info->ngroups)
948 return 0;
949
a86854d0
KC		 950 info->groups = devm_kcalloc(sprd_pctl->dev,
951 info->ngroups,
41d32cfc
BW		 952 sizeof(struct sprd_pin_group),
953 GFP_KERNEL);
954 if (!info->groups)
955 return -ENOMEM;
956
a86854d0
KC		 957 info->grp_names = devm_kcalloc(sprd_pctl->dev,
958 info->ngroups, sizeof(char *),
41d32cfc
BW		 959 GFP_KERNEL);
960 if (!info->grp_names)
961 return -ENOMEM;
962
963 temp = info->grp_names;
964 grp = info->groups;
965
966 for_each_child_of_node(np, child) {
967 ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
5a6bc290
ND		 968 if (ret) {
969 of_node_put(child);
41d32cfc 970 return ret;
5a6bc290 971 }
41d32cfc
BW		 972
973 *temp++ = grp->name;
974 grp++;
975
976 if (of_get_child_count(child) > 0) {
977 for_each_child_of_node(child, sub_child) {
978 ret = sprd_pinctrl_parse_groups(sub_child,
979 sprd_pctl, grp);
5a6bc290
ND		 980 if (ret) {
981 of_node_put(sub_child);
982 of_node_put(child);
41d32cfc 983 return ret;
5a6bc290 984 }
41d32cfc
BW		 985
986 *temp++ = grp->name;
987 grp++;
988 }
989 }
990 }
991
992 return 0;
993}
994
995static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
996 struct sprd_pins_info *sprd_soc_pin_info,
997 int pins_cnt)
998{
999 struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
1000 unsigned int ctrl_pin = 0, com_pin = 0;
1001 struct sprd_pin *pin;
1002 int i;
1003
1004 info->npins = pins_cnt;
a86854d0
KC		 1005 info->pins = devm_kcalloc(sprd_pctl->dev,
1006 info->npins, sizeof(struct sprd_pin),
41d32cfc
BW		 1007 GFP_KERNEL);
1008 if (!info->pins)
1009 return -ENOMEM;
1010
1011 for (i = 0, pin = info->pins; i < info->npins; i++, pin++) {
1012 unsigned int reg;
1013
1014 pin->name = sprd_soc_pin_info[i].name;
1015 pin->type = sprd_soc_pin_info[i].type;
1016 pin->number = sprd_soc_pin_info[i].num;
1017 reg = sprd_soc_pin_info[i].reg;
1018 if (pin->type == GLOBAL_CTRL_PIN) {
1019 pin->reg = (unsigned long)sprd_pctl->base +
1020 PINCTRL_REG_LEN * reg;
1021 pin->bit_offset = sprd_soc_pin_info[i].bit_offset;
1022 pin->bit_width = sprd_soc_pin_info[i].bit_width;
1023 ctrl_pin++;
1024 } else if (pin->type == COMMON_PIN) {
1025 pin->reg = (unsigned long)sprd_pctl->base +
1026 PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
1027 (i - ctrl_pin);
1028 com_pin++;
1029 } else if (pin->type == MISC_PIN) {
1030 pin->reg = (unsigned long)sprd_pctl->base +
1031 PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
1032 (i - ctrl_pin - com_pin);
1033 }
1034 }
1035
1036 for (i = 0, pin = info->pins; i < info->npins; pin++, i++) {
1037 dev_dbg(sprd_pctl->dev, "pin name[%s-%d], type = %d, "
1038 "bit offset = %ld, bit width = %ld, reg = 0x%lx\n",
1039 pin->name, pin->number, pin->type,
1040 pin->bit_offset, pin->bit_width, pin->reg);
1041 }
1042
1043 return 0;
1044}
1045
1046int sprd_pinctrl_core_probe(struct platform_device *pdev,
1047 struct sprd_pins_info *sprd_soc_pin_info,
1048 int pins_cnt)
1049{
1050 struct sprd_pinctrl *sprd_pctl;
1051 struct sprd_pinctrl_soc_info *pinctrl_info;
1052 struct pinctrl_pin_desc *pin_desc;
41d32cfc
BW		 1053 int ret, i;
1054
1055 sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl),
1056 GFP_KERNEL);
1057 if (!sprd_pctl)
1058 return -ENOMEM;
1059
e89febc7 1060 sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0);
41d32cfc
BW		 1061 if (IS_ERR(sprd_pctl->base))
1062 return PTR_ERR(sprd_pctl->base);
1063
1064 pinctrl_info = devm_kzalloc(&pdev->dev,
1065 sizeof(struct sprd_pinctrl_soc_info),
1066 GFP_KERNEL);
1067 if (!pinctrl_info)
1068 return -ENOMEM;
1069
1070 sprd_pctl->info = pinctrl_info;
1071 sprd_pctl->dev = &pdev->dev;
1072 platform_set_drvdata(pdev, sprd_pctl);
1073
1074 ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt);
1075 if (ret) {
1076 dev_err(&pdev->dev, "fail to add pins information\n");
1077 return ret;
1078 }
1079
63e037bc
BW		 1080 ret = sprd_pinctrl_parse_dt(sprd_pctl);
1081 if (ret) {
1082 dev_err(&pdev->dev, "fail to parse dt properties\n");
1083 return ret;
1084 }
1085
a86854d0
KC		 1086 pin_desc = devm_kcalloc(&pdev->dev,
1087 pinctrl_info->npins,
41d32cfc
BW		 1088 sizeof(struct pinctrl_pin_desc),
1089 GFP_KERNEL);
1090 if (!pin_desc)
1091 return -ENOMEM;
1092
1093 for (i = 0; i < pinctrl_info->npins; i++) {
1094 pin_desc[i].number = pinctrl_info->pins[i].number;
1095 pin_desc[i].name = pinctrl_info->pins[i].name;
1096 pin_desc[i].drv_data = pinctrl_info;
1097 }
1098
1099 sprd_pinctrl_desc.pins = pin_desc;
1100 sprd_pinctrl_desc.name = dev_name(&pdev->dev);
1101 sprd_pinctrl_desc.npins = pinctrl_info->npins;
1102
1103 sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc,
1104 &pdev->dev, (void *)sprd_pctl);
1105 if (IS_ERR(sprd_pctl->pctl)) {
1106 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1107 return PTR_ERR(sprd_pctl->pctl);
1108 }
1109
41d32cfc
BW		 1110 return 0;
1111}
1df49cc8 1112EXPORT_SYMBOL_GPL(sprd_pinctrl_core_probe);
41d32cfc
BW		 1113
1114int sprd_pinctrl_remove(struct platform_device *pdev)
1115{
1116 struct sprd_pinctrl *sprd_pctl = platform_get_drvdata(pdev);
1117
1118 pinctrl_unregister(sprd_pctl->pctl);
1119 return 0;
1120}
1df49cc8 1121EXPORT_SYMBOL_GPL(sprd_pinctrl_remove);
41d32cfc
BW		 1122
1123void sprd_pinctrl_shutdown(struct platform_device *pdev)
1124{
41470c37 1125 struct pinctrl *pinctl;
41d32cfc
BW		 1126 struct pinctrl_state *state;
1127
41470c37
DC		 1128 pinctl = devm_pinctrl_get(&pdev->dev);
1129 if (IS_ERR(pinctl))
1130 return;
41d32cfc 1131 state = pinctrl_lookup_state(pinctl, "shutdown");
41470c37
DC		 1132 if (IS_ERR(state))
1133 return;
1134 pinctrl_select_state(pinctl, state);
41d32cfc 1135}
1df49cc8 1136EXPORT_SYMBOL_GPL(sprd_pinctrl_shutdown);
41d32cfc
BW		 1137
1138MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver");
1139MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
1140MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)