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3370dc91 BS |
1 | /* |
2 | * pinmux driver for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/init.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/irq.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/irqdomain.h> | |
17 | #include <linux/irqchip/chained_irq.h> | |
18 | #include <linux/pinctrl/pinctrl.h> | |
19 | #include <linux/pinctrl/pinmux.h> | |
20 | #include <linux/pinctrl/consumer.h> | |
21 | #include <linux/pinctrl/machine.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_device.h> | |
25 | #include <linux/of_platform.h> | |
26 | #include <linux/bitops.h> | |
27 | #include <linux/gpio.h> | |
28 | #include <linux/of_gpio.h> | |
29 | #include <asm/mach/irq.h> | |
30 | ||
31 | #include "pinctrl-sirf.h" | |
32 | ||
33 | #define DRIVER_NAME "pinmux-sirf" | |
34 | ||
35 | struct sirfsoc_gpio_bank { | |
36 | struct of_mm_gpio_chip chip; | |
37 | struct irq_domain *domain; | |
38 | int id; | |
39 | int parent_irq; | |
40 | spinlock_t lock; | |
41 | bool is_marco; /* for marco, some registers are different with prima2 */ | |
42 | }; | |
43 | ||
44 | static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; | |
45 | static DEFINE_SPINLOCK(sgpio_lock); | |
46 | ||
47 | static struct sirfsoc_pin_group *sirfsoc_pin_groups; | |
48 | static int sirfsoc_pingrp_cnt; | |
49 | ||
50 | static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) | |
51 | { | |
52 | return sirfsoc_pingrp_cnt; | |
53 | } | |
54 | ||
55 | static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, | |
56 | unsigned selector) | |
57 | { | |
58 | return sirfsoc_pin_groups[selector].name; | |
59 | } | |
60 | ||
61 | static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
62 | const unsigned **pins, | |
63 | unsigned *num_pins) | |
64 | { | |
65 | *pins = sirfsoc_pin_groups[selector].pins; | |
66 | *num_pins = sirfsoc_pin_groups[selector].num_pins; | |
67 | return 0; | |
68 | } | |
69 | ||
70 | static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
71 | unsigned offset) | |
72 | { | |
73 | seq_printf(s, " " DRIVER_NAME); | |
74 | } | |
75 | ||
76 | static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, | |
77 | struct device_node *np_config, | |
78 | struct pinctrl_map **map, unsigned *num_maps) | |
79 | { | |
80 | struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); | |
81 | struct device_node *np; | |
82 | struct property *prop; | |
83 | const char *function, *group; | |
84 | int ret, index = 0, count = 0; | |
85 | ||
86 | /* calculate number of maps required */ | |
87 | for_each_child_of_node(np_config, np) { | |
88 | ret = of_property_read_string(np, "sirf,function", &function); | |
89 | if (ret < 0) | |
90 | return ret; | |
91 | ||
92 | ret = of_property_count_strings(np, "sirf,pins"); | |
93 | if (ret < 0) | |
94 | return ret; | |
95 | ||
96 | count += ret; | |
97 | } | |
98 | ||
99 | if (!count) { | |
100 | dev_err(spmx->dev, "No child nodes passed via DT\n"); | |
101 | return -ENODEV; | |
102 | } | |
103 | ||
104 | *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); | |
105 | if (!*map) | |
106 | return -ENOMEM; | |
107 | ||
108 | for_each_child_of_node(np_config, np) { | |
109 | of_property_read_string(np, "sirf,function", &function); | |
110 | of_property_for_each_string(np, "sirf,pins", prop, group) { | |
111 | (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; | |
112 | (*map)[index].data.mux.group = group; | |
113 | (*map)[index].data.mux.function = function; | |
114 | index++; | |
115 | } | |
116 | } | |
117 | ||
118 | *num_maps = count; | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, | |
124 | struct pinctrl_map *map, unsigned num_maps) | |
125 | { | |
126 | kfree(map); | |
127 | } | |
128 | ||
129 | static struct pinctrl_ops sirfsoc_pctrl_ops = { | |
130 | .get_groups_count = sirfsoc_get_groups_count, | |
131 | .get_group_name = sirfsoc_get_group_name, | |
132 | .get_group_pins = sirfsoc_get_group_pins, | |
133 | .pin_dbg_show = sirfsoc_pin_dbg_show, | |
134 | .dt_node_to_map = sirfsoc_dt_node_to_map, | |
135 | .dt_free_map = sirfsoc_dt_free_map, | |
136 | }; | |
137 | ||
138 | static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; | |
139 | static int sirfsoc_pmxfunc_cnt; | |
140 | ||
141 | static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, | |
142 | bool enable) | |
143 | { | |
144 | int i; | |
145 | const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; | |
146 | const struct sirfsoc_muxmask *mask = mux->muxmask; | |
147 | ||
148 | for (i = 0; i < mux->muxmask_counts; i++) { | |
149 | u32 muxval; | |
150 | if (!spmx->is_marco) { | |
151 | muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
152 | if (enable) | |
153 | muxval = muxval & ~mask[i].mask; | |
154 | else | |
155 | muxval = muxval | mask[i].mask; | |
156 | writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
157 | } else { | |
158 | if (enable) | |
159 | writel(mask[i].mask, spmx->gpio_virtbase + | |
160 | SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group)); | |
161 | else | |
162 | writel(mask[i].mask, spmx->gpio_virtbase + | |
163 | SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
164 | } | |
165 | } | |
166 | ||
167 | if (mux->funcmask && enable) { | |
168 | u32 func_en_val; | |
169 | func_en_val = | |
170 | readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); | |
171 | func_en_val = | |
172 | (func_en_val & ~mux->funcmask) | (mux-> | |
173 | funcval); | |
174 | writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); | |
175 | } | |
176 | } | |
177 | ||
178 | static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, | |
179 | unsigned group) | |
180 | { | |
181 | struct sirfsoc_pmx *spmx; | |
182 | ||
183 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
184 | sirfsoc_pinmux_endisable(spmx, selector, true); | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
189 | static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector, | |
190 | unsigned group) | |
191 | { | |
192 | struct sirfsoc_pmx *spmx; | |
193 | ||
194 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
195 | sirfsoc_pinmux_endisable(spmx, selector, false); | |
196 | } | |
197 | ||
198 | static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) | |
199 | { | |
200 | return sirfsoc_pmxfunc_cnt; | |
201 | } | |
202 | ||
203 | static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, | |
204 | unsigned selector) | |
205 | { | |
206 | return sirfsoc_pmx_functions[selector].name; | |
207 | } | |
208 | ||
209 | static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
210 | const char * const **groups, | |
211 | unsigned * const num_groups) | |
212 | { | |
213 | *groups = sirfsoc_pmx_functions[selector].groups; | |
214 | *num_groups = sirfsoc_pmx_functions[selector].num_groups; | |
215 | return 0; | |
216 | } | |
217 | ||
218 | static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, | |
219 | struct pinctrl_gpio_range *range, unsigned offset) | |
220 | { | |
221 | struct sirfsoc_pmx *spmx; | |
222 | ||
223 | int group = range->id; | |
224 | ||
225 | u32 muxval; | |
226 | ||
227 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
228 | ||
229 | if (!spmx->is_marco) { | |
230 | muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); | |
231 | muxval = muxval | (1 << (offset - range->pin_base)); | |
232 | writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); | |
233 | } else { | |
234 | writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + | |
235 | SIRFSOC_GPIO_PAD_EN(group)); | |
236 | } | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
241 | static struct pinmux_ops sirfsoc_pinmux_ops = { | |
242 | .enable = sirfsoc_pinmux_enable, | |
243 | .disable = sirfsoc_pinmux_disable, | |
244 | .get_functions_count = sirfsoc_pinmux_get_funcs_count, | |
245 | .get_function_name = sirfsoc_pinmux_get_func_name, | |
246 | .get_function_groups = sirfsoc_pinmux_get_groups, | |
247 | .gpio_request_enable = sirfsoc_pinmux_request_gpio, | |
248 | }; | |
249 | ||
250 | static struct pinctrl_desc sirfsoc_pinmux_desc = { | |
251 | .name = DRIVER_NAME, | |
252 | .pctlops = &sirfsoc_pctrl_ops, | |
253 | .pmxops = &sirfsoc_pinmux_ops, | |
254 | .owner = THIS_MODULE, | |
255 | }; | |
256 | ||
257 | /* | |
258 | * Todo: bind irq_chip to every pinctrl_gpio_range | |
259 | */ | |
260 | static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = { | |
261 | { | |
262 | .name = "sirfsoc-gpio*", | |
263 | .id = 0, | |
264 | .base = 0, | |
265 | .pin_base = 0, | |
266 | .npins = 32, | |
267 | }, { | |
268 | .name = "sirfsoc-gpio*", | |
269 | .id = 1, | |
270 | .base = 32, | |
271 | .pin_base = 32, | |
272 | .npins = 32, | |
273 | }, { | |
274 | .name = "sirfsoc-gpio*", | |
275 | .id = 2, | |
276 | .base = 64, | |
277 | .pin_base = 64, | |
278 | .npins = 32, | |
279 | }, { | |
280 | .name = "sirfsoc-gpio*", | |
281 | .id = 3, | |
282 | .base = 96, | |
283 | .pin_base = 96, | |
284 | .npins = 19, | |
285 | }, | |
286 | }; | |
287 | ||
288 | static void __iomem *sirfsoc_rsc_of_iomap(void) | |
289 | { | |
290 | const struct of_device_id rsc_ids[] = { | |
291 | { .compatible = "sirf,prima2-rsc" }, | |
292 | { .compatible = "sirf,marco-rsc" }, | |
293 | {} | |
294 | }; | |
295 | struct device_node *np; | |
296 | ||
297 | np = of_find_matching_node(NULL, rsc_ids); | |
298 | if (!np) | |
299 | panic("unable to find compatible rsc node in dtb\n"); | |
300 | ||
301 | return of_iomap(np, 0); | |
302 | } | |
303 | ||
304 | static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, | |
305 | const struct of_phandle_args *gpiospec, | |
306 | u32 *flags) | |
307 | { | |
308 | if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) | |
9c956909 | 309 | return -EINVAL; |
3370dc91 BS |
310 | |
311 | if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc) | |
9c956909 | 312 | return -EINVAL; |
3370dc91 BS |
313 | |
314 | if (flags) | |
9c956909 | 315 | *flags = gpiospec->args[1]; |
3370dc91 BS |
316 | |
317 | return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE; | |
318 | } | |
319 | ||
320 | static const struct of_device_id pinmux_ids[] = { | |
321 | { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, | |
322 | { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, | |
323 | { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, }, | |
324 | {} | |
325 | }; | |
326 | ||
327 | static int sirfsoc_pinmux_probe(struct platform_device *pdev) | |
328 | { | |
329 | int ret; | |
330 | struct sirfsoc_pmx *spmx; | |
331 | struct device_node *np = pdev->dev.of_node; | |
332 | const struct sirfsoc_pinctrl_data *pdata; | |
333 | int i; | |
334 | ||
335 | /* Create state holders etc for this driver */ | |
336 | spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); | |
337 | if (!spmx) | |
338 | return -ENOMEM; | |
339 | ||
340 | spmx->dev = &pdev->dev; | |
341 | ||
342 | platform_set_drvdata(pdev, spmx); | |
343 | ||
344 | spmx->gpio_virtbase = of_iomap(np, 0); | |
345 | if (!spmx->gpio_virtbase) { | |
346 | dev_err(&pdev->dev, "can't map gpio registers\n"); | |
347 | return -ENOMEM; | |
348 | } | |
349 | ||
350 | spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); | |
351 | if (!spmx->rsc_virtbase) { | |
352 | ret = -ENOMEM; | |
353 | dev_err(&pdev->dev, "can't map rsc registers\n"); | |
354 | goto out_no_rsc_remap; | |
355 | } | |
356 | ||
357 | if (of_device_is_compatible(np, "sirf,marco-pinctrl")) | |
358 | spmx->is_marco = 1; | |
359 | ||
360 | pdata = of_match_node(pinmux_ids, np)->data; | |
361 | sirfsoc_pin_groups = pdata->grps; | |
362 | sirfsoc_pingrp_cnt = pdata->grps_cnt; | |
363 | sirfsoc_pmx_functions = pdata->funcs; | |
364 | sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; | |
365 | sirfsoc_pinmux_desc.pins = pdata->pads; | |
366 | sirfsoc_pinmux_desc.npins = pdata->pads_cnt; | |
367 | ||
368 | ||
369 | /* Now register the pin controller and all pins it handles */ | |
370 | spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); | |
371 | if (!spmx->pmx) { | |
372 | dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); | |
373 | ret = -EINVAL; | |
374 | goto out_no_pmx; | |
375 | } | |
376 | ||
377 | for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) { | |
378 | sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc; | |
379 | pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]); | |
380 | } | |
381 | ||
382 | dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); | |
383 | ||
384 | return 0; | |
385 | ||
386 | out_no_pmx: | |
387 | iounmap(spmx->rsc_virtbase); | |
388 | out_no_rsc_remap: | |
389 | iounmap(spmx->gpio_virtbase); | |
390 | return ret; | |
391 | } | |
392 | ||
bc8d25a4 BS |
393 | #ifdef CONFIG_PM_SLEEP |
394 | static int sirfsoc_pinmux_suspend_noirq(struct device *dev) | |
395 | { | |
396 | int i, j; | |
397 | struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); | |
398 | ||
399 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
400 | for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { | |
401 | spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + | |
402 | SIRFSOC_GPIO_CTRL(i, j)); | |
403 | } | |
404 | spmx->ints_regs[i] = readl(spmx->gpio_virtbase + | |
405 | SIRFSOC_GPIO_INT_STATUS(i)); | |
406 | spmx->paden_regs[i] = readl(spmx->gpio_virtbase + | |
407 | SIRFSOC_GPIO_PAD_EN(i)); | |
408 | } | |
409 | spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); | |
410 | ||
411 | for (i = 0; i < 3; i++) | |
412 | spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static int sirfsoc_pinmux_resume_noirq(struct device *dev) | |
418 | { | |
419 | int i, j; | |
420 | struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); | |
421 | ||
422 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
423 | for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { | |
424 | writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + | |
425 | SIRFSOC_GPIO_CTRL(i, j)); | |
426 | } | |
427 | writel(spmx->ints_regs[i], spmx->gpio_virtbase + | |
428 | SIRFSOC_GPIO_INT_STATUS(i)); | |
429 | writel(spmx->paden_regs[i], spmx->gpio_virtbase + | |
430 | SIRFSOC_GPIO_PAD_EN(i)); | |
431 | } | |
432 | writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); | |
433 | ||
434 | for (i = 0; i < 3; i++) | |
435 | writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { | |
441 | .suspend_noirq = sirfsoc_pinmux_suspend_noirq, | |
442 | .resume_noirq = sirfsoc_pinmux_resume_noirq, | |
f6b17885 BS |
443 | .freeze_noirq = sirfsoc_pinmux_suspend_noirq, |
444 | .restore_noirq = sirfsoc_pinmux_resume_noirq, | |
bc8d25a4 BS |
445 | }; |
446 | #endif | |
447 | ||
3370dc91 BS |
448 | static struct platform_driver sirfsoc_pinmux_driver = { |
449 | .driver = { | |
450 | .name = DRIVER_NAME, | |
451 | .owner = THIS_MODULE, | |
452 | .of_match_table = pinmux_ids, | |
bc8d25a4 BS |
453 | #ifdef CONFIG_PM_SLEEP |
454 | .pm = &sirfsoc_pinmux_pm_ops, | |
455 | #endif | |
3370dc91 BS |
456 | }, |
457 | .probe = sirfsoc_pinmux_probe, | |
458 | }; | |
459 | ||
460 | static int __init sirfsoc_pinmux_init(void) | |
461 | { | |
462 | return platform_driver_register(&sirfsoc_pinmux_driver); | |
463 | } | |
464 | arch_initcall(sirfsoc_pinmux_init); | |
465 | ||
466 | static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
467 | { | |
468 | struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), | |
469 | struct sirfsoc_gpio_bank, chip); | |
470 | ||
471 | return irq_create_mapping(bank->domain, offset); | |
472 | } | |
473 | ||
474 | static inline int sirfsoc_gpio_to_offset(unsigned int gpio) | |
475 | { | |
476 | return gpio % SIRFSOC_GPIO_BANK_SIZE; | |
477 | } | |
478 | ||
479 | static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio) | |
480 | { | |
481 | return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; | |
482 | } | |
483 | ||
484 | static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip) | |
485 | { | |
486 | return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip); | |
487 | } | |
488 | ||
489 | static void sirfsoc_gpio_irq_ack(struct irq_data *d) | |
490 | { | |
491 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
492 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
493 | u32 val, offset; | |
494 | unsigned long flags; | |
495 | ||
496 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
497 | ||
498 | spin_lock_irqsave(&sgpio_lock, flags); | |
499 | ||
500 | val = readl(bank->chip.regs + offset); | |
501 | ||
502 | writel(val, bank->chip.regs + offset); | |
503 | ||
504 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
505 | } | |
506 | ||
507 | static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx) | |
508 | { | |
509 | u32 val, offset; | |
510 | unsigned long flags; | |
511 | ||
512 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
513 | ||
514 | spin_lock_irqsave(&sgpio_lock, flags); | |
515 | ||
516 | val = readl(bank->chip.regs + offset); | |
517 | val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
518 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
519 | writel(val, bank->chip.regs + offset); | |
520 | ||
521 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
522 | } | |
523 | ||
524 | static void sirfsoc_gpio_irq_mask(struct irq_data *d) | |
525 | { | |
526 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
527 | ||
528 | __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); | |
529 | } | |
530 | ||
531 | static void sirfsoc_gpio_irq_unmask(struct irq_data *d) | |
532 | { | |
533 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
534 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
535 | u32 val, offset; | |
536 | unsigned long flags; | |
537 | ||
538 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
539 | ||
540 | spin_lock_irqsave(&sgpio_lock, flags); | |
541 | ||
542 | val = readl(bank->chip.regs + offset); | |
543 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
544 | val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
545 | writel(val, bank->chip.regs + offset); | |
546 | ||
547 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
548 | } | |
549 | ||
550 | static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) | |
551 | { | |
552 | struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
553 | int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE; | |
554 | u32 val, offset; | |
555 | unsigned long flags; | |
556 | ||
557 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
558 | ||
559 | spin_lock_irqsave(&sgpio_lock, flags); | |
560 | ||
561 | val = readl(bank->chip.regs + offset); | |
562 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
563 | ||
564 | switch (type) { | |
565 | case IRQ_TYPE_NONE: | |
566 | break; | |
567 | case IRQ_TYPE_EDGE_RISING: | |
568 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
569 | val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; | |
570 | break; | |
571 | case IRQ_TYPE_EDGE_FALLING: | |
572 | val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
573 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
574 | break; | |
575 | case IRQ_TYPE_EDGE_BOTH: | |
576 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | | |
577 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
578 | break; | |
579 | case IRQ_TYPE_LEVEL_LOW: | |
580 | val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
581 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; | |
582 | break; | |
583 | case IRQ_TYPE_LEVEL_HIGH: | |
584 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
585 | val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
586 | break; | |
587 | } | |
588 | ||
589 | writel(val, bank->chip.regs + offset); | |
590 | ||
591 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static struct irq_chip sirfsoc_irq_chip = { | |
597 | .name = "sirf-gpio-irq", | |
598 | .irq_ack = sirfsoc_gpio_irq_ack, | |
599 | .irq_mask = sirfsoc_gpio_irq_mask, | |
600 | .irq_unmask = sirfsoc_gpio_irq_unmask, | |
601 | .irq_set_type = sirfsoc_gpio_irq_type, | |
602 | }; | |
603 | ||
604 | static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) | |
605 | { | |
606 | struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); | |
607 | u32 status, ctrl; | |
608 | int idx = 0; | |
609 | struct irq_chip *chip = irq_get_chip(irq); | |
610 | ||
611 | chained_irq_enter(chip, desc); | |
612 | ||
613 | status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); | |
614 | if (!status) { | |
615 | printk(KERN_WARNING | |
616 | "%s: gpio id %d status %#x no interrupt is flaged\n", | |
617 | __func__, bank->id, status); | |
618 | handle_bad_irq(irq, desc); | |
619 | return; | |
620 | } | |
621 | ||
622 | while (status) { | |
623 | ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); | |
624 | ||
625 | /* | |
626 | * Here we must check whether the corresponding GPIO's interrupt | |
627 | * has been enabled, otherwise just skip it | |
628 | */ | |
629 | if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { | |
630 | pr_debug("%s: gpio id %d idx %d happens\n", | |
631 | __func__, bank->id, idx); | |
632 | generic_handle_irq(irq_find_mapping(bank->domain, idx)); | |
633 | } | |
634 | ||
635 | idx++; | |
636 | status = status >> 1; | |
637 | } | |
638 | ||
639 | chained_irq_exit(chip, desc); | |
640 | } | |
641 | ||
642 | static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset) | |
643 | { | |
644 | u32 val; | |
645 | ||
646 | val = readl(bank->chip.regs + ctrl_offset); | |
647 | val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; | |
648 | writel(val, bank->chip.regs + ctrl_offset); | |
649 | } | |
650 | ||
651 | static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) | |
652 | { | |
653 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
654 | unsigned long flags; | |
655 | ||
656 | if (pinctrl_request_gpio(chip->base + offset)) | |
657 | return -ENODEV; | |
658 | ||
659 | spin_lock_irqsave(&bank->lock, flags); | |
660 | ||
661 | /* | |
662 | * default status: | |
663 | * set direction as input and mask irq | |
664 | */ | |
665 | sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
666 | __sirfsoc_gpio_irq_mask(bank, offset); | |
667 | ||
668 | spin_unlock_irqrestore(&bank->lock, flags); | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) | |
674 | { | |
675 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
676 | unsigned long flags; | |
677 | ||
678 | spin_lock_irqsave(&bank->lock, flags); | |
679 | ||
680 | __sirfsoc_gpio_irq_mask(bank, offset); | |
681 | sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
682 | ||
683 | spin_unlock_irqrestore(&bank->lock, flags); | |
684 | ||
685 | pinctrl_free_gpio(chip->base + offset); | |
686 | } | |
687 | ||
688 | static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
689 | { | |
690 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
691 | int idx = sirfsoc_gpio_to_offset(gpio); | |
692 | unsigned long flags; | |
693 | unsigned offset; | |
694 | ||
695 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
696 | ||
697 | spin_lock_irqsave(&bank->lock, flags); | |
698 | ||
699 | sirfsoc_gpio_set_input(bank, offset); | |
700 | ||
701 | spin_unlock_irqrestore(&bank->lock, flags); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset, | |
707 | int value) | |
708 | { | |
709 | u32 out_ctrl; | |
710 | unsigned long flags; | |
711 | ||
712 | spin_lock_irqsave(&bank->lock, flags); | |
713 | ||
714 | out_ctrl = readl(bank->chip.regs + offset); | |
715 | if (value) | |
716 | out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
717 | else | |
718 | out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
719 | ||
720 | out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
721 | out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; | |
722 | writel(out_ctrl, bank->chip.regs + offset); | |
723 | ||
724 | spin_unlock_irqrestore(&bank->lock, flags); | |
725 | } | |
726 | ||
727 | static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) | |
728 | { | |
729 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
730 | int idx = sirfsoc_gpio_to_offset(gpio); | |
731 | u32 offset; | |
732 | unsigned long flags; | |
733 | ||
734 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
735 | ||
736 | spin_lock_irqsave(&sgpio_lock, flags); | |
737 | ||
738 | sirfsoc_gpio_set_output(bank, offset, value); | |
739 | ||
740 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
745 | static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) | |
746 | { | |
747 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
748 | u32 val; | |
749 | unsigned long flags; | |
750 | ||
751 | spin_lock_irqsave(&bank->lock, flags); | |
752 | ||
753 | val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
754 | ||
755 | spin_unlock_irqrestore(&bank->lock, flags); | |
756 | ||
757 | return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); | |
758 | } | |
759 | ||
760 | static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, | |
761 | int value) | |
762 | { | |
763 | struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip); | |
764 | u32 ctrl; | |
765 | unsigned long flags; | |
766 | ||
767 | spin_lock_irqsave(&bank->lock, flags); | |
768 | ||
769 | ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
770 | if (value) | |
771 | ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
772 | else | |
773 | ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
774 | writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
775 | ||
776 | spin_unlock_irqrestore(&bank->lock, flags); | |
777 | } | |
778 | ||
779 | static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
780 | irq_hw_number_t hwirq) | |
781 | { | |
782 | struct sirfsoc_gpio_bank *bank = d->host_data; | |
783 | ||
784 | if (!bank) | |
785 | return -EINVAL; | |
786 | ||
787 | irq_set_chip(irq, &sirfsoc_irq_chip); | |
788 | irq_set_handler(irq, handle_level_irq); | |
789 | irq_set_chip_data(irq, bank); | |
790 | set_irq_flags(irq, IRQF_VALID); | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = { | |
796 | .map = sirfsoc_gpio_irq_map, | |
797 | .xlate = irq_domain_xlate_twocell, | |
798 | }; | |
799 | ||
800 | static void sirfsoc_gpio_set_pullup(const u32 *pullups) | |
801 | { | |
802 | int i, n; | |
803 | const unsigned long *p = (const unsigned long *)pullups; | |
804 | ||
805 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
806 | for_each_set_bit(n, p + i, BITS_PER_LONG) { | |
807 | u32 offset = SIRFSOC_GPIO_CTRL(i, n); | |
808 | u32 val = readl(sgpio_bank[i].chip.regs + offset); | |
809 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; | |
810 | val |= SIRFSOC_GPIO_CTL_PULL_HIGH; | |
811 | writel(val, sgpio_bank[i].chip.regs + offset); | |
812 | } | |
813 | } | |
814 | } | |
815 | ||
816 | static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns) | |
817 | { | |
818 | int i, n; | |
819 | const unsigned long *p = (const unsigned long *)pulldowns; | |
820 | ||
821 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
822 | for_each_set_bit(n, p + i, BITS_PER_LONG) { | |
823 | u32 offset = SIRFSOC_GPIO_CTRL(i, n); | |
824 | u32 val = readl(sgpio_bank[i].chip.regs + offset); | |
825 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; | |
826 | val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; | |
827 | writel(val, sgpio_bank[i].chip.regs + offset); | |
828 | } | |
829 | } | |
830 | } | |
831 | ||
832 | static int sirfsoc_gpio_probe(struct device_node *np) | |
833 | { | |
834 | int i, err = 0; | |
835 | struct sirfsoc_gpio_bank *bank; | |
2c9fdcf1 | 836 | void __iomem *regs; |
3370dc91 BS |
837 | struct platform_device *pdev; |
838 | bool is_marco = false; | |
839 | ||
840 | u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; | |
841 | ||
842 | pdev = of_find_device_by_node(np); | |
843 | if (!pdev) | |
844 | return -ENODEV; | |
845 | ||
846 | regs = of_iomap(np, 0); | |
847 | if (!regs) | |
848 | return -ENOMEM; | |
849 | ||
850 | if (of_device_is_compatible(np, "sirf,marco-pinctrl")) | |
851 | is_marco = 1; | |
852 | ||
853 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
854 | bank = &sgpio_bank[i]; | |
855 | spin_lock_init(&bank->lock); | |
856 | bank->chip.gc.request = sirfsoc_gpio_request; | |
857 | bank->chip.gc.free = sirfsoc_gpio_free; | |
858 | bank->chip.gc.direction_input = sirfsoc_gpio_direction_input; | |
859 | bank->chip.gc.get = sirfsoc_gpio_get_value; | |
860 | bank->chip.gc.direction_output = sirfsoc_gpio_direction_output; | |
861 | bank->chip.gc.set = sirfsoc_gpio_set_value; | |
862 | bank->chip.gc.to_irq = sirfsoc_gpio_to_irq; | |
863 | bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE; | |
864 | bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE; | |
865 | bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); | |
866 | bank->chip.gc.of_node = np; | |
867 | bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; | |
868 | bank->chip.gc.of_gpio_n_cells = 2; | |
869 | bank->chip.regs = regs; | |
870 | bank->id = i; | |
871 | bank->is_marco = is_marco; | |
872 | bank->parent_irq = platform_get_irq(pdev, i); | |
873 | if (bank->parent_irq < 0) { | |
874 | err = bank->parent_irq; | |
875 | goto out; | |
876 | } | |
877 | ||
878 | err = gpiochip_add(&bank->chip.gc); | |
879 | if (err) { | |
880 | pr_err("%s: error in probe function with status %d\n", | |
881 | np->full_name, err); | |
882 | goto out; | |
883 | } | |
884 | ||
885 | bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE, | |
886 | &sirfsoc_gpio_irq_simple_ops, bank); | |
887 | ||
888 | if (!bank->domain) { | |
889 | pr_err("%s: Failed to create irqdomain\n", np->full_name); | |
890 | err = -ENOSYS; | |
891 | goto out; | |
892 | } | |
893 | ||
894 | irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq); | |
895 | irq_set_handler_data(bank->parent_irq, bank); | |
896 | } | |
897 | ||
898 | if (!of_property_read_u32_array(np, "sirf,pullups", pullups, | |
899 | SIRFSOC_GPIO_NO_OF_BANKS)) | |
900 | sirfsoc_gpio_set_pullup(pullups); | |
901 | ||
902 | if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, | |
903 | SIRFSOC_GPIO_NO_OF_BANKS)) | |
904 | sirfsoc_gpio_set_pulldown(pulldowns); | |
905 | ||
906 | return 0; | |
907 | ||
908 | out: | |
909 | iounmap(regs); | |
910 | return err; | |
911 | } | |
912 | ||
913 | static int __init sirfsoc_gpio_init(void) | |
914 | { | |
915 | ||
916 | struct device_node *np; | |
917 | ||
918 | np = of_find_matching_node(NULL, pinmux_ids); | |
919 | ||
920 | if (!np) | |
921 | return -ENODEV; | |
922 | ||
923 | return sirfsoc_gpio_probe(np); | |
924 | } | |
925 | subsys_initcall(sirfsoc_gpio_init); | |
926 | ||
927 | MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " | |
928 | "Yuping Luo <yuping.luo@csr.com>, " | |
929 | "Barry Song <baohua.song@csr.com>"); | |
930 | MODULE_DESCRIPTION("SIRFSOC pin control driver"); | |
931 | MODULE_LICENSE("GPL"); |