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pinctrl: sh-pfc: r8a77995: Add MSIOF pins, groups and functions
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / pfc-r8a77995.c
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TK		 1/*
2 * R8A77995 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
16
17#include <linux/kernel.h>
18
19#include "core.h"
20#include "sh_pfc.h"
21
22#define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_9(0, fn, sfx), \
24 PORT_GP_32(1, fn, sfx), \
25 PORT_GP_32(2, fn, sfx), \
56d57391 26 PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
794a6711
TK		 27 PORT_GP_32(4, fn, sfx), \
28 PORT_GP_21(5, fn, sfx), \
29 PORT_GP_14(6, fn, sfx)
30
31/*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36/* GPSR0 */
37#define GPSR0_8 F_(MLB_SIG, IP0_27_24)
38#define GPSR0_7 F_(MLB_DAT, IP0_23_20)
39#define GPSR0_6 F_(MLB_CLK, IP0_19_16)
40#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
41#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
42#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
43#define GPSR0_2 F_(IRQ0_A, IP0_3_0)
44#define GPSR0_1 FM(USB0_OVC)
45#define GPSR0_0 FM(USB0_PWEN)
46
47/* GPSR1 */
48#define GPSR1_31 F_(QPOLB, IP4_27_24)
49#define GPSR1_30 F_(QPOLA, IP4_23_20)
50#define GPSR1_29 F_(DU_CDE, IP4_19_16)
51#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
52#define GPSR1_27 F_(DU_DISP, IP4_11_8)
53#define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
54#define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
55#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
56#define GPSR1_23 F_(DU_DR7, IP3_27_24)
57#define GPSR1_22 F_(DU_DR6, IP3_23_20)
58#define GPSR1_21 F_(DU_DR5, IP3_19_16)
59#define GPSR1_20 F_(DU_DR4, IP3_15_12)
60#define GPSR1_19 F_(DU_DR3, IP3_11_8)
61#define GPSR1_18 F_(DU_DR2, IP3_7_4)
62#define GPSR1_17 F_(DU_DR1, IP3_3_0)
63#define GPSR1_16 F_(DU_DR0, IP2_31_28)
64#define GPSR1_15 F_(DU_DG7, IP2_27_24)
65#define GPSR1_14 F_(DU_DG6, IP2_23_20)
66#define GPSR1_13 F_(DU_DG5, IP2_19_16)
67#define GPSR1_12 F_(DU_DG4, IP2_15_12)
68#define GPSR1_11 F_(DU_DG3, IP2_11_8)
69#define GPSR1_10 F_(DU_DG2, IP2_7_4)
70#define GPSR1_9 F_(DU_DG1, IP2_3_0)
71#define GPSR1_8 F_(DU_DG0, IP1_31_28)
72#define GPSR1_7 F_(DU_DB7, IP1_27_24)
73#define GPSR1_6 F_(DU_DB6, IP1_23_20)
74#define GPSR1_5 F_(DU_DB5, IP1_19_16)
75#define GPSR1_4 F_(DU_DB4, IP1_15_12)
76#define GPSR1_3 F_(DU_DB3, IP1_11_8)
77#define GPSR1_2 F_(DU_DB2, IP1_7_4)
78#define GPSR1_1 F_(DU_DB1, IP1_3_0)
79#define GPSR1_0 F_(DU_DB0, IP0_31_28)
80
81/* GPSR2 */
82#define GPSR2_31 F_(NFCE_N, IP8_19_16)
83#define GPSR2_30 F_(NFCLE, IP8_15_12)
84#define GPSR2_29 F_(NFALE, IP8_11_8)
85#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
86#define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
87#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
88#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
89#define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
90#define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
91#define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
92#define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
93#define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
94#define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
95#define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
96#define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
97#define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
98#define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
99#define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
100#define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
101#define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
102#define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
103#define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
104#define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
105#define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
106#define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
107#define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
108#define GPSR2_5 FM(VI4_DATA4)
109#define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
110#define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
111#define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
112#define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
113#define GPSR2_0 FM(VI4_CLK)
114
115/* GPSR3 */
116#define GPSR3_9 F_(NFDATA7, IP9_31_28)
117#define GPSR3_8 F_(NFDATA6, IP9_27_24)
118#define GPSR3_7 F_(NFDATA5, IP9_23_20)
119#define GPSR3_6 F_(NFDATA4, IP9_19_16)
120#define GPSR3_5 F_(NFDATA3, IP9_15_12)
121#define GPSR3_4 F_(NFDATA2, IP9_11_8)
122#define GPSR3_3 F_(NFDATA1, IP9_7_4)
123#define GPSR3_2 F_(NFDATA0, IP9_3_0)
124#define GPSR3_1 F_(NFWE_N, IP8_31_28)
125#define GPSR3_0 F_(NFRE_N, IP8_27_24)
126
127/* GPSR4 */
128#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
129#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
130#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
131#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
132#define GPSR4_27 FM(TX2)
133#define GPSR4_26 FM(RX2)
134#define GPSR4_25 F_(SCK2, IP12_11_8)
135#define GPSR4_24 F_(TX1_A, IP12_7_4)
136#define GPSR4_23 F_(RX1_A, IP12_3_0)
137#define GPSR4_22 F_(SCK1_A, IP11_31_28)
138#define GPSR4_21 F_(TX0_A, IP11_27_24)
139#define GPSR4_20 F_(RX0_A, IP11_23_20)
140#define GPSR4_19 F_(SCK0_A, IP11_19_16)
141#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
142#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
143#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
144#define GPSR4_15 FM(MSIOF0_RXD)
145#define GPSR4_14 FM(MSIOF0_TXD)
146#define GPSR4_13 FM(MSIOF0_SYNC)
147#define GPSR4_12 FM(MSIOF0_SCK)
148#define GPSR4_11 F_(SDA1, IP11_3_0)
149#define GPSR4_10 F_(SCL1, IP10_31_28)
150#define GPSR4_9 FM(SDA0)
151#define GPSR4_8 FM(SCL0)
152#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
153#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
154#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
155#define GPSR4_4 F_(SSI_WS34, IP10_15_12)
156#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
157#define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
158#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
159#define GPSR4_0 F_(NFRB_N, IP8_23_20)
160
161/* GPSR5 */
162#define GPSR5_20 FM(AVB0_LINK)
163#define GPSR5_19 FM(AVB0_PHY_INT)
164#define GPSR5_18 FM(AVB0_MAGIC)
165#define GPSR5_17 FM(AVB0_MDC)
166#define GPSR5_16 FM(AVB0_MDIO)
167#define GPSR5_15 FM(AVB0_TXCREFCLK)
168#define GPSR5_14 FM(AVB0_TD3)
169#define GPSR5_13 FM(AVB0_TD2)
170#define GPSR5_12 FM(AVB0_TD1)
171#define GPSR5_11 FM(AVB0_TD0)
172#define GPSR5_10 FM(AVB0_TXC)
173#define GPSR5_9 FM(AVB0_TX_CTL)
174#define GPSR5_8 FM(AVB0_RD3)
175#define GPSR5_7 FM(AVB0_RD2)
176#define GPSR5_6 FM(AVB0_RD1)
177#define GPSR5_5 FM(AVB0_RD0)
178#define GPSR5_4 FM(AVB0_RXC)
179#define GPSR5_3 FM(AVB0_RX_CTL)
180#define GPSR5_2 F_(CAN_CLK, IP12_23_20)
181#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
182#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
183
184/* GPSR6 */
185#define GPSR6_13 FM(RPC_INT_N)
186#define GPSR6_12 FM(RPC_RESET_N)
187#define GPSR6_11 FM(QSPI1_SSL)
188#define GPSR6_10 FM(QSPI1_IO3)
189#define GPSR6_9 FM(QSPI1_IO2)
190#define GPSR6_8 FM(QSPI1_MISO_IO1)
191#define GPSR6_7 FM(QSPI1_MOSI_IO0)
192#define GPSR6_6 FM(QSPI1_SPCLK)
193#define GPSR6_5 FM(QSPI0_SSL)
194#define GPSR6_4 FM(QSPI0_IO3)
195#define GPSR6_3 FM(QSPI0_IO2)
196#define GPSR6_2 FM(QSPI0_MISO_IO1)
197#define GPSR6_1 FM(QSPI0_MOSI_IO0)
198#define GPSR6_0 FM(QSPI0_SPCLK)
199
200/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
d8ee17f4
GU		 201#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 203#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233
234/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
235#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267
268/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
269#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301
302/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
303#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313
314#define PINMUX_GPSR \
315\
316 GPSR1_31 GPSR2_31 GPSR4_31 \
317 GPSR1_30 GPSR2_30 GPSR4_30 \
318 GPSR1_29 GPSR2_29 GPSR4_29 \
319 GPSR1_28 GPSR2_28 GPSR4_28 \
320 GPSR1_27 GPSR2_27 GPSR4_27 \
321 GPSR1_26 GPSR2_26 GPSR4_26 \
322 GPSR1_25 GPSR2_25 GPSR4_25 \
323 GPSR1_24 GPSR2_24 GPSR4_24 \
324 GPSR1_23 GPSR2_23 GPSR4_23 \
325 GPSR1_22 GPSR2_22 GPSR4_22 \
326 GPSR1_21 GPSR2_21 GPSR4_21 \
327 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
328 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
329 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
330 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
331 GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
332 GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
333 GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
334 GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
335 GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
336 GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
337 GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
338 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
339GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
340GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
341GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
342GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
343GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
344GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
345GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
346GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
347GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
348
349#define PINMUX_IPSR \
350\
351FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
352FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
353FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
354FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
355FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
356FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
357FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
358FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
359\
360FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
361FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
362FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
363FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
364FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
365FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
366FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
367FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
368\
369FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
370FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
371FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
372FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
373FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
374FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
375FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
376FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
377\
378FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
379FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
380FM(IP12_11_8) IP12_11_8 \
381FM(IP12_15_12) IP12_15_12 \
382FM(IP12_19_16) IP12_19_16 \
383FM(IP12_23_20) IP12_23_20 \
384FM(IP12_27_24) IP12_27_24 \
385FM(IP12_31_28) IP12_31_28 \
386
387/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
388#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
389#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
390#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
391#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
392#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
393#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
394#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
395#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
396#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
397#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
398#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
399#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
400#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
401#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
402#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
403#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
404#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
405#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
406#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
407#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
408#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
409#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
410
411#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
412#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
413#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
414#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
415#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
416#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
417
418
419#define PINMUX_MOD_SELS \
420\
421 MOD_SEL1_31 \
422MOD_SEL0_30 MOD_SEL1_30 \
423MOD_SEL0_29 MOD_SEL1_29 \
424MOD_SEL0_28 MOD_SEL1_28 \
425MOD_SEL0_27 MOD_SEL1_27 \
426MOD_SEL0_26 MOD_SEL1_26 \
427MOD_SEL0_25 \
428MOD_SEL0_24_23 \
429MOD_SEL0_22_21 \
430MOD_SEL0_20_19 \
431MOD_SEL0_18_17 \
432MOD_SEL0_15 \
433MOD_SEL0_14 \
434MOD_SEL0_13 \
435MOD_SEL0_12 \
436MOD_SEL0_11 \
437MOD_SEL0_10 \
438MOD_SEL0_5 \
439MOD_SEL0_4 \
440MOD_SEL0_3 \
441MOD_SEL0_2 \
442MOD_SEL0_1 \
443MOD_SEL0_0
444
445enum {
446 PINMUX_RESERVED = 0,
447
448 PINMUX_DATA_BEGIN,
449 GP_ALL(DATA),
450 PINMUX_DATA_END,
451
452#define F_(x, y)
453#define FM(x) FN_##x,
454 PINMUX_FUNCTION_BEGIN,
455 GP_ALL(FN),
456 PINMUX_GPSR
457 PINMUX_IPSR
458 PINMUX_MOD_SELS
459 PINMUX_FUNCTION_END,
460#undef F_
461#undef FM
462
463#define F_(x, y)
464#define FM(x) x##_MARK,
465 PINMUX_MARK_BEGIN,
466 PINMUX_GPSR
467 PINMUX_IPSR
468 PINMUX_MOD_SELS
469 PINMUX_MARK_END,
470#undef F_
471#undef FM
472};
473
474#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
475 PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
476
477#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
478 PINMUX_DATA(fn##_MARK, FN_##msel)
479
480static const u16 pinmux_data[] = {
481 PINMUX_DATA_GP_ALL(),
482
483 PINMUX_SINGLE(USB0_OVC),
484 PINMUX_SINGLE(USB0_PWEN),
485 PINMUX_SINGLE(VI4_DATA4),
486 PINMUX_SINGLE(VI4_CLK),
487 PINMUX_SINGLE(TX2),
488 PINMUX_SINGLE(RX2),
489 PINMUX_SINGLE(AVB0_LINK),
490 PINMUX_SINGLE(AVB0_PHY_INT),
491 PINMUX_SINGLE(AVB0_MAGIC),
492 PINMUX_SINGLE(AVB0_MDC),
493 PINMUX_SINGLE(AVB0_MDIO),
494 PINMUX_SINGLE(AVB0_TXCREFCLK),
495 PINMUX_SINGLE(AVB0_TD3),
496 PINMUX_SINGLE(AVB0_TD2),
497 PINMUX_SINGLE(AVB0_TD1),
498 PINMUX_SINGLE(AVB0_TD0),
499 PINMUX_SINGLE(AVB0_TXC),
500 PINMUX_SINGLE(AVB0_TX_CTL),
501 PINMUX_SINGLE(AVB0_RD3),
502 PINMUX_SINGLE(AVB0_RD2),
503 PINMUX_SINGLE(AVB0_RD1),
504 PINMUX_SINGLE(AVB0_RD0),
505 PINMUX_SINGLE(AVB0_RXC),
506 PINMUX_SINGLE(AVB0_RX_CTL),
507 PINMUX_SINGLE(RPC_INT_N),
508 PINMUX_SINGLE(RPC_RESET_N),
509 PINMUX_SINGLE(QSPI1_SSL),
510 PINMUX_SINGLE(QSPI1_IO3),
511 PINMUX_SINGLE(QSPI1_IO2),
512 PINMUX_SINGLE(QSPI1_MISO_IO1),
513 PINMUX_SINGLE(QSPI1_MOSI_IO0),
514 PINMUX_SINGLE(QSPI1_SPCLK),
515 PINMUX_SINGLE(QSPI0_SSL),
516 PINMUX_SINGLE(QSPI0_IO3),
517 PINMUX_SINGLE(QSPI0_IO2),
518 PINMUX_SINGLE(QSPI0_MISO_IO1),
519 PINMUX_SINGLE(QSPI0_MOSI_IO0),
520 PINMUX_SINGLE(QSPI0_SPCLK),
af4b609e
UH		 521 PINMUX_SINGLE(SCL0),
522 PINMUX_SINGLE(SDA0),
2ef7a12f
TK		 523 PINMUX_SINGLE(MSIOF0_RXD),
524 PINMUX_SINGLE(MSIOF0_TXD),
525 PINMUX_SINGLE(MSIOF0_SYNC),
526 PINMUX_SINGLE(MSIOF0_SCK),
794a6711
TK		 527
528 /* IPSR0 */
529 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
530 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
794a6711
TK		 531
532 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
794a6711
TK		 533
534 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
535 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
536
537 PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
538 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
539
540 PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
541 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
542 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
543
544 PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
545 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
546 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
547 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
548
549 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
550 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
551 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
552 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
553
554 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
555 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
556 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
557
558 /* IPSR1 */
559 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
560 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
561 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
562
563 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
564 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
565 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
566
567 PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
568 PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
569 PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
570
571 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
572 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
573 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
574
575 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
576 PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
577 PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
578
579 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
580 PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
581 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
582
583 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
584 PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
585 PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
586
587 PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
588 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
589 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
590
591 /* IPSR2 */
592 PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
593 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
594 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
595
596 PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
597 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
598
599 PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
600 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
601 PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
602
603 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
604 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
605 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
606
607 PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
608 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
609 PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
610
611 PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
612 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
613 PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
614
615 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
616 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
617 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
618
619 PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
620 PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
621 PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
622
623 /* IPSR3 */
624 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
625 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
626 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
627
628 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
629 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
630 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
631
632 PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
633 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
634 PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
635
636 PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
637 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
638 PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
639
640 PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
641 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
642 PINMUX_IPSR_GPSR(IP3_19_16, NMI),
643
644 PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
645 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
646 PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
647
648 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
649 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
650 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
651
652 PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
653 PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
654
655 /* IPSR4 */
656 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
657 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
658 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
659
660 PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
661 PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
662 PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
663
664 PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
665 PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
666 PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
667
668 PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
669 PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
670 PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
671 PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
672
673 PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
674 PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
675 PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
676
677 PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
678 PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
679
680 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
681 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
682
683 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
684 PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
685
686 /* IPSR5 */
687 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
688 PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
689
690 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
691 PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
692
693 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
694 PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
695
696 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
697 PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
698
699 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
700 PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
701
702 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
703 PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
704
705 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
706
707 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
708 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
709 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
710
711 /* IPSR6 */
712 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
713 PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
714
715 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
716 PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
717
718 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
719 PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
720
721 PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
722 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
723 PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
724
725 PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
726 PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
727 PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
728
729 PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
730 PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
731
732 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
733 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
734
735 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
736 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
737
738 /* IPSR7 */
739 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
740 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
741
742 PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
743 PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
744 PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
745
746 PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
747 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
748 PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
749
750 PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
751 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
752
753 PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
754 PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
755 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
756
757 PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
758 PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
759 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
760
761 PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
762
763 PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
764 PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
765 PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
766
767 PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
768 PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
769 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
770
771 /* IPSR8 */
772 PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
773 PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
774 PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
775 PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
776 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
777
778 PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
779 PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
780 PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
781 PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
782
783 PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
784 PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
785 PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
786 PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
787
788 PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
789 PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
790 PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
791 PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
792
793 PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
794 PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
795 PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
796
797 PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
798 PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
799 PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
800
801 PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
802 PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
803
804 PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
805 PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
806
807 /* IPSR9 */
808 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
809 PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
810
811 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
812 PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
813
814 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
815 PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
816
817 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
818 PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
819
820 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
821 PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
822
823 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
824 PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
825
826 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
827 PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
828
829 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
830 PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
831
832 /* IPSR10 */
833 PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
834 PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
835
836 PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
837 PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
838
839 PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
840 PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
841
842 PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
843 PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
844
845 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
846 PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
847 PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
848 PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
849 PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
850
851 PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
852 PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
853 PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
854 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
855
856 PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
857 PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
858 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
859 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
860
861 PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
862 PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
863
864 /* IPSR11 */
865 PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
866 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
867
868 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
869 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
870
871 PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
872 PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
873
874 PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
875 PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
876
877 PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
878 PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
879 PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
880
881 PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
882 PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
883 PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
884
885 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
886 PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
887 PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
888
889 PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
890 PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
891 PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
892 PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
893 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
894
895 /* IPSR12 */
896 PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
897 PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
898 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
899
900 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
901 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
902 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
903
904 PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
905 PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
906 PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
907
908 PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
909 PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
910 PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
911
912 PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
913 PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
914 PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
915
916 PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
917 PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
918 PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
919 PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
920
921 PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
922 PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
923 PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
924
925 PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
926 PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
927 PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
928
929 /* IPSR13 */
930 PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
931 PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
932 PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
933
934 PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
935 PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
936 PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
937};
938
939static const struct sh_pfc_pin pinmux_pins[] = {
940 PINMUX_GPIO_GP_ALL(),
941};
942
6e7b1ee8
KM		 943/* - AUDIO CLOCK ------------------------------------------------------------- */
944static const unsigned int audio_clk_a_pins[] = {
945 /* CLK A */
946 RCAR_GP_PIN(4, 1),
947};
948static const unsigned int audio_clk_a_mux[] = {
949 AUDIO_CLKA_MARK,
950};
951static const unsigned int audio_clk_b_pins[] = {
952 /* CLK B */
953 RCAR_GP_PIN(2, 27),
954};
955static const unsigned int audio_clk_b_mux[] = {
956 AUDIO_CLKB_MARK,
957};
958static const unsigned int audio_clkout_pins[] = {
959 /* CLKOUT */
960 RCAR_GP_PIN(4, 5),
961};
962static const unsigned int audio_clkout_mux[] = {
963 AUDIO_CLKOUT_MARK,
964};
965static const unsigned int audio_clkout1_pins[] = {
966 /* CLKOUT1 */
967 RCAR_GP_PIN(4, 22),
968};
969static const unsigned int audio_clkout1_mux[] = {
970 AUDIO_CLKOUT1_MARK,
971};
972
66abd968
YS		 973/* - EtherAVB --------------------------------------------------------------- */
974static const unsigned int avb0_link_pins[] = {
975 /* AVB0_LINK */
976 RCAR_GP_PIN(5, 20),
977};
978static const unsigned int avb0_link_mux[] = {
979 AVB0_LINK_MARK,
980};
981static const unsigned int avb0_magic_pins[] = {
982 /* AVB0_MAGIC */
983 RCAR_GP_PIN(5, 18),
984};
985static const unsigned int avb0_magic_mux[] = {
986 AVB0_MAGIC_MARK,
987};
988static const unsigned int avb0_phy_int_pins[] = {
989 /* AVB0_PHY_INT */
990 RCAR_GP_PIN(5, 19),
991};
992static const unsigned int avb0_phy_int_mux[] = {
993 AVB0_PHY_INT_MARK,
994};
3b047a95 995static const unsigned int avb0_mdio_pins[] = {
66abd968
YS		 996 /* AVB0_MDC, AVB0_MDIO */
997 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
998};
3b047a95 999static const unsigned int avb0_mdio_mux[] = {
66abd968
YS		 1000 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1001};
1002static const unsigned int avb0_mii_pins[] = {
1003 /*
1004 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
1005 * AVB0_TD1, AVB0_TD2, AVB0_TD3,
1006 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
1007 * AVB0_RD1, AVB0_RD2, AVB0_RD3,
1008 * AVB0_TXCREFCLK
1009 */
1010 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1011 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1012 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1013 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1014 RCAR_GP_PIN(5, 15),
1015};
1016static const unsigned int avb0_mii_mux[] = {
1017 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
1018 AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1019 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
1020 AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1021 AVB0_TXCREFCLK_MARK,
1022};
1023static const unsigned int avb0_avtp_pps_a_pins[] = {
1024 /* AVB0_AVTP_PPS_A */
1025 RCAR_GP_PIN(5, 2),
1026};
1027static const unsigned int avb0_avtp_pps_a_mux[] = {
1028 AVB0_AVTP_PPS_A_MARK,
1029};
1030static const unsigned int avb0_avtp_match_a_pins[] = {
1031 /* AVB0_AVTP_MATCH_A */
1032 RCAR_GP_PIN(5, 1),
1033};
1034static const unsigned int avb0_avtp_match_a_mux[] = {
1035 AVB0_AVTP_MATCH_A_MARK,
1036};
1037static const unsigned int avb0_avtp_capture_a_pins[] = {
1038 /* AVB0_AVTP_CAPTURE_A */
1039 RCAR_GP_PIN(5, 0),
1040};
1041static const unsigned int avb0_avtp_capture_a_mux[] = {
1042 AVB0_AVTP_CAPTURE_A_MARK,
1043};
1044static const unsigned int avb0_avtp_pps_b_pins[] = {
1045 /* AVB0_AVTP_PPS_B */
1046 RCAR_GP_PIN(4, 16),
1047};
1048static const unsigned int avb0_avtp_pps_b_mux[] = {
1049 AVB0_AVTP_PPS_B_MARK,
1050};
1051static const unsigned int avb0_avtp_match_b_pins[] = {
1052 /* AVB0_AVTP_MATCH_B */
1053 RCAR_GP_PIN(4, 18),
1054};
1055static const unsigned int avb0_avtp_match_b_mux[] = {
1056 AVB0_AVTP_MATCH_B_MARK,
1057};
1058static const unsigned int avb0_avtp_capture_b_pins[] = {
1059 /* AVB0_AVTP_CAPTURE_B */
1060 RCAR_GP_PIN(4, 17),
1061};
1062static const unsigned int avb0_avtp_capture_b_mux[] = {
1063 AVB0_AVTP_CAPTURE_B_MARK,
1064};
1065
c45985d3
UH		 1066/* - CAN ------------------------------------------------------------------ */
1067static const unsigned int can0_data_a_pins[] = {
1068 /* TX, RX */
1069 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1070};
1071static const unsigned int can0_data_a_mux[] = {
1072 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1073};
1074static const unsigned int can0_data_b_pins[] = {
1075 /* TX, RX */
1076 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
1077};
1078static const unsigned int can0_data_b_mux[] = {
1079 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1080};
1081static const unsigned int can1_data_a_pins[] = {
1082 /* TX, RX */
1083 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1084};
1085static const unsigned int can1_data_a_mux[] = {
1086 CAN1_TX_A_MARK, CAN1_RX_A_MARK,
1087};
1088static const unsigned int can1_data_b_pins[] = {
1089 /* TX, RX */
1090 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
1091};
1092static const unsigned int can1_data_b_mux[] = {
1093 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1094};
1095
1096/* - CAN Clock -------------------------------------------------------------- */
1097static const unsigned int can_clk_pins[] = {
1098 /* CLK */
1099 RCAR_GP_PIN(5, 2),
1100};
1101static const unsigned int can_clk_mux[] = {
1102 CAN_CLK_MARK,
1103};
1104
527890f7
UH		 1105/* - CAN FD ----------------------------------------------------------------- */
1106static const unsigned int canfd0_data_pins[] = {
1107 /* TX, RX */
1108 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1109};
1110static const unsigned int canfd0_data_mux[] = {
1111 CANFD0_TX_MARK, CANFD0_RX_MARK,
1112};
1113static const unsigned int canfd1_data_pins[] = {
1114 /* TX, RX */
1115 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1116};
1117static const unsigned int canfd1_data_mux[] = {
1118 CANFD1_TX_MARK, CANFD1_RX_MARK,
1119};
1120
65a90f04
UH		 1121/* - DU --------------------------------------------------------------------- */
1122static const unsigned int du_rgb666_pins[] = {
1123 /* R[7:2], G[7:2], B[7:2] */
1124 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1125 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1126 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1127 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1128 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1129 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1130};
1131static const unsigned int du_rgb666_mux[] = {
1132 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1133 DU_DR3_MARK, DU_DR2_MARK,
1134 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1135 DU_DG3_MARK, DU_DG2_MARK,
1136 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1137 DU_DB3_MARK, DU_DB2_MARK,
1138};
1139static const unsigned int du_rgb888_pins[] = {
1140 /* R[7:0], G[7:0], B[7:0] */
1141 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1142 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1143 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1144 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1145 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1146 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1147 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1148 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1149 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1150};
1151static const unsigned int du_rgb888_mux[] = {
1152 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1153 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1154 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1155 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1156 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1157 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1158};
1159static const unsigned int du_clk_in_1_pins[] = {
1160 /* CLKIN */
1161 RCAR_GP_PIN(1, 28),
1162};
1163static const unsigned int du_clk_in_1_mux[] = {
1164 DU_DOTCLKIN1_MARK
1165};
1166static const unsigned int du_clk_out_0_pins[] = {
1167 /* CLKOUT */
1168 RCAR_GP_PIN(1, 24),
1169};
1170static const unsigned int du_clk_out_0_mux[] = {
1171 DU_DOTCLKOUT0_MARK
1172};
1173static const unsigned int du_sync_pins[] = {
1174 /* VSYNC, HSYNC */
1175 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1176};
1177static const unsigned int du_sync_mux[] = {
1178 DU_VSYNC_MARK, DU_HSYNC_MARK
1179};
1180static const unsigned int du_disp_cde_pins[] = {
1181 /* DISP_CDE */
1182 RCAR_GP_PIN(1, 28),
1183};
1184static const unsigned int du_disp_cde_mux[] = {
1185 DU_DISP_CDE_MARK,
1186};
1187static const unsigned int du_cde_pins[] = {
1188 /* CDE */
1189 RCAR_GP_PIN(1, 29),
1190};
1191static const unsigned int du_cde_mux[] = {
1192 DU_CDE_MARK,
1193};
1194static const unsigned int du_disp_pins[] = {
1195 /* DISP */
1196 RCAR_GP_PIN(1, 27),
1197};
1198static const unsigned int du_disp_mux[] = {
1199 DU_DISP_MARK,
1200};
1201
e8c6b9ec
TK		 1202/* - I2C -------------------------------------------------------------------- */
1203static const unsigned int i2c0_pins[] = {
1204 /* SCL, SDA */
1205 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1206};
1207static const unsigned int i2c0_mux[] = {
1208 SCL0_MARK, SDA0_MARK,
1209};
1210static const unsigned int i2c1_pins[] = {
1211 /* SCL, SDA */
1212 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1213};
1214static const unsigned int i2c1_mux[] = {
1215 SCL1_MARK, SDA1_MARK,
1216};
1217static const unsigned int i2c2_a_pins[] = {
1218 /* SCL, SDA */
1219 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1220};
1221static const unsigned int i2c2_a_mux[] = {
1222 SCL2_A_MARK, SDA2_A_MARK,
1223};
1224static const unsigned int i2c2_b_pins[] = {
1225 /* SCL, SDA */
1226 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
1227};
1228static const unsigned int i2c2_b_mux[] = {
1229 SCL2_B_MARK, SDA2_B_MARK,
1230};
1231static const unsigned int i2c3_a_pins[] = {
1232 /* SCL, SDA */
1233 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1234};
1235static const unsigned int i2c3_a_mux[] = {
1236 SCL3_A_MARK, SDA3_A_MARK,
1237};
1238static const unsigned int i2c3_b_pins[] = {
1239 /* SCL, SDA */
1240 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1241};
1242static const unsigned int i2c3_b_mux[] = {
1243 SCL3_B_MARK, SDA3_B_MARK,
1244};
1245
4e5a70ff
TK		 1246/* - MMC ------------------------------------------------------------------- */
1247static const unsigned int mmc_data1_pins[] = {
1248 /* D0 */
1249 RCAR_GP_PIN(3, 2),
1250};
1251static const unsigned int mmc_data1_mux[] = {
1252 MMC_D0_MARK,
1253};
1254static const unsigned int mmc_data4_pins[] = {
1255 /* D[0:3] */
1256 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1257 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1258};
1259static const unsigned int mmc_data4_mux[] = {
1260 MMC_D0_MARK, MMC_D1_MARK,
1261 MMC_D2_MARK, MMC_D3_MARK,
1262};
1263static const unsigned int mmc_data8_pins[] = {
1264 /* D[0:7] */
1265 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1266 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1267 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1268 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1269};
1270static const unsigned int mmc_data8_mux[] = {
1271 MMC_D0_MARK, MMC_D1_MARK,
1272 MMC_D2_MARK, MMC_D3_MARK,
1273 MMC_D4_MARK, MMC_D5_MARK,
1274 MMC_D6_MARK, MMC_D7_MARK,
1275};
1276static const unsigned int mmc_ctrl_pins[] = {
1277 /* CLK, CMD */
1278 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1279};
1280static const unsigned int mmc_ctrl_mux[] = {
1281 MMC_CLK_MARK, MMC_CMD_MARK,
1282};
1283
2ef7a12f
TK		 1284/* - MSIOF0 ----------------------------------------------------------------- */
1285static const unsigned int msiof0_clk_pins[] = {
1286 /* SCK */
1287 RCAR_GP_PIN(4, 12),
1288};
1289
1290static const unsigned int msiof0_clk_mux[] = {
1291 MSIOF0_SCK_MARK,
1292};
1293
1294static const unsigned int msiof0_sync_pins[] = {
1295 /* SYNC */
1296 RCAR_GP_PIN(4, 13),
1297};
1298
1299static const unsigned int msiof0_sync_mux[] = {
1300 MSIOF0_SYNC_MARK,
1301};
1302
1303static const unsigned int msiof0_ss1_pins[] = {
1304 /* SS1 */
1305 RCAR_GP_PIN(4, 20),
1306};
1307
1308static const unsigned int msiof0_ss1_mux[] = {
1309 MSIOF0_SS1_MARK,
1310};
1311
1312static const unsigned int msiof0_ss2_pins[] = {
1313 /* SS2 */
1314 RCAR_GP_PIN(4, 21),
1315};
1316
1317static const unsigned int msiof0_ss2_mux[] = {
1318 MSIOF0_SS2_MARK,
1319};
1320
1321static const unsigned int msiof0_txd_pins[] = {
1322 /* TXD */
1323 RCAR_GP_PIN(4, 14),
1324};
1325
1326static const unsigned int msiof0_txd_mux[] = {
1327 MSIOF0_TXD_MARK,
1328};
1329
1330static const unsigned int msiof0_rxd_pins[] = {
1331 /* RXD */
1332 RCAR_GP_PIN(4, 15),
1333};
1334
1335static const unsigned int msiof0_rxd_mux[] = {
1336 MSIOF0_RXD_MARK,
1337};
1338
1339/* - MSIOF1 ----------------------------------------------------------------- */
1340static const unsigned int msiof1_clk_pins[] = {
1341 /* SCK */
1342 RCAR_GP_PIN(4, 16),
1343};
1344
1345static const unsigned int msiof1_clk_mux[] = {
1346 MSIOF1_SCK_MARK,
1347};
1348
1349static const unsigned int msiof1_sync_pins[] = {
1350 /* SYNC */
1351 RCAR_GP_PIN(4, 19),
1352};
1353
1354static const unsigned int msiof1_sync_mux[] = {
1355 MSIOF1_SYNC_MARK,
1356};
1357
1358static const unsigned int msiof1_ss1_pins[] = {
1359 /* SS1 */
1360 RCAR_GP_PIN(4, 25),
1361};
1362
1363static const unsigned int msiof1_ss1_mux[] = {
1364 MSIOF1_SS1_MARK,
1365};
1366
1367static const unsigned int msiof1_ss2_pins[] = {
1368 /* SS2 */
1369 RCAR_GP_PIN(4, 22),
1370};
1371
1372static const unsigned int msiof1_ss2_mux[] = {
1373 MSIOF1_SS2_MARK,
1374};
1375
1376static const unsigned int msiof1_txd_pins[] = {
1377 /* TXD */
1378 RCAR_GP_PIN(4, 17),
1379};
1380
1381static const unsigned int msiof1_txd_mux[] = {
1382 MSIOF1_TXD_MARK,
1383};
1384
1385static const unsigned int msiof1_rxd_pins[] = {
1386 /* RXD */
1387 RCAR_GP_PIN(4, 18),
1388};
1389
1390static const unsigned int msiof1_rxd_mux[] = {
1391 MSIOF1_RXD_MARK,
1392};
1393
1394/* - MSIOF2 ----------------------------------------------------------------- */
1395static const unsigned int msiof2_clk_pins[] = {
1396 /* SCK */
1397 RCAR_GP_PIN(0, 3),
1398};
1399
1400static const unsigned int msiof2_clk_mux[] = {
1401 MSIOF2_SCK_MARK,
1402};
1403
1404static const unsigned int msiof2_sync_a_pins[] = {
1405 /* SYNC */
1406 RCAR_GP_PIN(0, 6),
1407};
1408
1409static const unsigned int msiof2_sync_a_mux[] = {
1410 MSIOF2_SYNC_A_MARK,
1411};
1412
1413static const unsigned int msiof2_sync_b_pins[] = {
1414 /* SYNC */
1415 RCAR_GP_PIN(0, 2),
1416};
1417
1418static const unsigned int msiof2_sync_b_mux[] = {
1419 MSIOF2_SYNC_B_MARK,
1420};
1421
1422static const unsigned int msiof2_ss1_pins[] = {
1423 /* SS1 */
1424 RCAR_GP_PIN(0, 7),
1425};
1426
1427static const unsigned int msiof2_ss1_mux[] = {
1428 MSIOF2_SS1_MARK,
1429};
1430
1431static const unsigned int msiof2_ss2_pins[] = {
1432 /* SS2 */
1433 RCAR_GP_PIN(0, 8),
1434};
1435
1436static const unsigned int msiof2_ss2_mux[] = {
1437 MSIOF2_SS2_MARK,
1438};
1439
1440static const unsigned int msiof2_txd_pins[] = {
1441 /* TXD */
1442 RCAR_GP_PIN(0, 4),
1443};
1444
1445static const unsigned int msiof2_txd_mux[] = {
1446 MSIOF2_TXD_MARK,
1447};
1448
1449static const unsigned int msiof2_rxd_pins[] = {
1450 /* RXD */
1451 RCAR_GP_PIN(0, 5),
1452};
1453
1454static const unsigned int msiof2_rxd_mux[] = {
1455 MSIOF2_RXD_MARK,
1456};
1457
1458/* - MSIOF3 ----------------------------------------------------------------- */
1459static const unsigned int msiof3_clk_a_pins[] = {
1460 /* SCK */
1461 RCAR_GP_PIN(2, 24),
1462};
1463
1464static const unsigned int msiof3_clk_a_mux[] = {
1465 MSIOF3_SCK_A_MARK,
1466};
1467
1468static const unsigned int msiof3_sync_a_pins[] = {
1469 /* SYNC */
1470 RCAR_GP_PIN(2, 21),
1471};
1472
1473static const unsigned int msiof3_sync_a_mux[] = {
1474 MSIOF3_SYNC_A_MARK,
1475};
1476
1477static const unsigned int msiof3_ss1_a_pins[] = {
1478 /* SS1 */
1479 RCAR_GP_PIN(2, 14),
1480};
1481
1482static const unsigned int msiof3_ss1_a_mux[] = {
1483 MSIOF3_SS1_A_MARK,
1484};
1485
1486static const unsigned int msiof3_ss2_a_pins[] = {
1487 /* SS2 */
1488 RCAR_GP_PIN(2, 10),
1489};
1490
1491static const unsigned int msiof3_ss2_a_mux[] = {
1492 MSIOF3_SS2_A_MARK,
1493};
1494
1495static const unsigned int msiof3_txd_a_pins[] = {
1496 /* TXD */
1497 RCAR_GP_PIN(2, 22),
1498};
1499
1500static const unsigned int msiof3_txd_a_mux[] = {
1501 MSIOF3_TXD_A_MARK,
1502};
1503
1504static const unsigned int msiof3_rxd_a_pins[] = {
1505 /* RXD */
1506 RCAR_GP_PIN(2, 23),
1507};
1508
1509static const unsigned int msiof3_rxd_a_mux[] = {
1510 MSIOF3_RXD_A_MARK,
1511};
1512
1513static const unsigned int msiof3_clk_b_pins[] = {
1514 /* SCK */
1515 RCAR_GP_PIN(1, 8),
1516};
1517
1518static const unsigned int msiof3_clk_b_mux[] = {
1519 MSIOF3_SCK_B_MARK,
1520};
1521
1522static const unsigned int msiof3_sync_b_pins[] = {
1523 /* SYNC */
1524 RCAR_GP_PIN(1, 9),
1525};
1526
1527static const unsigned int msiof3_sync_b_mux[] = {
1528 MSIOF3_SYNC_B_MARK,
1529};
1530
1531static const unsigned int msiof3_ss1_b_pins[] = {
1532 /* SS1 */
1533 RCAR_GP_PIN(1, 6),
1534};
1535
1536static const unsigned int msiof3_ss1_b_mux[] = {
1537 MSIOF3_SS1_B_MARK,
1538};
1539
1540static const unsigned int msiof3_ss2_b_pins[] = {
1541 /* SS2 */
1542 RCAR_GP_PIN(1, 7),
1543};
1544
1545static const unsigned int msiof3_ss2_b_mux[] = {
1546 MSIOF3_SS2_B_MARK,
1547};
1548
1549static const unsigned int msiof3_txd_b_pins[] = {
1550 /* TXD */
1551 RCAR_GP_PIN(1, 0),
1552};
1553
1554static const unsigned int msiof3_txd_b_mux[] = {
1555 MSIOF3_TXD_B_MARK,
1556};
1557
1558static const unsigned int msiof3_rxd_b_pins[] = {
1559 /* RXD */
1560 RCAR_GP_PIN(1, 1),
1561};
1562
1563static const unsigned int msiof3_rxd_b_mux[] = {
1564 MSIOF3_RXD_B_MARK,
1565};
1566
47bb1296
TK		 1567/* - PWM0 ------------------------------------------------------------------ */
1568static const unsigned int pwm0_a_pins[] = {
1569 /* PWM */
1570 RCAR_GP_PIN(2, 1),
1571};
1572
1573static const unsigned int pwm0_a_mux[] = {
1574 PWM0_A_MARK,
1575};
1576
1577static const unsigned int pwm0_b_pins[] = {
1578 /* PWM */
1579 RCAR_GP_PIN(1, 18),
1580};
1581
1582static const unsigned int pwm0_b_mux[] = {
1583 PWM0_B_MARK,
1584};
1585
1586static const unsigned int pwm0_c_pins[] = {
1587 /* PWM */
1588 RCAR_GP_PIN(2, 29),
1589};
1590
1591static const unsigned int pwm0_c_mux[] = {
1592 PWM0_C_MARK,
1593};
1594
1595/* - PWM1 ------------------------------------------------------------------ */
1596static const unsigned int pwm1_a_pins[] = {
1597 /* PWM */
1598 RCAR_GP_PIN(2, 2),
1599};
1600
1601static const unsigned int pwm1_a_mux[] = {
1602 PWM1_A_MARK,
1603};
1604
1605static const unsigned int pwm1_b_pins[] = {
1606 /* PWM */
1607 RCAR_GP_PIN(1, 19),
1608};
1609
1610static const unsigned int pwm1_b_mux[] = {
1611 PWM1_B_MARK,
1612};
1613
1614static const unsigned int pwm1_c_pins[] = {
1615 /* PWM */
1616 RCAR_GP_PIN(2, 30),
1617};
1618
1619static const unsigned int pwm1_c_mux[] = {
1620 PWM1_C_MARK,
1621};
1622
1623/* - PWM2 ------------------------------------------------------------------ */
1624static const unsigned int pwm2_a_pins[] = {
1625 /* PWM */
1626 RCAR_GP_PIN(2, 3),
1627};
1628
1629static const unsigned int pwm2_a_mux[] = {
1630 PWM2_A_MARK,
1631};
1632
1633static const unsigned int pwm2_b_pins[] = {
1634 /* PWM */
1635 RCAR_GP_PIN(1, 22),
1636};
1637
1638static const unsigned int pwm2_b_mux[] = {
1639 PWM2_B_MARK,
1640};
1641
1642static const unsigned int pwm2_c_pins[] = {
1643 /* PWM */
1644 RCAR_GP_PIN(2, 31),
1645};
1646
1647static const unsigned int pwm2_c_mux[] = {
1648 PWM2_C_MARK,
1649};
1650
1651/* - PWM3 ------------------------------------------------------------------ */
1652static const unsigned int pwm3_a_pins[] = {
1653 /* PWM */
1654 RCAR_GP_PIN(2, 4),
1655};
1656
1657static const unsigned int pwm3_a_mux[] = {
1658 PWM3_A_MARK,
1659};
1660
1661static const unsigned int pwm3_b_pins[] = {
1662 /* PWM */
1663 RCAR_GP_PIN(1, 27),
1664};
1665
1666static const unsigned int pwm3_b_mux[] = {
1667 PWM3_B_MARK,
1668};
1669
1670static const unsigned int pwm3_c_pins[] = {
1671 /* PWM */
1672 RCAR_GP_PIN(4, 0),
1673};
1674
1675static const unsigned int pwm3_c_mux[] = {
1676 PWM3_C_MARK,
1677};
1678
ab04393c
TK		 1679/* - SCIF0 ------------------------------------------------------------------ */
1680static const unsigned int scif0_data_a_pins[] = {
1681 /* RX, TX */
1682 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1683};
1684static const unsigned int scif0_data_a_mux[] = {
1685 RX0_A_MARK, TX0_A_MARK,
1686};
1687static const unsigned int scif0_clk_a_pins[] = {
1688 /* SCK */
1689 RCAR_GP_PIN(4, 19),
1690};
1691static const unsigned int scif0_clk_a_mux[] = {
1692 SCK0_A_MARK,
1693};
1694static const unsigned int scif0_data_b_pins[] = {
1695 /* RX, TX */
1696 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
1697};
1698static const unsigned int scif0_data_b_mux[] = {
1699 RX0_B_MARK, TX0_B_MARK,
1700};
1701static const unsigned int scif0_clk_b_pins[] = {
1702 /* SCK */
1703 RCAR_GP_PIN(5, 2),
1704};
1705static const unsigned int scif0_clk_b_mux[] = {
1706 SCK0_B_MARK,
1707};
1708static const unsigned int scif0_ctrl_pins[] = {
1709 /* RTS, CTS */
1710 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1711};
1712static const unsigned int scif0_ctrl_mux[] = {
1713 RTS0_N_TANS_MARK, CTS0_N_MARK,
1714};
1715/* - SCIF1 ------------------------------------------------------------------ */
1716static const unsigned int scif1_data_a_pins[] = {
1717 /* RX, TX */
1718 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
1719};
1720static const unsigned int scif1_data_a_mux[] = {
1721 RX1_A_MARK, TX1_A_MARK,
1722};
1723static const unsigned int scif1_clk_a_pins[] = {
1724 /* SCK */
1725 RCAR_GP_PIN(4, 22),
1726};
1727static const unsigned int scif1_clk_a_mux[] = {
1728 SCK1_A_MARK,
1729};
1730static const unsigned int scif1_data_b_pins[] = {
1731 /* RX, TX */
1732 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
1733};
1734static const unsigned int scif1_data_b_mux[] = {
1735 RX1_B_MARK, TX1_B_MARK,
1736};
1737static const unsigned int scif1_clk_b_pins[] = {
1738 /* SCK */
1739 RCAR_GP_PIN(2, 25),
1740};
1741static const unsigned int scif1_clk_b_mux[] = {
1742 SCK1_B_MARK,
1743};
1744static const unsigned int scif1_ctrl_pins[] = {
1745 /* RTS, CTS */
1746 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1747};
1748static const unsigned int scif1_ctrl_mux[] = {
1749 RTS1_N_TANS_MARK, CTS1_N_MARK,
1750};
1751
1752/* - SCIF2 ------------------------------------------------------------------ */
1753static const unsigned int scif2_data_pins[] = {
1754 /* RX, TX */
1755 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
1756};
1757static const unsigned int scif2_data_mux[] = {
1758 RX2_MARK, TX2_MARK,
1759};
1760static const unsigned int scif2_clk_pins[] = {
1761 /* SCK */
1762 RCAR_GP_PIN(4, 25),
1763};
1764static const unsigned int scif2_clk_mux[] = {
1765 SCK2_MARK,
1766};
1767/* - SCIF3 ------------------------------------------------------------------ */
1768static const unsigned int scif3_data_a_pins[] = {
1769 /* RX, TX */
1770 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
1771};
1772static const unsigned int scif3_data_a_mux[] = {
1773 RX3_A_MARK, TX3_A_MARK,
1774};
1775static const unsigned int scif3_clk_a_pins[] = {
1776 /* SCK */
1777 RCAR_GP_PIN(2, 30),
1778};
1779static const unsigned int scif3_clk_a_mux[] = {
1780 SCK3_A_MARK,
1781};
1782static const unsigned int scif3_data_b_pins[] = {
1783 /* RX, TX */
1784 RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
1785};
1786static const unsigned int scif3_data_b_mux[] = {
1787 RX3_B_MARK, TX3_B_MARK,
1788};
1789static const unsigned int scif3_clk_b_pins[] = {
1790 /* SCK */
1791 RCAR_GP_PIN(1, 29),
1792};
1793static const unsigned int scif3_clk_b_mux[] = {
1794 SCK3_B_MARK,
1795};
1796/* - SCIF4 ------------------------------------------------------------------ */
1797static const unsigned int scif4_data_a_pins[] = {
1798 /* RX, TX */
1799 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1800};
1801static const unsigned int scif4_data_a_mux[] = {
1802 RX4_A_MARK, TX4_A_MARK,
1803};
1804static const unsigned int scif4_clk_a_pins[] = {
1805 /* SCK */
1806 RCAR_GP_PIN(2, 6),
1807};
1808static const unsigned int scif4_clk_a_mux[] = {
1809 SCK4_A_MARK,
1810};
1811static const unsigned int scif4_data_b_pins[] = {
1812 /* RX, TX */
1813 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1814};
1815static const unsigned int scif4_data_b_mux[] = {
1816 RX4_B_MARK, TX4_B_MARK,
1817};
1818static const unsigned int scif4_clk_b_pins[] = {
1819 /* SCK */
1820 RCAR_GP_PIN(1, 15),
1821};
1822static const unsigned int scif4_clk_b_mux[] = {
1823 SCK4_B_MARK,
1824};
1825/* - SCIF5 ------------------------------------------------------------------ */
1826static const unsigned int scif5_data_a_pins[] = {
1827 /* RX, TX */
1828 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1829};
1830static const unsigned int scif5_data_a_mux[] = {
1831 RX5_A_MARK, TX5_A_MARK,
1832};
1833static const unsigned int scif5_clk_a_pins[] = {
1834 /* SCK */
1835 RCAR_GP_PIN(0, 6),
1836};
1837static const unsigned int scif5_clk_a_mux[] = {
1838 SCK5_A_MARK,
1839};
1840static const unsigned int scif5_data_b_pins[] = {
1841 /* RX, TX */
1842 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1843};
1844static const unsigned int scif5_data_b_mux[] = {
1845 RX5_B_MARK, TX5_B_MARK,
1846};
1847static const unsigned int scif5_clk_b_pins[] = {
1848 /* SCK */
1849 RCAR_GP_PIN(1, 3),
1850};
1851static const unsigned int scif5_clk_b_mux[] = {
1852 SCK5_B_MARK,
1853};
1854/* - SCIF Clock ------------------------------------------------------------- */
1855static const unsigned int scif_clk_pins[] = {
1856 /* SCIF_CLK */
1857 RCAR_GP_PIN(2, 27),
1858};
1859static const unsigned int scif_clk_mux[] = {
1860 SCIF_CLK_MARK,
1861};
1862
7b9e64a6
KM		 1863/* - SSI ---------------------------------------------------------------*/
1864static const unsigned int ssi3_data_pins[] = {
1865 /* SDATA */
1866 RCAR_GP_PIN(4, 3),
1867};
1868static const unsigned int ssi3_data_mux[] = {
1869 SSI_SDATA3_MARK,
1870};
1871static const unsigned int ssi34_ctrl_pins[] = {
1872 /* SCK, WS */
1873 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
1874};
1875static const unsigned int ssi34_ctrl_mux[] = {
1876 SSI_SCK34_MARK, SSI_WS34_MARK,
1877};
1878static const unsigned int ssi4_ctrl_a_pins[] = {
1879 /* SCK, WS */
1880 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1881};
1882static const unsigned int ssi4_ctrl_a_mux[] = {
1883 SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
1884};
1885static const unsigned int ssi4_data_a_pins[] = {
1886 /* SDATA */
1887 RCAR_GP_PIN(4, 6),
1888};
1889static const unsigned int ssi4_data_a_mux[] = {
1890 SSI_SDATA4_A_MARK,
1891};
1892static const unsigned int ssi4_ctrl_b_pins[] = {
1893 /* SCK, WS */
1894 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
1895};
1896static const unsigned int ssi4_ctrl_b_mux[] = {
1897 SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
1898};
1899static const unsigned int ssi4_data_b_pins[] = {
1900 /* SDATA */
1901 RCAR_GP_PIN(2, 16),
1902};
1903static const unsigned int ssi4_data_b_mux[] = {
1904 SSI_SDATA4_B_MARK,
1905};
1906
f814def5
TK		 1907/* - USB0 ------------------------------------------------------------------- */
1908static const unsigned int usb0_pins[] = {
1909 /* PWEN, OVC */
1910 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1911};
1912static const unsigned int usb0_mux[] = {
1913 USB0_PWEN_MARK, USB0_OVC_MARK,
1914};
1915
fbd452ae 1916/* - VIN4 ------------------------------------------------------------------- */
fbd452ae 1917static const unsigned int vin4_data18_pins[] = {
fbd452ae
UH		 1918 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1919 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1920 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
fbd452ae
UH		 1921 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1922 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1923 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4fd82963
UH		 1924 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1925 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1926 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
fbd452ae
UH		 1927};
1928static const unsigned int vin4_data18_mux[] = {
fbd452ae
UH		 1929 VI4_DATA2_MARK, VI4_DATA3_MARK,
1930 VI4_DATA4_MARK, VI4_DATA5_MARK,
1931 VI4_DATA6_MARK, VI4_DATA7_MARK,
fbd452ae
UH		 1932 VI4_DATA10_MARK, VI4_DATA11_MARK,
1933 VI4_DATA12_MARK, VI4_DATA13_MARK,
1934 VI4_DATA14_MARK, VI4_DATA15_MARK,
4fd82963
UH		 1935 VI4_DATA18_MARK, VI4_DATA19_MARK,
1936 VI4_DATA20_MARK, VI4_DATA21_MARK,
1937 VI4_DATA22_MARK, VI4_DATA23_MARK,
fbd452ae 1938};
a6fff41f
UH		 1939static const union vin_data vin4_data_pins = {
1940 .data24 = {
1941 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1942 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1943 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1944 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1945 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1946 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1947 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1948 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1949 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1950 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1951 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1952 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1953 },
1954};
1955static const union vin_data vin4_data_mux = {
1956 .data24 = {
1957 VI4_DATA0_MARK, VI4_DATA1_MARK,
1958 VI4_DATA2_MARK, VI4_DATA3_MARK,
1959 VI4_DATA4_MARK, VI4_DATA5_MARK,
1960 VI4_DATA6_MARK, VI4_DATA7_MARK,
1961 VI4_DATA8_MARK, VI4_DATA9_MARK,
1962 VI4_DATA10_MARK, VI4_DATA11_MARK,
1963 VI4_DATA12_MARK, VI4_DATA13_MARK,
1964 VI4_DATA14_MARK, VI4_DATA15_MARK,
1965 VI4_DATA16_MARK, VI4_DATA17_MARK,
1966 VI4_DATA18_MARK, VI4_DATA19_MARK,
1967 VI4_DATA20_MARK, VI4_DATA21_MARK,
1968 VI4_DATA22_MARK, VI4_DATA23_MARK,
1969 },
fbd452ae
UH		 1970};
1971static const unsigned int vin4_sync_pins[] = {
1972 /* HSYNC#, VSYNC# */
1973 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1974};
1975static const unsigned int vin4_sync_mux[] = {
1976 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1977};
1978static const unsigned int vin4_field_pins[] = {
1979 /* FIELD */
1980 RCAR_GP_PIN(2, 27),
1981};
1982static const unsigned int vin4_field_mux[] = {
1983 VI4_FIELD_MARK,
1984};
1985static const unsigned int vin4_clkenb_pins[] = {
1986 /* CLKENB */
1987 RCAR_GP_PIN(2, 28),
1988};
1989static const unsigned int vin4_clkenb_mux[] = {
1990 VI4_CLKENB_MARK,
1991};
1992static const unsigned int vin4_clk_pins[] = {
1993 /* CLK */
1994 RCAR_GP_PIN(2, 0),
1995};
1996static const unsigned int vin4_clk_mux[] = {
1997 VI4_CLK_MARK,
1998};
1999
794a6711 2000static const struct sh_pfc_pin_group pinmux_groups[] = {
6e7b1ee8
KM		 2001 SH_PFC_PIN_GROUP(audio_clk_a),
2002 SH_PFC_PIN_GROUP(audio_clk_b),
2003 SH_PFC_PIN_GROUP(audio_clkout),
2004 SH_PFC_PIN_GROUP(audio_clkout1),
66abd968
YS		 2005 SH_PFC_PIN_GROUP(avb0_link),
2006 SH_PFC_PIN_GROUP(avb0_magic),
2007 SH_PFC_PIN_GROUP(avb0_phy_int),
3b047a95
GU		 2008 SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
2009 SH_PFC_PIN_GROUP(avb0_mdio),
66abd968
YS		 2010 SH_PFC_PIN_GROUP(avb0_mii),
2011 SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
2012 SH_PFC_PIN_GROUP(avb0_avtp_match_a),
2013 SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
2014 SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
2015 SH_PFC_PIN_GROUP(avb0_avtp_match_b),
2016 SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
c45985d3
UH		 2017 SH_PFC_PIN_GROUP(can0_data_a),
2018 SH_PFC_PIN_GROUP(can0_data_b),
2019 SH_PFC_PIN_GROUP(can1_data_a),
2020 SH_PFC_PIN_GROUP(can1_data_b),
2021 SH_PFC_PIN_GROUP(can_clk),
527890f7
UH		 2022 SH_PFC_PIN_GROUP(canfd0_data),
2023 SH_PFC_PIN_GROUP(canfd1_data),
65a90f04
UH		 2024 SH_PFC_PIN_GROUP(du_rgb666),
2025 SH_PFC_PIN_GROUP(du_rgb888),
2026 SH_PFC_PIN_GROUP(du_clk_in_1),
2027 SH_PFC_PIN_GROUP(du_clk_out_0),
2028 SH_PFC_PIN_GROUP(du_sync),
2029 SH_PFC_PIN_GROUP(du_disp_cde),
2030 SH_PFC_PIN_GROUP(du_cde),
2031 SH_PFC_PIN_GROUP(du_disp),
e8c6b9ec
TK		 2032 SH_PFC_PIN_GROUP(i2c0),
2033 SH_PFC_PIN_GROUP(i2c1),
2034 SH_PFC_PIN_GROUP(i2c2_a),
2035 SH_PFC_PIN_GROUP(i2c2_b),
2036 SH_PFC_PIN_GROUP(i2c3_a),
2037 SH_PFC_PIN_GROUP(i2c3_b),
4e5a70ff
TK		 2038 SH_PFC_PIN_GROUP(mmc_data1),
2039 SH_PFC_PIN_GROUP(mmc_data4),
2040 SH_PFC_PIN_GROUP(mmc_data8),
2041 SH_PFC_PIN_GROUP(mmc_ctrl),
2ef7a12f
TK		 2042 SH_PFC_PIN_GROUP(msiof0_clk),
2043 SH_PFC_PIN_GROUP(msiof0_sync),
2044 SH_PFC_PIN_GROUP(msiof0_ss1),
2045 SH_PFC_PIN_GROUP(msiof0_ss2),
2046 SH_PFC_PIN_GROUP(msiof0_txd),
2047 SH_PFC_PIN_GROUP(msiof0_rxd),
2048 SH_PFC_PIN_GROUP(msiof1_clk),
2049 SH_PFC_PIN_GROUP(msiof1_sync),
2050 SH_PFC_PIN_GROUP(msiof1_ss1),
2051 SH_PFC_PIN_GROUP(msiof1_ss2),
2052 SH_PFC_PIN_GROUP(msiof1_txd),
2053 SH_PFC_PIN_GROUP(msiof1_rxd),
2054 SH_PFC_PIN_GROUP(msiof2_clk),
2055 SH_PFC_PIN_GROUP(msiof2_sync_a),
2056 SH_PFC_PIN_GROUP(msiof2_sync_b),
2057 SH_PFC_PIN_GROUP(msiof2_ss1),
2058 SH_PFC_PIN_GROUP(msiof2_ss2),
2059 SH_PFC_PIN_GROUP(msiof2_txd),
2060 SH_PFC_PIN_GROUP(msiof2_rxd),
2061 SH_PFC_PIN_GROUP(msiof3_clk_a),
2062 SH_PFC_PIN_GROUP(msiof3_sync_a),
2063 SH_PFC_PIN_GROUP(msiof3_ss1_a),
2064 SH_PFC_PIN_GROUP(msiof3_ss2_a),
2065 SH_PFC_PIN_GROUP(msiof3_txd_a),
2066 SH_PFC_PIN_GROUP(msiof3_rxd_a),
2067 SH_PFC_PIN_GROUP(msiof3_clk_b),
2068 SH_PFC_PIN_GROUP(msiof3_sync_b),
2069 SH_PFC_PIN_GROUP(msiof3_ss1_b),
2070 SH_PFC_PIN_GROUP(msiof3_ss2_b),
2071 SH_PFC_PIN_GROUP(msiof3_txd_b),
2072 SH_PFC_PIN_GROUP(msiof3_rxd_b),
47bb1296
TK		 2073 SH_PFC_PIN_GROUP(pwm0_a),
2074 SH_PFC_PIN_GROUP(pwm0_b),
2075 SH_PFC_PIN_GROUP(pwm0_c),
2076 SH_PFC_PIN_GROUP(pwm1_a),
2077 SH_PFC_PIN_GROUP(pwm1_b),
2078 SH_PFC_PIN_GROUP(pwm1_c),
2079 SH_PFC_PIN_GROUP(pwm2_a),
2080 SH_PFC_PIN_GROUP(pwm2_b),
2081 SH_PFC_PIN_GROUP(pwm2_c),
2082 SH_PFC_PIN_GROUP(pwm3_a),
2083 SH_PFC_PIN_GROUP(pwm3_b),
2084 SH_PFC_PIN_GROUP(pwm3_c),
ab04393c
TK		 2085 SH_PFC_PIN_GROUP(scif0_data_a),
2086 SH_PFC_PIN_GROUP(scif0_clk_a),
2087 SH_PFC_PIN_GROUP(scif0_data_b),
2088 SH_PFC_PIN_GROUP(scif0_clk_b),
2089 SH_PFC_PIN_GROUP(scif0_ctrl),
2090 SH_PFC_PIN_GROUP(scif1_data_a),
2091 SH_PFC_PIN_GROUP(scif1_clk_a),
2092 SH_PFC_PIN_GROUP(scif1_data_b),
2093 SH_PFC_PIN_GROUP(scif1_clk_b),
2094 SH_PFC_PIN_GROUP(scif1_ctrl),
2095 SH_PFC_PIN_GROUP(scif2_data),
2096 SH_PFC_PIN_GROUP(scif2_clk),
2097 SH_PFC_PIN_GROUP(scif3_data_a),
2098 SH_PFC_PIN_GROUP(scif3_clk_a),
2099 SH_PFC_PIN_GROUP(scif3_data_b),
2100 SH_PFC_PIN_GROUP(scif3_clk_b),
2101 SH_PFC_PIN_GROUP(scif4_data_a),
2102 SH_PFC_PIN_GROUP(scif4_clk_a),
2103 SH_PFC_PIN_GROUP(scif4_data_b),
2104 SH_PFC_PIN_GROUP(scif4_clk_b),
2105 SH_PFC_PIN_GROUP(scif5_data_a),
2106 SH_PFC_PIN_GROUP(scif5_clk_a),
2107 SH_PFC_PIN_GROUP(scif5_data_b),
2108 SH_PFC_PIN_GROUP(scif5_clk_b),
2109 SH_PFC_PIN_GROUP(scif_clk),
7b9e64a6
KM		 2110 SH_PFC_PIN_GROUP(ssi3_data),
2111 SH_PFC_PIN_GROUP(ssi34_ctrl),
2112 SH_PFC_PIN_GROUP(ssi4_ctrl_a),
2113 SH_PFC_PIN_GROUP(ssi4_data_a),
2114 SH_PFC_PIN_GROUP(ssi4_ctrl_b),
2115 SH_PFC_PIN_GROUP(ssi4_data_b),
f814def5 2116 SH_PFC_PIN_GROUP(usb0),
a6fff41f
UH		 2117 VIN_DATA_PIN_GROUP(vin4_data, 8),
2118 VIN_DATA_PIN_GROUP(vin4_data, 10),
2119 VIN_DATA_PIN_GROUP(vin4_data, 12),
2120 VIN_DATA_PIN_GROUP(vin4_data, 16),
fbd452ae 2121 SH_PFC_PIN_GROUP(vin4_data18),
a6fff41f
UH		 2122 VIN_DATA_PIN_GROUP(vin4_data, 20),
2123 VIN_DATA_PIN_GROUP(vin4_data, 24),
fbd452ae
UH		 2124 SH_PFC_PIN_GROUP(vin4_sync),
2125 SH_PFC_PIN_GROUP(vin4_field),
2126 SH_PFC_PIN_GROUP(vin4_clkenb),
2127 SH_PFC_PIN_GROUP(vin4_clk),
ab04393c
TK		 2128};
2129
6e7b1ee8
KM		 2130static const char * const audio_clk_groups[] = {
2131 "audio_clk_a",
2132 "audio_clk_b",
2133 "audio_clkout",
2134 "audio_clkout1",
2135};
2136
66abd968
YS		 2137static const char * const avb0_groups[] = {
2138 "avb0_link",
2139 "avb0_magic",
2140 "avb0_phy_int",
3b047a95
GU		 2141 "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
2142 "avb0_mdio",
66abd968
YS		 2143 "avb0_mii",
2144 "avb0_avtp_pps_a",
2145 "avb0_avtp_match_a",
2146 "avb0_avtp_capture_a",
2147 "avb0_avtp_pps_b",
2148 "avb0_avtp_match_b",
2149 "avb0_avtp_capture_b",
2150};
2151
c45985d3
UH		 2152static const char * const can0_groups[] = {
2153 "can0_data_a",
2154 "can0_data_b",
2155};
2156static const char * const can1_groups[] = {
2157 "can1_data_a",
2158 "can1_data_b",
2159};
2160static const char * const can_clk_groups[] = {
2161 "can_clk",
2162};
2163
527890f7
UH		 2164static const char * const canfd0_groups[] = {
2165 "canfd0_data",
2166};
2167static const char * const canfd1_groups[] = {
2168 "canfd1_data",
2169};
2170
65a90f04
UH		 2171static const char * const du_groups[] = {
2172 "du_rgb666",
2173 "du_rgb888",
2174 "du_clk_in_1",
2175 "du_clk_out_0",
2176 "du_sync",
2177 "du_disp_cde",
2178 "du_cde",
2179 "du_disp",
2180};
2181
e8c6b9ec
TK		 2182static const char * const i2c0_groups[] = {
2183 "i2c0",
2184};
2185static const char * const i2c1_groups[] = {
2186 "i2c1",
2187};
2188
2189static const char * const i2c2_groups[] = {
2190 "i2c2_a",
2191 "i2c2_b",
2192};
2193
2194static const char * const i2c3_groups[] = {
2195 "i2c3_a",
2196 "i2c3_b",
2197};
2198
4e5a70ff
TK		 2199static const char * const mmc_groups[] = {
2200 "mmc_data1",
2201 "mmc_data4",
2202 "mmc_data8",
2203 "mmc_ctrl",
2204};
2205
47bb1296
TK		 2206static const char * const pwm0_groups[] = {
2207 "pwm0_a",
2208 "pwm0_b",
2209 "pwm0_c",
2210};
2211
2212static const char * const pwm1_groups[] = {
2213 "pwm1_a",
2214 "pwm1_b",
2215 "pwm1_c",
2216};
2217
2218static const char * const pwm2_groups[] = {
2219 "pwm2_a",
2220 "pwm2_b",
2221 "pwm2_c",
2222};
2223
2224static const char * const pwm3_groups[] = {
2225 "pwm3_a",
2226 "pwm3_b",
2227 "pwm3_c",
2228};
2229
ab04393c
TK		 2230static const char * const scif0_groups[] = {
2231 "scif0_data_a",
2232 "scif0_clk_a",
2233 "scif0_data_b",
2234 "scif0_clk_b",
2235 "scif0_ctrl",
2236};
2237
2238static const char * const scif1_groups[] = {
2239 "scif1_data_a",
2240 "scif1_clk_a",
2241 "scif1_data_b",
2242 "scif1_clk_b",
2243 "scif1_ctrl",
2244};
2245
2246static const char * const scif2_groups[] = {
2247 "scif2_data",
2248 "scif2_clk",
2249};
2250
2251static const char * const scif3_groups[] = {
2252 "scif3_data_a",
2253 "scif3_clk_a",
2254 "scif3_data_b",
2255 "scif3_clk_b",
2256};
2257
2258static const char * const scif4_groups[] = {
2259 "scif4_data_a",
2260 "scif4_clk_a",
2261 "scif4_data_b",
2262 "scif4_clk_b",
2263};
2264
2265static const char * const scif5_groups[] = {
2266 "scif5_data_a",
2267 "scif5_clk_a",
2268 "scif5_data_b",
2269 "scif5_clk_b",
2270};
2271
2272static const char * const scif_clk_groups[] = {
2273 "scif_clk",
794a6711
TK		 2274};
2275
7b9e64a6
KM		 2276static const char * const ssi_groups[] = {
2277 "ssi3_data",
2278 "ssi34_ctrl",
2279 "ssi4_ctrl_a",
2280 "ssi4_data_a",
2281 "ssi4_ctrl_b",
2282 "ssi4_data_b",
2283};
2284
f814def5
TK		 2285static const char * const usb0_groups[] = {
2286 "usb0",
2287};
2288
fbd452ae
UH		 2289static const char * const vin4_groups[] = {
2290 "vin4_data8",
2291 "vin4_data10",
2292 "vin4_data12",
2293 "vin4_data16",
2294 "vin4_data18",
2295 "vin4_data20",
2296 "vin4_data24",
2297 "vin4_sync",
2298 "vin4_field",
2299 "vin4_clkenb",
2300 "vin4_clk",
2301};
2302
2ef7a12f
TK		 2303static const char * const msiof0_groups[] = {
2304 "msiof0_clk",
2305 "msiof0_sync",
2306 "msiof0_ss1",
2307 "msiof0_ss2",
2308 "msiof0_txd",
2309 "msiof0_rxd",
2310};
2311
2312static const char * const msiof1_groups[] = {
2313 "msiof1_clk",
2314 "msiof1_sync",
2315 "msiof1_ss1",
2316 "msiof1_ss2",
2317 "msiof1_txd",
2318 "msiof1_rxd",
2319};
2320
2321static const char * const msiof2_groups[] = {
2322 "msiof2_clk",
2323 "msiof2_sync_a",
2324 "msiof2_sync_b",
2325 "msiof2_ss1",
2326 "msiof2_ss2",
2327 "msiof2_txd",
2328 "msiof2_rxd",
2329};
2330
2331static const char * const msiof3_groups[] = {
2332 "msiof3_clk_a",
2333 "msiof3_sync_a",
2334 "msiof3_ss1_a",
2335 "msiof3_ss2_a",
2336 "msiof3_txd_a",
2337 "msiof3_rxd_a",
2338 "msiof3_clk_b",
2339 "msiof3_sync_b",
2340 "msiof3_ss1_b",
2341 "msiof3_ss2_b",
2342 "msiof3_txd_b",
2343 "msiof3_rxd_b",
2344};
2345
794a6711 2346static const struct sh_pfc_function pinmux_functions[] = {
6e7b1ee8 2347 SH_PFC_FUNCTION(audio_clk),
66abd968 2348 SH_PFC_FUNCTION(avb0),
c45985d3
UH		 2349 SH_PFC_FUNCTION(can0),
2350 SH_PFC_FUNCTION(can1),
2351 SH_PFC_FUNCTION(can_clk),
527890f7
UH		 2352 SH_PFC_FUNCTION(canfd0),
2353 SH_PFC_FUNCTION(canfd1),
65a90f04 2354 SH_PFC_FUNCTION(du),
e8c6b9ec
TK		 2355 SH_PFC_FUNCTION(i2c0),
2356 SH_PFC_FUNCTION(i2c1),
2357 SH_PFC_FUNCTION(i2c2),
2358 SH_PFC_FUNCTION(i2c3),
4e5a70ff 2359 SH_PFC_FUNCTION(mmc),
2ef7a12f
TK		 2360 SH_PFC_FUNCTION(msiof0),
2361 SH_PFC_FUNCTION(msiof1),
2362 SH_PFC_FUNCTION(msiof2),
2363 SH_PFC_FUNCTION(msiof3),
47bb1296
TK		 2364 SH_PFC_FUNCTION(pwm0),
2365 SH_PFC_FUNCTION(pwm1),
2366 SH_PFC_FUNCTION(pwm2),
2367 SH_PFC_FUNCTION(pwm3),
ab04393c
TK		 2368 SH_PFC_FUNCTION(scif0),
2369 SH_PFC_FUNCTION(scif1),
2370 SH_PFC_FUNCTION(scif2),
2371 SH_PFC_FUNCTION(scif3),
2372 SH_PFC_FUNCTION(scif4),
2373 SH_PFC_FUNCTION(scif5),
2374 SH_PFC_FUNCTION(scif_clk),
7b9e64a6 2375 SH_PFC_FUNCTION(ssi),
f814def5 2376 SH_PFC_FUNCTION(usb0),
fbd452ae 2377 SH_PFC_FUNCTION(vin4),
794a6711
TK		 2378};
2379
2380static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2381#define F_(x, y) FN_##y
2382#define FM(x) FN_##x
2383 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2384 0, 0,
2385 0, 0,
2386 0, 0,
2387 0, 0,
2388 0, 0,
2389 0, 0,
2390 0, 0,
2391 0, 0,
2392 0, 0,
2393 0, 0,
2394 0, 0,
2395 0, 0,
2396 0, 0,
2397 0, 0,
2398 0, 0,
2399 0, 0,
2400 0, 0,
2401 0, 0,
2402 0, 0,
2403 0, 0,
2404 0, 0,
2405 0, 0,
2406 0, 0,
2407 GP_0_8_FN, GPSR0_8,
2408 GP_0_7_FN, GPSR0_7,
2409 GP_0_6_FN, GPSR0_6,
2410 GP_0_5_FN, GPSR0_5,
2411 GP_0_4_FN, GPSR0_4,
2412 GP_0_3_FN, GPSR0_3,
2413 GP_0_2_FN, GPSR0_2,
2414 GP_0_1_FN, GPSR0_1,
2415 GP_0_0_FN, GPSR0_0, }
2416 },
2417 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2418 GP_1_31_FN, GPSR1_31,
2419 GP_1_30_FN, GPSR1_30,
2420 GP_1_29_FN, GPSR1_29,
2421 GP_1_28_FN, GPSR1_28,
2422 GP_1_27_FN, GPSR1_27,
2423 GP_1_26_FN, GPSR1_26,
2424 GP_1_25_FN, GPSR1_25,
2425 GP_1_24_FN, GPSR1_24,
2426 GP_1_23_FN, GPSR1_23,
2427 GP_1_22_FN, GPSR1_22,
2428 GP_1_21_FN, GPSR1_21,
2429 GP_1_20_FN, GPSR1_20,
2430 GP_1_19_FN, GPSR1_19,
2431 GP_1_18_FN, GPSR1_18,
2432 GP_1_17_FN, GPSR1_17,
2433 GP_1_16_FN, GPSR1_16,
2434 GP_1_15_FN, GPSR1_15,
2435 GP_1_14_FN, GPSR1_14,
2436 GP_1_13_FN, GPSR1_13,
2437 GP_1_12_FN, GPSR1_12,
2438 GP_1_11_FN, GPSR1_11,
2439 GP_1_10_FN, GPSR1_10,
2440 GP_1_9_FN, GPSR1_9,
2441 GP_1_8_FN, GPSR1_8,
2442 GP_1_7_FN, GPSR1_7,
2443 GP_1_6_FN, GPSR1_6,
2444 GP_1_5_FN, GPSR1_5,
2445 GP_1_4_FN, GPSR1_4,
2446 GP_1_3_FN, GPSR1_3,
2447 GP_1_2_FN, GPSR1_2,
2448 GP_1_1_FN, GPSR1_1,
2449 GP_1_0_FN, GPSR1_0, }
2450 },
2451 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2452 GP_2_31_FN, GPSR2_31,
2453 GP_2_30_FN, GPSR2_30,
2454 GP_2_29_FN, GPSR2_29,
2455 GP_2_28_FN, GPSR2_28,
2456 GP_2_27_FN, GPSR2_27,
2457 GP_2_26_FN, GPSR2_26,
2458 GP_2_25_FN, GPSR2_25,
2459 GP_2_24_FN, GPSR2_24,
2460 GP_2_23_FN, GPSR2_23,
2461 GP_2_22_FN, GPSR2_22,
2462 GP_2_21_FN, GPSR2_21,
2463 GP_2_20_FN, GPSR2_20,
2464 GP_2_19_FN, GPSR2_19,
2465 GP_2_18_FN, GPSR2_18,
2466 GP_2_17_FN, GPSR2_17,
2467 GP_2_16_FN, GPSR2_16,
2468 GP_2_15_FN, GPSR2_15,
2469 GP_2_14_FN, GPSR2_14,
2470 GP_2_13_FN, GPSR2_13,
2471 GP_2_12_FN, GPSR2_12,
2472 GP_2_11_FN, GPSR2_11,
2473 GP_2_10_FN, GPSR2_10,
2474 GP_2_9_FN, GPSR2_9,
2475 GP_2_8_FN, GPSR2_8,
2476 GP_2_7_FN, GPSR2_7,
2477 GP_2_6_FN, GPSR2_6,
2478 GP_2_5_FN, GPSR2_5,
2479 GP_2_4_FN, GPSR2_4,
2480 GP_2_3_FN, GPSR2_3,
2481 GP_2_2_FN, GPSR2_2,
2482 GP_2_1_FN, GPSR2_1,
2483 GP_2_0_FN, GPSR2_0, }
2484 },
2485 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2486 0, 0,
2487 0, 0,
2488 0, 0,
2489 0, 0,
2490 0, 0,
2491 0, 0,
2492 0, 0,
2493 0, 0,
2494 0, 0,
2495 0, 0,
2496 0, 0,
2497 0, 0,
2498 0, 0,
2499 0, 0,
2500 0, 0,
2501 0, 0,
2502 0, 0,
2503 0, 0,
2504 0, 0,
2505 0, 0,
2506 0, 0,
2507 0, 0,
2508 GP_3_9_FN, GPSR3_9,
2509 GP_3_8_FN, GPSR3_8,
2510 GP_3_7_FN, GPSR3_7,
2511 GP_3_6_FN, GPSR3_6,
2512 GP_3_5_FN, GPSR3_5,
2513 GP_3_4_FN, GPSR3_4,
2514 GP_3_3_FN, GPSR3_3,
2515 GP_3_2_FN, GPSR3_2,
2516 GP_3_1_FN, GPSR3_1,
2517 GP_3_0_FN, GPSR3_0, }
2518 },
2519 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2520 GP_4_31_FN, GPSR4_31,
2521 GP_4_30_FN, GPSR4_30,
2522 GP_4_29_FN, GPSR4_29,
2523 GP_4_28_FN, GPSR4_28,
2524 GP_4_27_FN, GPSR4_27,
2525 GP_4_26_FN, GPSR4_26,
2526 GP_4_25_FN, GPSR4_25,
2527 GP_4_24_FN, GPSR4_24,
2528 GP_4_23_FN, GPSR4_23,
2529 GP_4_22_FN, GPSR4_22,
2530 GP_4_21_FN, GPSR4_21,
2531 GP_4_20_FN, GPSR4_20,
2532 GP_4_19_FN, GPSR4_19,
2533 GP_4_18_FN, GPSR4_18,
2534 GP_4_17_FN, GPSR4_17,
2535 GP_4_16_FN, GPSR4_16,
2536 GP_4_15_FN, GPSR4_15,
2537 GP_4_14_FN, GPSR4_14,
2538 GP_4_13_FN, GPSR4_13,
2539 GP_4_12_FN, GPSR4_12,
2540 GP_4_11_FN, GPSR4_11,
2541 GP_4_10_FN, GPSR4_10,
2542 GP_4_9_FN, GPSR4_9,
2543 GP_4_8_FN, GPSR4_8,
2544 GP_4_7_FN, GPSR4_7,
2545 GP_4_6_FN, GPSR4_6,
2546 GP_4_5_FN, GPSR4_5,
2547 GP_4_4_FN, GPSR4_4,
2548 GP_4_3_FN, GPSR4_3,
2549 GP_4_2_FN, GPSR4_2,
2550 GP_4_1_FN, GPSR4_1,
2551 GP_4_0_FN, GPSR4_0, }
2552 },
2553 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2554 0, 0,
2555 0, 0,
2556 0, 0,
2557 0, 0,
2558 0, 0,
2559 0, 0,
2560 0, 0,
2561 0, 0,
2562 0, 0,
2563 0, 0,
2564 0, 0,
2565 GP_5_20_FN, GPSR5_20,
2566 GP_5_19_FN, GPSR5_19,
2567 GP_5_18_FN, GPSR5_18,
2568 GP_5_17_FN, GPSR5_17,
2569 GP_5_16_FN, GPSR5_16,
2570 GP_5_15_FN, GPSR5_15,
2571 GP_5_14_FN, GPSR5_14,
2572 GP_5_13_FN, GPSR5_13,
2573 GP_5_12_FN, GPSR5_12,
2574 GP_5_11_FN, GPSR5_11,
2575 GP_5_10_FN, GPSR5_10,
2576 GP_5_9_FN, GPSR5_9,
2577 GP_5_8_FN, GPSR5_8,
2578 GP_5_7_FN, GPSR5_7,
2579 GP_5_6_FN, GPSR5_6,
2580 GP_5_5_FN, GPSR5_5,
2581 GP_5_4_FN, GPSR5_4,
2582 GP_5_3_FN, GPSR5_3,
2583 GP_5_2_FN, GPSR5_2,
2584 GP_5_1_FN, GPSR5_1,
2585 GP_5_0_FN, GPSR5_0, }
2586 },
2587 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2588 0, 0,
2589 0, 0,
2590 0, 0,
2591 0, 0,
2592 0, 0,
2593 0, 0,
2594 0, 0,
2595 0, 0,
2596 0, 0,
2597 0, 0,
2598 0, 0,
2599 0, 0,
2600 0, 0,
2601 0, 0,
2602 0, 0,
2603 0, 0,
2604 0, 0,
2605 0, 0,
2606 GP_6_13_FN, GPSR6_13,
2607 GP_6_12_FN, GPSR6_12,
2608 GP_6_11_FN, GPSR6_11,
2609 GP_6_10_FN, GPSR6_10,
2610 GP_6_9_FN, GPSR6_9,
2611 GP_6_8_FN, GPSR6_8,
2612 GP_6_7_FN, GPSR6_7,
2613 GP_6_6_FN, GPSR6_6,
2614 GP_6_5_FN, GPSR6_5,
2615 GP_6_4_FN, GPSR6_4,
2616 GP_6_3_FN, GPSR6_3,
2617 GP_6_2_FN, GPSR6_2,
2618 GP_6_1_FN, GPSR6_1,
2619 GP_6_0_FN, GPSR6_0, }
2620 },
2621#undef F_
2622#undef FM
2623
2624#define F_(x, y) x,
2625#define FM(x) FN_##x,
2626 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2627 IP0_31_28
2628 IP0_27_24
2629 IP0_23_20
2630 IP0_19_16
2631 IP0_15_12
2632 IP0_11_8
2633 IP0_7_4
2634 IP0_3_0 }
2635 },
2636 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2637 IP1_31_28
2638 IP1_27_24
2639 IP1_23_20
2640 IP1_19_16
2641 IP1_15_12
2642 IP1_11_8
2643 IP1_7_4
2644 IP1_3_0 }
2645 },
2646 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2647 IP2_31_28
2648 IP2_27_24
2649 IP2_23_20
2650 IP2_19_16
2651 IP2_15_12
2652 IP2_11_8
2653 IP2_7_4
2654 IP2_3_0 }
2655 },
2656 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2657 IP3_31_28
2658 IP3_27_24
2659 IP3_23_20
2660 IP3_19_16
2661 IP3_15_12
2662 IP3_11_8
2663 IP3_7_4
2664 IP3_3_0 }
2665 },
2666 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2667 IP4_31_28
2668 IP4_27_24
2669 IP4_23_20
2670 IP4_19_16
2671 IP4_15_12
2672 IP4_11_8
2673 IP4_7_4
2674 IP4_3_0 }
2675 },
2676 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2677 IP5_31_28
2678 IP5_27_24
2679 IP5_23_20
2680 IP5_19_16
2681 IP5_15_12
2682 IP5_11_8
2683 IP5_7_4
2684 IP5_3_0 }
2685 },
2686 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2687 IP6_31_28
2688 IP6_27_24
2689 IP6_23_20
2690 IP6_19_16
2691 IP6_15_12
2692 IP6_11_8
2693 IP6_7_4
2694 IP6_3_0 }
2695 },
2696 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2697 IP7_31_28
2698 IP7_27_24
2699 IP7_23_20
2700 IP7_19_16
2701 IP7_15_12
2702 IP7_11_8
2703 IP7_7_4
2704 IP7_3_0 }
2705 },
2706 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2707 IP8_31_28
2708 IP8_27_24
2709 IP8_23_20
2710 IP8_19_16
2711 IP8_15_12
2712 IP8_11_8
2713 IP8_7_4
2714 IP8_3_0 }
2715 },
2716 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2717 IP9_31_28
2718 IP9_27_24
2719 IP9_23_20
2720 IP9_19_16
2721 IP9_15_12
2722 IP9_11_8
2723 IP9_7_4
2724 IP9_3_0 }
2725 },
2726 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2727 IP10_31_28
2728 IP10_27_24
2729 IP10_23_20
2730 IP10_19_16
2731 IP10_15_12
2732 IP10_11_8
2733 IP10_7_4
2734 IP10_3_0 }
2735 },
2736 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2737 IP11_31_28
2738 IP11_27_24
2739 IP11_23_20
2740 IP11_19_16
2741 IP11_15_12
2742 IP11_11_8
2743 IP11_7_4
2744 IP11_3_0 }
2745 },
2746 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2747 IP12_31_28
2748 IP12_27_24
2749 IP12_23_20
2750 IP12_19_16
2751 IP12_15_12
2752 IP12_11_8
2753 IP12_7_4
2754 IP12_3_0 }
2755 },
2756 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2757 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2758 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2759 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2760 /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2761 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2762 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2763 IP13_7_4
2764 IP13_3_0 }
2765 },
2766#undef F_
2767#undef FM
2768
2769#define F_(x, y) x,
2770#define FM(x) FN_##x,
2771 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2772 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
2773 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
2774 /* RESERVED 31 */
2775 0, 0,
2776 MOD_SEL0_30
2777 MOD_SEL0_29
2778 MOD_SEL0_28
2779 MOD_SEL0_27
2780 MOD_SEL0_26
2781 MOD_SEL0_25
2782 MOD_SEL0_24_23
2783 MOD_SEL0_22_21
2784 MOD_SEL0_20_19
2785 MOD_SEL0_18_17
2786 /* RESERVED 16 */
2787 0, 0,
2788 MOD_SEL0_15
2789 MOD_SEL0_14
2790 MOD_SEL0_13
2791 MOD_SEL0_12
2792 MOD_SEL0_11
2793 MOD_SEL0_10
2794 /* RESERVED 9, 8, 7, 6 */
2795 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2796 MOD_SEL0_5
2797 MOD_SEL0_4
2798 MOD_SEL0_3
2799 MOD_SEL0_2
2800 MOD_SEL0_1
2801 MOD_SEL0_0 }
2802 },
2803 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2804 1, 1, 1, 1, 1, 1, 2, 4, 4,
2805 4, 4, 4, 4) {
2806 MOD_SEL1_31
2807 MOD_SEL1_30
2808 MOD_SEL1_29
2809 MOD_SEL1_28
2810 MOD_SEL1_27
2811 MOD_SEL1_26
2812 /* RESERVED 25, 24 */
2813 0, 0, 0, 0,
2814 /* RESERVED 23, 22, 21, 20 */
2815 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2816 /* RESERVED 19, 18, 17, 16 */
2817 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2818 /* RESERVED 15, 14, 13, 12 */
2819 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2820 /* RESERVED 11, 10, 9, 8 */
2821 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2822 /* RESERVED 7, 6, 5, 4 */
2823 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2824 /* RESERVED 3, 2, 1, 0 */
2825 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
2826 },
2827 { },
2828};
2829
56d57391
TK		 2830static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2831{
2832 int bit = -EINVAL;
2833
2834 *pocctrl = 0xe6060380;
2835
2836 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
2837 bit = 29 - (pin - RCAR_GP_PIN(3, 0));
2838
2839 return bit;
2840}
2841
2842static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
2843 .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
2844};
2845
794a6711
TK		 2846const struct sh_pfc_soc_info r8a77995_pinmux_info = {
2847 .name = "r8a77995_pfc",
56d57391 2848 .ops = &r8a77995_pinmux_ops,
794a6711
TK		 2849 .unlock_reg = 0xe6060000, /* PMMR */
2850
2851 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2852
2853 .pins = pinmux_pins,
2854 .nr_pins = ARRAY_SIZE(pinmux_pins),
2855 .groups = pinmux_groups,
2856 .nr_groups = ARRAY_SIZE(pinmux_groups),
2857 .functions = pinmux_functions,
2858 .nr_functions = ARRAY_SIZE(pinmux_functions),
2859
2860 .cfg_regs = pinmux_config_regs,
2861
2862 .pinmux_data = pinmux_data,
2863 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2864};
Linux 6.x block layer and io_uring tree(s)