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6d4036a1 TK |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * R8A77990 processor support - PFC hardware block. | |
4 | * | |
5 | * Copyright (C) 2018 Renesas Electronics Corp. | |
6 | * | |
7 | * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c | |
8 | * | |
9 | * R8A7796 processor support - PFC hardware block. | |
10 | * | |
11 | * Copyright (C) 2016-2017 Renesas Electronics Corp. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | ||
16 | #include "core.h" | |
17 | #include "sh_pfc.h" | |
18 | ||
83f6941a TK |
19 | #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \ |
20 | SH_PFC_PIN_CFG_PULL_DOWN) | |
21 | ||
22 | #define CPU_ALL_PORT(fn, sfx) \ | |
23 | PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ | |
24 | PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ | |
25 | PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ | |
26 | PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \ | |
27 | PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \ | |
28 | PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ | |
29 | PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS) | |
6d4036a1 TK |
30 | /* |
31 | * F_() : just information | |
32 | * FM() : macro for FN_xxx / xxx_MARK | |
33 | */ | |
34 | ||
35 | /* GPSR0 */ | |
36 | #define GPSR0_17 F_(SDA4, IP7_27_24) | |
37 | #define GPSR0_16 F_(SCL4, IP7_23_20) | |
38 | #define GPSR0_15 F_(D15, IP7_19_16) | |
39 | #define GPSR0_14 F_(D14, IP7_15_12) | |
40 | #define GPSR0_13 F_(D13, IP7_11_8) | |
41 | #define GPSR0_12 F_(D12, IP7_7_4) | |
42 | #define GPSR0_11 F_(D11, IP7_3_0) | |
43 | #define GPSR0_10 F_(D10, IP6_31_28) | |
44 | #define GPSR0_9 F_(D9, IP6_27_24) | |
45 | #define GPSR0_8 F_(D8, IP6_23_20) | |
46 | #define GPSR0_7 F_(D7, IP6_19_16) | |
47 | #define GPSR0_6 F_(D6, IP6_15_12) | |
48 | #define GPSR0_5 F_(D5, IP6_11_8) | |
49 | #define GPSR0_4 F_(D4, IP6_7_4) | |
50 | #define GPSR0_3 F_(D3, IP6_3_0) | |
51 | #define GPSR0_2 F_(D2, IP5_31_28) | |
52 | #define GPSR0_1 F_(D1, IP5_27_24) | |
53 | #define GPSR0_0 F_(D0, IP5_23_20) | |
54 | ||
55 | /* GPSR1 */ | |
56 | #define GPSR1_22 F_(WE0_N, IP5_19_16) | |
57 | #define GPSR1_21 F_(CS0_N, IP5_15_12) | |
58 | #define GPSR1_20 FM(CLKOUT) | |
59 | #define GPSR1_19 F_(A19, IP5_11_8) | |
60 | #define GPSR1_18 F_(A18, IP5_7_4) | |
61 | #define GPSR1_17 F_(A17, IP5_3_0) | |
62 | #define GPSR1_16 F_(A16, IP4_31_28) | |
63 | #define GPSR1_15 F_(A15, IP4_27_24) | |
64 | #define GPSR1_14 F_(A14, IP4_23_20) | |
65 | #define GPSR1_13 F_(A13, IP4_19_16) | |
66 | #define GPSR1_12 F_(A12, IP4_15_12) | |
67 | #define GPSR1_11 F_(A11, IP4_11_8) | |
68 | #define GPSR1_10 F_(A10, IP4_7_4) | |
69 | #define GPSR1_9 F_(A9, IP4_3_0) | |
70 | #define GPSR1_8 F_(A8, IP3_31_28) | |
71 | #define GPSR1_7 F_(A7, IP3_27_24) | |
72 | #define GPSR1_6 F_(A6, IP3_23_20) | |
73 | #define GPSR1_5 F_(A5, IP3_19_16) | |
74 | #define GPSR1_4 F_(A4, IP3_15_12) | |
75 | #define GPSR1_3 F_(A3, IP3_11_8) | |
76 | #define GPSR1_2 F_(A2, IP3_7_4) | |
77 | #define GPSR1_1 F_(A1, IP3_3_0) | |
78 | #define GPSR1_0 F_(A0, IP2_31_28) | |
79 | ||
80 | /* GPSR2 */ | |
81 | #define GPSR2_25 F_(EX_WAIT0, IP2_27_24) | |
82 | #define GPSR2_24 F_(RD_WR_N, IP2_23_20) | |
83 | #define GPSR2_23 F_(RD_N, IP2_19_16) | |
84 | #define GPSR2_22 F_(BS_N, IP2_15_12) | |
85 | #define GPSR2_21 FM(AVB_PHY_INT) | |
86 | #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0) | |
87 | #define GPSR2_19 FM(AVB_RD3) | |
88 | #define GPSR2_18 F_(AVB_RD2, IP1_31_28) | |
89 | #define GPSR2_17 F_(AVB_RD1, IP1_27_24) | |
90 | #define GPSR2_16 F_(AVB_RD0, IP1_23_20) | |
91 | #define GPSR2_15 FM(AVB_RXC) | |
92 | #define GPSR2_14 FM(AVB_RX_CTL) | |
93 | #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16) | |
94 | #define GPSR2_12 F_(RPC_INT_N, IP1_15_12) | |
95 | #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8) | |
96 | #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4) | |
97 | #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0) | |
98 | #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28) | |
99 | #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24) | |
100 | #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20) | |
101 | #define GPSR2_5 FM(QSPI0_SSL) | |
102 | #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16) | |
103 | #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12) | |
104 | #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8) | |
105 | #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4) | |
106 | #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0) | |
107 | ||
108 | /* GPSR3 */ | |
109 | #define GPSR3_15 F_(SD1_WP, IP11_7_4) | |
110 | #define GPSR3_14 F_(SD1_CD, IP11_3_0) | |
111 | #define GPSR3_13 F_(SD0_WP, IP10_31_28) | |
112 | #define GPSR3_12 F_(SD0_CD, IP10_27_24) | |
113 | #define GPSR3_11 F_(SD1_DAT3, IP9_11_8) | |
114 | #define GPSR3_10 F_(SD1_DAT2, IP9_7_4) | |
115 | #define GPSR3_9 F_(SD1_DAT1, IP9_3_0) | |
116 | #define GPSR3_8 F_(SD1_DAT0, IP8_31_28) | |
117 | #define GPSR3_7 F_(SD1_CMD, IP8_27_24) | |
118 | #define GPSR3_6 F_(SD1_CLK, IP8_23_20) | |
119 | #define GPSR3_5 F_(SD0_DAT3, IP8_19_16) | |
120 | #define GPSR3_4 F_(SD0_DAT2, IP8_15_12) | |
121 | #define GPSR3_3 F_(SD0_DAT1, IP8_11_8) | |
122 | #define GPSR3_2 F_(SD0_DAT0, IP8_7_4) | |
123 | #define GPSR3_1 F_(SD0_CMD, IP8_3_0) | |
124 | #define GPSR3_0 F_(SD0_CLK, IP7_31_28) | |
125 | ||
126 | /* GPSR4 */ | |
127 | #define GPSR4_10 F_(SD3_DS, IP10_23_20) | |
128 | #define GPSR4_9 F_(SD3_DAT7, IP10_19_16) | |
129 | #define GPSR4_8 F_(SD3_DAT6, IP10_15_12) | |
130 | #define GPSR4_7 F_(SD3_DAT5, IP10_11_8) | |
131 | #define GPSR4_6 F_(SD3_DAT4, IP10_7_4) | |
132 | #define GPSR4_5 F_(SD3_DAT3, IP10_3_0) | |
133 | #define GPSR4_4 F_(SD3_DAT2, IP9_31_28) | |
134 | #define GPSR4_3 F_(SD3_DAT1, IP9_27_24) | |
135 | #define GPSR4_2 F_(SD3_DAT0, IP9_23_20) | |
136 | #define GPSR4_1 F_(SD3_CMD, IP9_19_16) | |
137 | #define GPSR4_0 F_(SD3_CLK, IP9_15_12) | |
138 | ||
139 | /* GPSR5 */ | |
140 | #define GPSR5_19 F_(MLB_DAT, IP13_23_20) | |
141 | #define GPSR5_18 F_(MLB_SIG, IP13_19_16) | |
142 | #define GPSR5_17 F_(MLB_CLK, IP13_15_12) | |
143 | #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8) | |
144 | #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4) | |
145 | #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0) | |
146 | #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28) | |
147 | #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24) | |
148 | #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20) | |
149 | #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16) | |
150 | #define GPSR5_9 F_(RX2_A, IP12_15_12) | |
151 | #define GPSR5_8 F_(TX2_A, IP12_11_8) | |
152 | #define GPSR5_7 F_(SCK2_A, IP12_7_4) | |
153 | #define GPSR5_6 F_(TX1, IP12_3_0) | |
154 | #define GPSR5_5 F_(RX1, IP11_31_28) | |
155 | #define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20) | |
156 | #define GPSR5_3 F_(CTS0_N_A, IP11_19_16) | |
157 | #define GPSR5_2 F_(TX0_A, IP11_15_12) | |
158 | #define GPSR5_1 F_(RX0_A, IP11_11_8) | |
159 | #define GPSR5_0 F_(SCK0_A, IP11_27_24) | |
160 | ||
161 | /* GPSR6 */ | |
162 | #define GPSR6_17 F_(USB30_PWEN, IP15_27_24) | |
163 | #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16) | |
164 | #define GPSR6_15 F_(SSI_WS6, IP15_15_12) | |
165 | #define GPSR6_14 F_(SSI_SCK6, IP15_11_8) | |
166 | #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4) | |
167 | #define GPSR6_12 F_(SSI_WS5, IP15_3_0) | |
168 | #define GPSR6_11 F_(SSI_SCK5, IP14_31_28) | |
169 | #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24) | |
170 | #define GPSR6_9 F_(USB30_OVC, IP15_31_28) | |
171 | #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20) | |
172 | #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20) | |
173 | #define GPSR6_6 F_(SSI_WS349, IP14_19_16) | |
174 | #define GPSR6_5 F_(SSI_SCK349, IP14_15_12) | |
175 | #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8) | |
176 | #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4) | |
177 | #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0) | |
178 | #define GPSR6_1 F_(SSI_WS01239, IP13_31_28) | |
179 | #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24) | |
180 | ||
181 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ | |
182 | #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
183 | #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
184 | #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
185 | #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
186 | #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
187 | #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
188 | #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
189 | #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
190 | #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
191 | #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
192 | #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
193 | #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
194 | #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
195 | #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
196 | #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
197 | #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
198 | #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
199 | #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
200 | #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
201 | #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
202 | #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
203 | #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
204 | #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
205 | #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
206 | #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
207 | #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
208 | #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
209 | #define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
210 | #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
211 | #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
212 | #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
213 | #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
214 | ||
215 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ | |
216 | #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
217 | #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
218 | #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
219 | #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
220 | #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
221 | #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
222 | #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
223 | #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
224 | #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
225 | #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
226 | #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
227 | #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
228 | #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
229 | #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
230 | #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
231 | #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
232 | #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
233 | #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
234 | #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
235 | #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
236 | #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
237 | #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
238 | #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
239 | #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
240 | #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
241 | #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
242 | #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
243 | #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
244 | #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
245 | #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
246 | #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
247 | #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
248 | ||
249 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ | |
250 | #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
251 | #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
252 | #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
253 | #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
254 | #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
255 | #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
256 | #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
257 | #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
258 | #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
259 | #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
260 | #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
261 | #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
262 | #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
263 | #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
264 | #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
265 | #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
266 | #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
267 | #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
268 | #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
269 | #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
270 | #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
271 | #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
272 | #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
273 | #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
274 | #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
275 | #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
276 | #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
277 | #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
278 | #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
279 | #define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
747c5417 | 280 | #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
6d4036a1 TK |
281 | #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
282 | ||
283 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ | |
284 | #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
285 | #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
286 | #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
287 | #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
288 | #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
289 | #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
290 | #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
291 | #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
292 | #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
293 | #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
294 | #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
295 | #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
296 | #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
297 | #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
298 | #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
299 | #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
300 | #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
301 | #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
302 | #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
303 | #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
304 | #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
305 | #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
306 | #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
307 | #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
308 | #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
309 | #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
310 | #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
311 | #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
312 | #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
313 | #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
314 | #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
315 | #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
316 | ||
317 | #define PINMUX_GPSR \ | |
318 | \ | |
319 | \ | |
320 | \ | |
321 | \ | |
322 | \ | |
323 | \ | |
324 | \ | |
325 | GPSR2_25 \ | |
326 | GPSR2_24 \ | |
327 | GPSR2_23 \ | |
328 | GPSR1_22 GPSR2_22 \ | |
329 | GPSR1_21 GPSR2_21 \ | |
330 | GPSR1_20 GPSR2_20 \ | |
331 | GPSR1_19 GPSR2_19 GPSR5_19 \ | |
332 | GPSR1_18 GPSR2_18 GPSR5_18 \ | |
333 | GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \ | |
334 | GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \ | |
335 | GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \ | |
336 | GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \ | |
337 | GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \ | |
338 | GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \ | |
339 | GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \ | |
340 | GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ | |
341 | GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ | |
342 | GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ | |
343 | GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ | |
344 | GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ | |
345 | GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ | |
346 | GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ | |
347 | GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ | |
348 | GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ | |
349 | GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ | |
350 | GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 | |
351 | ||
352 | #define PINMUX_IPSR \ | |
353 | \ | |
354 | FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ | |
355 | FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ | |
356 | FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ | |
357 | FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ | |
358 | FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ | |
359 | FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ | |
360 | FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ | |
361 | FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ | |
362 | \ | |
363 | FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ | |
364 | FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ | |
365 | FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ | |
366 | FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ | |
367 | FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ | |
368 | FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ | |
369 | FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ | |
370 | FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ | |
371 | \ | |
372 | FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ | |
373 | FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ | |
374 | FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ | |
375 | FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ | |
376 | FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ | |
377 | FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ | |
378 | FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ | |
379 | FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ | |
380 | \ | |
381 | FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ | |
382 | FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ | |
383 | FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ | |
384 | FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ | |
385 | FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ | |
386 | FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ | |
387 | FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ | |
388 | FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 | |
389 | ||
390 | /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ | |
391 | #define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_1) FM(SEL_ADGB_2) F_(0, 0) | |
392 | #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) | |
393 | #define MOD_SEL0_27_26 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) F_(0, 0) | |
394 | #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1) | |
395 | #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) | |
396 | #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) | |
397 | #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) | |
398 | #define MOD_SEL0_21_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) FM(SEL_I2C1_2) FM(SEL_I2C1_3) FM(SEL_I2C1_4) F_(0, 0) F_(0, 0) F_(0, 0) | |
399 | #define MOD_SEL0_19_18_17 FM(SEL_I2C2_0) FM(SEL_I2C2_1) FM(SEL_I2C2_2) FM(SEL_I2C2_3) FM(SEL_I2C2_4) F_(0, 0) F_(0, 0) F_(0, 0) | |
400 | #define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1) | |
401 | #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) | |
402 | #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) | |
403 | #define MOD_SEL0_13_12 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0) | |
404 | #define MOD_SEL0_11_10 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0) | |
405 | #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1) | |
406 | #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1) | |
407 | #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1) | |
408 | #define MOD_SEL0_6_5 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) FM(SEL_REMOCON_2) F_(0, 0) | |
409 | #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1) | |
410 | #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) | |
411 | #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) | |
412 | #define MOD_SEL0_1_0 FM(SEL_SPEED_PULSE_IF_0) FM(SEL_SPEED_PULSE_IF_1) FM(SEL_SPEED_PULSE_IF_2) F_(0, 0) | |
413 | ||
414 | /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ | |
415 | #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) | |
416 | #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1) | |
417 | #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) | |
418 | #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) | |
419 | #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) | |
420 | #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) | |
421 | #define MOD_SEL1_24_23_22 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) FM(SEL_HSCIF3_4) F_(0, 0) F_(0, 0) F_(0, 0) | |
422 | #define MOD_SEL1_21_20_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) FM(SEL_HSCIF4_2) FM(SEL_HSCIF4_3) FM(SEL_HSCIF4_4) F_(0, 0) F_(0, 0) F_(0, 0) | |
423 | #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1) | |
424 | #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1) | |
425 | #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) | |
426 | #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) | |
427 | #define MOD_SEL1_14_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) FM(SEL_SCIF3_2) F_(0, 0) | |
428 | #define MOD_SEL1_12_11 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) | |
429 | #define MOD_SEL1_10_9 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) FM(SEL_SCIF5_2) F_(0, 0) | |
430 | #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1) | |
431 | #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1) | |
432 | #define MOD_SEL1_6_5 FM(SEL_ADGC_0) FM(SEL_ADGC_1) FM(SEL_ADGC_2) F_(0, 0) | |
433 | #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1) | |
434 | ||
435 | #define PINMUX_MOD_SELS \ | |
436 | \ | |
437 | MOD_SEL1_31 \ | |
438 | MOD_SEL0_30_29 MOD_SEL1_30 \ | |
439 | MOD_SEL1_29 \ | |
440 | MOD_SEL0_28 MOD_SEL1_28 \ | |
441 | MOD_SEL0_27_26 \ | |
442 | MOD_SEL1_26 \ | |
443 | MOD_SEL0_25 MOD_SEL1_25 \ | |
444 | MOD_SEL0_24 MOD_SEL1_24_23_22 \ | |
445 | MOD_SEL0_23 \ | |
446 | MOD_SEL0_22 \ | |
447 | MOD_SEL0_21_20 MOD_SEL1_21_20_19 \ | |
448 | MOD_SEL0_19_18_17 MOD_SEL1_18 \ | |
449 | MOD_SEL1_17 \ | |
450 | MOD_SEL0_16 MOD_SEL1_16 \ | |
451 | MOD_SEL0_15 MOD_SEL1_15 \ | |
452 | MOD_SEL0_14 MOD_SEL1_14_13 \ | |
453 | MOD_SEL0_13_12 \ | |
454 | MOD_SEL1_12_11 \ | |
455 | MOD_SEL0_11_10 \ | |
456 | MOD_SEL1_10_9 \ | |
457 | MOD_SEL0_9 \ | |
458 | MOD_SEL0_8 MOD_SEL1_8 \ | |
459 | MOD_SEL0_7 MOD_SEL1_7 \ | |
460 | MOD_SEL0_6_5 MOD_SEL1_6_5 \ | |
461 | MOD_SEL0_4 MOD_SEL1_4 \ | |
462 | MOD_SEL0_3 \ | |
463 | MOD_SEL0_2 \ | |
464 | MOD_SEL0_1_0 | |
465 | ||
83f6941a TK |
466 | /* |
467 | * These pins are not able to be muxed but have other properties | |
468 | * that can be set, such as pull-up/pull-down enable. | |
469 | */ | |
470 | #define PINMUX_STATIC \ | |
471 | FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \ | |
472 | FM(AVB_TD3) \ | |
473 | FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \ | |
474 | FM(ASEBRK) \ | |
475 | FM(MLB_REF) | |
476 | ||
6d4036a1 TK |
477 | enum { |
478 | PINMUX_RESERVED = 0, | |
479 | ||
480 | PINMUX_DATA_BEGIN, | |
481 | GP_ALL(DATA), | |
482 | PINMUX_DATA_END, | |
483 | ||
484 | #define F_(x, y) | |
485 | #define FM(x) FN_##x, | |
486 | PINMUX_FUNCTION_BEGIN, | |
487 | GP_ALL(FN), | |
488 | PINMUX_GPSR | |
489 | PINMUX_IPSR | |
490 | PINMUX_MOD_SELS | |
491 | PINMUX_FUNCTION_END, | |
492 | #undef F_ | |
493 | #undef FM | |
494 | ||
495 | #define F_(x, y) | |
496 | #define FM(x) x##_MARK, | |
497 | PINMUX_MARK_BEGIN, | |
498 | PINMUX_GPSR | |
499 | PINMUX_IPSR | |
500 | PINMUX_MOD_SELS | |
83f6941a | 501 | PINMUX_STATIC |
6d4036a1 TK |
502 | PINMUX_MARK_END, |
503 | #undef F_ | |
504 | #undef FM | |
505 | }; | |
506 | ||
507 | static const u16 pinmux_data[] = { | |
508 | PINMUX_DATA_GP_ALL(), | |
509 | ||
83f6941a TK |
510 | PINMUX_SINGLE(CLKOUT), |
511 | PINMUX_SINGLE(AVB_PHY_INT), | |
512 | PINMUX_SINGLE(AVB_RD3), | |
513 | PINMUX_SINGLE(AVB_RXC), | |
514 | PINMUX_SINGLE(AVB_RX_CTL), | |
515 | PINMUX_SINGLE(QSPI0_SSL), | |
516 | ||
6d4036a1 TK |
517 | /* IPSR0 */ |
518 | PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK), | |
519 | PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0), | |
520 | ||
521 | PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0), | |
522 | PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0), | |
523 | ||
524 | PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1), | |
525 | PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0), | |
526 | ||
527 | PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2), | |
528 | PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A), | |
529 | ||
530 | PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3), | |
531 | PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0), | |
532 | ||
533 | PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK), | |
534 | PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0), | |
535 | PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1), | |
536 | PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0), | |
537 | ||
538 | PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0), | |
539 | PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0), | |
540 | PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B), | |
541 | PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0), | |
542 | ||
543 | PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1), | |
544 | PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0), | |
545 | PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1), | |
546 | PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0), | |
547 | ||
548 | /* IPSR1 */ | |
549 | PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2), | |
550 | PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0), | |
551 | PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C), | |
552 | PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0), | |
553 | ||
554 | PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3), | |
555 | PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0), | |
556 | PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2), | |
557 | PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0), | |
558 | ||
559 | PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL), | |
560 | PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0), | |
561 | PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2), | |
562 | PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0), | |
563 | ||
564 | PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N), | |
565 | PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0), | |
566 | PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2), | |
567 | PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0), | |
568 | ||
569 | PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N), | |
570 | PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0), | |
571 | PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2), | |
572 | PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0), | |
573 | ||
574 | PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0), | |
575 | ||
576 | PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1), | |
577 | ||
578 | PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2), | |
579 | ||
580 | /* IPSR2 */ | |
581 | PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK), | |
582 | ||
583 | PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO), | |
584 | ||
585 | PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC), | |
586 | ||
587 | PINMUX_IPSR_GPSR(IP2_15_12, BS_N), | |
588 | PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0), | |
589 | PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC), | |
590 | PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK), | |
591 | PINMUX_IPSR_GPSR(IP2_15_12, TX3_C), | |
592 | PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1), | |
593 | ||
594 | PINMUX_IPSR_GPSR(IP2_19_16, RD_N), | |
595 | PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0), | |
596 | PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK), | |
597 | PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD), | |
598 | PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2), | |
599 | PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A), | |
600 | PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1), | |
601 | ||
602 | PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N), | |
603 | PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0), | |
604 | PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A), | |
605 | PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N), | |
606 | PINMUX_IPSR_GPSR(IP2_23_20, TX5_B), | |
607 | PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2), | |
608 | PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0), | |
609 | ||
610 | PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0), | |
611 | PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0), | |
612 | PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A), | |
613 | PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N), | |
614 | PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1), | |
615 | PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0), | |
616 | ||
617 | PINMUX_IPSR_GPSR(IP2_31_28, A0), | |
618 | PINMUX_IPSR_GPSR(IP2_31_28, IRQ0), | |
619 | PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0), | |
620 | PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1), | |
621 | PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0), | |
622 | PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE), | |
623 | PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3), | |
624 | PINMUX_IPSR_GPSR(IP2_31_28, IERX), | |
625 | PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE), | |
626 | ||
627 | /* IPSR3 */ | |
628 | PINMUX_IPSR_GPSR(IP3_3_0, A1), | |
629 | PINMUX_IPSR_GPSR(IP3_3_0, IRQ1), | |
630 | PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0), | |
631 | PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1), | |
632 | PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0), | |
633 | PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE), | |
634 | PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1), | |
635 | PINMUX_IPSR_GPSR(IP3_3_0, IETX), | |
636 | PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE), | |
637 | ||
638 | PINMUX_IPSR_GPSR(IP3_7_4, A2), | |
639 | PINMUX_IPSR_GPSR(IP3_7_4, IRQ2), | |
640 | PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS), | |
641 | PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB), | |
642 | PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0), | |
643 | PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP), | |
644 | PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1), | |
645 | PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE), | |
646 | ||
647 | PINMUX_IPSR_GPSR(IP3_11_8, A3), | |
648 | PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0), | |
649 | PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0), | |
650 | PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12), | |
651 | PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0), | |
652 | PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D), | |
653 | PINMUX_IPSR_GPSR(IP3_11_8, IECLK), | |
654 | PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), | |
655 | ||
656 | PINMUX_IPSR_GPSR(IP3_15_12, A4), | |
657 | PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0), | |
658 | PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), | |
659 | PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), | |
660 | PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), | |
661 | PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), | |
662 | PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1), | |
663 | ||
664 | PINMUX_IPSR_GPSR(IP3_19_16, A5), | |
665 | PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0), | |
666 | PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1), | |
667 | PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9), | |
668 | PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1), | |
669 | PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1), | |
670 | PINMUX_IPSR_GPSR(IP3_19_16, QPOLA), | |
671 | ||
672 | PINMUX_IPSR_GPSR(IP3_23_20, A6), | |
673 | PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0), | |
674 | PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1), | |
675 | PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10), | |
676 | PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1), | |
677 | ||
678 | PINMUX_IPSR_GPSR(IP3_27_24, A7), | |
679 | PINMUX_IPSR_GPSR(IP3_27_24, TX4_A), | |
680 | PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B), | |
681 | PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11), | |
682 | PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1), | |
683 | ||
684 | PINMUX_IPSR_GPSR(IP3_31_28, A8), | |
685 | PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0), | |
686 | PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1), | |
687 | PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2), | |
688 | PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0), | |
689 | PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC), | |
690 | PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1), | |
691 | PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS), | |
692 | ||
693 | /* IPSR4 */ | |
694 | PINMUX_IPSR_GPSR(IP4_3_0, A9), | |
695 | PINMUX_IPSR_GPSR(IP4_3_0, TX5_A), | |
696 | PINMUX_IPSR_GPSR(IP4_3_0, IRQ3), | |
697 | PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16), | |
698 | PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0), | |
699 | PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7), | |
700 | PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15), | |
701 | ||
702 | PINMUX_IPSR_GPSR(IP4_7_4, A10), | |
703 | PINMUX_IPSR_GPSR(IP4_7_4, IRQ4), | |
704 | PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1), | |
705 | PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13), | |
706 | PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0), | |
707 | PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5), | |
708 | PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B), | |
709 | PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13), | |
710 | ||
711 | PINMUX_IPSR_GPSR(IP4_11_8, A11), | |
712 | PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0), | |
713 | PINMUX_IPSR_GPSR(IP4_11_8, TX3_B), | |
714 | PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C), | |
715 | PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC), | |
716 | PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1), | |
717 | PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS), | |
718 | ||
719 | PINMUX_IPSR_GPSR(IP4_15_12, A12), | |
720 | PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0), | |
721 | PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B), | |
722 | PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17), | |
723 | PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0), | |
724 | PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6), | |
725 | PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14), | |
726 | ||
727 | PINMUX_IPSR_GPSR(IP4_19_16, A13), | |
728 | PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0), | |
729 | PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1), | |
730 | PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14), | |
731 | PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3), | |
732 | PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2), | |
733 | PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2), | |
734 | ||
735 | PINMUX_IPSR_GPSR(IP4_23_20, A14), | |
736 | PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1), | |
737 | PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1), | |
738 | PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15), | |
739 | PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D), | |
740 | PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3), | |
741 | PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3), | |
742 | ||
743 | PINMUX_IPSR_GPSR(IP4_27_24, A15), | |
744 | PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2), | |
745 | PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B), | |
746 | PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18), | |
747 | PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0), | |
748 | PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4), | |
749 | PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4), | |
750 | ||
751 | PINMUX_IPSR_GPSR(IP4_31_28, A16), | |
752 | PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC), | |
753 | PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B), | |
754 | PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19), | |
755 | PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0), | |
756 | PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5), | |
757 | PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5), | |
758 | ||
759 | /* IPSR5 */ | |
760 | PINMUX_IPSR_GPSR(IP5_3_0, A17), | |
761 | PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), | |
762 | PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20), | |
763 | PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0), | |
764 | PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6), | |
765 | PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6), | |
766 | ||
767 | PINMUX_IPSR_GPSR(IP5_7_4, A18), | |
768 | PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), | |
769 | PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21), | |
770 | PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0), | |
771 | PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0), | |
772 | PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4), | |
773 | PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0), | |
774 | ||
775 | PINMUX_IPSR_GPSR(IP5_11_8, A19), | |
776 | PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), | |
777 | PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22), | |
778 | PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0), | |
779 | PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1), | |
780 | PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E), | |
781 | PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1), | |
782 | ||
783 | PINMUX_IPSR_GPSR(IP5_15_12, CS0_N), | |
784 | PINMUX_IPSR_GPSR(IP5_15_12, SCL5), | |
785 | PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0), | |
786 | PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1), | |
787 | PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16), | |
788 | ||
789 | PINMUX_IPSR_GPSR(IP5_19_16, WE0_N), | |
790 | PINMUX_IPSR_GPSR(IP5_19_16, SDA5), | |
791 | PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1), | |
792 | PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1), | |
793 | PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17), | |
794 | ||
795 | PINMUX_IPSR_GPSR(IP5_23_20, D0), | |
796 | PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), | |
797 | PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2), | |
798 | PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2), | |
799 | PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18), | |
800 | ||
801 | PINMUX_IPSR_GPSR(IP5_27_24, D1), | |
802 | PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0), | |
803 | PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0), | |
804 | PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), | |
805 | PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), | |
806 | PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), | |
807 | PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), | |
808 | PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), | |
809 | ||
810 | PINMUX_IPSR_GPSR(IP5_31_28, D2), | |
811 | PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0), | |
812 | PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2), | |
813 | PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0), | |
814 | PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3), | |
815 | PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2), | |
816 | PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19), | |
817 | ||
818 | /* IPSR6 */ | |
819 | PINMUX_IPSR_GPSR(IP6_3_0, D3), | |
820 | PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A), | |
821 | PINMUX_IPSR_GPSR(IP6_3_0, TX5_C), | |
822 | PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0), | |
823 | PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4), | |
824 | PINMUX_IPSR_GPSR(IP6_3_0, TX4_C), | |
825 | PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20), | |
826 | ||
827 | PINMUX_IPSR_GPSR(IP6_7_4, D4), | |
828 | PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), | |
829 | PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), | |
830 | PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), | |
831 | PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0), | |
832 | PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), | |
833 | PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), | |
834 | ||
835 | PINMUX_IPSR_GPSR(IP6_11_8, D5), | |
836 | PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0), | |
837 | PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1), | |
838 | PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5), | |
839 | PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1), | |
840 | PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21), | |
841 | ||
842 | PINMUX_IPSR_GPSR(IP6_15_12, D6), | |
843 | PINMUX_IPSR_GPSR(IP6_15_12, TX3_A), | |
844 | PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B), | |
845 | PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6), | |
846 | PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1), | |
847 | PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22), | |
848 | ||
849 | PINMUX_IPSR_GPSR(IP6_19_16, D7), | |
850 | PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX), | |
851 | PINMUX_IPSR_GPSR(IP6_19_16, IRQ5), | |
852 | PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX), | |
853 | PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0), | |
854 | PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1), | |
855 | ||
856 | PINMUX_IPSR_GPSR(IP6_23_20, D8), | |
857 | PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0), | |
858 | PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1), | |
859 | PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0), | |
860 | PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7), | |
861 | PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1), | |
862 | PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4), | |
863 | PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23), | |
864 | ||
865 | PINMUX_IPSR_GPSR(IP6_27_24, D9), | |
866 | PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0), | |
867 | PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0), | |
868 | PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0), | |
869 | PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1), | |
870 | PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4), | |
871 | PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8), | |
872 | ||
873 | PINMUX_IPSR_GPSR(IP6_31_28, D10), | |
874 | PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0), | |
875 | PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0), | |
876 | PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1), | |
877 | PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1), | |
878 | PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E), | |
879 | PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9), | |
880 | ||
881 | /* IPSR7 */ | |
882 | PINMUX_IPSR_GPSR(IP7_3_0, D11), | |
883 | PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A), | |
884 | PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0), | |
885 | PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2), | |
886 | PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1), | |
887 | PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4), | |
888 | PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10), | |
889 | ||
890 | PINMUX_IPSR_GPSR(IP7_7_4, D12), | |
891 | PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX), | |
892 | PINMUX_IPSR_GPSR(IP7_7_4, TX4_B), | |
893 | PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX), | |
894 | PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0), | |
895 | PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1), | |
896 | ||
897 | PINMUX_IPSR_GPSR(IP7_11_8, D13), | |
898 | PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX), | |
899 | PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1), | |
900 | PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX), | |
901 | PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0), | |
902 | PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1), | |
903 | PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1), | |
904 | ||
905 | PINMUX_IPSR_GPSR(IP7_15_12, D14), | |
906 | PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK), | |
907 | PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0), | |
908 | PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A), | |
909 | PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1), | |
910 | PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1), | |
911 | ||
912 | PINMUX_IPSR_GPSR(IP7_19_16, D15), | |
913 | PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A), | |
914 | PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A), | |
915 | PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A), | |
916 | PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3), | |
917 | PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11), | |
918 | ||
919 | PINMUX_IPSR_GPSR(IP7_23_20, SCL4), | |
920 | PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26), | |
921 | PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0), | |
922 | PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1), | |
923 | PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1), | |
924 | PINMUX_IPSR_GPSR(IP7_23_20, QCLK), | |
925 | ||
926 | PINMUX_IPSR_GPSR(IP7_27_24, SDA4), | |
927 | PINMUX_IPSR_GPSR(IP7_27_24, WE1_N), | |
928 | PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1), | |
929 | PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1), | |
930 | PINMUX_IPSR_GPSR(IP7_27_24, QPOLB), | |
931 | ||
932 | PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK), | |
933 | PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8), | |
934 | PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2), | |
935 | PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1), | |
936 | PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4), | |
937 | PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1), | |
938 | ||
939 | /* IPSR8 */ | |
940 | PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD), | |
941 | PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9), | |
942 | PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1), | |
943 | PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1), | |
944 | ||
945 | PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0), | |
946 | PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10), | |
947 | PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B), | |
948 | PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1), | |
949 | ||
950 | PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1), | |
951 | PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11), | |
952 | PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2), | |
953 | PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1), | |
954 | PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1), | |
955 | ||
956 | PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2), | |
957 | PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12), | |
958 | PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2), | |
959 | PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1), | |
960 | PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B), | |
961 | ||
962 | PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3), | |
963 | PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13), | |
964 | PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2), | |
965 | PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4), | |
966 | PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2), | |
967 | PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), | |
968 | ||
969 | PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), | |
970 | PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), | |
971 | ||
972 | PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), | |
973 | PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), | |
974 | ||
975 | PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), | |
976 | PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1), | |
977 | ||
978 | /* IPSR9 */ | |
979 | PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), | |
980 | PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1), | |
981 | ||
982 | PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), | |
983 | PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1), | |
984 | ||
985 | PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), | |
986 | PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1), | |
987 | ||
988 | PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), | |
989 | PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), | |
990 | ||
991 | PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD), | |
992 | PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N), | |
993 | ||
994 | PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0), | |
995 | PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0), | |
996 | ||
997 | PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1), | |
998 | PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1), | |
999 | ||
1000 | PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2), | |
1001 | PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2), | |
1002 | ||
1003 | /* IPSR10 */ | |
1004 | PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3), | |
1005 | PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3), | |
1006 | ||
1007 | PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4), | |
1008 | PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4), | |
1009 | ||
1010 | PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5), | |
1011 | PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5), | |
1012 | ||
1013 | PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6), | |
1014 | PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6), | |
1015 | ||
1016 | PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7), | |
1017 | PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7), | |
1018 | ||
1019 | PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS), | |
1020 | PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), | |
1021 | ||
1022 | PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), | |
1023 | PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A), | |
1024 | PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), | |
1025 | PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), | |
1026 | PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), | |
1027 | PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), | |
1028 | PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), | |
1029 | PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), | |
1030 | ||
1031 | PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), | |
1032 | PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A), | |
1033 | PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), | |
1034 | PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), | |
1035 | PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), | |
1036 | PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), | |
1037 | PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), | |
1038 | PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), | |
1039 | ||
1040 | /* IPSR11 */ | |
1041 | PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), | |
1042 | PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0), | |
1043 | PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), | |
1044 | PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), | |
1045 | PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), | |
1046 | ||
1047 | PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), | |
1048 | PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0), | |
1049 | PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), | |
1050 | PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), | |
1051 | PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), | |
1052 | ||
1053 | PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), | |
1054 | PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), | |
1055 | PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), | |
1056 | PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), | |
1057 | PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), | |
1058 | ||
1059 | PINMUX_IPSR_GPSR(IP11_15_12, TX0_A), | |
1060 | PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), | |
1061 | PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), | |
1062 | PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), | |
1063 | PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), | |
1064 | ||
1065 | PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), | |
1066 | PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0), | |
1067 | PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), | |
1068 | PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), | |
1069 | PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), | |
1070 | PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), | |
1071 | ||
1072 | PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0), | |
1073 | PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0), | |
1074 | PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), | |
1075 | PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), | |
1076 | PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), | |
1077 | PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0), | |
1078 | ||
1079 | PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), | |
1080 | PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), | |
1081 | PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), | |
1082 | PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), | |
1083 | PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), | |
1084 | PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), | |
747c5417 | 1085 | PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), |
6d4036a1 TK |
1086 | |
1087 | PINMUX_IPSR_GPSR(IP11_31_28, RX1), | |
1088 | PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1), | |
1089 | PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1), | |
1090 | PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B), | |
1091 | ||
1092 | /* IPSR12 */ | |
1093 | PINMUX_IPSR_GPSR(IP12_3_0, TX1), | |
1094 | PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B), | |
1095 | PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1), | |
1096 | PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B), | |
1097 | ||
1098 | PINMUX_IPSR_GPSR(IP12_7_4, SCK2_A), | |
1099 | PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0), | |
1100 | PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0), | |
1101 | PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N), | |
1102 | PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0), | |
1103 | PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0), | |
1104 | PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1), | |
1105 | ||
1106 | PINMUX_IPSR_GPSR(IP12_11_8, TX2_A), | |
1107 | PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0), | |
1108 | PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A), | |
1109 | PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0), | |
1110 | PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0), | |
1111 | PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1), | |
1112 | ||
1113 | PINMUX_IPSR_GPSR(IP12_15_12, RX2_A), | |
1114 | PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A), | |
1115 | PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A), | |
1116 | PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0), | |
1117 | PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0), | |
1118 | PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1), | |
1119 | ||
1120 | PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK), | |
1121 | PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78), | |
1122 | ||
1123 | PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD), | |
1124 | PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78), | |
1125 | PINMUX_IPSR_GPSR(IP12_23_20, TX2_B), | |
1126 | ||
1127 | PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD), | |
1128 | PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7), | |
1129 | PINMUX_IPSR_GPSR(IP12_27_24, RX2_B), | |
1130 | ||
1131 | PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), | |
1132 | PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B), | |
1133 | PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8), | |
1134 | ||
1135 | /* IPSR13 */ | |
1136 | PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), | |
1137 | PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0), | |
1138 | PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4), | |
1139 | PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0), | |
1140 | PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C), | |
1141 | PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0), | |
1142 | ||
1143 | PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), | |
1144 | PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A), | |
1145 | PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4), | |
1146 | PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0), | |
1147 | PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2), | |
1148 | PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A), | |
1149 | ||
1150 | PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9), | |
1151 | PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0), | |
1152 | PINMUX_IPSR_GPSR(IP13_11_8, SCK1), | |
1153 | ||
1154 | PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK), | |
1155 | PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1), | |
1156 | PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0), | |
1157 | PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1), | |
1158 | PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1), | |
1159 | PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A), | |
1160 | ||
1161 | PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG), | |
1162 | PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1), | |
1163 | PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), | |
1164 | PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), | |
1165 | PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), | |
1166 | PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), | |
1167 | ||
1168 | PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), | |
1169 | PINMUX_IPSR_GPSR(IP13_23_20, TX0_B), | |
1170 | PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0), | |
1171 | PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A), | |
1172 | ||
1173 | PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239), | |
1174 | ||
1175 | PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239), | |
1176 | ||
1177 | /* IPSR14 */ | |
1178 | PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0), | |
1179 | ||
1180 | PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1), | |
1181 | PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1), | |
1182 | PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1), | |
1183 | ||
1184 | PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2), | |
1185 | PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B), | |
1186 | PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0), | |
1187 | PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1), | |
1188 | ||
1189 | PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349), | |
1190 | PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2), | |
1191 | ||
1192 | PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349), | |
1193 | PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2), | |
1194 | ||
1195 | PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3), | |
1196 | PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C), | |
1197 | PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1), | |
1198 | PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1), | |
1199 | ||
1200 | PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4), | |
1201 | PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0), | |
1202 | PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1), | |
1203 | ||
1204 | PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5), | |
1205 | PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1), | |
1206 | PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B), | |
1207 | PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3), | |
1208 | PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1), | |
1209 | ||
1210 | /* IPSR15 */ | |
1211 | PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5), | |
1212 | PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B), | |
1213 | PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1), | |
1214 | PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3), | |
1215 | ||
1216 | PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5), | |
1217 | PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1), | |
1218 | PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2), | |
1219 | PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0), | |
1220 | ||
1221 | PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6), | |
1222 | PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0), | |
1223 | PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2), | |
1224 | PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1), | |
1225 | PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1), | |
1226 | PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B), | |
1227 | ||
1228 | PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6), | |
1229 | PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), | |
1230 | PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C), | |
1231 | PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), | |
1232 | PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), | |
1233 | PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), | |
1234 | PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), | |
1235 | ||
1236 | PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), | |
1237 | PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), | |
1238 | PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C), | |
1239 | PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3), | |
1240 | PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3), | |
1241 | PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1), | |
1242 | PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B), | |
1243 | ||
1244 | PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA), | |
1245 | ||
1246 | PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN), | |
1247 | PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A), | |
1248 | ||
1249 | PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC), | |
1250 | PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0), | |
83f6941a TK |
1251 | |
1252 | /* | |
1253 | * Static pins can not be muxed between different functions but | |
1254 | * still need mark entries in the pinmux list. Add each static | |
1255 | * pin to the list without an associated function. The sh-pfc | |
1256 | * core will do the right thing and skip trying to mux the pin | |
1257 | * while still applying configuration to it. | |
1258 | */ | |
1259 | #define FM(x) PINMUX_DATA(x##_MARK, 0), | |
1260 | PINMUX_STATIC | |
1261 | #undef FM | |
6d4036a1 TK |
1262 | }; |
1263 | ||
83f6941a TK |
1264 | /* |
1265 | * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs. | |
1266 | * Physical layout rows: A - AE, cols: 1 - 25. | |
1267 | */ | |
1268 | #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) | |
1269 | #define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300) | |
1270 | #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) | |
1271 | #define PIN_NONE U16_MAX | |
1272 | ||
6d4036a1 TK |
1273 | static const struct sh_pfc_pin pinmux_pins[] = { |
1274 | PINMUX_GPIO_GP_ALL(), | |
83f6941a TK |
1275 | |
1276 | /* | |
1277 | * Pins not associated with a GPIO port. | |
1278 | * | |
1279 | * The pin positions are different between different R8A77990 | |
1280 | * packages, all that is needed for the pfc driver is a unique | |
1281 | * number for each pin. To this end use the pin layout from | |
1282 | * R8A77990 to calculate a unique number for each pin. | |
1283 | */ | |
1284 | SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS), | |
1285 | SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS), | |
1286 | SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS), | |
1287 | SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS), | |
1288 | SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS), | |
1289 | SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS), | |
1290 | SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS), | |
1291 | SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS), | |
1292 | SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS), | |
1293 | SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS), | |
1294 | SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS), | |
1295 | SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS), | |
1296 | SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS), | |
1297 | SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS), | |
1298 | SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS), | |
1299 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS), | |
6d4036a1 TK |
1300 | }; |
1301 | ||
7cf9733f TK |
1302 | /* - EtherAVB --------------------------------------------------------------- */ |
1303 | static const unsigned int avb_link_pins[] = { | |
1304 | /* AVB_LINK */ | |
1305 | RCAR_GP_PIN(2, 23), | |
1306 | }; | |
1307 | ||
1308 | static const unsigned int avb_link_mux[] = { | |
1309 | AVB_LINK_MARK, | |
1310 | }; | |
1311 | ||
1312 | static const unsigned int avb_magic_pins[] = { | |
1313 | /* AVB_MAGIC */ | |
1314 | RCAR_GP_PIN(2, 22), | |
1315 | }; | |
1316 | ||
1317 | static const unsigned int avb_magic_mux[] = { | |
1318 | AVB_MAGIC_MARK, | |
1319 | }; | |
1320 | ||
1321 | static const unsigned int avb_phy_int_pins[] = { | |
1322 | /* AVB_PHY_INT */ | |
1323 | RCAR_GP_PIN(2, 21), | |
1324 | }; | |
1325 | ||
1326 | static const unsigned int avb_phy_int_mux[] = { | |
1327 | AVB_PHY_INT_MARK, | |
1328 | }; | |
1329 | ||
1330 | static const unsigned int avb_mii_pins[] = { | |
1331 | /* | |
1332 | * AVB_RX_CTL, AVB_RXC, AVB_RD0, | |
1333 | * AVB_RD1, AVB_RD2, AVB_RD3, | |
1334 | * AVB_TXCREFCLK | |
1335 | */ | |
1336 | RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), | |
1337 | RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), | |
1338 | RCAR_GP_PIN(2, 20), | |
1339 | }; | |
1340 | ||
1341 | static const unsigned int avb_mii_mux[] = { | |
1342 | AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, | |
1343 | AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, | |
1344 | AVB_TXCREFCLK_MARK, | |
1345 | }; | |
1346 | ||
1347 | static const unsigned int avb_avtp_pps_pins[] = { | |
1348 | /* AVB_AVTP_PPS */ | |
1349 | RCAR_GP_PIN(1, 2), | |
1350 | }; | |
1351 | ||
1352 | static const unsigned int avb_avtp_pps_mux[] = { | |
1353 | AVB_AVTP_PPS_MARK, | |
1354 | }; | |
1355 | ||
1356 | static const unsigned int avb_avtp_match_a_pins[] = { | |
1357 | /* AVB_AVTP_MATCH_A */ | |
1358 | RCAR_GP_PIN(2, 24), | |
1359 | }; | |
1360 | ||
1361 | static const unsigned int avb_avtp_match_a_mux[] = { | |
1362 | AVB_AVTP_MATCH_A_MARK, | |
1363 | }; | |
1364 | ||
1365 | static const unsigned int avb_avtp_capture_a_pins[] = { | |
1366 | /* AVB_AVTP_CAPTURE_A */ | |
1367 | RCAR_GP_PIN(2, 25), | |
1368 | }; | |
1369 | ||
1370 | static const unsigned int avb_avtp_capture_a_mux[] = { | |
1371 | AVB_AVTP_CAPTURE_A_MARK, | |
1372 | }; | |
1373 | ||
33f8dadc TK |
1374 | /* - I2C -------------------------------------------------------------------- */ |
1375 | static const unsigned int i2c1_a_pins[] = { | |
1376 | /* SCL, SDA */ | |
1377 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), | |
1378 | }; | |
1379 | ||
1380 | static const unsigned int i2c1_a_mux[] = { | |
1381 | SCL1_A_MARK, SDA1_A_MARK, | |
1382 | }; | |
1383 | ||
1384 | static const unsigned int i2c1_b_pins[] = { | |
1385 | /* SCL, SDA */ | |
1386 | RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), | |
1387 | }; | |
1388 | ||
1389 | static const unsigned int i2c1_b_mux[] = { | |
1390 | SCL1_B_MARK, SDA1_B_MARK, | |
1391 | }; | |
1392 | ||
1393 | static const unsigned int i2c1_c_pins[] = { | |
1394 | /* SCL, SDA */ | |
1395 | RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5), | |
1396 | }; | |
1397 | ||
1398 | static const unsigned int i2c1_c_mux[] = { | |
1399 | SCL1_C_MARK, SDA1_C_MARK, | |
1400 | }; | |
1401 | ||
1402 | static const unsigned int i2c1_d_pins[] = { | |
1403 | /* SCL, SDA */ | |
1404 | RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), | |
1405 | }; | |
1406 | ||
1407 | static const unsigned int i2c1_d_mux[] = { | |
1408 | SCL1_D_MARK, SDA1_D_MARK, | |
1409 | }; | |
1410 | ||
1411 | static const unsigned int i2c2_a_pins[] = { | |
1412 | /* SCL, SDA */ | |
1413 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0), | |
1414 | }; | |
1415 | ||
1416 | static const unsigned int i2c2_a_mux[] = { | |
1417 | SCL2_A_MARK, SDA2_A_MARK, | |
1418 | }; | |
1419 | ||
1420 | static const unsigned int i2c2_b_pins[] = { | |
1421 | /* SCL, SDA */ | |
1422 | RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), | |
1423 | }; | |
1424 | ||
1425 | static const unsigned int i2c2_b_mux[] = { | |
1426 | SCL2_B_MARK, SDA2_B_MARK, | |
1427 | }; | |
1428 | ||
1429 | static const unsigned int i2c2_c_pins[] = { | |
1430 | /* SCL, SDA */ | |
1431 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), | |
1432 | }; | |
1433 | ||
1434 | static const unsigned int i2c2_c_mux[] = { | |
1435 | SCL2_C_MARK, SDA2_C_MARK, | |
1436 | }; | |
1437 | ||
1438 | static const unsigned int i2c2_d_pins[] = { | |
1439 | /* SCL, SDA */ | |
1440 | RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), | |
1441 | }; | |
1442 | ||
1443 | static const unsigned int i2c2_d_mux[] = { | |
1444 | SCL2_D_MARK, SDA2_D_MARK, | |
1445 | }; | |
1446 | ||
1447 | static const unsigned int i2c2_e_pins[] = { | |
1448 | /* SCL, SDA */ | |
1449 | RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), | |
1450 | }; | |
1451 | ||
1452 | static const unsigned int i2c2_e_mux[] = { | |
1453 | SCL2_E_MARK, SDA2_E_MARK, | |
1454 | }; | |
1455 | ||
1456 | static const unsigned int i2c4_pins[] = { | |
1457 | /* SCL, SDA */ | |
1458 | RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), | |
1459 | }; | |
1460 | ||
1461 | static const unsigned int i2c4_mux[] = { | |
1462 | SCL4_MARK, SDA4_MARK, | |
1463 | }; | |
1464 | ||
1465 | static const unsigned int i2c5_pins[] = { | |
1466 | /* SCL, SDA */ | |
1467 | RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), | |
1468 | }; | |
1469 | ||
1470 | static const unsigned int i2c5_mux[] = { | |
1471 | SCL5_MARK, SDA5_MARK, | |
1472 | }; | |
1473 | ||
1474 | static const unsigned int i2c6_a_pins[] = { | |
1475 | /* SCL, SDA */ | |
1476 | RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), | |
1477 | }; | |
1478 | ||
1479 | static const unsigned int i2c6_a_mux[] = { | |
1480 | SCL6_A_MARK, SDA6_A_MARK, | |
1481 | }; | |
1482 | ||
1483 | static const unsigned int i2c6_b_pins[] = { | |
1484 | /* SCL, SDA */ | |
1485 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), | |
1486 | }; | |
1487 | ||
1488 | static const unsigned int i2c6_b_mux[] = { | |
1489 | SCL6_B_MARK, SDA6_B_MARK, | |
1490 | }; | |
1491 | ||
1492 | static const unsigned int i2c7_a_pins[] = { | |
1493 | /* SCL, SDA */ | |
1494 | RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25), | |
1495 | }; | |
1496 | ||
1497 | static const unsigned int i2c7_a_mux[] = { | |
1498 | SCL7_A_MARK, SDA7_A_MARK, | |
1499 | }; | |
1500 | ||
1501 | static const unsigned int i2c7_b_pins[] = { | |
1502 | /* SCL, SDA */ | |
1503 | RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), | |
1504 | }; | |
1505 | ||
1506 | static const unsigned int i2c7_b_mux[] = { | |
1507 | SCL7_B_MARK, SDA7_B_MARK, | |
1508 | }; | |
1509 | ||
6d3789e7 TK |
1510 | /* - SCIF0 ------------------------------------------------------------------ */ |
1511 | static const unsigned int scif0_data_a_pins[] = { | |
1512 | /* RX, TX */ | |
1513 | RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), | |
1514 | }; | |
1515 | ||
1516 | static const unsigned int scif0_data_a_mux[] = { | |
1517 | RX0_A_MARK, TX0_A_MARK, | |
1518 | }; | |
1519 | ||
1520 | static const unsigned int scif0_clk_a_pins[] = { | |
1521 | /* SCK */ | |
1522 | RCAR_GP_PIN(5, 0), | |
1523 | }; | |
1524 | ||
1525 | static const unsigned int scif0_clk_a_mux[] = { | |
1526 | SCK0_A_MARK, | |
1527 | }; | |
1528 | ||
1529 | static const unsigned int scif0_ctrl_a_pins[] = { | |
1530 | /* RTS, CTS */ | |
1531 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), | |
1532 | }; | |
1533 | ||
1534 | static const unsigned int scif0_ctrl_a_mux[] = { | |
1535 | RTS0_N_TANS_A_MARK, CTS0_N_A_MARK, | |
1536 | }; | |
1537 | ||
1538 | static const unsigned int scif0_data_b_pins[] = { | |
1539 | /* RX, TX */ | |
1540 | RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), | |
1541 | }; | |
1542 | ||
1543 | static const unsigned int scif0_data_b_mux[] = { | |
1544 | RX0_B_MARK, TX0_B_MARK, | |
1545 | }; | |
1546 | ||
1547 | static const unsigned int scif0_clk_b_pins[] = { | |
1548 | /* SCK */ | |
1549 | RCAR_GP_PIN(5, 18), | |
1550 | }; | |
1551 | ||
1552 | static const unsigned int scif0_clk_b_mux[] = { | |
1553 | SCK0_B_MARK, | |
1554 | }; | |
1555 | ||
1556 | /* - SCIF1 ------------------------------------------------------------------ */ | |
1557 | static const unsigned int scif1_data_pins[] = { | |
1558 | /* RX, TX */ | |
1559 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
1560 | }; | |
1561 | ||
1562 | static const unsigned int scif1_data_mux[] = { | |
1563 | RX1_MARK, TX1_MARK, | |
1564 | }; | |
1565 | ||
1566 | static const unsigned int scif1_clk_pins[] = { | |
1567 | /* SCK */ | |
1568 | RCAR_GP_PIN(5, 16), | |
1569 | }; | |
1570 | ||
1571 | static const unsigned int scif1_clk_mux[] = { | |
1572 | SCK1_MARK, | |
1573 | }; | |
1574 | ||
1575 | static const unsigned int scif1_ctrl_pins[] = { | |
1576 | /* RTS, CTS */ | |
1577 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7), | |
1578 | }; | |
1579 | ||
1580 | static const unsigned int scif1_ctrl_mux[] = { | |
1581 | RTS1_N_TANS_MARK, CTS1_N_MARK, | |
1582 | }; | |
1583 | ||
1584 | /* - SCIF2 ------------------------------------------------------------------ */ | |
1585 | static const unsigned int scif2_data_a_pins[] = { | |
1586 | /* RX, TX */ | |
1587 | RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), | |
1588 | }; | |
1589 | ||
1590 | static const unsigned int scif2_data_a_mux[] = { | |
1591 | RX2_A_MARK, TX2_A_MARK, | |
1592 | }; | |
1593 | ||
1594 | static const unsigned int scif2_clk_a_pins[] = { | |
1595 | /* SCK */ | |
1596 | RCAR_GP_PIN(5, 7), | |
1597 | }; | |
1598 | ||
1599 | static const unsigned int scif2_clk_a_mux[] = { | |
1600 | SCK2_A_MARK, | |
1601 | }; | |
1602 | ||
1603 | static const unsigned int scif2_data_b_pins[] = { | |
1604 | /* RX, TX */ | |
1605 | RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), | |
1606 | }; | |
1607 | ||
1608 | static const unsigned int scif2_data_b_mux[] = { | |
1609 | RX2_B_MARK, TX2_B_MARK, | |
1610 | }; | |
1611 | ||
1612 | /* - SCIF3 ------------------------------------------------------------------ */ | |
1613 | static const unsigned int scif3_data_a_pins[] = { | |
1614 | /* RX, TX */ | |
1615 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), | |
1616 | }; | |
1617 | ||
1618 | static const unsigned int scif3_data_a_mux[] = { | |
1619 | RX3_A_MARK, TX3_A_MARK, | |
1620 | }; | |
1621 | ||
1622 | static const unsigned int scif3_clk_a_pins[] = { | |
1623 | /* SCK */ | |
1624 | RCAR_GP_PIN(0, 1), | |
1625 | }; | |
1626 | ||
1627 | static const unsigned int scif3_clk_a_mux[] = { | |
1628 | SCK3_A_MARK, | |
1629 | }; | |
1630 | ||
1631 | static const unsigned int scif3_ctrl_a_pins[] = { | |
1632 | /* RTS, CTS */ | |
1633 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), | |
1634 | }; | |
1635 | ||
1636 | static const unsigned int scif3_ctrl_a_mux[] = { | |
1637 | RTS3_N_TANS_A_MARK, CTS3_N_A_MARK, | |
1638 | }; | |
1639 | ||
1640 | static const unsigned int scif3_data_b_pins[] = { | |
1641 | /* RX, TX */ | |
1642 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), | |
1643 | }; | |
1644 | ||
1645 | static const unsigned int scif3_data_b_mux[] = { | |
1646 | RX3_B_MARK, TX3_B_MARK, | |
1647 | }; | |
1648 | ||
1649 | static const unsigned int scif3_data_c_pins[] = { | |
1650 | /* RX, TX */ | |
1651 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), | |
1652 | }; | |
1653 | ||
1654 | static const unsigned int scif3_data_c_mux[] = { | |
1655 | RX3_C_MARK, TX3_C_MARK, | |
1656 | }; | |
1657 | ||
1658 | static const unsigned int scif3_clk_c_pins[] = { | |
1659 | /* SCK */ | |
1660 | RCAR_GP_PIN(2, 24), | |
1661 | }; | |
1662 | ||
1663 | static const unsigned int scif3_clk_c_mux[] = { | |
1664 | SCK3_C_MARK, | |
1665 | }; | |
1666 | ||
1667 | /* - SCIF4 ------------------------------------------------------------------ */ | |
1668 | static const unsigned int scif4_data_a_pins[] = { | |
1669 | /* RX, TX */ | |
1670 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
1671 | }; | |
1672 | ||
1673 | static const unsigned int scif4_data_a_mux[] = { | |
1674 | RX4_A_MARK, TX4_A_MARK, | |
1675 | }; | |
1676 | ||
1677 | static const unsigned int scif4_clk_a_pins[] = { | |
1678 | /* SCK */ | |
1679 | RCAR_GP_PIN(1, 5), | |
1680 | }; | |
1681 | ||
1682 | static const unsigned int scif4_clk_a_mux[] = { | |
1683 | SCK4_A_MARK, | |
1684 | }; | |
1685 | ||
1686 | static const unsigned int scif4_ctrl_a_pins[] = { | |
1687 | /* RTS, CTS */ | |
1688 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), | |
1689 | }; | |
1690 | ||
1691 | static const unsigned int scif4_ctrl_a_mux[] = { | |
1692 | RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, | |
1693 | }; | |
1694 | ||
1695 | static const unsigned int scif4_data_b_pins[] = { | |
1696 | /* RX, TX */ | |
1697 | RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), | |
1698 | }; | |
1699 | ||
1700 | static const unsigned int scif4_data_b_mux[] = { | |
1701 | RX4_B_MARK, TX4_B_MARK, | |
1702 | }; | |
1703 | ||
1704 | static const unsigned int scif4_clk_b_pins[] = { | |
1705 | /* SCK */ | |
1706 | RCAR_GP_PIN(0, 8), | |
1707 | }; | |
1708 | ||
1709 | static const unsigned int scif4_clk_b_mux[] = { | |
1710 | SCK4_B_MARK, | |
1711 | }; | |
1712 | ||
1713 | static const unsigned int scif4_data_c_pins[] = { | |
1714 | /* RX, TX */ | |
1715 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | |
1716 | }; | |
1717 | ||
1718 | static const unsigned int scif4_data_c_mux[] = { | |
1719 | RX4_C_MARK, TX4_C_MARK, | |
1720 | }; | |
1721 | ||
1722 | static const unsigned int scif4_ctrl_c_pins[] = { | |
1723 | /* RTS, CTS */ | |
1724 | RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), | |
1725 | }; | |
1726 | ||
1727 | static const unsigned int scif4_ctrl_c_mux[] = { | |
1728 | RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, | |
1729 | }; | |
1730 | ||
1731 | /* - SCIF5 ------------------------------------------------------------------ */ | |
1732 | static const unsigned int scif5_data_a_pins[] = { | |
1733 | /* RX, TX */ | |
1734 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9), | |
1735 | }; | |
1736 | ||
1737 | static const unsigned int scif5_data_a_mux[] = { | |
1738 | RX5_A_MARK, TX5_A_MARK, | |
1739 | }; | |
1740 | ||
1741 | static const unsigned int scif5_clk_a_pins[] = { | |
1742 | /* SCK */ | |
1743 | RCAR_GP_PIN(1, 13), | |
1744 | }; | |
1745 | ||
1746 | static const unsigned int scif5_clk_a_mux[] = { | |
1747 | SCK5_A_MARK, | |
1748 | }; | |
1749 | ||
1750 | static const unsigned int scif5_data_b_pins[] = { | |
1751 | /* RX, TX */ | |
1752 | RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), | |
1753 | }; | |
1754 | ||
1755 | static const unsigned int scif5_data_b_mux[] = { | |
1756 | RX5_B_MARK, TX5_B_MARK, | |
1757 | }; | |
1758 | ||
1759 | static const unsigned int scif5_data_c_pins[] = { | |
1760 | /* RX, TX */ | |
1761 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | |
1762 | }; | |
1763 | ||
1764 | static const unsigned int scif5_data_c_mux[] = { | |
1765 | RX5_C_MARK, TX5_C_MARK, | |
1766 | }; | |
1767 | ||
1768 | /* - SCIF Clock ------------------------------------------------------------- */ | |
1769 | static const unsigned int scif_clk_a_pins[] = { | |
1770 | /* SCIF_CLK */ | |
1771 | RCAR_GP_PIN(5, 3), | |
1772 | }; | |
1773 | ||
1774 | static const unsigned int scif_clk_a_mux[] = { | |
1775 | SCIF_CLK_A_MARK, | |
1776 | }; | |
1777 | ||
1778 | static const unsigned int scif_clk_b_pins[] = { | |
1779 | /* SCIF_CLK */ | |
1780 | RCAR_GP_PIN(5, 7), | |
1781 | }; | |
1782 | ||
1783 | static const unsigned int scif_clk_b_mux[] = { | |
1784 | SCIF_CLK_B_MARK, | |
1785 | }; | |
1786 | ||
d7b535f9 TK |
1787 | /* - USB0 ------------------------------------------------------------------- */ |
1788 | static const unsigned int usb0_a_pins[] = { | |
1789 | /* PWEN, OVC */ | |
1790 | RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), | |
1791 | }; | |
1792 | ||
1793 | static const unsigned int usb0_a_mux[] = { | |
1794 | USB0_PWEN_A_MARK, USB0_OVC_A_MARK, | |
1795 | }; | |
1796 | ||
1797 | static const unsigned int usb0_b_pins[] = { | |
1798 | /* PWEN, OVC */ | |
1799 | RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), | |
1800 | }; | |
1801 | ||
1802 | static const unsigned int usb0_b_mux[] = { | |
1803 | USB0_PWEN_B_MARK, USB0_OVC_B_MARK, | |
1804 | }; | |
1805 | ||
1806 | static const unsigned int usb0_id_pins[] = { | |
1807 | /* ID */ | |
1808 | RCAR_GP_PIN(5, 0) | |
1809 | }; | |
1810 | ||
1811 | static const unsigned int usb0_id_mux[] = { | |
1812 | USB0_ID_MARK, | |
1813 | }; | |
1814 | ||
6d4036a1 | 1815 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
7cf9733f TK |
1816 | SH_PFC_PIN_GROUP(avb_link), |
1817 | SH_PFC_PIN_GROUP(avb_magic), | |
1818 | SH_PFC_PIN_GROUP(avb_phy_int), | |
1819 | SH_PFC_PIN_GROUP(avb_mii), | |
1820 | SH_PFC_PIN_GROUP(avb_avtp_pps), | |
1821 | SH_PFC_PIN_GROUP(avb_avtp_match_a), | |
1822 | SH_PFC_PIN_GROUP(avb_avtp_capture_a), | |
33f8dadc TK |
1823 | SH_PFC_PIN_GROUP(i2c1_a), |
1824 | SH_PFC_PIN_GROUP(i2c1_b), | |
1825 | SH_PFC_PIN_GROUP(i2c1_c), | |
1826 | SH_PFC_PIN_GROUP(i2c1_d), | |
1827 | SH_PFC_PIN_GROUP(i2c2_a), | |
1828 | SH_PFC_PIN_GROUP(i2c2_b), | |
1829 | SH_PFC_PIN_GROUP(i2c2_c), | |
1830 | SH_PFC_PIN_GROUP(i2c2_d), | |
1831 | SH_PFC_PIN_GROUP(i2c2_e), | |
1832 | SH_PFC_PIN_GROUP(i2c4), | |
1833 | SH_PFC_PIN_GROUP(i2c5), | |
1834 | SH_PFC_PIN_GROUP(i2c6_a), | |
1835 | SH_PFC_PIN_GROUP(i2c6_b), | |
1836 | SH_PFC_PIN_GROUP(i2c7_a), | |
1837 | SH_PFC_PIN_GROUP(i2c7_b), | |
6d3789e7 TK |
1838 | SH_PFC_PIN_GROUP(scif0_data_a), |
1839 | SH_PFC_PIN_GROUP(scif0_clk_a), | |
1840 | SH_PFC_PIN_GROUP(scif0_ctrl_a), | |
1841 | SH_PFC_PIN_GROUP(scif0_data_b), | |
1842 | SH_PFC_PIN_GROUP(scif0_clk_b), | |
1843 | SH_PFC_PIN_GROUP(scif1_data), | |
1844 | SH_PFC_PIN_GROUP(scif1_clk), | |
1845 | SH_PFC_PIN_GROUP(scif1_ctrl), | |
1846 | SH_PFC_PIN_GROUP(scif2_data_a), | |
1847 | SH_PFC_PIN_GROUP(scif2_clk_a), | |
1848 | SH_PFC_PIN_GROUP(scif2_data_b), | |
1849 | SH_PFC_PIN_GROUP(scif3_data_a), | |
1850 | SH_PFC_PIN_GROUP(scif3_clk_a), | |
1851 | SH_PFC_PIN_GROUP(scif3_ctrl_a), | |
1852 | SH_PFC_PIN_GROUP(scif3_data_b), | |
1853 | SH_PFC_PIN_GROUP(scif3_data_c), | |
1854 | SH_PFC_PIN_GROUP(scif3_clk_c), | |
1855 | SH_PFC_PIN_GROUP(scif4_data_a), | |
1856 | SH_PFC_PIN_GROUP(scif4_clk_a), | |
1857 | SH_PFC_PIN_GROUP(scif4_ctrl_a), | |
1858 | SH_PFC_PIN_GROUP(scif4_data_b), | |
1859 | SH_PFC_PIN_GROUP(scif4_clk_b), | |
1860 | SH_PFC_PIN_GROUP(scif4_data_c), | |
1861 | SH_PFC_PIN_GROUP(scif4_ctrl_c), | |
1862 | SH_PFC_PIN_GROUP(scif5_data_a), | |
1863 | SH_PFC_PIN_GROUP(scif5_clk_a), | |
1864 | SH_PFC_PIN_GROUP(scif5_data_b), | |
1865 | SH_PFC_PIN_GROUP(scif5_data_c), | |
1866 | SH_PFC_PIN_GROUP(scif_clk_a), | |
1867 | SH_PFC_PIN_GROUP(scif_clk_b), | |
d7b535f9 TK |
1868 | SH_PFC_PIN_GROUP(usb0_a), |
1869 | SH_PFC_PIN_GROUP(usb0_b), | |
1870 | SH_PFC_PIN_GROUP(usb0_id), | |
6d3789e7 TK |
1871 | }; |
1872 | ||
7cf9733f TK |
1873 | static const char * const avb_groups[] = { |
1874 | "avb_link", | |
1875 | "avb_magic", | |
1876 | "avb_phy_int", | |
1877 | "avb_mii", | |
1878 | "avb_avtp_pps", | |
1879 | "avb_avtp_match_a", | |
1880 | "avb_avtp_capture_a", | |
1881 | }; | |
1882 | ||
33f8dadc TK |
1883 | static const char * const i2c1_groups[] = { |
1884 | "i2c1_a", | |
1885 | "i2c1_b", | |
1886 | "i2c1_c", | |
1887 | "i2c1_d", | |
1888 | }; | |
1889 | ||
1890 | static const char * const i2c2_groups[] = { | |
1891 | "i2c2_a", | |
1892 | "i2c2_b", | |
1893 | "i2c2_c", | |
1894 | "i2c2_d", | |
1895 | "i2c2_e", | |
1896 | }; | |
1897 | ||
1898 | static const char * const i2c4_groups[] = { | |
1899 | "i2c4", | |
1900 | }; | |
1901 | ||
1902 | static const char * const i2c5_groups[] = { | |
1903 | "i2c5", | |
1904 | }; | |
1905 | ||
1906 | static const char * const i2c6_groups[] = { | |
1907 | "i2c6_a", | |
1908 | "i2c6_b", | |
1909 | }; | |
1910 | ||
1911 | static const char * const i2c7_groups[] = { | |
1912 | "i2c7_a", | |
1913 | "i2c7_b", | |
1914 | }; | |
1915 | ||
6d3789e7 TK |
1916 | static const char * const scif0_groups[] = { |
1917 | "scif0_data_a", | |
1918 | "scif0_clk_a", | |
1919 | "scif0_ctrl_a", | |
1920 | "scif0_data_b", | |
1921 | "scif0_clk_b", | |
1922 | }; | |
1923 | ||
1924 | static const char * const scif1_groups[] = { | |
1925 | "scif1_data", | |
1926 | "scif1_clk", | |
1927 | "scif1_ctrl", | |
1928 | }; | |
1929 | ||
1930 | static const char * const scif2_groups[] = { | |
1931 | "scif2_data_a", | |
1932 | "scif2_clk_a", | |
1933 | "scif2_data_b", | |
1934 | }; | |
1935 | ||
1936 | static const char * const scif3_groups[] = { | |
1937 | "scif3_data_a", | |
1938 | "scif3_clk_a", | |
1939 | "scif3_ctrl_a", | |
1940 | "scif3_data_b", | |
1941 | "scif3_data_c", | |
1942 | "scif3_clk_c", | |
1943 | }; | |
1944 | ||
1945 | static const char * const scif4_groups[] = { | |
1946 | "scif4_data_a", | |
1947 | "scif4_clk_a", | |
1948 | "scif4_ctrl_a", | |
1949 | "scif4_data_b", | |
1950 | "scif4_clk_b", | |
1951 | "scif4_data_c", | |
1952 | "scif4_ctrl_c", | |
1953 | }; | |
1954 | ||
1955 | static const char * const scif5_groups[] = { | |
1956 | "scif5_data_a", | |
1957 | "scif5_clk_a", | |
1958 | "scif5_data_b", | |
1959 | "scif5_data_c", | |
1960 | }; | |
1961 | ||
1962 | static const char * const scif_clk_groups[] = { | |
1963 | "scif_clk_a", | |
1964 | "scif_clk_b", | |
6d4036a1 TK |
1965 | }; |
1966 | ||
d7b535f9 TK |
1967 | static const char * const usb0_groups[] = { |
1968 | "usb0_a", | |
1969 | "usb0_b", | |
1970 | "usb0_id", | |
1971 | }; | |
1972 | ||
6d4036a1 | 1973 | static const struct sh_pfc_function pinmux_functions[] = { |
7cf9733f | 1974 | SH_PFC_FUNCTION(avb), |
33f8dadc TK |
1975 | SH_PFC_FUNCTION(i2c1), |
1976 | SH_PFC_FUNCTION(i2c2), | |
1977 | SH_PFC_FUNCTION(i2c4), | |
1978 | SH_PFC_FUNCTION(i2c5), | |
1979 | SH_PFC_FUNCTION(i2c6), | |
1980 | SH_PFC_FUNCTION(i2c7), | |
6d3789e7 TK |
1981 | SH_PFC_FUNCTION(scif0), |
1982 | SH_PFC_FUNCTION(scif1), | |
1983 | SH_PFC_FUNCTION(scif2), | |
1984 | SH_PFC_FUNCTION(scif3), | |
1985 | SH_PFC_FUNCTION(scif4), | |
1986 | SH_PFC_FUNCTION(scif5), | |
1987 | SH_PFC_FUNCTION(scif_clk), | |
d7b535f9 | 1988 | SH_PFC_FUNCTION(usb0), |
6d4036a1 TK |
1989 | }; |
1990 | ||
1991 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | |
1992 | #define F_(x, y) FN_##y | |
1993 | #define FM(x) FN_##x | |
1994 | { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { | |
1995 | 0, 0, | |
1996 | 0, 0, | |
1997 | 0, 0, | |
1998 | 0, 0, | |
1999 | 0, 0, | |
2000 | 0, 0, | |
2001 | 0, 0, | |
2002 | 0, 0, | |
2003 | 0, 0, | |
2004 | 0, 0, | |
2005 | 0, 0, | |
2006 | 0, 0, | |
2007 | 0, 0, | |
2008 | 0, 0, | |
2009 | GP_0_17_FN, GPSR0_17, | |
2010 | GP_0_16_FN, GPSR0_16, | |
2011 | GP_0_15_FN, GPSR0_15, | |
2012 | GP_0_14_FN, GPSR0_14, | |
2013 | GP_0_13_FN, GPSR0_13, | |
2014 | GP_0_12_FN, GPSR0_12, | |
2015 | GP_0_11_FN, GPSR0_11, | |
2016 | GP_0_10_FN, GPSR0_10, | |
2017 | GP_0_9_FN, GPSR0_9, | |
2018 | GP_0_8_FN, GPSR0_8, | |
2019 | GP_0_7_FN, GPSR0_7, | |
2020 | GP_0_6_FN, GPSR0_6, | |
2021 | GP_0_5_FN, GPSR0_5, | |
2022 | GP_0_4_FN, GPSR0_4, | |
2023 | GP_0_3_FN, GPSR0_3, | |
2024 | GP_0_2_FN, GPSR0_2, | |
2025 | GP_0_1_FN, GPSR0_1, | |
2026 | GP_0_0_FN, GPSR0_0, } | |
2027 | }, | |
2028 | { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { | |
2029 | 0, 0, | |
2030 | 0, 0, | |
2031 | 0, 0, | |
2032 | 0, 0, | |
2033 | 0, 0, | |
2034 | 0, 0, | |
2035 | 0, 0, | |
2036 | 0, 0, | |
2037 | 0, 0, | |
2038 | GP_1_22_FN, GPSR1_22, | |
2039 | GP_1_21_FN, GPSR1_21, | |
2040 | GP_1_20_FN, GPSR1_20, | |
2041 | GP_1_19_FN, GPSR1_19, | |
2042 | GP_1_18_FN, GPSR1_18, | |
2043 | GP_1_17_FN, GPSR1_17, | |
2044 | GP_1_16_FN, GPSR1_16, | |
2045 | GP_1_15_FN, GPSR1_15, | |
2046 | GP_1_14_FN, GPSR1_14, | |
2047 | GP_1_13_FN, GPSR1_13, | |
2048 | GP_1_12_FN, GPSR1_12, | |
2049 | GP_1_11_FN, GPSR1_11, | |
2050 | GP_1_10_FN, GPSR1_10, | |
2051 | GP_1_9_FN, GPSR1_9, | |
2052 | GP_1_8_FN, GPSR1_8, | |
2053 | GP_1_7_FN, GPSR1_7, | |
2054 | GP_1_6_FN, GPSR1_6, | |
2055 | GP_1_5_FN, GPSR1_5, | |
2056 | GP_1_4_FN, GPSR1_4, | |
2057 | GP_1_3_FN, GPSR1_3, | |
2058 | GP_1_2_FN, GPSR1_2, | |
2059 | GP_1_1_FN, GPSR1_1, | |
2060 | GP_1_0_FN, GPSR1_0, } | |
2061 | }, | |
2062 | { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { | |
2063 | 0, 0, | |
2064 | 0, 0, | |
2065 | 0, 0, | |
2066 | 0, 0, | |
2067 | 0, 0, | |
2068 | 0, 0, | |
2069 | GP_2_25_FN, GPSR2_25, | |
2070 | GP_2_24_FN, GPSR2_24, | |
2071 | GP_2_23_FN, GPSR2_23, | |
2072 | GP_2_22_FN, GPSR2_22, | |
2073 | GP_2_21_FN, GPSR2_21, | |
2074 | GP_2_20_FN, GPSR2_20, | |
2075 | GP_2_19_FN, GPSR2_19, | |
2076 | GP_2_18_FN, GPSR2_18, | |
2077 | GP_2_17_FN, GPSR2_17, | |
2078 | GP_2_16_FN, GPSR2_16, | |
2079 | GP_2_15_FN, GPSR2_15, | |
2080 | GP_2_14_FN, GPSR2_14, | |
2081 | GP_2_13_FN, GPSR2_13, | |
2082 | GP_2_12_FN, GPSR2_12, | |
2083 | GP_2_11_FN, GPSR2_11, | |
2084 | GP_2_10_FN, GPSR2_10, | |
2085 | GP_2_9_FN, GPSR2_9, | |
2086 | GP_2_8_FN, GPSR2_8, | |
2087 | GP_2_7_FN, GPSR2_7, | |
2088 | GP_2_6_FN, GPSR2_6, | |
2089 | GP_2_5_FN, GPSR2_5, | |
2090 | GP_2_4_FN, GPSR2_4, | |
2091 | GP_2_3_FN, GPSR2_3, | |
2092 | GP_2_2_FN, GPSR2_2, | |
2093 | GP_2_1_FN, GPSR2_1, | |
2094 | GP_2_0_FN, GPSR2_0, } | |
2095 | }, | |
2096 | { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { | |
2097 | 0, 0, | |
2098 | 0, 0, | |
2099 | 0, 0, | |
2100 | 0, 0, | |
2101 | 0, 0, | |
2102 | 0, 0, | |
2103 | 0, 0, | |
2104 | 0, 0, | |
2105 | 0, 0, | |
2106 | 0, 0, | |
2107 | 0, 0, | |
2108 | 0, 0, | |
2109 | 0, 0, | |
2110 | 0, 0, | |
2111 | 0, 0, | |
2112 | 0, 0, | |
2113 | GP_3_15_FN, GPSR3_15, | |
2114 | GP_3_14_FN, GPSR3_14, | |
2115 | GP_3_13_FN, GPSR3_13, | |
2116 | GP_3_12_FN, GPSR3_12, | |
2117 | GP_3_11_FN, GPSR3_11, | |
2118 | GP_3_10_FN, GPSR3_10, | |
2119 | GP_3_9_FN, GPSR3_9, | |
2120 | GP_3_8_FN, GPSR3_8, | |
2121 | GP_3_7_FN, GPSR3_7, | |
2122 | GP_3_6_FN, GPSR3_6, | |
2123 | GP_3_5_FN, GPSR3_5, | |
2124 | GP_3_4_FN, GPSR3_4, | |
2125 | GP_3_3_FN, GPSR3_3, | |
2126 | GP_3_2_FN, GPSR3_2, | |
2127 | GP_3_1_FN, GPSR3_1, | |
2128 | GP_3_0_FN, GPSR3_0, } | |
2129 | }, | |
2130 | { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { | |
2131 | 0, 0, | |
2132 | 0, 0, | |
2133 | 0, 0, | |
2134 | 0, 0, | |
2135 | 0, 0, | |
2136 | 0, 0, | |
2137 | 0, 0, | |
2138 | 0, 0, | |
2139 | 0, 0, | |
2140 | 0, 0, | |
2141 | 0, 0, | |
2142 | 0, 0, | |
2143 | 0, 0, | |
2144 | 0, 0, | |
2145 | 0, 0, | |
2146 | 0, 0, | |
2147 | 0, 0, | |
2148 | 0, 0, | |
2149 | 0, 0, | |
2150 | 0, 0, | |
2151 | 0, 0, | |
2152 | GP_4_10_FN, GPSR4_10, | |
2153 | GP_4_9_FN, GPSR4_9, | |
2154 | GP_4_8_FN, GPSR4_8, | |
2155 | GP_4_7_FN, GPSR4_7, | |
2156 | GP_4_6_FN, GPSR4_6, | |
2157 | GP_4_5_FN, GPSR4_5, | |
2158 | GP_4_4_FN, GPSR4_4, | |
2159 | GP_4_3_FN, GPSR4_3, | |
2160 | GP_4_2_FN, GPSR4_2, | |
2161 | GP_4_1_FN, GPSR4_1, | |
2162 | GP_4_0_FN, GPSR4_0, } | |
2163 | }, | |
2164 | { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { | |
2165 | 0, 0, | |
2166 | 0, 0, | |
2167 | 0, 0, | |
2168 | 0, 0, | |
2169 | 0, 0, | |
2170 | 0, 0, | |
2171 | 0, 0, | |
2172 | 0, 0, | |
2173 | 0, 0, | |
2174 | 0, 0, | |
2175 | 0, 0, | |
2176 | 0, 0, | |
2177 | GP_5_19_FN, GPSR5_19, | |
2178 | GP_5_18_FN, GPSR5_18, | |
2179 | GP_5_17_FN, GPSR5_17, | |
2180 | GP_5_16_FN, GPSR5_16, | |
2181 | GP_5_15_FN, GPSR5_15, | |
2182 | GP_5_14_FN, GPSR5_14, | |
2183 | GP_5_13_FN, GPSR5_13, | |
2184 | GP_5_12_FN, GPSR5_12, | |
2185 | GP_5_11_FN, GPSR5_11, | |
2186 | GP_5_10_FN, GPSR5_10, | |
2187 | GP_5_9_FN, GPSR5_9, | |
2188 | GP_5_8_FN, GPSR5_8, | |
2189 | GP_5_7_FN, GPSR5_7, | |
2190 | GP_5_6_FN, GPSR5_6, | |
2191 | GP_5_5_FN, GPSR5_5, | |
2192 | GP_5_4_FN, GPSR5_4, | |
2193 | GP_5_3_FN, GPSR5_3, | |
2194 | GP_5_2_FN, GPSR5_2, | |
2195 | GP_5_1_FN, GPSR5_1, | |
2196 | GP_5_0_FN, GPSR5_0, } | |
2197 | }, | |
2198 | { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { | |
2199 | 0, 0, | |
2200 | 0, 0, | |
2201 | 0, 0, | |
2202 | 0, 0, | |
2203 | 0, 0, | |
2204 | 0, 0, | |
2205 | 0, 0, | |
2206 | 0, 0, | |
2207 | 0, 0, | |
2208 | 0, 0, | |
2209 | 0, 0, | |
2210 | 0, 0, | |
2211 | 0, 0, | |
2212 | 0, 0, | |
2213 | GP_6_17_FN, GPSR6_17, | |
2214 | GP_6_16_FN, GPSR6_16, | |
2215 | GP_6_15_FN, GPSR6_15, | |
2216 | GP_6_14_FN, GPSR6_14, | |
2217 | GP_6_13_FN, GPSR6_13, | |
2218 | GP_6_12_FN, GPSR6_12, | |
2219 | GP_6_11_FN, GPSR6_11, | |
2220 | GP_6_10_FN, GPSR6_10, | |
2221 | GP_6_9_FN, GPSR6_9, | |
2222 | GP_6_8_FN, GPSR6_8, | |
2223 | GP_6_7_FN, GPSR6_7, | |
2224 | GP_6_6_FN, GPSR6_6, | |
2225 | GP_6_5_FN, GPSR6_5, | |
2226 | GP_6_4_FN, GPSR6_4, | |
2227 | GP_6_3_FN, GPSR6_3, | |
2228 | GP_6_2_FN, GPSR6_2, | |
2229 | GP_6_1_FN, GPSR6_1, | |
2230 | GP_6_0_FN, GPSR6_0, } | |
2231 | }, | |
2232 | #undef F_ | |
2233 | #undef FM | |
2234 | ||
2235 | #define F_(x, y) x, | |
2236 | #define FM(x) FN_##x, | |
2237 | { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { | |
2238 | IP0_31_28 | |
2239 | IP0_27_24 | |
2240 | IP0_23_20 | |
2241 | IP0_19_16 | |
2242 | IP0_15_12 | |
2243 | IP0_11_8 | |
2244 | IP0_7_4 | |
2245 | IP0_3_0 } | |
2246 | }, | |
2247 | { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { | |
2248 | IP1_31_28 | |
2249 | IP1_27_24 | |
2250 | IP1_23_20 | |
2251 | IP1_19_16 | |
2252 | IP1_15_12 | |
2253 | IP1_11_8 | |
2254 | IP1_7_4 | |
2255 | IP1_3_0 } | |
2256 | }, | |
2257 | { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { | |
2258 | IP2_31_28 | |
2259 | IP2_27_24 | |
2260 | IP2_23_20 | |
2261 | IP2_19_16 | |
2262 | IP2_15_12 | |
2263 | IP2_11_8 | |
2264 | IP2_7_4 | |
2265 | IP2_3_0 } | |
2266 | }, | |
2267 | { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { | |
2268 | IP3_31_28 | |
2269 | IP3_27_24 | |
2270 | IP3_23_20 | |
2271 | IP3_19_16 | |
2272 | IP3_15_12 | |
2273 | IP3_11_8 | |
2274 | IP3_7_4 | |
2275 | IP3_3_0 } | |
2276 | }, | |
2277 | { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { | |
2278 | IP4_31_28 | |
2279 | IP4_27_24 | |
2280 | IP4_23_20 | |
2281 | IP4_19_16 | |
2282 | IP4_15_12 | |
2283 | IP4_11_8 | |
2284 | IP4_7_4 | |
2285 | IP4_3_0 } | |
2286 | }, | |
2287 | { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { | |
2288 | IP5_31_28 | |
2289 | IP5_27_24 | |
2290 | IP5_23_20 | |
2291 | IP5_19_16 | |
2292 | IP5_15_12 | |
2293 | IP5_11_8 | |
2294 | IP5_7_4 | |
2295 | IP5_3_0 } | |
2296 | }, | |
2297 | { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { | |
2298 | IP6_31_28 | |
2299 | IP6_27_24 | |
2300 | IP6_23_20 | |
2301 | IP6_19_16 | |
2302 | IP6_15_12 | |
2303 | IP6_11_8 | |
2304 | IP6_7_4 | |
2305 | IP6_3_0 } | |
2306 | }, | |
2307 | { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { | |
2308 | IP7_31_28 | |
2309 | IP7_27_24 | |
2310 | IP7_23_20 | |
2311 | IP7_19_16 | |
2312 | IP7_15_12 | |
2313 | IP7_11_8 | |
2314 | IP7_7_4 | |
2315 | IP7_3_0 } | |
2316 | }, | |
2317 | { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { | |
2318 | IP8_31_28 | |
2319 | IP8_27_24 | |
2320 | IP8_23_20 | |
2321 | IP8_19_16 | |
2322 | IP8_15_12 | |
2323 | IP8_11_8 | |
2324 | IP8_7_4 | |
2325 | IP8_3_0 } | |
2326 | }, | |
2327 | { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { | |
2328 | IP9_31_28 | |
2329 | IP9_27_24 | |
2330 | IP9_23_20 | |
2331 | IP9_19_16 | |
2332 | IP9_15_12 | |
2333 | IP9_11_8 | |
2334 | IP9_7_4 | |
2335 | IP9_3_0 } | |
2336 | }, | |
2337 | { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { | |
2338 | IP10_31_28 | |
2339 | IP10_27_24 | |
2340 | IP10_23_20 | |
2341 | IP10_19_16 | |
2342 | IP10_15_12 | |
2343 | IP10_11_8 | |
2344 | IP10_7_4 | |
2345 | IP10_3_0 } | |
2346 | }, | |
2347 | { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { | |
2348 | IP11_31_28 | |
2349 | IP11_27_24 | |
2350 | IP11_23_20 | |
2351 | IP11_19_16 | |
2352 | IP11_15_12 | |
2353 | IP11_11_8 | |
2354 | IP11_7_4 | |
2355 | IP11_3_0 } | |
2356 | }, | |
2357 | { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { | |
2358 | IP12_31_28 | |
2359 | IP12_27_24 | |
2360 | IP12_23_20 | |
2361 | IP12_19_16 | |
2362 | IP12_15_12 | |
2363 | IP12_11_8 | |
2364 | IP12_7_4 | |
2365 | IP12_3_0 } | |
2366 | }, | |
2367 | { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { | |
2368 | IP13_31_28 | |
2369 | IP13_27_24 | |
2370 | IP13_23_20 | |
2371 | IP13_19_16 | |
2372 | IP13_15_12 | |
2373 | IP13_11_8 | |
2374 | IP13_7_4 | |
2375 | IP13_3_0 } | |
2376 | }, | |
2377 | { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { | |
2378 | IP14_31_28 | |
2379 | IP14_27_24 | |
2380 | IP14_23_20 | |
2381 | IP14_19_16 | |
2382 | IP14_15_12 | |
2383 | IP14_11_8 | |
2384 | IP14_7_4 | |
2385 | IP14_3_0 } | |
2386 | }, | |
2387 | { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { | |
2388 | IP15_31_28 | |
2389 | IP15_27_24 | |
2390 | IP15_23_20 | |
2391 | IP15_19_16 | |
2392 | IP15_15_12 | |
2393 | IP15_11_8 | |
2394 | IP15_7_4 | |
2395 | IP15_3_0 } | |
2396 | }, | |
2397 | #undef F_ | |
2398 | #undef FM | |
2399 | ||
2400 | #define F_(x, y) x, | |
2401 | #define FM(x) FN_##x, | |
2402 | { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, | |
2403 | 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, | |
2404 | 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) { | |
2405 | /* RESERVED 31 */ | |
2406 | 0, 0, | |
2407 | MOD_SEL0_30_29 | |
2408 | MOD_SEL0_28 | |
2409 | MOD_SEL0_27_26 | |
2410 | MOD_SEL0_25 | |
2411 | MOD_SEL0_24 | |
2412 | MOD_SEL0_23 | |
2413 | MOD_SEL0_22 | |
2414 | MOD_SEL0_21_20 | |
2415 | MOD_SEL0_19_18_17 | |
2416 | MOD_SEL0_16 | |
2417 | MOD_SEL0_15 | |
2418 | MOD_SEL0_14 | |
2419 | MOD_SEL0_13_12 | |
2420 | MOD_SEL0_11_10 | |
2421 | MOD_SEL0_9 | |
2422 | MOD_SEL0_8 | |
2423 | MOD_SEL0_7 | |
2424 | MOD_SEL0_6_5 | |
2425 | MOD_SEL0_4 | |
2426 | MOD_SEL0_3 | |
2427 | MOD_SEL0_2 | |
2428 | MOD_SEL0_1_0 } | |
2429 | }, | |
2430 | { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, | |
2431 | 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, | |
2432 | 1, 2, 2, 2, 1, 1, 2, 1, 4) { | |
2433 | MOD_SEL1_31 | |
2434 | MOD_SEL1_30 | |
2435 | MOD_SEL1_29 | |
2436 | MOD_SEL1_28 | |
2437 | /* RESERVED 27 */ | |
2438 | 0, 0, | |
2439 | MOD_SEL1_26 | |
2440 | MOD_SEL1_25 | |
2441 | MOD_SEL1_24_23_22 | |
2442 | MOD_SEL1_21_20_19 | |
2443 | MOD_SEL1_18 | |
2444 | MOD_SEL1_17 | |
2445 | MOD_SEL1_16 | |
2446 | MOD_SEL1_15 | |
2447 | MOD_SEL1_14_13 | |
2448 | MOD_SEL1_12_11 | |
2449 | MOD_SEL1_10_9 | |
2450 | MOD_SEL1_8 | |
2451 | MOD_SEL1_7 | |
2452 | MOD_SEL1_6_5 | |
2453 | MOD_SEL1_4 | |
2454 | /* RESERVED 3, 2, 1, 0 */ | |
2455 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | |
2456 | }, | |
2457 | { }, | |
2458 | }; | |
2459 | ||
83f6941a TK |
2460 | static const struct pinmux_bias_reg pinmux_bias_regs[] = { |
2461 | { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { | |
2462 | [0] = RCAR_GP_PIN(2, 23), /* RD# */ | |
2463 | [1] = RCAR_GP_PIN(2, 22), /* BS# */ | |
2464 | [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */ | |
2465 | [3] = PIN_NUMBER('P', 5), /* AVB_MDC */ | |
2466 | [4] = PIN_NUMBER('P', 4), /* AVB_MDIO */ | |
2467 | [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */ | |
2468 | [6] = PIN_NUMBER('N', 6), /* AVB_TD3 */ | |
2469 | [7] = PIN_NUMBER('N', 5), /* AVB_TD2 */ | |
2470 | [8] = PIN_NUMBER('N', 3), /* AVB_TD1 */ | |
2471 | [9] = PIN_NUMBER('N', 2), /* AVB_TD0 */ | |
2472 | [10] = PIN_NUMBER('N', 1), /* AVB_TXC */ | |
2473 | [11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */ | |
2474 | [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */ | |
2475 | [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */ | |
2476 | [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */ | |
2477 | [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */ | |
2478 | [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */ | |
2479 | [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */ | |
2480 | [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */ | |
2481 | [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */ | |
2482 | [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */ | |
2483 | [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */ | |
2484 | [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */ | |
2485 | [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */ | |
2486 | [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */ | |
2487 | [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */ | |
2488 | [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */ | |
2489 | [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */ | |
2490 | [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */ | |
2491 | [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */ | |
2492 | [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */ | |
2493 | [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */ | |
2494 | } }, | |
2495 | { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { | |
2496 | [0] = RCAR_GP_PIN(0, 4), /* D4 */ | |
2497 | [1] = RCAR_GP_PIN(0, 3), /* D3 */ | |
2498 | [2] = RCAR_GP_PIN(0, 2), /* D2 */ | |
2499 | [3] = RCAR_GP_PIN(0, 1), /* D1 */ | |
2500 | [4] = RCAR_GP_PIN(0, 0), /* D0 */ | |
2501 | [5] = RCAR_GP_PIN(1, 22), /* WE0# */ | |
2502 | [6] = RCAR_GP_PIN(1, 21), /* CS0# */ | |
2503 | [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */ | |
2504 | [8] = RCAR_GP_PIN(1, 19), /* A19 */ | |
2505 | [9] = RCAR_GP_PIN(1, 18), /* A18 */ | |
2506 | [10] = RCAR_GP_PIN(1, 17), /* A17 */ | |
2507 | [11] = RCAR_GP_PIN(1, 16), /* A16 */ | |
2508 | [12] = RCAR_GP_PIN(1, 15), /* A15 */ | |
2509 | [13] = RCAR_GP_PIN(1, 14), /* A14 */ | |
2510 | [14] = RCAR_GP_PIN(1, 13), /* A13 */ | |
2511 | [15] = RCAR_GP_PIN(1, 12), /* A12 */ | |
2512 | [16] = RCAR_GP_PIN(1, 11), /* A11 */ | |
2513 | [17] = RCAR_GP_PIN(1, 10), /* A10 */ | |
2514 | [18] = RCAR_GP_PIN(1, 9), /* A9 */ | |
2515 | [19] = RCAR_GP_PIN(1, 8), /* A8 */ | |
2516 | [20] = RCAR_GP_PIN(1, 7), /* A7 */ | |
2517 | [21] = RCAR_GP_PIN(1, 6), /* A6 */ | |
2518 | [22] = RCAR_GP_PIN(1, 5), /* A5 */ | |
2519 | [23] = RCAR_GP_PIN(1, 4), /* A4 */ | |
2520 | [24] = RCAR_GP_PIN(1, 3), /* A3 */ | |
2521 | [25] = RCAR_GP_PIN(1, 2), /* A2 */ | |
2522 | [26] = RCAR_GP_PIN(1, 1), /* A1 */ | |
2523 | [27] = RCAR_GP_PIN(1, 0), /* A0 */ | |
2524 | [28] = PIN_NONE, | |
2525 | [29] = PIN_NONE, | |
2526 | [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */ | |
2527 | [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */ | |
2528 | } }, | |
2529 | { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { | |
2530 | [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ | |
2531 | [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ | |
2532 | [2] = PIN_NUMBER('H', 1), /* ASEBRK */ | |
2533 | [3] = PIN_NONE, | |
2534 | [4] = PIN_NUMBER('G', 2), /* TDI */ | |
2535 | [5] = PIN_NUMBER('F', 3), /* TMS */ | |
2536 | [6] = PIN_NUMBER('F', 4), /* TCK */ | |
2537 | [7] = PIN_NUMBER('F', 1), /* TRST# */ | |
2538 | [8] = PIN_NONE, | |
2539 | [9] = PIN_NONE, | |
2540 | [10] = PIN_NONE, | |
2541 | [11] = PIN_NONE, | |
2542 | [12] = PIN_NONE, | |
2543 | [13] = PIN_NONE, | |
2544 | [14] = PIN_NONE, | |
2545 | [15] = PIN_NUMBER('G', 3), /* FSCLKST# */ | |
2546 | [16] = RCAR_GP_PIN(0, 17), /* SDA4 */ | |
2547 | [17] = RCAR_GP_PIN(0, 16), /* SCL4 */ | |
2548 | [18] = PIN_NONE, | |
2549 | [19] = PIN_NONE, | |
2550 | [20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */ | |
2551 | [21] = RCAR_GP_PIN(0, 15), /* D15 */ | |
2552 | [22] = RCAR_GP_PIN(0, 14), /* D14 */ | |
2553 | [23] = RCAR_GP_PIN(0, 13), /* D13 */ | |
2554 | [24] = RCAR_GP_PIN(0, 12), /* D12 */ | |
2555 | [25] = RCAR_GP_PIN(0, 11), /* D11 */ | |
2556 | [26] = RCAR_GP_PIN(0, 10), /* D10 */ | |
2557 | [27] = RCAR_GP_PIN(0, 9), /* D9 */ | |
2558 | [28] = RCAR_GP_PIN(0, 8), /* D8 */ | |
2559 | [29] = RCAR_GP_PIN(0, 7), /* D7 */ | |
2560 | [30] = RCAR_GP_PIN(0, 6), /* D6 */ | |
2561 | [31] = RCAR_GP_PIN(0, 5), /* D5 */ | |
2562 | } }, | |
2563 | { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { | |
2564 | [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ | |
2565 | [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */ | |
2566 | [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ | |
2567 | [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ | |
2568 | [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ | |
2569 | [5] = PIN_NONE, | |
2570 | [6] = PIN_NONE, | |
2571 | [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */ | |
2572 | [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */ | |
2573 | [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ | |
2574 | [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */ | |
2575 | [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */ | |
2576 | [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */ | |
2577 | [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */ | |
2578 | [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */ | |
2579 | [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */ | |
2580 | [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */ | |
2581 | [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */ | |
2582 | [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */ | |
2583 | [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */ | |
2584 | [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */ | |
2585 | [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */ | |
2586 | [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ | |
2587 | [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ | |
2588 | [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ | |
2589 | [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ | |
2590 | [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ | |
2591 | [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ | |
2592 | [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ | |
2593 | [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ | |
2594 | [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ | |
2595 | [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ | |
2596 | } }, | |
2597 | { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { | |
2598 | [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */ | |
2599 | [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ | |
2600 | [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ | |
2601 | [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ | |
2602 | [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ | |
2603 | [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ | |
2604 | [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ | |
2605 | [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ | |
2606 | [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ | |
2607 | [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ | |
2608 | [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ | |
2609 | [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */ | |
2610 | [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */ | |
2611 | [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ | |
2612 | [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ | |
2613 | [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ | |
2614 | [16] = PIN_NUMBER('T', 21), /* MLB_REF */ | |
2615 | [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */ | |
2616 | [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */ | |
2617 | [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */ | |
2618 | [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */ | |
2619 | [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */ | |
2620 | [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */ | |
2621 | [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */ | |
2622 | [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */ | |
2623 | [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */ | |
2624 | [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */ | |
2625 | [27] = RCAR_GP_PIN(5, 9), /* RX2_A */ | |
2626 | [28] = RCAR_GP_PIN(5, 8), /* TX2_A */ | |
2627 | [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */ | |
2628 | [30] = RCAR_GP_PIN(5, 6), /* TX1 */ | |
2629 | [31] = RCAR_GP_PIN(5, 5), /* RX1 */ | |
2630 | } }, | |
2631 | { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { | |
2632 | [0] = PIN_NONE, | |
2633 | [1] = PIN_NONE, | |
2634 | [2] = PIN_NONE, | |
2635 | [3] = PIN_NONE, | |
2636 | [4] = PIN_NONE, | |
2637 | [5] = PIN_NONE, | |
2638 | [6] = PIN_NONE, | |
2639 | [7] = PIN_NONE, | |
2640 | [8] = PIN_NONE, | |
2641 | [9] = PIN_NONE, | |
2642 | [10] = PIN_NONE, | |
2643 | [11] = PIN_NONE, | |
2644 | [12] = PIN_NONE, | |
2645 | [13] = PIN_NONE, | |
2646 | [14] = PIN_NONE, | |
2647 | [15] = PIN_NONE, | |
2648 | [16] = PIN_NONE, | |
2649 | [17] = PIN_NONE, | |
2650 | [18] = PIN_NONE, | |
2651 | [19] = PIN_NONE, | |
2652 | [20] = PIN_NONE, | |
2653 | [21] = PIN_NONE, | |
2654 | [22] = PIN_NONE, | |
2655 | [23] = PIN_NONE, | |
2656 | [24] = PIN_NONE, | |
2657 | [25] = PIN_NONE, | |
2658 | [26] = PIN_NONE, | |
2659 | [27] = PIN_NONE, | |
2660 | [28] = PIN_NONE, | |
2661 | [29] = PIN_NONE, | |
2662 | [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */ | |
2663 | [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */ | |
2664 | } }, | |
2665 | { /* sentinel */ }, | |
2666 | }; | |
2667 | ||
2668 | static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc, | |
2669 | unsigned int pin) | |
2670 | { | |
2671 | const struct pinmux_bias_reg *reg; | |
2672 | unsigned int bit; | |
2673 | ||
2674 | reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); | |
2675 | if (!reg) | |
2676 | return PIN_CONFIG_BIAS_DISABLE; | |
2677 | ||
2678 | if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) | |
2679 | return PIN_CONFIG_BIAS_DISABLE; | |
2680 | else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) | |
2681 | return PIN_CONFIG_BIAS_PULL_UP; | |
2682 | else | |
2683 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
2684 | } | |
2685 | ||
2686 | static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, | |
2687 | unsigned int bias) | |
2688 | { | |
2689 | const struct pinmux_bias_reg *reg; | |
2690 | u32 enable, updown; | |
2691 | unsigned int bit; | |
2692 | ||
2693 | reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); | |
2694 | if (!reg) | |
2695 | return; | |
2696 | ||
2697 | enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); | |
2698 | if (bias != PIN_CONFIG_BIAS_DISABLE) | |
2699 | enable |= BIT(bit); | |
2700 | ||
2701 | updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); | |
2702 | if (bias == PIN_CONFIG_BIAS_PULL_UP) | |
2703 | updown |= BIT(bit); | |
2704 | ||
2705 | sh_pfc_write(pfc, reg->pud, updown); | |
2706 | sh_pfc_write(pfc, reg->puen, enable); | |
2707 | } | |
2708 | ||
2709 | static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { | |
2710 | .get_bias = r8a77990_pinmux_get_bias, | |
2711 | .set_bias = r8a77990_pinmux_set_bias, | |
2712 | }; | |
2713 | ||
6d4036a1 TK |
2714 | const struct sh_pfc_soc_info r8a77990_pinmux_info = { |
2715 | .name = "r8a77990_pfc", | |
83f6941a | 2716 | .ops = &r8a77990_pinmux_ops, |
6d4036a1 TK |
2717 | .unlock_reg = 0xe6060000, /* PMMR */ |
2718 | ||
2719 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
2720 | ||
2721 | .pins = pinmux_pins, | |
2722 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
2723 | .groups = pinmux_groups, | |
2724 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
2725 | .functions = pinmux_functions, | |
2726 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
2727 | ||
2728 | .cfg_regs = pinmux_config_regs, | |
83f6941a | 2729 | .bias_regs = pinmux_bias_regs, |
6d4036a1 TK |
2730 | |
2731 | .pinmux_data = pinmux_data, | |
2732 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
2733 | }; |