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pinctrl: sh-pfc: r8a7796: Fix to delete A20..A25 pins function definitions
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
CommitLineData
0b0ffc96 1/*
b205914c 2 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 3 *
b205914c 4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
0b0ffc96
TK		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
b205914c 12#include <linux/sys_soc.h>
0b0ffc96
TK		 13
14#include "core.h"
15#include "sh_pfc.h"
16
56065524
UH		 17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
0b0ffc96 21#define CPU_ALL_PORT(fn, sfx) \
56065524 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
82d2de5a 23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
56065524
UH		 24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
82d2de5a 58#define GPSR1_28 FM(CLKOUT)
0b0ffc96
TK		 59#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
60#define GPSR1_26 F_(WE1_N, IP5_7_4)
61#define GPSR1_25 F_(WE0_N, IP5_3_0)
62#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
63#define GPSR1_23 F_(RD_N, IP4_27_24)
64#define GPSR1_22 F_(BS_N, IP4_23_20)
fc8fd9be 65#define GPSR1_21 F_(CS1_N, IP4_19_16)
0b0ffc96
TK		 66#define GPSR1_20 F_(CS0_N, IP4_15_12)
67#define GPSR1_19 F_(A19, IP4_11_8)
68#define GPSR1_18 F_(A18, IP4_7_4)
69#define GPSR1_17 F_(A17, IP4_3_0)
70#define GPSR1_16 F_(A16, IP3_31_28)
71#define GPSR1_15 F_(A15, IP3_27_24)
72#define GPSR1_14 F_(A14, IP3_23_20)
73#define GPSR1_13 F_(A13, IP3_19_16)
74#define GPSR1_12 F_(A12, IP3_15_12)
75#define GPSR1_11 F_(A11, IP3_11_8)
76#define GPSR1_10 F_(A10, IP3_7_4)
77#define GPSR1_9 F_(A9, IP3_3_0)
78#define GPSR1_8 F_(A8, IP2_31_28)
79#define GPSR1_7 F_(A7, IP2_27_24)
80#define GPSR1_6 F_(A6, IP2_23_20)
81#define GPSR1_5 F_(A5, IP2_19_16)
82#define GPSR1_4 F_(A4, IP2_15_12)
83#define GPSR1_3 F_(A3, IP2_11_8)
84#define GPSR1_2 F_(A2, IP2_7_4)
85#define GPSR1_1 F_(A1, IP2_3_0)
86#define GPSR1_0 F_(A0, IP1_31_28)
87
88/* GPSR2 */
89#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
90#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
91#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
92#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
93#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
94#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
95#define GPSR2_8 F_(PWM2_A, IP1_27_24)
96#define GPSR2_7 F_(PWM1_A, IP1_23_20)
97#define GPSR2_6 F_(PWM0, IP1_19_16)
98#define GPSR2_5 F_(IRQ5, IP1_15_12)
99#define GPSR2_4 F_(IRQ4, IP1_11_8)
100#define GPSR2_3 F_(IRQ3, IP1_7_4)
101#define GPSR2_2 F_(IRQ2, IP1_3_0)
102#define GPSR2_1 F_(IRQ1, IP0_31_28)
103#define GPSR2_0 F_(IRQ0, IP0_27_24)
104
105/* GPSR3 */
b205914c
GU		 106#define GPSR3_15 F_(SD1_WP, IP11_23_20)
107#define GPSR3_14 F_(SD1_CD, IP11_19_16)
108#define GPSR3_13 F_(SD0_WP, IP11_15_12)
109#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 110#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
111#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
112#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
113#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
114#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
115#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
116#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
117#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
118#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
119#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
120#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
121#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
122
123/* GPSR4 */
b205914c
GU		 124#define GPSR4_17 F_(SD3_DS, IP11_7_4)
125#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
126#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
127#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
128#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
129#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
130#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
131#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
132#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
133#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
134#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
135#define GPSR4_6 F_(SD2_DS, IP9_27_24)
136#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
137#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
138#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
139#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
140#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 141#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
142
143/* GPSR5 */
b205914c
GU		 144#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
145#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
146#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 147#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 148#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 149#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 150#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
151#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 152#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 153#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
154#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
155#define GPSR5_14 F_(HTX0, IP13_19_16)
156#define GPSR5_13 F_(HRX0, IP13_15_12)
157#define GPSR5_12 F_(HSCK0, IP13_11_8)
158#define GPSR5_11 F_(RX2_A, IP13_7_4)
159#define GPSR5_10 F_(TX2_A, IP13_3_0)
160#define GPSR5_9 F_(SCK2, IP12_31_28)
161#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
162#define GPSR5_7 F_(CTS1_N, IP12_23_20)
163#define GPSR5_6 F_(TX1_A, IP12_19_16)
164#define GPSR5_5 F_(RX1_A, IP12_15_12)
165#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
166#define GPSR5_3 F_(CTS0_N, IP12_7_4)
167#define GPSR5_2 F_(TX0, IP12_3_0)
168#define GPSR5_1 F_(RX0, IP11_31_28)
169#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 170
171/* GPSR6 */
f9d13080
YS		 172#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
173#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
b205914c
GU		 174#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
175#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
176#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
177#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
178#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
179#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
180#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
181#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
182#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
183#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
184#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
185#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
186#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
187#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
188#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
189#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 190#define GPSR6_13 FM(SSI_SDATA5)
191#define GPSR6_12 FM(SSI_WS5)
192#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 193#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
194#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
195#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
196#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 197#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
198#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 199#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
200#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
201#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
202#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
203#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 204
205/* GPSR7 */
206#define GPSR7_3 FM(HDMI1_CEC)
207#define GPSR7_2 FM(HDMI0_CEC)
208#define GPSR7_1 FM(AVS2)
209#define GPSR7_0 FM(AVS1)
210
211
212/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
213#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 217#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96 218#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
e2ab1770
TK		 219#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 221#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
7716c51b
TK		 222#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 228#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232
233/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
234#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
fc8fd9be 251#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 252#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 274#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 283#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 288#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 306#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 307
308/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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GU		 309#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337
338/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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KM		 342#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 344#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
bad7cc19
TK		 364#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
365#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
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TK		 366
367#define PINMUX_GPSR \
368\
369 GPSR6_31 \
370 GPSR6_30 \
371 GPSR6_29 \
82d2de5a 372 GPSR1_28 GPSR6_28 \
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TK		 373 GPSR1_27 GPSR6_27 \
374 GPSR1_26 GPSR6_26 \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
401
402#define PINMUX_IPSR \
403\
404FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412\
413FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
30cd1c46 416FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
0b0ffc96
TK		 417FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421\
422FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430\
431FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439\
b205914c
GU		 440FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 448
449/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 450#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 451#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 455#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 468
469/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
ae03c4ec 472#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
0b0ffc96
TK		 473#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
eada11ac 483#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
0b0ffc96
TK		 484#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
492
493/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
494#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 497#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 500#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
501#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
502#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
503#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
504#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 505#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
506
b205914c 507#define PINMUX_MOD_SELS \
0b0ffc96 508\
b205914c
GU		 509MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
510 MOD_SEL2_30 \
0b0ffc96 511 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 512MOD_SEL0_28_27 MOD_SEL2_28_27 \
513MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
514 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 515MOD_SEL0_23 MOD_SEL1_23_22_21 \
3c612d2c 516MOD_SEL0_22 \
b205914c
GU		 517MOD_SEL0_21 MOD_SEL2_21 \
518MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
519MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
520MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
521 MOD_SEL2_17 \
522MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 523 MOD_SEL1_15_14 \
b205914c
GU		 524MOD_SEL0_14_13 \
525 MOD_SEL1_13 \
0b0ffc96
TK		 526MOD_SEL0_12 MOD_SEL1_12 \
527MOD_SEL0_11 MOD_SEL1_11 \
528MOD_SEL0_10 MOD_SEL1_10 \
b205914c 529MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 530MOD_SEL0_7_6 \
531 MOD_SEL1_6 \
b205914c
GU		 532MOD_SEL0_5 MOD_SEL1_5 \
533MOD_SEL0_4_3 MOD_SEL1_4 \
534 MOD_SEL1_3 \
535 MOD_SEL1_2 \
0b0ffc96
TK		 536 MOD_SEL1_1 \
537 MOD_SEL1_0 MOD_SEL2_0
538
ea9c7405
NS		 539/*
540 * These pins are not able to be muxed but have other properties
541 * that can be set, such as drive-strength or pull-up/pull-down enable.
542 */
543#define PINMUX_STATIC \
544 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
545 FM(QSPI0_IO2) FM(QSPI0_IO3) \
546 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
547 FM(QSPI1_IO2) FM(QSPI1_IO3) \
548 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
549 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
550 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
551 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
82d2de5a 552 FM(PRESETOUT) \
ea9c7405 553 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 554 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96
TK		 555
556enum {
557 PINMUX_RESERVED = 0,
558
559 PINMUX_DATA_BEGIN,
560 GP_ALL(DATA),
561 PINMUX_DATA_END,
562
563#define F_(x, y)
564#define FM(x) FN_##x,
565 PINMUX_FUNCTION_BEGIN,
566 GP_ALL(FN),
567 PINMUX_GPSR
568 PINMUX_IPSR
569 PINMUX_MOD_SELS
570 PINMUX_FUNCTION_END,
571#undef F_
572#undef FM
573
574#define F_(x, y)
575#define FM(x) x##_MARK,
576 PINMUX_MARK_BEGIN,
577 PINMUX_GPSR
578 PINMUX_IPSR
579 PINMUX_MOD_SELS
ea9c7405 580 PINMUX_STATIC
0b0ffc96
TK		 581 PINMUX_MARK_END,
582#undef F_
583#undef FM
584};
585
586static const u16 pinmux_data[] = {
587 PINMUX_DATA_GP_ALL(),
588
8d4df573
GU		 589 PINMUX_SINGLE(AVS1),
590 PINMUX_SINGLE(AVS2),
82d2de5a 591 PINMUX_SINGLE(CLKOUT),
8d4df573
GU		 592 PINMUX_SINGLE(HDMI0_CEC),
593 PINMUX_SINGLE(HDMI1_CEC),
d07640f5
KM		 594 PINMUX_SINGLE(I2C_SEL_0_1),
595 PINMUX_SINGLE(I2C_SEL_3_1),
596 PINMUX_SINGLE(I2C_SEL_5_1),
8d4df573
GU		 597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
0b0ffc96 604 /* IPSR0 */
e01678e3 605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
e01678e3 608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
e01678e3 612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
e01678e3 616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
b205914c 623 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
0b0ffc96
TK		 624
625 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
626 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
627 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
628
e01678e3
GU		 629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
631 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 632 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 635 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 636
e01678e3
GU		 637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 644
645 /* IPSR1 */
e01678e3
GU		 646 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
647 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
648 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 649 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 651 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 652
e01678e3
GU		 653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
e01678e3 655 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 656 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
657 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 658 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 659
e01678e3
GU		 660 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
661 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
e01678e3 662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 665 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 666
e01678e3
GU		 667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
e01678e3 669 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 670 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
671 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 672 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
673 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 674
e01678e3
GU		 675 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
676 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
0b0ffc96
TK		 677 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
679
680 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
0b0ffc96
TK		 681 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
682 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
684
685 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
0b0ffc96
TK		 686 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
687 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
688
e01678e3
GU		 689 PINMUX_IPSR_GPSR(IP1_31_28, A0),
690 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 691 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 692 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
693 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 694 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
695
696 /* IPSR2 */
e01678e3
GU		 697 PINMUX_IPSR_GPSR(IP2_3_0, A1),
698 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 699 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 700 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
701 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 702 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
703
e01678e3
GU		 704 PINMUX_IPSR_GPSR(IP2_7_4, A2),
705 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 706 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 707 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
708 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 709 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
710
e01678e3
GU		 711 PINMUX_IPSR_GPSR(IP2_11_8, A3),
712 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 713 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 714 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
715 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 716 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
717
e01678e3
GU		 718 PINMUX_IPSR_GPSR(IP2_15_12, A4),
719 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 720 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 721 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
722 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
723 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 724
e01678e3
GU		 725 PINMUX_IPSR_GPSR(IP2_19_16, A5),
726 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 727 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
728 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 729 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
730 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
731 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 732
e01678e3
GU		 733 PINMUX_IPSR_GPSR(IP2_23_20, A6),
734 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 735 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
736 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 737 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
738 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
739 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 740
e01678e3
GU		 741 PINMUX_IPSR_GPSR(IP2_27_24, A7),
742 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 743 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
744 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 745 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
746 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
747 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 748
e01678e3 749 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 750 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
751 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
752 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
753 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
754 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
756
757 /* IPSR3 */
e01678e3 758 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 759 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
760 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 761 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 762
e01678e3 763 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 764 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
765 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 766 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 767
e01678e3 768 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 769 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
770 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
771 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 772 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
773 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 774 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
776 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
777
e01678e3
GU		 778 PINMUX_IPSR_GPSR(IP3_15_12, A12),
779 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 780 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
781 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 782 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
783 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 784
e01678e3
GU		 785 PINMUX_IPSR_GPSR(IP3_19_16, A13),
786 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 787 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
788 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 789 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
790 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 791
e01678e3
GU		 792 PINMUX_IPSR_GPSR(IP3_23_20, A14),
793 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 794 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 795 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
796 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
797 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 798
e01678e3
GU		 799 PINMUX_IPSR_GPSR(IP3_27_24, A15),
800 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 801 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 802 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
803 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
804 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 805
e01678e3
GU		 806 PINMUX_IPSR_GPSR(IP3_31_28, A16),
807 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
808 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
809 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 810
811 /* IPSR4 */
e01678e3
GU		 812 PINMUX_IPSR_GPSR(IP4_3_0, A17),
813 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
814 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
815 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
816
817 PINMUX_IPSR_GPSR(IP4_7_4, A18),
818 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
819 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
820 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
821
822 PINMUX_IPSR_GPSR(IP4_11_8, A19),
823 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
824 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
825 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
826
827 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
828 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
829
fc8fd9be 830 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
e01678e3 831 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 832 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
833
e01678e3
GU		 834 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
835 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 836 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 837 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
838 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
839 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
840 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 841 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
842
e01678e3 843 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 844 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
845 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
846 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
849
e01678e3 850 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 851 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
852 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
856
857 /* IPSR5 */
e01678e3 858 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 859 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 860 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
861 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 862 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 863 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 864 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
865
e01678e3 866 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 867 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 868 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
869 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 870 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 871 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
872 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 873 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
874
875 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 876 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
877 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
878 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 879
e01678e3 880 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 881 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
882 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 883 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
884 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 885
e01678e3 886 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 887 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
888 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 889 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
890 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 891
e01678e3 892 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 893 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 894 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
895 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 896
e01678e3 897 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 898 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 899 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
900 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 901
e01678e3 902 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 903 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 904 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
905 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 906
907 /* IPSR6 */
e01678e3 908 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 909 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 910 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
911 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 912
b205914c
GU		 913 PINMUX_IPSR_GPSR(IP6_7_4, D6),
914 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
915 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
916 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 917
b205914c
GU		 918 PINMUX_IPSR_GPSR(IP6_11_8, D7),
919 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
920 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
921 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 922
b205914c
GU		 923 PINMUX_IPSR_GPSR(IP6_15_12, D8),
924 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
925 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
926 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
927 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
928 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 929
b205914c
GU		 930 PINMUX_IPSR_GPSR(IP6_19_16, D9),
931 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
932 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
933 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
934 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 935
b205914c
GU		 936 PINMUX_IPSR_GPSR(IP6_23_20, D10),
937 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
938 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
940 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
941 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
942 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 943
b205914c
GU		 944 PINMUX_IPSR_GPSR(IP6_27_24, D11),
945 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
946 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
947 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
948 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
949 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
950 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 951
b205914c
GU		 952 PINMUX_IPSR_GPSR(IP6_31_28, D12),
953 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
954 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
955 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
956 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
957 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 958
b205914c
GU		 959 /* IPSR7 */
960 PINMUX_IPSR_GPSR(IP7_3_0, D13),
961 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
962 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
963 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
964 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
965 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 966
b205914c
GU		 967 PINMUX_IPSR_GPSR(IP7_7_4, D14),
968 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
969 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
970 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
971 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
972 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
973 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 974
b205914c
GU		 975 PINMUX_IPSR_GPSR(IP7_11_8, D15),
976 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
977 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
978 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
979 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
980 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
981 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 982
b205914c
GU		 983 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
984 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
985 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 986
b205914c
GU		 987 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
988 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 990
b205914c
GU		 991 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
992 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
994 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 995
b205914c
GU		 996 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
997 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
998 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
999 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1000
b205914c
GU		 1001 /* IPSR8 */
1002 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1003 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1004 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1005 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1006
b205914c
GU		 1007 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1008 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1009 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1010 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1011
b205914c
GU		 1012 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1013 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1014 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1015
b205914c
GU		 1016 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1017 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
3c612d2c 1018 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
b205914c
GU		 1019 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1020 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1021
b205914c
GU		 1022 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1024 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
3c612d2c 1025 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
b205914c
GU		 1026 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1027 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1028
b205914c
GU		 1029 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1031 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
3c612d2c 1032 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
b205914c
GU		 1033 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1034 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1035
b205914c
GU		 1036 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1038 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
3c612d2c 1039 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
b205914c
GU		 1040 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1041 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1042
b205914c
GU		 1043 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1045 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
3c612d2c 1046 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
b205914c
GU		 1047 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1048 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1049
b205914c
GU		 1050 /* IPSR9 */
1051 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1052 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1053
b205914c
GU		 1054 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1055 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1056
b205914c
GU		 1057 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1058 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1059
b205914c
GU		 1060 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1061 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1062
b205914c
GU		 1063 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1064 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1065
b205914c
GU		 1066 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1067 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1068
b205914c
GU		 1069 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1070 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1071 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1072
b205914c
GU		 1073 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1074 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1075
b205914c
GU		 1076 /* IPSR10 */
1077 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1078 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1079
b205914c
GU		 1080 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1081 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1082
b205914c
GU		 1083 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1084 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1085
b205914c
GU		 1086 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1087 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1088
b205914c
GU		 1089 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1090 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1091
b205914c
GU		 1092 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1093 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1094 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1095
b205914c
GU		 1096 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1097 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1099
b205914c
GU		 1100 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1101 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1102 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1103
b205914c
GU		 1104 /* IPSR11 */
1105 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1106 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1107 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1108
1109 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1110 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1111
1112 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1113 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1114 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1115
1116 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1117 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1118
1119 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1120 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1121
1122 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1123 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1124
1125 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1126 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1127 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1128 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1129 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1132 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1133 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1135
1136 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1137 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1138 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1139 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1140 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1141
b205914c
GU		 1142 /* IPSR12 */
1143 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1144 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1145 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1146 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1147 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1148
1149 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1150 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1151 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1152 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1153 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1154 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1155 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1156 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1157
1158 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1159 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1160 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1161 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1162 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1163 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1164 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1165 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1166
1167 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1168 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1169 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1170 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1171 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1172
1173 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1176 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1177 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1178
1179 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1180 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1182 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1183 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1184 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1185 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1186
1187 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1188 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1190 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1191 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1192 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1193 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1194
1195 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
eada11ac 1196 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
b205914c
GU		 1197 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1198 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1199 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1200 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1201 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1202
b205914c
GU		 1203 /* IPSR13 */
1204 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1205 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1206 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1207 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1208 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1209 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1210
1211 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1212 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1213 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1214 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1215 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1216 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1217
1218 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1219 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1220 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1221 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1222 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1223 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1225 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1226
1227 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1228 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1229 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1230 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1231 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1232 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1233
1234 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1235 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1236 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1237 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1238 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1239 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1240
1241 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1242 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1243 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1244 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1245 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1246 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1247 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1248 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1249
1250 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1251 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1252 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1253 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1254 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1255 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1256 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1257
1258 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1259 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1260 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1261 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1262
b205914c
GU		 1263 /* IPSR14 */
1264 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1265 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
3c612d2c 1266 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
b205914c
GU		 1267 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1268 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1269 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1270 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
ae03c4ec 1271 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
b205914c
GU		 1272
1273 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1274 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1275 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1276 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1277 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1278 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1279 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1280 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1281
1282 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1283 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1284 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1287 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1288 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1289 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1292 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1293 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1294
1295 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1296 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1297
1298 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1299 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1300
1301 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1302 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1303
b205914c
GU		 1304 /* IPSR15 */
1305 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1306
1307 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1308 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1309
68e63892 1310 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1311 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1312 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1313
68e63892 1314 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1315 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1316 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1317 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1318
1319 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1320 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1321 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1322 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1323 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1324 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1326
1327 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1328 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1329 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1332 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1334
1335 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1336 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1337 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1338 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1340 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1342
1343 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1344 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1345 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1346 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1348 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1350
b205914c
GU		 1351 /* IPSR16 */
1352 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1353 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1354 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1355
1356 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1357 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1358 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1361 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1362 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1363
1364 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1365 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1366 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1367 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1368 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1369 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1370 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1371
1372 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1373 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1374 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1375 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1377 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1378 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1379
1380 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1381 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1385 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1386 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
ae03c4ec 1387 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
b205914c
GU		 1388
1389 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1390 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1391 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1392 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1393 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1394 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1395 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1396
1397 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1398 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1399 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1400 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1402 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
712f36fb 1404 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
20cacae1 1405
b205914c
GU		 1406 /* IPSR17 */
1407 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1408 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1409
1410 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
eada11ac 1411 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
b205914c
GU		 1412 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1413 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
ae03c4ec 1414 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
b205914c
GU		 1415
1416 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1417 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1418 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1419 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1420 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1421 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1422 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1423
1424 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1425 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1426 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1427 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1429 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1430
1431 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1432 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1433 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1434 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1435 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1436 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1437 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1438 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1439 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1440
1441 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1442 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1443 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1444 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1445 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1446 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1447 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1448 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1449 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1450
1451 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1452 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1453 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1454 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
50d83156 1455 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
b205914c
GU		 1456 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1457 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
ae03c4ec 1458 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
b205914c
GU		 1459 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1460 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1461 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1462
1463 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1464 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1465 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1466 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1467 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1468 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1469 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1470 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1471 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1472
1473 /* IPSR18 */
f9d13080 1474 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
b205914c
GU		 1475 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1476 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1477 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1478 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1479 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1480 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1481 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1482 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1483
f9d13080 1484 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
b205914c
GU		 1485 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1486 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1487 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1488 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1489 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1490 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1491 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1492 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1493
b205914c
GU		 1494/*
1495 * Static pins can not be muxed between different functions but
1496 * still needs a mark entry in the pinmux list. Add each static
1497 * pin to the list without an associated function. The sh-pfc
1498 * core will do the right thing and skip trying to mux then pin
1499 * while still applying configuration to it
1500 */
1501#define FM(x) PINMUX_DATA(x##_MARK, 0),
1502 PINMUX_STATIC
1503#undef FM
9b132ba3
KM		 1504};
1505
b205914c 1506/*
ecd54509 1507 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
b205914c
GU		 1508 * Physical layout rows: A - AW, cols: 1 - 39.
1509 */
1510#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1511#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1512#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
6f4b74f3 1513#define PIN_NONE U16_MAX
b205914c
GU		 1514
1515static const struct sh_pfc_pin pinmux_pins[] = {
1516 PINMUX_GPIO_GP_ALL(),
76250a6c 1517
b205914c
GU		 1518 /*
1519 * Pins not associated with a GPIO port.
1520 *
1521 * The pin positions are different between different r8a7795
1522 * packages, all that is needed for the pfc driver is a unique
1523 * number for each pin. To this end use the pin layout from
1524 * R-Car H3SiP to calculate a unique number for each pin.
1525 */
1526 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1527 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1528 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1529 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1570};
1571
55bfea9f
KM		 1572/* - AUDIO CLOCK ------------------------------------------------------------ */
1573static const unsigned int audio_clk_a_a_pins[] = {
1574 /* CLK A */
1575 RCAR_GP_PIN(6, 22),
1576};
1577static const unsigned int audio_clk_a_a_mux[] = {
1578 AUDIO_CLKA_A_MARK,
1579};
1580static const unsigned int audio_clk_a_b_pins[] = {
1581 /* CLK A */
1582 RCAR_GP_PIN(5, 4),
1583};
1584static const unsigned int audio_clk_a_b_mux[] = {
1585 AUDIO_CLKA_B_MARK,
1586};
1587static const unsigned int audio_clk_a_c_pins[] = {
1588 /* CLK A */
1589 RCAR_GP_PIN(5, 19),
1590};
1591static const unsigned int audio_clk_a_c_mux[] = {
1592 AUDIO_CLKA_C_MARK,
1593};
1594static const unsigned int audio_clk_b_a_pins[] = {
1595 /* CLK B */
1596 RCAR_GP_PIN(5, 12),
1597};
1598static const unsigned int audio_clk_b_a_mux[] = {
1599 AUDIO_CLKB_A_MARK,
1600};
1601static const unsigned int audio_clk_b_b_pins[] = {
1602 /* CLK B */
1603 RCAR_GP_PIN(6, 23),
1604};
1605static const unsigned int audio_clk_b_b_mux[] = {
1606 AUDIO_CLKB_B_MARK,
1607};
1608static const unsigned int audio_clk_c_a_pins[] = {
1609 /* CLK C */
1610 RCAR_GP_PIN(5, 21),
1611};
1612static const unsigned int audio_clk_c_a_mux[] = {
1613 AUDIO_CLKC_A_MARK,
1614};
1615static const unsigned int audio_clk_c_b_pins[] = {
1616 /* CLK C */
1617 RCAR_GP_PIN(5, 0),
1618};
1619static const unsigned int audio_clk_c_b_mux[] = {
1620 AUDIO_CLKC_B_MARK,
1621};
1622static const unsigned int audio_clkout_a_pins[] = {
1623 /* CLKOUT */
1624 RCAR_GP_PIN(5, 18),
1625};
1626static const unsigned int audio_clkout_a_mux[] = {
1627 AUDIO_CLKOUT_A_MARK,
1628};
1629static const unsigned int audio_clkout_b_pins[] = {
1630 /* CLKOUT */
1631 RCAR_GP_PIN(6, 28),
1632};
1633static const unsigned int audio_clkout_b_mux[] = {
1634 AUDIO_CLKOUT_B_MARK,
1635};
1636static const unsigned int audio_clkout_c_pins[] = {
1637 /* CLKOUT */
1638 RCAR_GP_PIN(5, 3),
1639};
1640static const unsigned int audio_clkout_c_mux[] = {
1641 AUDIO_CLKOUT_C_MARK,
1642};
1643static const unsigned int audio_clkout_d_pins[] = {
1644 /* CLKOUT */
1645 RCAR_GP_PIN(5, 21),
1646};
1647static const unsigned int audio_clkout_d_mux[] = {
1648 AUDIO_CLKOUT_D_MARK,
1649};
1650static const unsigned int audio_clkout1_a_pins[] = {
1651 /* CLKOUT1 */
1652 RCAR_GP_PIN(5, 15),
1653};
1654static const unsigned int audio_clkout1_a_mux[] = {
1655 AUDIO_CLKOUT1_A_MARK,
1656};
1657static const unsigned int audio_clkout1_b_pins[] = {
1658 /* CLKOUT1 */
1659 RCAR_GP_PIN(6, 29),
1660};
1661static const unsigned int audio_clkout1_b_mux[] = {
1662 AUDIO_CLKOUT1_B_MARK,
1663};
1664static const unsigned int audio_clkout2_a_pins[] = {
1665 /* CLKOUT2 */
1666 RCAR_GP_PIN(5, 16),
1667};
1668static const unsigned int audio_clkout2_a_mux[] = {
1669 AUDIO_CLKOUT2_A_MARK,
1670};
1671static const unsigned int audio_clkout2_b_pins[] = {
1672 /* CLKOUT2 */
1673 RCAR_GP_PIN(6, 30),
1674};
1675static const unsigned int audio_clkout2_b_mux[] = {
1676 AUDIO_CLKOUT2_B_MARK,
1677};
1678static const unsigned int audio_clkout3_a_pins[] = {
1679 /* CLKOUT3 */
1680 RCAR_GP_PIN(5, 19),
1681};
1682static const unsigned int audio_clkout3_a_mux[] = {
1683 AUDIO_CLKOUT3_A_MARK,
1684};
1685static const unsigned int audio_clkout3_b_pins[] = {
1686 /* CLKOUT3 */
1687 RCAR_GP_PIN(6, 31),
1688};
1689static const unsigned int audio_clkout3_b_mux[] = {
1690 AUDIO_CLKOUT3_B_MARK,
1691};
1692
30c078de
GU		 1693/* - EtherAVB --------------------------------------------------------------- */
1694static const unsigned int avb_link_pins[] = {
1695 /* AVB_LINK */
1696 RCAR_GP_PIN(2, 12),
1697};
1698static const unsigned int avb_link_mux[] = {
1699 AVB_LINK_MARK,
1700};
1701static const unsigned int avb_magic_pins[] = {
1702 /* AVB_MAGIC_ */
1703 RCAR_GP_PIN(2, 10),
1704};
1705static const unsigned int avb_magic_mux[] = {
1706 AVB_MAGIC_MARK,
1707};
1708static const unsigned int avb_phy_int_pins[] = {
1709 /* AVB_PHY_INT */
1710 RCAR_GP_PIN(2, 11),
1711};
1712static const unsigned int avb_phy_int_mux[] = {
1713 AVB_PHY_INT_MARK,
1714};
1715static const unsigned int avb_mdc_pins[] = {
1716 /* AVB_MDC, AVB_MDIO */
1717 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1718};
1719static const unsigned int avb_mdc_mux[] = {
1720 AVB_MDC_MARK, AVB_MDIO_MARK,
1721};
1722static const unsigned int avb_mii_pins[] = {
1723 /*
1724 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1725 * AVB_TD1, AVB_TD2, AVB_TD3,
1726 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1727 * AVB_RD1, AVB_RD2, AVB_RD3,
1728 * AVB_TXCREFCLK
1729 */
1730 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1731 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1732 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1733 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1734 PIN_NUMBER('A', 12),
1735
1736};
1737static const unsigned int avb_mii_mux[] = {
1738 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1739 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1740 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1741 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1742 AVB_TXCREFCLK_MARK,
1743};
1744static const unsigned int avb_avtp_pps_pins[] = {
1745 /* AVB_AVTP_PPS */
1746 RCAR_GP_PIN(2, 6),
1747};
1748static const unsigned int avb_avtp_pps_mux[] = {
1749 AVB_AVTP_PPS_MARK,
1750};
1751static const unsigned int avb_avtp_match_a_pins[] = {
1752 /* AVB_AVTP_MATCH_A */
1753 RCAR_GP_PIN(2, 13),
1754};
1755static const unsigned int avb_avtp_match_a_mux[] = {
1756 AVB_AVTP_MATCH_A_MARK,
1757};
1758static const unsigned int avb_avtp_capture_a_pins[] = {
1759 /* AVB_AVTP_CAPTURE_A */
1760 RCAR_GP_PIN(2, 14),
1761};
1762static const unsigned int avb_avtp_capture_a_mux[] = {
1763 AVB_AVTP_CAPTURE_A_MARK,
1764};
1765static const unsigned int avb_avtp_match_b_pins[] = {
1766 /* AVB_AVTP_MATCH_B */
1767 RCAR_GP_PIN(1, 8),
1768};
1769static const unsigned int avb_avtp_match_b_mux[] = {
1770 AVB_AVTP_MATCH_B_MARK,
1771};
1772static const unsigned int avb_avtp_capture_b_pins[] = {
1773 /* AVB_AVTP_CAPTURE_B */
1774 RCAR_GP_PIN(1, 11),
1775};
1776static const unsigned int avb_avtp_capture_b_mux[] = {
1777 AVB_AVTP_CAPTURE_B_MARK,
1778};
1779
a678abfe
RS		 1780/* - CAN ------------------------------------------------------------------ */
1781static const unsigned int can0_data_a_pins[] = {
1782 /* TX, RX */
1783 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1784};
1785static const unsigned int can0_data_a_mux[] = {
1786 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1787};
1788static const unsigned int can0_data_b_pins[] = {
1789 /* TX, RX */
1790 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1791};
1792static const unsigned int can0_data_b_mux[] = {
1793 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1794};
1795static const unsigned int can1_data_pins[] = {
1796 /* TX, RX */
1797 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1798};
1799static const unsigned int can1_data_mux[] = {
1800 CAN1_TX_MARK, CAN1_RX_MARK,
1801};
1802
1803/* - CAN Clock -------------------------------------------------------------- */
1804static const unsigned int can_clk_pins[] = {
1805 /* CLK */
1806 RCAR_GP_PIN(1, 25),
1807};
1808static const unsigned int can_clk_mux[] = {
1809 CAN_CLK_MARK,
1810};
1811
0e1c7a94
RS		 1812/* - CAN FD --------------------------------------------------------------- */
1813static const unsigned int canfd0_data_a_pins[] = {
1814 /* TX, RX */
1815 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1816};
1817static const unsigned int canfd0_data_a_mux[] = {
1818 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1819};
1820static const unsigned int canfd0_data_b_pins[] = {
1821 /* TX, RX */
1822 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1823};
1824static const unsigned int canfd0_data_b_mux[] = {
1825 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1826};
1827static const unsigned int canfd1_data_pins[] = {
1828 /* TX, RX */
1829 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1830};
1831static const unsigned int canfd1_data_mux[] = {
1832 CANFD1_TX_MARK, CANFD1_RX_MARK,
1833};
1834
641b0ab8
DB		 1835/* - DRIF0 --------------------------------------------------------------- */
1836static const unsigned int drif0_ctrl_a_pins[] = {
1837 /* CLK, SYNC */
1838 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1839};
1840static const unsigned int drif0_ctrl_a_mux[] = {
1841 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1842};
1843static const unsigned int drif0_data0_a_pins[] = {
1844 /* D0 */
1845 RCAR_GP_PIN(6, 10),
1846};
1847static const unsigned int drif0_data0_a_mux[] = {
1848 RIF0_D0_A_MARK,
1849};
1850static const unsigned int drif0_data1_a_pins[] = {
1851 /* D1 */
1852 RCAR_GP_PIN(6, 7),
1853};
1854static const unsigned int drif0_data1_a_mux[] = {
1855 RIF0_D1_A_MARK,
1856};
1857static const unsigned int drif0_ctrl_b_pins[] = {
1858 /* CLK, SYNC */
1859 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1860};
1861static const unsigned int drif0_ctrl_b_mux[] = {
1862 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1863};
1864static const unsigned int drif0_data0_b_pins[] = {
1865 /* D0 */
1866 RCAR_GP_PIN(5, 1),
1867};
1868static const unsigned int drif0_data0_b_mux[] = {
1869 RIF0_D0_B_MARK,
1870};
1871static const unsigned int drif0_data1_b_pins[] = {
1872 /* D1 */
1873 RCAR_GP_PIN(5, 2),
1874};
1875static const unsigned int drif0_data1_b_mux[] = {
1876 RIF0_D1_B_MARK,
1877};
1878static const unsigned int drif0_ctrl_c_pins[] = {
1879 /* CLK, SYNC */
1880 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1881};
1882static const unsigned int drif0_ctrl_c_mux[] = {
1883 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1884};
1885static const unsigned int drif0_data0_c_pins[] = {
1886 /* D0 */
1887 RCAR_GP_PIN(5, 13),
1888};
1889static const unsigned int drif0_data0_c_mux[] = {
1890 RIF0_D0_C_MARK,
1891};
1892static const unsigned int drif0_data1_c_pins[] = {
1893 /* D1 */
1894 RCAR_GP_PIN(5, 14),
1895};
1896static const unsigned int drif0_data1_c_mux[] = {
1897 RIF0_D1_C_MARK,
1898};
1899/* - DRIF1 --------------------------------------------------------------- */
1900static const unsigned int drif1_ctrl_a_pins[] = {
1901 /* CLK, SYNC */
1902 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1903};
1904static const unsigned int drif1_ctrl_a_mux[] = {
1905 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1906};
1907static const unsigned int drif1_data0_a_pins[] = {
1908 /* D0 */
1909 RCAR_GP_PIN(6, 19),
1910};
1911static const unsigned int drif1_data0_a_mux[] = {
1912 RIF1_D0_A_MARK,
1913};
1914static const unsigned int drif1_data1_a_pins[] = {
1915 /* D1 */
1916 RCAR_GP_PIN(6, 20),
1917};
1918static const unsigned int drif1_data1_a_mux[] = {
1919 RIF1_D1_A_MARK,
1920};
1921static const unsigned int drif1_ctrl_b_pins[] = {
1922 /* CLK, SYNC */
1923 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1924};
1925static const unsigned int drif1_ctrl_b_mux[] = {
1926 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1927};
1928static const unsigned int drif1_data0_b_pins[] = {
1929 /* D0 */
1930 RCAR_GP_PIN(5, 7),
1931};
1932static const unsigned int drif1_data0_b_mux[] = {
1933 RIF1_D0_B_MARK,
1934};
1935static const unsigned int drif1_data1_b_pins[] = {
1936 /* D1 */
1937 RCAR_GP_PIN(5, 8),
1938};
1939static const unsigned int drif1_data1_b_mux[] = {
1940 RIF1_D1_B_MARK,
1941};
1942static const unsigned int drif1_ctrl_c_pins[] = {
1943 /* CLK, SYNC */
1944 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1945};
1946static const unsigned int drif1_ctrl_c_mux[] = {
1947 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1948};
1949static const unsigned int drif1_data0_c_pins[] = {
1950 /* D0 */
1951 RCAR_GP_PIN(5, 6),
1952};
1953static const unsigned int drif1_data0_c_mux[] = {
1954 RIF1_D0_C_MARK,
1955};
1956static const unsigned int drif1_data1_c_pins[] = {
1957 /* D1 */
1958 RCAR_GP_PIN(5, 10),
1959};
1960static const unsigned int drif1_data1_c_mux[] = {
1961 RIF1_D1_C_MARK,
1962};
1963/* - DRIF2 --------------------------------------------------------------- */
1964static const unsigned int drif2_ctrl_a_pins[] = {
1965 /* CLK, SYNC */
1966 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1967};
1968static const unsigned int drif2_ctrl_a_mux[] = {
1969 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1970};
1971static const unsigned int drif2_data0_a_pins[] = {
1972 /* D0 */
1973 RCAR_GP_PIN(6, 7),
1974};
1975static const unsigned int drif2_data0_a_mux[] = {
1976 RIF2_D0_A_MARK,
1977};
1978static const unsigned int drif2_data1_a_pins[] = {
1979 /* D1 */
1980 RCAR_GP_PIN(6, 10),
1981};
1982static const unsigned int drif2_data1_a_mux[] = {
1983 RIF2_D1_A_MARK,
1984};
1985static const unsigned int drif2_ctrl_b_pins[] = {
1986 /* CLK, SYNC */
1987 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1988};
1989static const unsigned int drif2_ctrl_b_mux[] = {
1990 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1991};
1992static const unsigned int drif2_data0_b_pins[] = {
1993 /* D0 */
1994 RCAR_GP_PIN(6, 30),
1995};
1996static const unsigned int drif2_data0_b_mux[] = {
1997 RIF2_D0_B_MARK,
1998};
1999static const unsigned int drif2_data1_b_pins[] = {
2000 /* D1 */
2001 RCAR_GP_PIN(6, 31),
2002};
2003static const unsigned int drif2_data1_b_mux[] = {
2004 RIF2_D1_B_MARK,
2005};
2006/* - DRIF3 --------------------------------------------------------------- */
2007static const unsigned int drif3_ctrl_a_pins[] = {
2008 /* CLK, SYNC */
2009 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2010};
2011static const unsigned int drif3_ctrl_a_mux[] = {
2012 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2013};
2014static const unsigned int drif3_data0_a_pins[] = {
2015 /* D0 */
2016 RCAR_GP_PIN(6, 19),
2017};
2018static const unsigned int drif3_data0_a_mux[] = {
2019 RIF3_D0_A_MARK,
2020};
2021static const unsigned int drif3_data1_a_pins[] = {
2022 /* D1 */
2023 RCAR_GP_PIN(6, 20),
2024};
2025static const unsigned int drif3_data1_a_mux[] = {
2026 RIF3_D1_A_MARK,
2027};
2028static const unsigned int drif3_ctrl_b_pins[] = {
2029 /* CLK, SYNC */
2030 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2031};
2032static const unsigned int drif3_ctrl_b_mux[] = {
2033 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2034};
2035static const unsigned int drif3_data0_b_pins[] = {
2036 /* D0 */
2037 RCAR_GP_PIN(6, 28),
2038};
2039static const unsigned int drif3_data0_b_mux[] = {
2040 RIF3_D0_B_MARK,
2041};
2042static const unsigned int drif3_data1_b_pins[] = {
2043 /* D1 */
2044 RCAR_GP_PIN(6, 29),
2045};
2046static const unsigned int drif3_data1_b_mux[] = {
2047 RIF3_D1_B_MARK,
2048};
2049
a20a6585
LP		 2050/* - DU --------------------------------------------------------------------- */
2051static const unsigned int du_rgb666_pins[] = {
2052 /* R[7:2], G[7:2], B[7:2] */
2053 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2054 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2055 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2056 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2057 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2058 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2059};
2060static const unsigned int du_rgb666_mux[] = {
2061 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2062 DU_DR3_MARK, DU_DR2_MARK,
2063 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2064 DU_DG3_MARK, DU_DG2_MARK,
2065 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2066 DU_DB3_MARK, DU_DB2_MARK,
2067};
2068static const unsigned int du_rgb888_pins[] = {
2069 /* R[7:0], G[7:0], B[7:0] */
2070 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2071 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2072 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2073 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2074 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2075 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2076 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2077 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2078 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2079};
2080static const unsigned int du_rgb888_mux[] = {
2081 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2082 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2083 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2084 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2085 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2086 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2087};
2088static const unsigned int du_clk_out_0_pins[] = {
2089 /* CLKOUT */
2090 RCAR_GP_PIN(1, 27),
2091};
2092static const unsigned int du_clk_out_0_mux[] = {
2093 DU_DOTCLKOUT0_MARK
2094};
2095static const unsigned int du_clk_out_1_pins[] = {
2096 /* CLKOUT */
2097 RCAR_GP_PIN(2, 3),
2098};
2099static const unsigned int du_clk_out_1_mux[] = {
2100 DU_DOTCLKOUT1_MARK
2101};
2102static const unsigned int du_sync_pins[] = {
2103 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2104 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2105};
2106static const unsigned int du_sync_mux[] = {
2107 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2108};
2109static const unsigned int du_oddf_pins[] = {
2110 /* EXDISP/EXODDF/EXCDE */
2111 RCAR_GP_PIN(2, 2),
2112};
2113static const unsigned int du_oddf_mux[] = {
2114 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2115};
2116static const unsigned int du_cde_pins[] = {
2117 /* CDE */
2118 RCAR_GP_PIN(2, 0),
2119};
2120static const unsigned int du_cde_mux[] = {
2121 DU_CDE_MARK,
2122};
2123static const unsigned int du_disp_pins[] = {
2124 /* DISP */
2125 RCAR_GP_PIN(2, 1),
2126};
2127static const unsigned int du_disp_mux[] = {
2128 DU_DISP_MARK,
2129};
2130
7a362e34
WS		 2131/* - HSCIF0 ----------------------------------------------------------------- */
2132static const unsigned int hscif0_data_pins[] = {
2133 /* RX, TX */
2134 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2135};
2136static const unsigned int hscif0_data_mux[] = {
2137 HRX0_MARK, HTX0_MARK,
2138};
2139static const unsigned int hscif0_clk_pins[] = {
2140 /* SCK */
2141 RCAR_GP_PIN(5, 12),
2142};
2143static const unsigned int hscif0_clk_mux[] = {
2144 HSCK0_MARK,
2145};
2146static const unsigned int hscif0_ctrl_pins[] = {
2147 /* RTS, CTS */
2148 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2149};
2150static const unsigned int hscif0_ctrl_mux[] = {
2151 HRTS0_N_MARK, HCTS0_N_MARK,
2152};
2153/* - HSCIF1 ----------------------------------------------------------------- */
2154static const unsigned int hscif1_data_a_pins[] = {
2155 /* RX, TX */
2156 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2157};
2158static const unsigned int hscif1_data_a_mux[] = {
2159 HRX1_A_MARK, HTX1_A_MARK,
2160};
2161static const unsigned int hscif1_clk_a_pins[] = {
2162 /* SCK */
2163 RCAR_GP_PIN(6, 21),
2164};
2165static const unsigned int hscif1_clk_a_mux[] = {
2166 HSCK1_A_MARK,
2167};
2168static const unsigned int hscif1_ctrl_a_pins[] = {
2169 /* RTS, CTS */
2170 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2171};
2172static const unsigned int hscif1_ctrl_a_mux[] = {
2173 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2174};
2175
2176static const unsigned int hscif1_data_b_pins[] = {
2177 /* RX, TX */
2178 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2179};
2180static const unsigned int hscif1_data_b_mux[] = {
2181 HRX1_B_MARK, HTX1_B_MARK,
2182};
2183static const unsigned int hscif1_clk_b_pins[] = {
2184 /* SCK */
2185 RCAR_GP_PIN(5, 0),
2186};
2187static const unsigned int hscif1_clk_b_mux[] = {
2188 HSCK1_B_MARK,
2189};
2190static const unsigned int hscif1_ctrl_b_pins[] = {
2191 /* RTS, CTS */
2192 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2193};
2194static const unsigned int hscif1_ctrl_b_mux[] = {
2195 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2196};
2197/* - HSCIF2 ----------------------------------------------------------------- */
2198static const unsigned int hscif2_data_a_pins[] = {
2199 /* RX, TX */
2200 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2201};
2202static const unsigned int hscif2_data_a_mux[] = {
2203 HRX2_A_MARK, HTX2_A_MARK,
2204};
2205static const unsigned int hscif2_clk_a_pins[] = {
2206 /* SCK */
2207 RCAR_GP_PIN(6, 10),
2208};
2209static const unsigned int hscif2_clk_a_mux[] = {
2210 HSCK2_A_MARK,
2211};
2212static const unsigned int hscif2_ctrl_a_pins[] = {
2213 /* RTS, CTS */
2214 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2215};
2216static const unsigned int hscif2_ctrl_a_mux[] = {
2217 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2218};
2219
2220static const unsigned int hscif2_data_b_pins[] = {
2221 /* RX, TX */
2222 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2223};
2224static const unsigned int hscif2_data_b_mux[] = {
2225 HRX2_B_MARK, HTX2_B_MARK,
2226};
2227static const unsigned int hscif2_clk_b_pins[] = {
2228 /* SCK */
2229 RCAR_GP_PIN(6, 21),
2230};
2231static const unsigned int hscif2_clk_b_mux[] = {
2232 HSCK2_B_MARK,
2233};
2234static const unsigned int hscif2_ctrl_b_pins[] = {
2235 /* RTS, CTS */
2236 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2237};
2238static const unsigned int hscif2_ctrl_b_mux[] = {
2239 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2240};
2241
2242static const unsigned int hscif2_data_c_pins[] = {
2243 /* RX, TX */
2244 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2245};
2246static const unsigned int hscif2_data_c_mux[] = {
2247 HRX2_C_MARK, HTX2_C_MARK,
2248};
2249static const unsigned int hscif2_clk_c_pins[] = {
2250 /* SCK */
2251 RCAR_GP_PIN(6, 24),
2252};
2253static const unsigned int hscif2_clk_c_mux[] = {
2254 HSCK2_C_MARK,
2255};
2256static const unsigned int hscif2_ctrl_c_pins[] = {
2257 /* RTS, CTS */
2258 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2259};
2260static const unsigned int hscif2_ctrl_c_mux[] = {
2261 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2262};
2263/* - HSCIF3 ----------------------------------------------------------------- */
2264static const unsigned int hscif3_data_a_pins[] = {
2265 /* RX, TX */
2266 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2267};
2268static const unsigned int hscif3_data_a_mux[] = {
2269 HRX3_A_MARK, HTX3_A_MARK,
2270};
2271static const unsigned int hscif3_clk_pins[] = {
2272 /* SCK */
2273 RCAR_GP_PIN(1, 22),
2274};
2275static const unsigned int hscif3_clk_mux[] = {
2276 HSCK3_MARK,
2277};
2278static const unsigned int hscif3_ctrl_pins[] = {
2279 /* RTS, CTS */
2280 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2281};
2282static const unsigned int hscif3_ctrl_mux[] = {
2283 HRTS3_N_MARK, HCTS3_N_MARK,
2284};
2285
2286static const unsigned int hscif3_data_b_pins[] = {
2287 /* RX, TX */
2288 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2289};
2290static const unsigned int hscif3_data_b_mux[] = {
2291 HRX3_B_MARK, HTX3_B_MARK,
2292};
2293static const unsigned int hscif3_data_c_pins[] = {
2294 /* RX, TX */
2295 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2296};
2297static const unsigned int hscif3_data_c_mux[] = {
2298 HRX3_C_MARK, HTX3_C_MARK,
2299};
2300static const unsigned int hscif3_data_d_pins[] = {
2301 /* RX, TX */
2302 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2303};
2304static const unsigned int hscif3_data_d_mux[] = {
2305 HRX3_D_MARK, HTX3_D_MARK,
2306};
2307/* - HSCIF4 ----------------------------------------------------------------- */
2308static const unsigned int hscif4_data_a_pins[] = {
2309 /* RX, TX */
2310 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2311};
2312static const unsigned int hscif4_data_a_mux[] = {
2313 HRX4_A_MARK, HTX4_A_MARK,
2314};
2315static const unsigned int hscif4_clk_pins[] = {
2316 /* SCK */
2317 RCAR_GP_PIN(1, 11),
2318};
2319static const unsigned int hscif4_clk_mux[] = {
2320 HSCK4_MARK,
2321};
2322static const unsigned int hscif4_ctrl_pins[] = {
2323 /* RTS, CTS */
2324 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2325};
2326static const unsigned int hscif4_ctrl_mux[] = {
2327 HRTS4_N_MARK, HCTS4_N_MARK,
2328};
2329
2330static const unsigned int hscif4_data_b_pins[] = {
2331 /* RX, TX */
2332 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2333};
2334static const unsigned int hscif4_data_b_mux[] = {
2335 HRX4_B_MARK, HTX4_B_MARK,
2336};
2337
f62d4c9e
WS		 2338/* - I2C -------------------------------------------------------------------- */
2339static const unsigned int i2c1_a_pins[] = {
2340 /* SDA, SCL */
2341 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2342};
2343static const unsigned int i2c1_a_mux[] = {
2344 SDA1_A_MARK, SCL1_A_MARK,
2345};
2346static const unsigned int i2c1_b_pins[] = {
2347 /* SDA, SCL */
2348 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2349};
2350static const unsigned int i2c1_b_mux[] = {
2351 SDA1_B_MARK, SCL1_B_MARK,
2352};
2353static const unsigned int i2c2_a_pins[] = {
2354 /* SDA, SCL */
2355 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2356};
2357static const unsigned int i2c2_a_mux[] = {
2358 SDA2_A_MARK, SCL2_A_MARK,
2359};
2360static const unsigned int i2c2_b_pins[] = {
2361 /* SDA, SCL */
2362 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2363};
2364static const unsigned int i2c2_b_mux[] = {
2365 SDA2_B_MARK, SCL2_B_MARK,
2366};
2367static const unsigned int i2c6_a_pins[] = {
2368 /* SDA, SCL */
2369 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2370};
2371static const unsigned int i2c6_a_mux[] = {
2372 SDA6_A_MARK, SCL6_A_MARK,
2373};
2374static const unsigned int i2c6_b_pins[] = {
2375 /* SDA, SCL */
2376 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2377};
2378static const unsigned int i2c6_b_mux[] = {
2379 SDA6_B_MARK, SCL6_B_MARK,
2380};
2381static const unsigned int i2c6_c_pins[] = {
2382 /* SDA, SCL */
2383 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2384};
2385static const unsigned int i2c6_c_mux[] = {
2386 SDA6_C_MARK, SCL6_C_MARK,
2387};
2388
8480e6ca
GU		 2389/* - INTC-EX ---------------------------------------------------------------- */
2390static const unsigned int intc_ex_irq0_pins[] = {
2391 /* IRQ0 */
2392 RCAR_GP_PIN(2, 0),
2393};
2394static const unsigned int intc_ex_irq0_mux[] = {
2395 IRQ0_MARK,
2396};
2397static const unsigned int intc_ex_irq1_pins[] = {
2398 /* IRQ1 */
2399 RCAR_GP_PIN(2, 1),
2400};
2401static const unsigned int intc_ex_irq1_mux[] = {
2402 IRQ1_MARK,
2403};
2404static const unsigned int intc_ex_irq2_pins[] = {
2405 /* IRQ2 */
2406 RCAR_GP_PIN(2, 2),
2407};
2408static const unsigned int intc_ex_irq2_mux[] = {
2409 IRQ2_MARK,
2410};
2411static const unsigned int intc_ex_irq3_pins[] = {
2412 /* IRQ3 */
2413 RCAR_GP_PIN(2, 3),
2414};
2415static const unsigned int intc_ex_irq3_mux[] = {
2416 IRQ3_MARK,
2417};
2418static const unsigned int intc_ex_irq4_pins[] = {
2419 /* IRQ4 */
2420 RCAR_GP_PIN(2, 4),
2421};
2422static const unsigned int intc_ex_irq4_mux[] = {
2423 IRQ4_MARK,
2424};
2425static const unsigned int intc_ex_irq5_pins[] = {
2426 /* IRQ5 */
2427 RCAR_GP_PIN(2, 5),
2428};
2429static const unsigned int intc_ex_irq5_mux[] = {
2430 IRQ5_MARK,
2431};
2432
3e6c7727
GU		 2433/* - MSIOF0 ----------------------------------------------------------------- */
2434static const unsigned int msiof0_clk_pins[] = {
2435 /* SCK */
2436 RCAR_GP_PIN(5, 17),
2437};
2438static const unsigned int msiof0_clk_mux[] = {
2439 MSIOF0_SCK_MARK,
2440};
2441static const unsigned int msiof0_sync_pins[] = {
2442 /* SYNC */
2443 RCAR_GP_PIN(5, 18),
2444};
2445static const unsigned int msiof0_sync_mux[] = {
2446 MSIOF0_SYNC_MARK,
2447};
2448static const unsigned int msiof0_ss1_pins[] = {
2449 /* SS1 */
2450 RCAR_GP_PIN(5, 19),
2451};
2452static const unsigned int msiof0_ss1_mux[] = {
2453 MSIOF0_SS1_MARK,
2454};
2455static const unsigned int msiof0_ss2_pins[] = {
2456 /* SS2 */
2457 RCAR_GP_PIN(5, 21),
2458};
2459static const unsigned int msiof0_ss2_mux[] = {
2460 MSIOF0_SS2_MARK,
2461};
2462static const unsigned int msiof0_txd_pins[] = {
2463 /* TXD */
2464 RCAR_GP_PIN(5, 20),
2465};
2466static const unsigned int msiof0_txd_mux[] = {
2467 MSIOF0_TXD_MARK,
2468};
2469static const unsigned int msiof0_rxd_pins[] = {
2470 /* RXD */
2471 RCAR_GP_PIN(5, 22),
2472};
2473static const unsigned int msiof0_rxd_mux[] = {
2474 MSIOF0_RXD_MARK,
2475};
2476/* - MSIOF1 ----------------------------------------------------------------- */
2477static const unsigned int msiof1_clk_a_pins[] = {
2478 /* SCK */
2479 RCAR_GP_PIN(6, 8),
2480};
2481static const unsigned int msiof1_clk_a_mux[] = {
2482 MSIOF1_SCK_A_MARK,
2483};
2484static const unsigned int msiof1_sync_a_pins[] = {
2485 /* SYNC */
2486 RCAR_GP_PIN(6, 9),
2487};
2488static const unsigned int msiof1_sync_a_mux[] = {
2489 MSIOF1_SYNC_A_MARK,
2490};
2491static const unsigned int msiof1_ss1_a_pins[] = {
2492 /* SS1 */
2493 RCAR_GP_PIN(6, 5),
2494};
2495static const unsigned int msiof1_ss1_a_mux[] = {
2496 MSIOF1_SS1_A_MARK,
2497};
2498static const unsigned int msiof1_ss2_a_pins[] = {
2499 /* SS2 */
2500 RCAR_GP_PIN(6, 6),
2501};
2502static const unsigned int msiof1_ss2_a_mux[] = {
2503 MSIOF1_SS2_A_MARK,
2504};
2505static const unsigned int msiof1_txd_a_pins[] = {
2506 /* TXD */
2507 RCAR_GP_PIN(6, 7),
2508};
2509static const unsigned int msiof1_txd_a_mux[] = {
2510 MSIOF1_TXD_A_MARK,
2511};
2512static const unsigned int msiof1_rxd_a_pins[] = {
2513 /* RXD */
2514 RCAR_GP_PIN(6, 10),
2515};
2516static const unsigned int msiof1_rxd_a_mux[] = {
2517 MSIOF1_RXD_A_MARK,
2518};
2519static const unsigned int msiof1_clk_b_pins[] = {
2520 /* SCK */
2521 RCAR_GP_PIN(5, 9),
2522};
2523static const unsigned int msiof1_clk_b_mux[] = {
2524 MSIOF1_SCK_B_MARK,
2525};
2526static const unsigned int msiof1_sync_b_pins[] = {
2527 /* SYNC */
2528 RCAR_GP_PIN(5, 3),
2529};
2530static const unsigned int msiof1_sync_b_mux[] = {
2531 MSIOF1_SYNC_B_MARK,
2532};
2533static const unsigned int msiof1_ss1_b_pins[] = {
2534 /* SS1 */
2535 RCAR_GP_PIN(5, 4),
2536};
2537static const unsigned int msiof1_ss1_b_mux[] = {
2538 MSIOF1_SS1_B_MARK,
2539};
2540static const unsigned int msiof1_ss2_b_pins[] = {
2541 /* SS2 */
2542 RCAR_GP_PIN(5, 0),
2543};
2544static const unsigned int msiof1_ss2_b_mux[] = {
2545 MSIOF1_SS2_B_MARK,
2546};
2547static const unsigned int msiof1_txd_b_pins[] = {
2548 /* TXD */
2549 RCAR_GP_PIN(5, 8),
2550};
2551static const unsigned int msiof1_txd_b_mux[] = {
2552 MSIOF1_TXD_B_MARK,
2553};
2554static const unsigned int msiof1_rxd_b_pins[] = {
2555 /* RXD */
2556 RCAR_GP_PIN(5, 7),
2557};
2558static const unsigned int msiof1_rxd_b_mux[] = {
2559 MSIOF1_RXD_B_MARK,
2560};
2561static const unsigned int msiof1_clk_c_pins[] = {
2562 /* SCK */
2563 RCAR_GP_PIN(6, 17),
2564};
2565static const unsigned int msiof1_clk_c_mux[] = {
2566 MSIOF1_SCK_C_MARK,
2567};
2568static const unsigned int msiof1_sync_c_pins[] = {
2569 /* SYNC */
2570 RCAR_GP_PIN(6, 18),
2571};
2572static const unsigned int msiof1_sync_c_mux[] = {
2573 MSIOF1_SYNC_C_MARK,
2574};
2575static const unsigned int msiof1_ss1_c_pins[] = {
2576 /* SS1 */
2577 RCAR_GP_PIN(6, 21),
2578};
2579static const unsigned int msiof1_ss1_c_mux[] = {
2580 MSIOF1_SS1_C_MARK,
2581};
2582static const unsigned int msiof1_ss2_c_pins[] = {
2583 /* SS2 */
2584 RCAR_GP_PIN(6, 27),
2585};
2586static const unsigned int msiof1_ss2_c_mux[] = {
2587 MSIOF1_SS2_C_MARK,
2588};
2589static const unsigned int msiof1_txd_c_pins[] = {
2590 /* TXD */
2591 RCAR_GP_PIN(6, 20),
2592};
2593static const unsigned int msiof1_txd_c_mux[] = {
2594 MSIOF1_TXD_C_MARK,
2595};
2596static const unsigned int msiof1_rxd_c_pins[] = {
2597 /* RXD */
2598 RCAR_GP_PIN(6, 19),
2599};
2600static const unsigned int msiof1_rxd_c_mux[] = {
2601 MSIOF1_RXD_C_MARK,
2602};
2603static const unsigned int msiof1_clk_d_pins[] = {
2604 /* SCK */
2605 RCAR_GP_PIN(5, 12),
2606};
2607static const unsigned int msiof1_clk_d_mux[] = {
2608 MSIOF1_SCK_D_MARK,
2609};
2610static const unsigned int msiof1_sync_d_pins[] = {
2611 /* SYNC */
2612 RCAR_GP_PIN(5, 15),
2613};
2614static const unsigned int msiof1_sync_d_mux[] = {
2615 MSIOF1_SYNC_D_MARK,
2616};
2617static const unsigned int msiof1_ss1_d_pins[] = {
2618 /* SS1 */
2619 RCAR_GP_PIN(5, 16),
2620};
2621static const unsigned int msiof1_ss1_d_mux[] = {
2622 MSIOF1_SS1_D_MARK,
2623};
2624static const unsigned int msiof1_ss2_d_pins[] = {
2625 /* SS2 */
2626 RCAR_GP_PIN(5, 21),
2627};
2628static const unsigned int msiof1_ss2_d_mux[] = {
2629 MSIOF1_SS2_D_MARK,
2630};
2631static const unsigned int msiof1_txd_d_pins[] = {
2632 /* TXD */
2633 RCAR_GP_PIN(5, 14),
2634};
2635static const unsigned int msiof1_txd_d_mux[] = {
2636 MSIOF1_TXD_D_MARK,
2637};
2638static const unsigned int msiof1_rxd_d_pins[] = {
2639 /* RXD */
2640 RCAR_GP_PIN(5, 13),
2641};
2642static const unsigned int msiof1_rxd_d_mux[] = {
2643 MSIOF1_RXD_D_MARK,
2644};
2645static const unsigned int msiof1_clk_e_pins[] = {
2646 /* SCK */
2647 RCAR_GP_PIN(3, 0),
2648};
2649static const unsigned int msiof1_clk_e_mux[] = {
2650 MSIOF1_SCK_E_MARK,
2651};
2652static const unsigned int msiof1_sync_e_pins[] = {
2653 /* SYNC */
2654 RCAR_GP_PIN(3, 1),
2655};
2656static const unsigned int msiof1_sync_e_mux[] = {
2657 MSIOF1_SYNC_E_MARK,
2658};
2659static const unsigned int msiof1_ss1_e_pins[] = {
2660 /* SS1 */
2661 RCAR_GP_PIN(3, 4),
2662};
2663static const unsigned int msiof1_ss1_e_mux[] = {
2664 MSIOF1_SS1_E_MARK,
2665};
2666static const unsigned int msiof1_ss2_e_pins[] = {
2667 /* SS2 */
2668 RCAR_GP_PIN(3, 5),
2669};
2670static const unsigned int msiof1_ss2_e_mux[] = {
2671 MSIOF1_SS2_E_MARK,
2672};
2673static const unsigned int msiof1_txd_e_pins[] = {
2674 /* TXD */
2675 RCAR_GP_PIN(3, 3),
2676};
2677static const unsigned int msiof1_txd_e_mux[] = {
2678 MSIOF1_TXD_E_MARK,
2679};
2680static const unsigned int msiof1_rxd_e_pins[] = {
2681 /* RXD */
2682 RCAR_GP_PIN(3, 2),
2683};
2684static const unsigned int msiof1_rxd_e_mux[] = {
2685 MSIOF1_RXD_E_MARK,
2686};
2687static const unsigned int msiof1_clk_f_pins[] = {
2688 /* SCK */
2689 RCAR_GP_PIN(5, 23),
2690};
2691static const unsigned int msiof1_clk_f_mux[] = {
2692 MSIOF1_SCK_F_MARK,
2693};
2694static const unsigned int msiof1_sync_f_pins[] = {
2695 /* SYNC */
2696 RCAR_GP_PIN(5, 24),
2697};
2698static const unsigned int msiof1_sync_f_mux[] = {
2699 MSIOF1_SYNC_F_MARK,
2700};
2701static const unsigned int msiof1_ss1_f_pins[] = {
2702 /* SS1 */
2703 RCAR_GP_PIN(6, 1),
2704};
2705static const unsigned int msiof1_ss1_f_mux[] = {
2706 MSIOF1_SS1_F_MARK,
2707};
2708static const unsigned int msiof1_ss2_f_pins[] = {
2709 /* SS2 */
2710 RCAR_GP_PIN(6, 2),
2711};
2712static const unsigned int msiof1_ss2_f_mux[] = {
2713 MSIOF1_SS2_F_MARK,
2714};
2715static const unsigned int msiof1_txd_f_pins[] = {
2716 /* TXD */
2717 RCAR_GP_PIN(6, 0),
2718};
2719static const unsigned int msiof1_txd_f_mux[] = {
2720 MSIOF1_TXD_F_MARK,
2721};
2722static const unsigned int msiof1_rxd_f_pins[] = {
2723 /* RXD */
2724 RCAR_GP_PIN(5, 25),
2725};
2726static const unsigned int msiof1_rxd_f_mux[] = {
2727 MSIOF1_RXD_F_MARK,
2728};
2729static const unsigned int msiof1_clk_g_pins[] = {
2730 /* SCK */
2731 RCAR_GP_PIN(3, 6),
2732};
2733static const unsigned int msiof1_clk_g_mux[] = {
2734 MSIOF1_SCK_G_MARK,
2735};
2736static const unsigned int msiof1_sync_g_pins[] = {
2737 /* SYNC */
2738 RCAR_GP_PIN(3, 7),
2739};
2740static const unsigned int msiof1_sync_g_mux[] = {
2741 MSIOF1_SYNC_G_MARK,
2742};
2743static const unsigned int msiof1_ss1_g_pins[] = {
2744 /* SS1 */
2745 RCAR_GP_PIN(3, 10),
2746};
2747static const unsigned int msiof1_ss1_g_mux[] = {
2748 MSIOF1_SS1_G_MARK,
2749};
2750static const unsigned int msiof1_ss2_g_pins[] = {
2751 /* SS2 */
2752 RCAR_GP_PIN(3, 11),
2753};
2754static const unsigned int msiof1_ss2_g_mux[] = {
2755 MSIOF1_SS2_G_MARK,
2756};
2757static const unsigned int msiof1_txd_g_pins[] = {
2758 /* TXD */
2759 RCAR_GP_PIN(3, 9),
2760};
2761static const unsigned int msiof1_txd_g_mux[] = {
2762 MSIOF1_TXD_G_MARK,
2763};
2764static const unsigned int msiof1_rxd_g_pins[] = {
2765 /* RXD */
2766 RCAR_GP_PIN(3, 8),
2767};
2768static const unsigned int msiof1_rxd_g_mux[] = {
2769 MSIOF1_RXD_G_MARK,
2770};
2771/* - MSIOF2 ----------------------------------------------------------------- */
2772static const unsigned int msiof2_clk_a_pins[] = {
2773 /* SCK */
2774 RCAR_GP_PIN(1, 9),
2775};
2776static const unsigned int msiof2_clk_a_mux[] = {
2777 MSIOF2_SCK_A_MARK,
2778};
2779static const unsigned int msiof2_sync_a_pins[] = {
2780 /* SYNC */
2781 RCAR_GP_PIN(1, 8),
2782};
2783static const unsigned int msiof2_sync_a_mux[] = {
2784 MSIOF2_SYNC_A_MARK,
2785};
2786static const unsigned int msiof2_ss1_a_pins[] = {
2787 /* SS1 */
2788 RCAR_GP_PIN(1, 6),
2789};
2790static const unsigned int msiof2_ss1_a_mux[] = {
2791 MSIOF2_SS1_A_MARK,
2792};
2793static const unsigned int msiof2_ss2_a_pins[] = {
2794 /* SS2 */
2795 RCAR_GP_PIN(1, 7),
2796};
2797static const unsigned int msiof2_ss2_a_mux[] = {
2798 MSIOF2_SS2_A_MARK,
2799};
2800static const unsigned int msiof2_txd_a_pins[] = {
2801 /* TXD */
2802 RCAR_GP_PIN(1, 11),
2803};
2804static const unsigned int msiof2_txd_a_mux[] = {
2805 MSIOF2_TXD_A_MARK,
2806};
2807static const unsigned int msiof2_rxd_a_pins[] = {
2808 /* RXD */
2809 RCAR_GP_PIN(1, 10),
2810};
2811static const unsigned int msiof2_rxd_a_mux[] = {
2812 MSIOF2_RXD_A_MARK,
2813};
2814static const unsigned int msiof2_clk_b_pins[] = {
2815 /* SCK */
2816 RCAR_GP_PIN(0, 4),
2817};
2818static const unsigned int msiof2_clk_b_mux[] = {
2819 MSIOF2_SCK_B_MARK,
2820};
2821static const unsigned int msiof2_sync_b_pins[] = {
2822 /* SYNC */
2823 RCAR_GP_PIN(0, 5),
2824};
2825static const unsigned int msiof2_sync_b_mux[] = {
2826 MSIOF2_SYNC_B_MARK,
2827};
2828static const unsigned int msiof2_ss1_b_pins[] = {
2829 /* SS1 */
2830 RCAR_GP_PIN(0, 0),
2831};
2832static const unsigned int msiof2_ss1_b_mux[] = {
2833 MSIOF2_SS1_B_MARK,
2834};
2835static const unsigned int msiof2_ss2_b_pins[] = {
2836 /* SS2 */
2837 RCAR_GP_PIN(0, 1),
2838};
2839static const unsigned int msiof2_ss2_b_mux[] = {
2840 MSIOF2_SS2_B_MARK,
2841};
2842static const unsigned int msiof2_txd_b_pins[] = {
2843 /* TXD */
2844 RCAR_GP_PIN(0, 7),
2845};
2846static const unsigned int msiof2_txd_b_mux[] = {
2847 MSIOF2_TXD_B_MARK,
2848};
2849static const unsigned int msiof2_rxd_b_pins[] = {
2850 /* RXD */
2851 RCAR_GP_PIN(0, 6),
2852};
2853static const unsigned int msiof2_rxd_b_mux[] = {
2854 MSIOF2_RXD_B_MARK,
2855};
2856static const unsigned int msiof2_clk_c_pins[] = {
2857 /* SCK */
2858 RCAR_GP_PIN(2, 12),
2859};
2860static const unsigned int msiof2_clk_c_mux[] = {
2861 MSIOF2_SCK_C_MARK,
2862};
2863static const unsigned int msiof2_sync_c_pins[] = {
2864 /* SYNC */
2865 RCAR_GP_PIN(2, 11),
2866};
2867static const unsigned int msiof2_sync_c_mux[] = {
2868 MSIOF2_SYNC_C_MARK,
2869};
2870static const unsigned int msiof2_ss1_c_pins[] = {
2871 /* SS1 */
2872 RCAR_GP_PIN(2, 10),
2873};
2874static const unsigned int msiof2_ss1_c_mux[] = {
2875 MSIOF2_SS1_C_MARK,
2876};
2877static const unsigned int msiof2_ss2_c_pins[] = {
2878 /* SS2 */
2879 RCAR_GP_PIN(2, 9),
2880};
2881static const unsigned int msiof2_ss2_c_mux[] = {
2882 MSIOF2_SS2_C_MARK,
2883};
2884static const unsigned int msiof2_txd_c_pins[] = {
2885 /* TXD */
2886 RCAR_GP_PIN(2, 14),
2887};
2888static const unsigned int msiof2_txd_c_mux[] = {
2889 MSIOF2_TXD_C_MARK,
2890};
2891static const unsigned int msiof2_rxd_c_pins[] = {
2892 /* RXD */
2893 RCAR_GP_PIN(2, 13),
2894};
2895static const unsigned int msiof2_rxd_c_mux[] = {
2896 MSIOF2_RXD_C_MARK,
2897};
2898static const unsigned int msiof2_clk_d_pins[] = {
2899 /* SCK */
2900 RCAR_GP_PIN(0, 8),
2901};
2902static const unsigned int msiof2_clk_d_mux[] = {
2903 MSIOF2_SCK_D_MARK,
2904};
2905static const unsigned int msiof2_sync_d_pins[] = {
2906 /* SYNC */
2907 RCAR_GP_PIN(0, 9),
2908};
2909static const unsigned int msiof2_sync_d_mux[] = {
2910 MSIOF2_SYNC_D_MARK,
2911};
2912static const unsigned int msiof2_ss1_d_pins[] = {
2913 /* SS1 */
2914 RCAR_GP_PIN(0, 12),
2915};
2916static const unsigned int msiof2_ss1_d_mux[] = {
2917 MSIOF2_SS1_D_MARK,
2918};
2919static const unsigned int msiof2_ss2_d_pins[] = {
2920 /* SS2 */
2921 RCAR_GP_PIN(0, 13),
2922};
2923static const unsigned int msiof2_ss2_d_mux[] = {
2924 MSIOF2_SS2_D_MARK,
2925};
2926static const unsigned int msiof2_txd_d_pins[] = {
2927 /* TXD */
2928 RCAR_GP_PIN(0, 11),
2929};
2930static const unsigned int msiof2_txd_d_mux[] = {
2931 MSIOF2_TXD_D_MARK,
2932};
2933static const unsigned int msiof2_rxd_d_pins[] = {
2934 /* RXD */
2935 RCAR_GP_PIN(0, 10),
2936};
2937static const unsigned int msiof2_rxd_d_mux[] = {
2938 MSIOF2_RXD_D_MARK,
2939};
2940/* - MSIOF3 ----------------------------------------------------------------- */
2941static const unsigned int msiof3_clk_a_pins[] = {
2942 /* SCK */
2943 RCAR_GP_PIN(0, 0),
2944};
2945static const unsigned int msiof3_clk_a_mux[] = {
2946 MSIOF3_SCK_A_MARK,
2947};
2948static const unsigned int msiof3_sync_a_pins[] = {
2949 /* SYNC */
2950 RCAR_GP_PIN(0, 1),
2951};
2952static const unsigned int msiof3_sync_a_mux[] = {
2953 MSIOF3_SYNC_A_MARK,
2954};
2955static const unsigned int msiof3_ss1_a_pins[] = {
2956 /* SS1 */
2957 RCAR_GP_PIN(0, 14),
2958};
2959static const unsigned int msiof3_ss1_a_mux[] = {
2960 MSIOF3_SS1_A_MARK,
2961};
2962static const unsigned int msiof3_ss2_a_pins[] = {
2963 /* SS2 */
2964 RCAR_GP_PIN(0, 15),
2965};
2966static const unsigned int msiof3_ss2_a_mux[] = {
2967 MSIOF3_SS2_A_MARK,
2968};
2969static const unsigned int msiof3_txd_a_pins[] = {
2970 /* TXD */
2971 RCAR_GP_PIN(0, 3),
2972};
2973static const unsigned int msiof3_txd_a_mux[] = {
2974 MSIOF3_TXD_A_MARK,
2975};
2976static const unsigned int msiof3_rxd_a_pins[] = {
2977 /* RXD */
2978 RCAR_GP_PIN(0, 2),
2979};
2980static const unsigned int msiof3_rxd_a_mux[] = {
2981 MSIOF3_RXD_A_MARK,
2982};
2983static const unsigned int msiof3_clk_b_pins[] = {
2984 /* SCK */
2985 RCAR_GP_PIN(1, 2),
2986};
2987static const unsigned int msiof3_clk_b_mux[] = {
2988 MSIOF3_SCK_B_MARK,
2989};
2990static const unsigned int msiof3_sync_b_pins[] = {
2991 /* SYNC */
2992 RCAR_GP_PIN(1, 0),
2993};
2994static const unsigned int msiof3_sync_b_mux[] = {
2995 MSIOF3_SYNC_B_MARK,
2996};
2997static const unsigned int msiof3_ss1_b_pins[] = {
2998 /* SS1 */
2999 RCAR_GP_PIN(1, 4),
3000};
3001static const unsigned int msiof3_ss1_b_mux[] = {
3002 MSIOF3_SS1_B_MARK,
3003};
3004static const unsigned int msiof3_ss2_b_pins[] = {
3005 /* SS2 */
3006 RCAR_GP_PIN(1, 5),
3007};
3008static const unsigned int msiof3_ss2_b_mux[] = {
3009 MSIOF3_SS2_B_MARK,
3010};
3011static const unsigned int msiof3_txd_b_pins[] = {
3012 /* TXD */
3013 RCAR_GP_PIN(1, 1),
3014};
3015static const unsigned int msiof3_txd_b_mux[] = {
3016 MSIOF3_TXD_B_MARK,
3017};
3018static const unsigned int msiof3_rxd_b_pins[] = {
3019 /* RXD */
3020 RCAR_GP_PIN(1, 3),
3021};
3022static const unsigned int msiof3_rxd_b_mux[] = {
3023 MSIOF3_RXD_B_MARK,
3024};
3025static const unsigned int msiof3_clk_c_pins[] = {
3026 /* SCK */
3027 RCAR_GP_PIN(1, 12),
3028};
3029static const unsigned int msiof3_clk_c_mux[] = {
3030 MSIOF3_SCK_C_MARK,
3031};
3032static const unsigned int msiof3_sync_c_pins[] = {
3033 /* SYNC */
3034 RCAR_GP_PIN(1, 13),
3035};
3036static const unsigned int msiof3_sync_c_mux[] = {
3037 MSIOF3_SYNC_C_MARK,
3038};
3039static const unsigned int msiof3_txd_c_pins[] = {
3040 /* TXD */
3041 RCAR_GP_PIN(1, 15),
3042};
3043static const unsigned int msiof3_txd_c_mux[] = {
3044 MSIOF3_TXD_C_MARK,
3045};
3046static const unsigned int msiof3_rxd_c_pins[] = {
3047 /* RXD */
3048 RCAR_GP_PIN(1, 14),
3049};
3050static const unsigned int msiof3_rxd_c_mux[] = {
3051 MSIOF3_RXD_C_MARK,
3052};
3053static const unsigned int msiof3_clk_d_pins[] = {
3054 /* SCK */
3055 RCAR_GP_PIN(1, 22),
3056};
3057static const unsigned int msiof3_clk_d_mux[] = {
3058 MSIOF3_SCK_D_MARK,
3059};
3060static const unsigned int msiof3_sync_d_pins[] = {
3061 /* SYNC */
3062 RCAR_GP_PIN(1, 23),
3063};
3064static const unsigned int msiof3_sync_d_mux[] = {
3065 MSIOF3_SYNC_D_MARK,
3066};
3067static const unsigned int msiof3_ss1_d_pins[] = {
3068 /* SS1 */
3069 RCAR_GP_PIN(1, 26),
3070};
3071static const unsigned int msiof3_ss1_d_mux[] = {
3072 MSIOF3_SS1_D_MARK,
3073};
3074static const unsigned int msiof3_txd_d_pins[] = {
3075 /* TXD */
3076 RCAR_GP_PIN(1, 25),
3077};
3078static const unsigned int msiof3_txd_d_mux[] = {
3079 MSIOF3_TXD_D_MARK,
3080};
3081static const unsigned int msiof3_rxd_d_pins[] = {
3082 /* RXD */
3083 RCAR_GP_PIN(1, 24),
3084};
3085static const unsigned int msiof3_rxd_d_mux[] = {
3086 MSIOF3_RXD_D_MARK,
3087};
3088static const unsigned int msiof3_clk_e_pins[] = {
3089 /* SCK */
3090 RCAR_GP_PIN(2, 3),
3091};
3092static const unsigned int msiof3_clk_e_mux[] = {
3093 MSIOF3_SCK_E_MARK,
3094};
3095static const unsigned int msiof3_sync_e_pins[] = {
3096 /* SYNC */
3097 RCAR_GP_PIN(2, 2),
3098};
3099static const unsigned int msiof3_sync_e_mux[] = {
3100 MSIOF3_SYNC_E_MARK,
3101};
3102static const unsigned int msiof3_ss1_e_pins[] = {
3103 /* SS1 */
3104 RCAR_GP_PIN(2, 1),
3105};
3106static const unsigned int msiof3_ss1_e_mux[] = {
3107 MSIOF3_SS1_E_MARK,
3108};
3109static const unsigned int msiof3_ss2_e_pins[] = {
3110 /* SS1 */
3111 RCAR_GP_PIN(2, 0),
3112};
3113static const unsigned int msiof3_ss2_e_mux[] = {
3114 MSIOF3_SS2_E_MARK,
3115};
3116static const unsigned int msiof3_txd_e_pins[] = {
3117 /* TXD */
3118 RCAR_GP_PIN(2, 5),
3119};
3120static const unsigned int msiof3_txd_e_mux[] = {
3121 MSIOF3_TXD_E_MARK,
3122};
3123static const unsigned int msiof3_rxd_e_pins[] = {
3124 /* RXD */
3125 RCAR_GP_PIN(2, 4),
3126};
3127static const unsigned int msiof3_rxd_e_mux[] = {
3128 MSIOF3_RXD_E_MARK,
3129};
3130
c03a133b
LP		 3131/* - PWM0 --------------------------------------------------------------------*/
3132static const unsigned int pwm0_pins[] = {
3133 /* PWM */
3134 RCAR_GP_PIN(2, 6),
3135};
3136static const unsigned int pwm0_mux[] = {
3137 PWM0_MARK,
3138};
3139/* - PWM1 --------------------------------------------------------------------*/
3140static const unsigned int pwm1_a_pins[] = {
3141 /* PWM */
3142 RCAR_GP_PIN(2, 7),
3143};
3144static const unsigned int pwm1_a_mux[] = {
3145 PWM1_A_MARK,
3146};
3147static const unsigned int pwm1_b_pins[] = {
3148 /* PWM */
3149 RCAR_GP_PIN(1, 8),
3150};
3151static const unsigned int pwm1_b_mux[] = {
3152 PWM1_B_MARK,
3153};
3154/* - PWM2 --------------------------------------------------------------------*/
3155static const unsigned int pwm2_a_pins[] = {
3156 /* PWM */
3157 RCAR_GP_PIN(2, 8),
3158};
3159static const unsigned int pwm2_a_mux[] = {
3160 PWM2_A_MARK,
3161};
3162static const unsigned int pwm2_b_pins[] = {
3163 /* PWM */
3164 RCAR_GP_PIN(1, 11),
3165};
3166static const unsigned int pwm2_b_mux[] = {
3167 PWM2_B_MARK,
3168};
3169/* - PWM3 --------------------------------------------------------------------*/
3170static const unsigned int pwm3_a_pins[] = {
3171 /* PWM */
3172 RCAR_GP_PIN(1, 0),
3173};
3174static const unsigned int pwm3_a_mux[] = {
3175 PWM3_A_MARK,
3176};
3177static const unsigned int pwm3_b_pins[] = {
3178 /* PWM */
3179 RCAR_GP_PIN(2, 2),
3180};
3181static const unsigned int pwm3_b_mux[] = {
3182 PWM3_B_MARK,
3183};
3184/* - PWM4 --------------------------------------------------------------------*/
3185static const unsigned int pwm4_a_pins[] = {
3186 /* PWM */
3187 RCAR_GP_PIN(1, 1),
3188};
3189static const unsigned int pwm4_a_mux[] = {
3190 PWM4_A_MARK,
3191};
3192static const unsigned int pwm4_b_pins[] = {
3193 /* PWM */
3194 RCAR_GP_PIN(2, 3),
3195};
3196static const unsigned int pwm4_b_mux[] = {
3197 PWM4_B_MARK,
3198};
3199/* - PWM5 --------------------------------------------------------------------*/
3200static const unsigned int pwm5_a_pins[] = {
3201 /* PWM */
3202 RCAR_GP_PIN(1, 2),
3203};
3204static const unsigned int pwm5_a_mux[] = {
3205 PWM5_A_MARK,
3206};
3207static const unsigned int pwm5_b_pins[] = {
3208 /* PWM */
3209 RCAR_GP_PIN(2, 4),
3210};
3211static const unsigned int pwm5_b_mux[] = {
3212 PWM5_B_MARK,
3213};
3214/* - PWM6 --------------------------------------------------------------------*/
3215static const unsigned int pwm6_a_pins[] = {
3216 /* PWM */
3217 RCAR_GP_PIN(1, 3),
3218};
3219static const unsigned int pwm6_a_mux[] = {
3220 PWM6_A_MARK,
3221};
3222static const unsigned int pwm6_b_pins[] = {
3223 /* PWM */
3224 RCAR_GP_PIN(2, 5),
3225};
3226static const unsigned int pwm6_b_mux[] = {
3227 PWM6_B_MARK,
3228};
3229
e7ad4d3c
GU		 3230/* - SCIF0 ------------------------------------------------------------------ */
3231static const unsigned int scif0_data_pins[] = {
3232 /* RX, TX */
3233 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3234};
3235static const unsigned int scif0_data_mux[] = {
3236 RX0_MARK, TX0_MARK,
3237};
3238static const unsigned int scif0_clk_pins[] = {
3239 /* SCK */
3240 RCAR_GP_PIN(5, 0),
3241};
3242static const unsigned int scif0_clk_mux[] = {
3243 SCK0_MARK,
3244};
3245static const unsigned int scif0_ctrl_pins[] = {
3246 /* RTS, CTS */
3247 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3248};
3249static const unsigned int scif0_ctrl_mux[] = {
3250 RTS0_N_TANS_MARK, CTS0_N_MARK,
3251};
3252/* - SCIF1 ------------------------------------------------------------------ */
3253static const unsigned int scif1_data_a_pins[] = {
3254 /* RX, TX */
3255 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3256};
3257static const unsigned int scif1_data_a_mux[] = {
3258 RX1_A_MARK, TX1_A_MARK,
3259};
3260static const unsigned int scif1_clk_pins[] = {
3261 /* SCK */
3262 RCAR_GP_PIN(6, 21),
3263};
3264static const unsigned int scif1_clk_mux[] = {
3265 SCK1_MARK,
3266};
3267static const unsigned int scif1_ctrl_pins[] = {
3268 /* RTS, CTS */
3269 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3270};
3271static const unsigned int scif1_ctrl_mux[] = {
3272 RTS1_N_TANS_MARK, CTS1_N_MARK,
3273};
3274
3275static const unsigned int scif1_data_b_pins[] = {
3276 /* RX, TX */
3277 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3278};
3279static const unsigned int scif1_data_b_mux[] = {
3280 RX1_B_MARK, TX1_B_MARK,
3281};
3282/* - SCIF2 ------------------------------------------------------------------ */
3283static const unsigned int scif2_data_a_pins[] = {
3284 /* RX, TX */
3285 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3286};
3287static const unsigned int scif2_data_a_mux[] = {
3288 RX2_A_MARK, TX2_A_MARK,
3289};
3290static const unsigned int scif2_clk_pins[] = {
3291 /* SCK */
3292 RCAR_GP_PIN(5, 9),
3293};
3294static const unsigned int scif2_clk_mux[] = {
3295 SCK2_MARK,
3296};
3297static const unsigned int scif2_data_b_pins[] = {
3298 /* RX, TX */
3299 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3300};
3301static const unsigned int scif2_data_b_mux[] = {
3302 RX2_B_MARK, TX2_B_MARK,
3303};
3304/* - SCIF3 ------------------------------------------------------------------ */
3305static const unsigned int scif3_data_a_pins[] = {
3306 /* RX, TX */
3307 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3308};
3309static const unsigned int scif3_data_a_mux[] = {
3310 RX3_A_MARK, TX3_A_MARK,
3311};
3312static const unsigned int scif3_clk_pins[] = {
3313 /* SCK */
3314 RCAR_GP_PIN(1, 22),
3315};
3316static const unsigned int scif3_clk_mux[] = {
3317 SCK3_MARK,
3318};
3319static const unsigned int scif3_ctrl_pins[] = {
3320 /* RTS, CTS */
3321 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3322};
3323static const unsigned int scif3_ctrl_mux[] = {
3324 RTS3_N_TANS_MARK, CTS3_N_MARK,
3325};
3326static const unsigned int scif3_data_b_pins[] = {
3327 /* RX, TX */
3328 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3329};
3330static const unsigned int scif3_data_b_mux[] = {
3331 RX3_B_MARK, TX3_B_MARK,
3332};
3333/* - SCIF4 ------------------------------------------------------------------ */
3334static const unsigned int scif4_data_a_pins[] = {
3335 /* RX, TX */
3336 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3337};
3338static const unsigned int scif4_data_a_mux[] = {
3339 RX4_A_MARK, TX4_A_MARK,
3340};
3341static const unsigned int scif4_clk_a_pins[] = {
3342 /* SCK */
3343 RCAR_GP_PIN(2, 10),
3344};
3345static const unsigned int scif4_clk_a_mux[] = {
3346 SCK4_A_MARK,
3347};
3348static const unsigned int scif4_ctrl_a_pins[] = {
3349 /* RTS, CTS */
3350 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3351};
3352static const unsigned int scif4_ctrl_a_mux[] = {
3353 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3354};
3355static const unsigned int scif4_data_b_pins[] = {
3356 /* RX, TX */
3357 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3358};
3359static const unsigned int scif4_data_b_mux[] = {
3360 RX4_B_MARK, TX4_B_MARK,
3361};
3362static const unsigned int scif4_clk_b_pins[] = {
3363 /* SCK */
3364 RCAR_GP_PIN(1, 5),
3365};
3366static const unsigned int scif4_clk_b_mux[] = {
3367 SCK4_B_MARK,
3368};
3369static const unsigned int scif4_ctrl_b_pins[] = {
3370 /* RTS, CTS */
3371 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3372};
3373static const unsigned int scif4_ctrl_b_mux[] = {
3374 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3375};
3376static const unsigned int scif4_data_c_pins[] = {
3377 /* RX, TX */
3378 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3379};
3380static const unsigned int scif4_data_c_mux[] = {
3381 RX4_C_MARK, TX4_C_MARK,
3382};
3383static const unsigned int scif4_clk_c_pins[] = {
3384 /* SCK */
3385 RCAR_GP_PIN(0, 8),
3386};
3387static const unsigned int scif4_clk_c_mux[] = {
3388 SCK4_C_MARK,
3389};
3390static const unsigned int scif4_ctrl_c_pins[] = {
3391 /* RTS, CTS */
3392 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3393};
3394static const unsigned int scif4_ctrl_c_mux[] = {
3395 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3396};
3397/* - SCIF5 ------------------------------------------------------------------ */
3398static const unsigned int scif5_data_a_pins[] = {
3399 /* RX, TX */
3400 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3401};
3402static const unsigned int scif5_data_a_mux[] = {
3403 RX5_A_MARK, TX5_A_MARK,
3404};
3405static const unsigned int scif5_clk_a_pins[] = {
3406 /* SCK */
3407 RCAR_GP_PIN(6, 21),
3408};
3409static const unsigned int scif5_clk_a_mux[] = {
3410 SCK5_A_MARK,
3411};
3412static const unsigned int scif5_data_b_pins[] = {
3413 /* RX, TX */
3414 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3415};
3416static const unsigned int scif5_data_b_mux[] = {
3417 RX5_B_MARK, TX5_B_MARK,
3418};
3419static const unsigned int scif5_clk_b_pins[] = {
3420 /* SCK */
3421 RCAR_GP_PIN(5, 0),
3422};
3423static const unsigned int scif5_clk_b_mux[] = {
3424 SCK5_B_MARK,
3425};
3426
b4062b46
GU		 3427/* - SCIF Clock ------------------------------------------------------------- */
3428static const unsigned int scif_clk_a_pins[] = {
3429 /* SCIF_CLK */
3430 RCAR_GP_PIN(6, 23),
3431};
3432static const unsigned int scif_clk_a_mux[] = {
3433 SCIF_CLK_A_MARK,
3434};
3435static const unsigned int scif_clk_b_pins[] = {
3436 /* SCIF_CLK */
3437 RCAR_GP_PIN(5, 9),
3438};
3439static const unsigned int scif_clk_b_mux[] = {
3440 SCIF_CLK_B_MARK,
3441};
3442
9ed13958
TK		 3443/* - SDHI0 ------------------------------------------------------------------ */
3444static const unsigned int sdhi0_data1_pins[] = {
3445 /* D0 */
3446 RCAR_GP_PIN(3, 2),
3447};
3448static const unsigned int sdhi0_data1_mux[] = {
3449 SD0_DAT0_MARK,
3450};
3451static const unsigned int sdhi0_data4_pins[] = {
3452 /* D[0:3] */
3453 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3454 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3455};
3456static const unsigned int sdhi0_data4_mux[] = {
3457 SD0_DAT0_MARK, SD0_DAT1_MARK,
3458 SD0_DAT2_MARK, SD0_DAT3_MARK,
3459};
3460static const unsigned int sdhi0_ctrl_pins[] = {
3461 /* CLK, CMD */
3462 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3463};
3464static const unsigned int sdhi0_ctrl_mux[] = {
3465 SD0_CLK_MARK, SD0_CMD_MARK,
3466};
3467static const unsigned int sdhi0_cd_pins[] = {
3468 /* CD */
3469 RCAR_GP_PIN(3, 12),
3470};
3471static const unsigned int sdhi0_cd_mux[] = {
3472 SD0_CD_MARK,
3473};
3474static const unsigned int sdhi0_wp_pins[] = {
3475 /* WP */
3476 RCAR_GP_PIN(3, 13),
3477};
3478static const unsigned int sdhi0_wp_mux[] = {
3479 SD0_WP_MARK,
3480};
3481/* - SDHI1 ------------------------------------------------------------------ */
3482static const unsigned int sdhi1_data1_pins[] = {
3483 /* D0 */
3484 RCAR_GP_PIN(3, 8),
3485};
3486static const unsigned int sdhi1_data1_mux[] = {
3487 SD1_DAT0_MARK,
3488};
3489static const unsigned int sdhi1_data4_pins[] = {
3490 /* D[0:3] */
3491 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3492 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3493};
3494static const unsigned int sdhi1_data4_mux[] = {
3495 SD1_DAT0_MARK, SD1_DAT1_MARK,
3496 SD1_DAT2_MARK, SD1_DAT3_MARK,
3497};
3498static const unsigned int sdhi1_ctrl_pins[] = {
3499 /* CLK, CMD */
3500 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3501};
3502static const unsigned int sdhi1_ctrl_mux[] = {
3503 SD1_CLK_MARK, SD1_CMD_MARK,
3504};
3505static const unsigned int sdhi1_cd_pins[] = {
3506 /* CD */
3507 RCAR_GP_PIN(3, 14),
3508};
3509static const unsigned int sdhi1_cd_mux[] = {
3510 SD1_CD_MARK,
3511};
3512static const unsigned int sdhi1_wp_pins[] = {
3513 /* WP */
3514 RCAR_GP_PIN(3, 15),
3515};
3516static const unsigned int sdhi1_wp_mux[] = {
3517 SD1_WP_MARK,
3518};
3519/* - SDHI2 ------------------------------------------------------------------ */
3520static const unsigned int sdhi2_data1_pins[] = {
3521 /* D0 */
3522 RCAR_GP_PIN(4, 2),
3523};
3524static const unsigned int sdhi2_data1_mux[] = {
3525 SD2_DAT0_MARK,
3526};
3527static const unsigned int sdhi2_data4_pins[] = {
3528 /* D[0:3] */
3529 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3530 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3531};
3532static const unsigned int sdhi2_data4_mux[] = {
3533 SD2_DAT0_MARK, SD2_DAT1_MARK,
3534 SD2_DAT2_MARK, SD2_DAT3_MARK,
3535};
3536static const unsigned int sdhi2_data8_pins[] = {
3537 /* D[0:7] */
3538 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3539 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3540 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3541 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3542};
3543static const unsigned int sdhi2_data8_mux[] = {
3544 SD2_DAT0_MARK, SD2_DAT1_MARK,
3545 SD2_DAT2_MARK, SD2_DAT3_MARK,
3546 SD2_DAT4_MARK, SD2_DAT5_MARK,
3547 SD2_DAT6_MARK, SD2_DAT7_MARK,
3548};
3549static const unsigned int sdhi2_ctrl_pins[] = {
3550 /* CLK, CMD */
3551 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3552};
3553static const unsigned int sdhi2_ctrl_mux[] = {
3554 SD2_CLK_MARK, SD2_CMD_MARK,
3555};
3556static const unsigned int sdhi2_cd_a_pins[] = {
3557 /* CD */
3558 RCAR_GP_PIN(4, 13),
3559};
3560static const unsigned int sdhi2_cd_a_mux[] = {
3561 SD2_CD_A_MARK,
3562};
3563static const unsigned int sdhi2_cd_b_pins[] = {
3564 /* CD */
3565 RCAR_GP_PIN(5, 10),
3566};
3567static const unsigned int sdhi2_cd_b_mux[] = {
3568 SD2_CD_B_MARK,
3569};
3570static const unsigned int sdhi2_wp_a_pins[] = {
3571 /* WP */
3572 RCAR_GP_PIN(4, 14),
3573};
3574static const unsigned int sdhi2_wp_a_mux[] = {
3575 SD2_WP_A_MARK,
3576};
3577static const unsigned int sdhi2_wp_b_pins[] = {
3578 /* WP */
3579 RCAR_GP_PIN(5, 11),
3580};
3581static const unsigned int sdhi2_wp_b_mux[] = {
3582 SD2_WP_B_MARK,
3583};
3584static const unsigned int sdhi2_ds_pins[] = {
3585 /* DS */
3586 RCAR_GP_PIN(4, 6),
3587};
3588static const unsigned int sdhi2_ds_mux[] = {
3589 SD2_DS_MARK,
3590};
3591/* - SDHI3 ------------------------------------------------------------------ */
3592static const unsigned int sdhi3_data1_pins[] = {
3593 /* D0 */
3594 RCAR_GP_PIN(4, 9),
3595};
3596static const unsigned int sdhi3_data1_mux[] = {
3597 SD3_DAT0_MARK,
3598};
3599static const unsigned int sdhi3_data4_pins[] = {
3600 /* D[0:3] */
3601 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3602 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3603};
3604static const unsigned int sdhi3_data4_mux[] = {
3605 SD3_DAT0_MARK, SD3_DAT1_MARK,
3606 SD3_DAT2_MARK, SD3_DAT3_MARK,
3607};
3608static const unsigned int sdhi3_data8_pins[] = {
3609 /* D[0:7] */
3610 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3611 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3612 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3613 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3614};
3615static const unsigned int sdhi3_data8_mux[] = {
3616 SD3_DAT0_MARK, SD3_DAT1_MARK,
3617 SD3_DAT2_MARK, SD3_DAT3_MARK,
3618 SD3_DAT4_MARK, SD3_DAT5_MARK,
3619 SD3_DAT6_MARK, SD3_DAT7_MARK,
3620};
3621static const unsigned int sdhi3_ctrl_pins[] = {
3622 /* CLK, CMD */
3623 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3624};
3625static const unsigned int sdhi3_ctrl_mux[] = {
3626 SD3_CLK_MARK, SD3_CMD_MARK,
3627};
3628static const unsigned int sdhi3_cd_pins[] = {
3629 /* CD */
3630 RCAR_GP_PIN(4, 15),
3631};
3632static const unsigned int sdhi3_cd_mux[] = {
3633 SD3_CD_MARK,
3634};
3635static const unsigned int sdhi3_wp_pins[] = {
3636 /* WP */
3637 RCAR_GP_PIN(4, 16),
3638};
3639static const unsigned int sdhi3_wp_mux[] = {
3640 SD3_WP_MARK,
3641};
3642static const unsigned int sdhi3_ds_pins[] = {
3643 /* DS */
3644 RCAR_GP_PIN(4, 17),
3645};
3646static const unsigned int sdhi3_ds_mux[] = {
3647 SD3_DS_MARK,
3648};
3649
0526234d
KM		 3650/* - SSI -------------------------------------------------------------------- */
3651static const unsigned int ssi0_data_pins[] = {
3652 /* SDATA */
3653 RCAR_GP_PIN(6, 2),
3654};
3655static const unsigned int ssi0_data_mux[] = {
3656 SSI_SDATA0_MARK,
3657};
3658static const unsigned int ssi01239_ctrl_pins[] = {
3659 /* SCK, WS */
3660 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3661};
3662static const unsigned int ssi01239_ctrl_mux[] = {
3663 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3664};
3665static const unsigned int ssi1_data_a_pins[] = {
3666 /* SDATA */
3667 RCAR_GP_PIN(6, 3),
3668};
3669static const unsigned int ssi1_data_a_mux[] = {
3670 SSI_SDATA1_A_MARK,
3671};
3672static const unsigned int ssi1_data_b_pins[] = {
3673 /* SDATA */
3674 RCAR_GP_PIN(5, 12),
3675};
3676static const unsigned int ssi1_data_b_mux[] = {
3677 SSI_SDATA1_B_MARK,
3678};
3679static const unsigned int ssi1_ctrl_a_pins[] = {
3680 /* SCK, WS */
3681 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3682};
3683static const unsigned int ssi1_ctrl_a_mux[] = {
3684 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3685};
3686static const unsigned int ssi1_ctrl_b_pins[] = {
3687 /* SCK, WS */
3688 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3689};
3690static const unsigned int ssi1_ctrl_b_mux[] = {
3691 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3692};
3693static const unsigned int ssi2_data_a_pins[] = {
3694 /* SDATA */
3695 RCAR_GP_PIN(6, 4),
3696};
3697static const unsigned int ssi2_data_a_mux[] = {
3698 SSI_SDATA2_A_MARK,
3699};
3700static const unsigned int ssi2_data_b_pins[] = {
3701 /* SDATA */
3702 RCAR_GP_PIN(5, 13),
3703};
3704static const unsigned int ssi2_data_b_mux[] = {
3705 SSI_SDATA2_B_MARK,
3706};
3707static const unsigned int ssi2_ctrl_a_pins[] = {
3708 /* SCK, WS */
3709 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3710};
3711static const unsigned int ssi2_ctrl_a_mux[] = {
3712 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3713};
3714static const unsigned int ssi2_ctrl_b_pins[] = {
3715 /* SCK, WS */
3716 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3717};
3718static const unsigned int ssi2_ctrl_b_mux[] = {
3719 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3720};
3721static const unsigned int ssi3_data_pins[] = {
3722 /* SDATA */
3723 RCAR_GP_PIN(6, 7),
3724};
3725static const unsigned int ssi3_data_mux[] = {
3726 SSI_SDATA3_MARK,
3727};
3728static const unsigned int ssi349_ctrl_pins[] = {
3729 /* SCK, WS */
3730 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3731};
3732static const unsigned int ssi349_ctrl_mux[] = {
3733 SSI_SCK349_MARK, SSI_WS349_MARK,
3734};
3735static const unsigned int ssi4_data_pins[] = {
3736 /* SDATA */
3737 RCAR_GP_PIN(6, 10),
3738};
3739static const unsigned int ssi4_data_mux[] = {
3740 SSI_SDATA4_MARK,
3741};
3742static const unsigned int ssi4_ctrl_pins[] = {
3743 /* SCK, WS */
3744 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3745};
3746static const unsigned int ssi4_ctrl_mux[] = {
3747 SSI_SCK4_MARK, SSI_WS4_MARK,
3748};
3749static const unsigned int ssi5_data_pins[] = {
3750 /* SDATA */
3751 RCAR_GP_PIN(6, 13),
3752};
3753static const unsigned int ssi5_data_mux[] = {
3754 SSI_SDATA5_MARK,
3755};
3756static const unsigned int ssi5_ctrl_pins[] = {
3757 /* SCK, WS */
3758 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3759};
3760static const unsigned int ssi5_ctrl_mux[] = {
3761 SSI_SCK5_MARK, SSI_WS5_MARK,
3762};
3763static const unsigned int ssi6_data_pins[] = {
3764 /* SDATA */
3765 RCAR_GP_PIN(6, 16),
3766};
3767static const unsigned int ssi6_data_mux[] = {
3768 SSI_SDATA6_MARK,
3769};
3770static const unsigned int ssi6_ctrl_pins[] = {
3771 /* SCK, WS */
3772 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3773};
3774static const unsigned int ssi6_ctrl_mux[] = {
3775 SSI_SCK6_MARK, SSI_WS6_MARK,
3776};
3777static const unsigned int ssi7_data_pins[] = {
3778 /* SDATA */
3779 RCAR_GP_PIN(6, 19),
3780};
3781static const unsigned int ssi7_data_mux[] = {
3782 SSI_SDATA7_MARK,
3783};
3784static const unsigned int ssi78_ctrl_pins[] = {
3785 /* SCK, WS */
3786 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3787};
3788static const unsigned int ssi78_ctrl_mux[] = {
3789 SSI_SCK78_MARK, SSI_WS78_MARK,
3790};
3791static const unsigned int ssi8_data_pins[] = {
3792 /* SDATA */
3793 RCAR_GP_PIN(6, 20),
3794};
3795static const unsigned int ssi8_data_mux[] = {
3796 SSI_SDATA8_MARK,
3797};
3798static const unsigned int ssi9_data_a_pins[] = {
3799 /* SDATA */
3800 RCAR_GP_PIN(6, 21),
3801};
3802static const unsigned int ssi9_data_a_mux[] = {
3803 SSI_SDATA9_A_MARK,
3804};
3805static const unsigned int ssi9_data_b_pins[] = {
3806 /* SDATA */
3807 RCAR_GP_PIN(5, 14),
3808};
3809static const unsigned int ssi9_data_b_mux[] = {
3810 SSI_SDATA9_B_MARK,
3811};
3812static const unsigned int ssi9_ctrl_a_pins[] = {
3813 /* SCK, WS */
3814 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3815};
3816static const unsigned int ssi9_ctrl_a_mux[] = {
3817 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3818};
3819static const unsigned int ssi9_ctrl_b_pins[] = {
3820 /* SCK, WS */
3821 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3822};
3823static const unsigned int ssi9_ctrl_b_mux[] = {
3824 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3825};
3826
933ddbe5
YS		 3827/* - USB0 ------------------------------------------------------------------- */
3828static const unsigned int usb0_pins[] = {
3829 /* PWEN, OVC */
3830 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3831};
3832static const unsigned int usb0_mux[] = {
3833 USB0_PWEN_MARK, USB0_OVC_MARK,
3834};
3835/* - USB1 ------------------------------------------------------------------- */
3836static const unsigned int usb1_pins[] = {
3837 /* PWEN, OVC */
3838 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3839};
3840static const unsigned int usb1_mux[] = {
3841 USB1_PWEN_MARK, USB1_OVC_MARK,
3842};
3843/* - USB2 ------------------------------------------------------------------- */
3844static const unsigned int usb2_pins[] = {
3845 /* PWEN, OVC */
3846 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3847};
3848static const unsigned int usb2_mux[] = {
3849 USB2_PWEN_MARK, USB2_OVC_MARK,
3850};
3851/* - USB2_CH3 --------------------------------------------------------------- */
3852static const unsigned int usb2_ch3_pins[] = {
3853 /* PWEN, OVC */
3854 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3855};
3856static const unsigned int usb2_ch3_mux[] = {
3857 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3858};
3859
5ec8a41a
TK		 3860/* - USB30 ------------------------------------------------------------------ */
3861static const unsigned int usb30_pins[] = {
3862 /* PWEN, OVC */
3863 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3864};
3865static const unsigned int usb30_mux[] = {
3866 USB30_PWEN_MARK, USB30_OVC_MARK,
3867};
3868
b205914c 3869static const struct sh_pfc_pin_group pinmux_groups[] = {
55bfea9f
KM		 3870 SH_PFC_PIN_GROUP(audio_clk_a_a),
3871 SH_PFC_PIN_GROUP(audio_clk_a_b),
3872 SH_PFC_PIN_GROUP(audio_clk_a_c),
3873 SH_PFC_PIN_GROUP(audio_clk_b_a),
3874 SH_PFC_PIN_GROUP(audio_clk_b_b),
3875 SH_PFC_PIN_GROUP(audio_clk_c_a),
3876 SH_PFC_PIN_GROUP(audio_clk_c_b),
3877 SH_PFC_PIN_GROUP(audio_clkout_a),
3878 SH_PFC_PIN_GROUP(audio_clkout_b),
3879 SH_PFC_PIN_GROUP(audio_clkout_c),
3880 SH_PFC_PIN_GROUP(audio_clkout_d),
3881 SH_PFC_PIN_GROUP(audio_clkout1_a),
3882 SH_PFC_PIN_GROUP(audio_clkout1_b),
3883 SH_PFC_PIN_GROUP(audio_clkout2_a),
3884 SH_PFC_PIN_GROUP(audio_clkout2_b),
3885 SH_PFC_PIN_GROUP(audio_clkout3_a),
3886 SH_PFC_PIN_GROUP(audio_clkout3_b),
30c078de
GU		 3887 SH_PFC_PIN_GROUP(avb_link),
3888 SH_PFC_PIN_GROUP(avb_magic),
3889 SH_PFC_PIN_GROUP(avb_phy_int),
3890 SH_PFC_PIN_GROUP(avb_mdc),
3891 SH_PFC_PIN_GROUP(avb_mii),
3892 SH_PFC_PIN_GROUP(avb_avtp_pps),
3893 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3894 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3895 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3896 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a678abfe
RS		 3897 SH_PFC_PIN_GROUP(can0_data_a),
3898 SH_PFC_PIN_GROUP(can0_data_b),
3899 SH_PFC_PIN_GROUP(can1_data),
3900 SH_PFC_PIN_GROUP(can_clk),
0e1c7a94
RS		 3901 SH_PFC_PIN_GROUP(canfd0_data_a),
3902 SH_PFC_PIN_GROUP(canfd0_data_b),
3903 SH_PFC_PIN_GROUP(canfd1_data),
641b0ab8
DB		 3904 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3905 SH_PFC_PIN_GROUP(drif0_data0_a),
3906 SH_PFC_PIN_GROUP(drif0_data1_a),
3907 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3908 SH_PFC_PIN_GROUP(drif0_data0_b),
3909 SH_PFC_PIN_GROUP(drif0_data1_b),
3910 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3911 SH_PFC_PIN_GROUP(drif0_data0_c),
3912 SH_PFC_PIN_GROUP(drif0_data1_c),
3913 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3914 SH_PFC_PIN_GROUP(drif1_data0_a),
3915 SH_PFC_PIN_GROUP(drif1_data1_a),
3916 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3917 SH_PFC_PIN_GROUP(drif1_data0_b),
3918 SH_PFC_PIN_GROUP(drif1_data1_b),
3919 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3920 SH_PFC_PIN_GROUP(drif1_data0_c),
3921 SH_PFC_PIN_GROUP(drif1_data1_c),
3922 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3923 SH_PFC_PIN_GROUP(drif2_data0_a),
3924 SH_PFC_PIN_GROUP(drif2_data1_a),
3925 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3926 SH_PFC_PIN_GROUP(drif2_data0_b),
3927 SH_PFC_PIN_GROUP(drif2_data1_b),
3928 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3929 SH_PFC_PIN_GROUP(drif3_data0_a),
3930 SH_PFC_PIN_GROUP(drif3_data1_a),
3931 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3932 SH_PFC_PIN_GROUP(drif3_data0_b),
3933 SH_PFC_PIN_GROUP(drif3_data1_b),
a20a6585
LP		 3934 SH_PFC_PIN_GROUP(du_rgb666),
3935 SH_PFC_PIN_GROUP(du_rgb888),
3936 SH_PFC_PIN_GROUP(du_clk_out_0),
3937 SH_PFC_PIN_GROUP(du_clk_out_1),
3938 SH_PFC_PIN_GROUP(du_sync),
3939 SH_PFC_PIN_GROUP(du_oddf),
3940 SH_PFC_PIN_GROUP(du_cde),
3941 SH_PFC_PIN_GROUP(du_disp),
7a362e34
WS		 3942 SH_PFC_PIN_GROUP(hscif0_data),
3943 SH_PFC_PIN_GROUP(hscif0_clk),
3944 SH_PFC_PIN_GROUP(hscif0_ctrl),
3945 SH_PFC_PIN_GROUP(hscif1_data_a),
3946 SH_PFC_PIN_GROUP(hscif1_clk_a),
3947 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3948 SH_PFC_PIN_GROUP(hscif1_data_b),
3949 SH_PFC_PIN_GROUP(hscif1_clk_b),
3950 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3951 SH_PFC_PIN_GROUP(hscif2_data_a),
3952 SH_PFC_PIN_GROUP(hscif2_clk_a),
3953 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3954 SH_PFC_PIN_GROUP(hscif2_data_b),
3955 SH_PFC_PIN_GROUP(hscif2_clk_b),
3956 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3957 SH_PFC_PIN_GROUP(hscif2_data_c),
3958 SH_PFC_PIN_GROUP(hscif2_clk_c),
3959 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3960 SH_PFC_PIN_GROUP(hscif3_data_a),
3961 SH_PFC_PIN_GROUP(hscif3_clk),
3962 SH_PFC_PIN_GROUP(hscif3_ctrl),
3963 SH_PFC_PIN_GROUP(hscif3_data_b),
3964 SH_PFC_PIN_GROUP(hscif3_data_c),
3965 SH_PFC_PIN_GROUP(hscif3_data_d),
3966 SH_PFC_PIN_GROUP(hscif4_data_a),
3967 SH_PFC_PIN_GROUP(hscif4_clk),
3968 SH_PFC_PIN_GROUP(hscif4_ctrl),
3969 SH_PFC_PIN_GROUP(hscif4_data_b),
f62d4c9e
WS		 3970 SH_PFC_PIN_GROUP(i2c1_a),
3971 SH_PFC_PIN_GROUP(i2c1_b),
3972 SH_PFC_PIN_GROUP(i2c2_a),
3973 SH_PFC_PIN_GROUP(i2c2_b),
3974 SH_PFC_PIN_GROUP(i2c6_a),
3975 SH_PFC_PIN_GROUP(i2c6_b),
3976 SH_PFC_PIN_GROUP(i2c6_c),
8480e6ca
GU		 3977 SH_PFC_PIN_GROUP(intc_ex_irq0),
3978 SH_PFC_PIN_GROUP(intc_ex_irq1),
3979 SH_PFC_PIN_GROUP(intc_ex_irq2),
3980 SH_PFC_PIN_GROUP(intc_ex_irq3),
3981 SH_PFC_PIN_GROUP(intc_ex_irq4),
3982 SH_PFC_PIN_GROUP(intc_ex_irq5),
3e6c7727
GU		 3983 SH_PFC_PIN_GROUP(msiof0_clk),
3984 SH_PFC_PIN_GROUP(msiof0_sync),
3985 SH_PFC_PIN_GROUP(msiof0_ss1),
3986 SH_PFC_PIN_GROUP(msiof0_ss2),
3987 SH_PFC_PIN_GROUP(msiof0_txd),
3988 SH_PFC_PIN_GROUP(msiof0_rxd),
3989 SH_PFC_PIN_GROUP(msiof1_clk_a),
3990 SH_PFC_PIN_GROUP(msiof1_sync_a),
3991 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3992 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3993 SH_PFC_PIN_GROUP(msiof1_txd_a),
3994 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3995 SH_PFC_PIN_GROUP(msiof1_clk_b),
3996 SH_PFC_PIN_GROUP(msiof1_sync_b),
3997 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3998 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3999 SH_PFC_PIN_GROUP(msiof1_txd_b),
4000 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4001 SH_PFC_PIN_GROUP(msiof1_clk_c),
4002 SH_PFC_PIN_GROUP(msiof1_sync_c),
4003 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4004 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4005 SH_PFC_PIN_GROUP(msiof1_txd_c),
4006 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4007 SH_PFC_PIN_GROUP(msiof1_clk_d),
4008 SH_PFC_PIN_GROUP(msiof1_sync_d),
4009 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4010 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4011 SH_PFC_PIN_GROUP(msiof1_txd_d),
4012 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4013 SH_PFC_PIN_GROUP(msiof1_clk_e),
4014 SH_PFC_PIN_GROUP(msiof1_sync_e),
4015 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4016 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4017 SH_PFC_PIN_GROUP(msiof1_txd_e),
4018 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4019 SH_PFC_PIN_GROUP(msiof1_clk_f),
4020 SH_PFC_PIN_GROUP(msiof1_sync_f),
4021 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4022 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4023 SH_PFC_PIN_GROUP(msiof1_txd_f),
4024 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4025 SH_PFC_PIN_GROUP(msiof1_clk_g),
4026 SH_PFC_PIN_GROUP(msiof1_sync_g),
4027 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4028 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4029 SH_PFC_PIN_GROUP(msiof1_txd_g),
4030 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4031 SH_PFC_PIN_GROUP(msiof2_clk_a),
4032 SH_PFC_PIN_GROUP(msiof2_sync_a),
4033 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4034 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4035 SH_PFC_PIN_GROUP(msiof2_txd_a),
4036 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4037 SH_PFC_PIN_GROUP(msiof2_clk_b),
4038 SH_PFC_PIN_GROUP(msiof2_sync_b),
4039 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4040 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4041 SH_PFC_PIN_GROUP(msiof2_txd_b),
4042 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4043 SH_PFC_PIN_GROUP(msiof2_clk_c),
4044 SH_PFC_PIN_GROUP(msiof2_sync_c),
4045 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4046 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4047 SH_PFC_PIN_GROUP(msiof2_txd_c),
4048 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4049 SH_PFC_PIN_GROUP(msiof2_clk_d),
4050 SH_PFC_PIN_GROUP(msiof2_sync_d),
4051 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4052 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4053 SH_PFC_PIN_GROUP(msiof2_txd_d),
4054 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4055 SH_PFC_PIN_GROUP(msiof3_clk_a),
4056 SH_PFC_PIN_GROUP(msiof3_sync_a),
4057 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4058 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4059 SH_PFC_PIN_GROUP(msiof3_txd_a),
4060 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4061 SH_PFC_PIN_GROUP(msiof3_clk_b),
4062 SH_PFC_PIN_GROUP(msiof3_sync_b),
4063 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4064 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4065 SH_PFC_PIN_GROUP(msiof3_txd_b),
4066 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4067 SH_PFC_PIN_GROUP(msiof3_clk_c),
4068 SH_PFC_PIN_GROUP(msiof3_sync_c),
4069 SH_PFC_PIN_GROUP(msiof3_txd_c),
4070 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4071 SH_PFC_PIN_GROUP(msiof3_clk_d),
4072 SH_PFC_PIN_GROUP(msiof3_sync_d),
4073 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4074 SH_PFC_PIN_GROUP(msiof3_txd_d),
4075 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4076 SH_PFC_PIN_GROUP(msiof3_clk_e),
4077 SH_PFC_PIN_GROUP(msiof3_sync_e),
4078 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4079 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4080 SH_PFC_PIN_GROUP(msiof3_txd_e),
4081 SH_PFC_PIN_GROUP(msiof3_rxd_e),
c03a133b
LP		 4082 SH_PFC_PIN_GROUP(pwm0),
4083 SH_PFC_PIN_GROUP(pwm1_a),
4084 SH_PFC_PIN_GROUP(pwm1_b),
4085 SH_PFC_PIN_GROUP(pwm2_a),
4086 SH_PFC_PIN_GROUP(pwm2_b),
4087 SH_PFC_PIN_GROUP(pwm3_a),
4088 SH_PFC_PIN_GROUP(pwm3_b),
4089 SH_PFC_PIN_GROUP(pwm4_a),
4090 SH_PFC_PIN_GROUP(pwm4_b),
4091 SH_PFC_PIN_GROUP(pwm5_a),
4092 SH_PFC_PIN_GROUP(pwm5_b),
4093 SH_PFC_PIN_GROUP(pwm6_a),
4094 SH_PFC_PIN_GROUP(pwm6_b),
e7ad4d3c
GU		 4095 SH_PFC_PIN_GROUP(scif0_data),
4096 SH_PFC_PIN_GROUP(scif0_clk),
4097 SH_PFC_PIN_GROUP(scif0_ctrl),
4098 SH_PFC_PIN_GROUP(scif1_data_a),
4099 SH_PFC_PIN_GROUP(scif1_clk),
4100 SH_PFC_PIN_GROUP(scif1_ctrl),
4101 SH_PFC_PIN_GROUP(scif1_data_b),
4102 SH_PFC_PIN_GROUP(scif2_data_a),
4103 SH_PFC_PIN_GROUP(scif2_clk),
4104 SH_PFC_PIN_GROUP(scif2_data_b),
4105 SH_PFC_PIN_GROUP(scif3_data_a),
4106 SH_PFC_PIN_GROUP(scif3_clk),
4107 SH_PFC_PIN_GROUP(scif3_ctrl),
4108 SH_PFC_PIN_GROUP(scif3_data_b),
4109 SH_PFC_PIN_GROUP(scif4_data_a),
4110 SH_PFC_PIN_GROUP(scif4_clk_a),
4111 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4112 SH_PFC_PIN_GROUP(scif4_data_b),
4113 SH_PFC_PIN_GROUP(scif4_clk_b),
4114 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4115 SH_PFC_PIN_GROUP(scif4_data_c),
4116 SH_PFC_PIN_GROUP(scif4_clk_c),
4117 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4118 SH_PFC_PIN_GROUP(scif5_data_a),
4119 SH_PFC_PIN_GROUP(scif5_clk_a),
4120 SH_PFC_PIN_GROUP(scif5_data_b),
4121 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 4122 SH_PFC_PIN_GROUP(scif_clk_a),
4123 SH_PFC_PIN_GROUP(scif_clk_b),
9ed13958
TK		 4124 SH_PFC_PIN_GROUP(sdhi0_data1),
4125 SH_PFC_PIN_GROUP(sdhi0_data4),
4126 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4127 SH_PFC_PIN_GROUP(sdhi0_cd),
4128 SH_PFC_PIN_GROUP(sdhi0_wp),
4129 SH_PFC_PIN_GROUP(sdhi1_data1),
4130 SH_PFC_PIN_GROUP(sdhi1_data4),
4131 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4132 SH_PFC_PIN_GROUP(sdhi1_cd),
4133 SH_PFC_PIN_GROUP(sdhi1_wp),
4134 SH_PFC_PIN_GROUP(sdhi2_data1),
4135 SH_PFC_PIN_GROUP(sdhi2_data4),
4136 SH_PFC_PIN_GROUP(sdhi2_data8),
4137 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4138 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4139 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4140 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4141 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4142 SH_PFC_PIN_GROUP(sdhi2_ds),
4143 SH_PFC_PIN_GROUP(sdhi3_data1),
4144 SH_PFC_PIN_GROUP(sdhi3_data4),
4145 SH_PFC_PIN_GROUP(sdhi3_data8),
4146 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4147 SH_PFC_PIN_GROUP(sdhi3_cd),
4148 SH_PFC_PIN_GROUP(sdhi3_wp),
4149 SH_PFC_PIN_GROUP(sdhi3_ds),
0526234d
KM		 4150 SH_PFC_PIN_GROUP(ssi0_data),
4151 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4152 SH_PFC_PIN_GROUP(ssi1_data_a),
4153 SH_PFC_PIN_GROUP(ssi1_data_b),
4154 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4155 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4156 SH_PFC_PIN_GROUP(ssi2_data_a),
4157 SH_PFC_PIN_GROUP(ssi2_data_b),
4158 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4159 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4160 SH_PFC_PIN_GROUP(ssi3_data),
4161 SH_PFC_PIN_GROUP(ssi349_ctrl),
4162 SH_PFC_PIN_GROUP(ssi4_data),
4163 SH_PFC_PIN_GROUP(ssi4_ctrl),
4164 SH_PFC_PIN_GROUP(ssi5_data),
4165 SH_PFC_PIN_GROUP(ssi5_ctrl),
4166 SH_PFC_PIN_GROUP(ssi6_data),
4167 SH_PFC_PIN_GROUP(ssi6_ctrl),
4168 SH_PFC_PIN_GROUP(ssi7_data),
4169 SH_PFC_PIN_GROUP(ssi78_ctrl),
4170 SH_PFC_PIN_GROUP(ssi8_data),
4171 SH_PFC_PIN_GROUP(ssi9_data_a),
4172 SH_PFC_PIN_GROUP(ssi9_data_b),
4173 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4174 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
933ddbe5
YS		 4175 SH_PFC_PIN_GROUP(usb0),
4176 SH_PFC_PIN_GROUP(usb1),
4177 SH_PFC_PIN_GROUP(usb2),
4178 SH_PFC_PIN_GROUP(usb2_ch3),
5ec8a41a 4179 SH_PFC_PIN_GROUP(usb30),
e7ad4d3c
GU		 4180};
4181
55bfea9f
KM		 4182static const char * const audio_clk_groups[] = {
4183 "audio_clk_a_a",
4184 "audio_clk_a_b",
4185 "audio_clk_a_c",
4186 "audio_clk_b_a",
4187 "audio_clk_b_b",
4188 "audio_clk_c_a",
4189 "audio_clk_c_b",
4190 "audio_clkout_a",
4191 "audio_clkout_b",
4192 "audio_clkout_c",
4193 "audio_clkout_d",
4194 "audio_clkout1_a",
4195 "audio_clkout1_b",
4196 "audio_clkout2_a",
4197 "audio_clkout2_b",
4198 "audio_clkout3_a",
4199 "audio_clkout3_b",
4200};
4201
30c078de
GU		 4202static const char * const avb_groups[] = {
4203 "avb_link",
4204 "avb_magic",
4205 "avb_phy_int",
4206 "avb_mdc",
4207 "avb_mii",
4208 "avb_avtp_pps",
4209 "avb_avtp_match_a",
4210 "avb_avtp_capture_a",
4211 "avb_avtp_match_b",
4212 "avb_avtp_capture_b",
4213};
4214
a678abfe
RS		 4215static const char * const can0_groups[] = {
4216 "can0_data_a",
4217 "can0_data_b",
4218};
4219
4220static const char * const can1_groups[] = {
4221 "can1_data",
4222};
4223
4224static const char * const can_clk_groups[] = {
4225 "can_clk",
4226};
4227
0e1c7a94
RS		 4228static const char * const canfd0_groups[] = {
4229 "canfd0_data_a",
4230 "canfd0_data_b",
4231};
4232
4233static const char * const canfd1_groups[] = {
4234 "canfd1_data",
4235};
4236
641b0ab8
DB		 4237static const char * const drif0_groups[] = {
4238 "drif0_ctrl_a",
4239 "drif0_data0_a",
4240 "drif0_data1_a",
4241 "drif0_ctrl_b",
4242 "drif0_data0_b",
4243 "drif0_data1_b",
4244 "drif0_ctrl_c",
4245 "drif0_data0_c",
4246 "drif0_data1_c",
4247};
4248
4249static const char * const drif1_groups[] = {
4250 "drif1_ctrl_a",
4251 "drif1_data0_a",
4252 "drif1_data1_a",
4253 "drif1_ctrl_b",
4254 "drif1_data0_b",
4255 "drif1_data1_b",
4256 "drif1_ctrl_c",
4257 "drif1_data0_c",
4258 "drif1_data1_c",
4259};
4260
4261static const char * const drif2_groups[] = {
4262 "drif2_ctrl_a",
4263 "drif2_data0_a",
4264 "drif2_data1_a",
4265 "drif2_ctrl_b",
4266 "drif2_data0_b",
4267 "drif2_data1_b",
4268};
4269
4270static const char * const drif3_groups[] = {
4271 "drif3_ctrl_a",
4272 "drif3_data0_a",
4273 "drif3_data1_a",
4274 "drif3_ctrl_b",
4275 "drif3_data0_b",
4276 "drif3_data1_b",
4277};
4278
a20a6585
LP		 4279static const char * const du_groups[] = {
4280 "du_rgb666",
4281 "du_rgb888",
4282 "du_clk_out_0",
4283 "du_clk_out_1",
4284 "du_sync",
4285 "du_oddf",
4286 "du_cde",
4287 "du_disp",
4288};
4289
7a362e34
WS		 4290static const char * const hscif0_groups[] = {
4291 "hscif0_data",
4292 "hscif0_clk",
4293 "hscif0_ctrl",
4294};
4295
4296static const char * const hscif1_groups[] = {
4297 "hscif1_data_a",
4298 "hscif1_clk_a",
4299 "hscif1_ctrl_a",
4300 "hscif1_data_b",
4301 "hscif1_clk_b",
4302 "hscif1_ctrl_b",
4303};
4304
4305static const char * const hscif2_groups[] = {
4306 "hscif2_data_a",
4307 "hscif2_clk_a",
4308 "hscif2_ctrl_a",
4309 "hscif2_data_b",
4310 "hscif2_clk_b",
4311 "hscif2_ctrl_b",
4312 "hscif2_data_c",
4313 "hscif2_clk_c",
4314 "hscif2_ctrl_c",
4315};
4316
4317static const char * const hscif3_groups[] = {
4318 "hscif3_data_a",
4319 "hscif3_clk",
4320 "hscif3_ctrl",
4321 "hscif3_data_b",
4322 "hscif3_data_c",
4323 "hscif3_data_d",
4324};
4325
4326static const char * const hscif4_groups[] = {
4327 "hscif4_data_a",
4328 "hscif4_clk",
4329 "hscif4_ctrl",
4330 "hscif4_data_b",
4331};
4332
f62d4c9e
WS		 4333static const char * const i2c1_groups[] = {
4334 "i2c1_a",
4335 "i2c1_b",
4336};
4337
4338static const char * const i2c2_groups[] = {
4339 "i2c2_a",
4340 "i2c2_b",
4341};
4342
4343static const char * const i2c6_groups[] = {
4344 "i2c6_a",
4345 "i2c6_b",
4346 "i2c6_c",
4347};
4348
8480e6ca
GU		 4349static const char * const intc_ex_groups[] = {
4350 "intc_ex_irq0",
4351 "intc_ex_irq1",
4352 "intc_ex_irq2",
4353 "intc_ex_irq3",
4354 "intc_ex_irq4",
4355 "intc_ex_irq5",
4356};
4357
3e6c7727
GU		 4358static const char * const msiof0_groups[] = {
4359 "msiof0_clk",
4360 "msiof0_sync",
4361 "msiof0_ss1",
4362 "msiof0_ss2",
4363 "msiof0_txd",
4364 "msiof0_rxd",
4365};
4366
4367static const char * const msiof1_groups[] = {
4368 "msiof1_clk_a",
4369 "msiof1_sync_a",
4370 "msiof1_ss1_a",
4371 "msiof1_ss2_a",
4372 "msiof1_txd_a",
4373 "msiof1_rxd_a",
4374 "msiof1_clk_b",
4375 "msiof1_sync_b",
4376 "msiof1_ss1_b",
4377 "msiof1_ss2_b",
4378 "msiof1_txd_b",
4379 "msiof1_rxd_b",
4380 "msiof1_clk_c",
4381 "msiof1_sync_c",
4382 "msiof1_ss1_c",
4383 "msiof1_ss2_c",
4384 "msiof1_txd_c",
4385 "msiof1_rxd_c",
4386 "msiof1_clk_d",
4387 "msiof1_sync_d",
4388 "msiof1_ss1_d",
4389 "msiof1_ss2_d",
4390 "msiof1_txd_d",
4391 "msiof1_rxd_d",
4392 "msiof1_clk_e",
4393 "msiof1_sync_e",
4394 "msiof1_ss1_e",
4395 "msiof1_ss2_e",
4396 "msiof1_txd_e",
4397 "msiof1_rxd_e",
4398 "msiof1_clk_f",
4399 "msiof1_sync_f",
4400 "msiof1_ss1_f",
4401 "msiof1_ss2_f",
4402 "msiof1_txd_f",
4403 "msiof1_rxd_f",
4404 "msiof1_clk_g",
4405 "msiof1_sync_g",
4406 "msiof1_ss1_g",
4407 "msiof1_ss2_g",
4408 "msiof1_txd_g",
4409 "msiof1_rxd_g",
4410};
4411
4412static const char * const msiof2_groups[] = {
4413 "msiof2_clk_a",
4414 "msiof2_sync_a",
4415 "msiof2_ss1_a",
4416 "msiof2_ss2_a",
4417 "msiof2_txd_a",
4418 "msiof2_rxd_a",
4419 "msiof2_clk_b",
4420 "msiof2_sync_b",
4421 "msiof2_ss1_b",
4422 "msiof2_ss2_b",
4423 "msiof2_txd_b",
4424 "msiof2_rxd_b",
4425 "msiof2_clk_c",
4426 "msiof2_sync_c",
4427 "msiof2_ss1_c",
4428 "msiof2_ss2_c",
4429 "msiof2_txd_c",
4430 "msiof2_rxd_c",
4431 "msiof2_clk_d",
4432 "msiof2_sync_d",
4433 "msiof2_ss1_d",
4434 "msiof2_ss2_d",
4435 "msiof2_txd_d",
4436 "msiof2_rxd_d",
4437};
4438
4439static const char * const msiof3_groups[] = {
4440 "msiof3_clk_a",
4441 "msiof3_sync_a",
4442 "msiof3_ss1_a",
4443 "msiof3_ss2_a",
4444 "msiof3_txd_a",
4445 "msiof3_rxd_a",
4446 "msiof3_clk_b",
4447 "msiof3_sync_b",
4448 "msiof3_ss1_b",
4449 "msiof3_ss2_b",
4450 "msiof3_txd_b",
4451 "msiof3_rxd_b",
4452 "msiof3_clk_c",
4453 "msiof3_sync_c",
4454 "msiof3_txd_c",
4455 "msiof3_rxd_c",
4456 "msiof3_clk_d",
4457 "msiof3_sync_d",
4458 "msiof3_ss1_d",
4459 "msiof3_txd_d",
4460 "msiof3_rxd_d",
4461 "msiof3_clk_e",
4462 "msiof3_sync_e",
4463 "msiof3_ss1_e",
4464 "msiof3_ss2_e",
4465 "msiof3_txd_e",
4466 "msiof3_rxd_e",
4467};
4468
c03a133b
LP		 4469static const char * const pwm0_groups[] = {
4470 "pwm0",
4471};
4472
4473static const char * const pwm1_groups[] = {
4474 "pwm1_a",
4475 "pwm1_b",
4476};
4477
4478static const char * const pwm2_groups[] = {
4479 "pwm2_a",
4480 "pwm2_b",
4481};
4482
4483static const char * const pwm3_groups[] = {
4484 "pwm3_a",
4485 "pwm3_b",
4486};
4487
4488static const char * const pwm4_groups[] = {
4489 "pwm4_a",
4490 "pwm4_b",
4491};
4492
4493static const char * const pwm5_groups[] = {
4494 "pwm5_a",
4495 "pwm5_b",
4496};
4497
4498static const char * const pwm6_groups[] = {
4499 "pwm6_a",
4500 "pwm6_b",
4501};
4502
e7ad4d3c
GU		 4503static const char * const scif0_groups[] = {
4504 "scif0_data",
4505 "scif0_clk",
4506 "scif0_ctrl",
4507};
4508
4509static const char * const scif1_groups[] = {
4510 "scif1_data_a",
4511 "scif1_clk",
4512 "scif1_ctrl",
4513 "scif1_data_b",
4514};
4515
4516static const char * const scif2_groups[] = {
4517 "scif2_data_a",
4518 "scif2_clk",
4519 "scif2_data_b",
4520};
4521
4522static const char * const scif3_groups[] = {
4523 "scif3_data_a",
4524 "scif3_clk",
4525 "scif3_ctrl",
4526 "scif3_data_b",
4527};
4528
4529static const char * const scif4_groups[] = {
4530 "scif4_data_a",
4531 "scif4_clk_a",
4532 "scif4_ctrl_a",
4533 "scif4_data_b",
4534 "scif4_clk_b",
4535 "scif4_ctrl_b",
4536 "scif4_data_c",
4537 "scif4_clk_c",
4538 "scif4_ctrl_c",
4539};
4540
4541static const char * const scif5_groups[] = {
4542 "scif5_data_a",
4543 "scif5_clk_a",
4544 "scif5_data_b",
4545 "scif5_clk_b",
76250a6c
TK		 4546};
4547
d14a39ed
GU		 4548static const char * const scif_clk_groups[] = {
4549 "scif_clk_a",
4550 "scif_clk_b",
4551};
4552
9ed13958
TK		 4553static const char * const sdhi0_groups[] = {
4554 "sdhi0_data1",
4555 "sdhi0_data4",
4556 "sdhi0_ctrl",
4557 "sdhi0_cd",
4558 "sdhi0_wp",
4559};
4560
4561static const char * const sdhi1_groups[] = {
4562 "sdhi1_data1",
4563 "sdhi1_data4",
4564 "sdhi1_ctrl",
4565 "sdhi1_cd",
4566 "sdhi1_wp",
4567};
4568
4569static const char * const sdhi2_groups[] = {
4570 "sdhi2_data1",
4571 "sdhi2_data4",
4572 "sdhi2_data8",
4573 "sdhi2_ctrl",
4574 "sdhi2_cd_a",
4575 "sdhi2_wp_a",
4576 "sdhi2_cd_b",
4577 "sdhi2_wp_b",
4578 "sdhi2_ds",
4579};
4580
4581static const char * const sdhi3_groups[] = {
4582 "sdhi3_data1",
4583 "sdhi3_data4",
4584 "sdhi3_data8",
4585 "sdhi3_ctrl",
4586 "sdhi3_cd",
4587 "sdhi3_wp",
4588 "sdhi3_ds",
4589};
4590
0526234d
KM		 4591static const char * const ssi_groups[] = {
4592 "ssi0_data",
4593 "ssi01239_ctrl",
4594 "ssi1_data_a",
4595 "ssi1_data_b",
4596 "ssi1_ctrl_a",
4597 "ssi1_ctrl_b",
4598 "ssi2_data_a",
4599 "ssi2_data_b",
4600 "ssi2_ctrl_a",
4601 "ssi2_ctrl_b",
4602 "ssi3_data",
4603 "ssi349_ctrl",
4604 "ssi4_data",
4605 "ssi4_ctrl",
4606 "ssi5_data",
4607 "ssi5_ctrl",
4608 "ssi6_data",
4609 "ssi6_ctrl",
4610 "ssi7_data",
4611 "ssi78_ctrl",
4612 "ssi8_data",
4613 "ssi9_data_a",
4614 "ssi9_data_b",
4615 "ssi9_ctrl_a",
4616 "ssi9_ctrl_b",
4617};
4618
933ddbe5
YS		 4619static const char * const usb0_groups[] = {
4620 "usb0",
4621};
4622
4623static const char * const usb1_groups[] = {
4624 "usb1",
4625};
4626
4627static const char * const usb2_groups[] = {
4628 "usb2",
4629};
4630
4631static const char * const usb2_ch3_groups[] = {
4632 "usb2_ch3",
4633};
4634
5ec8a41a
TK		 4635static const char * const usb30_groups[] = {
4636 "usb30",
4637};
4638
0b0ffc96 4639static const struct sh_pfc_function pinmux_functions[] = {
55bfea9f 4640 SH_PFC_FUNCTION(audio_clk),
30c078de 4641 SH_PFC_FUNCTION(avb),
a678abfe
RS		 4642 SH_PFC_FUNCTION(can0),
4643 SH_PFC_FUNCTION(can1),
4644 SH_PFC_FUNCTION(can_clk),
0e1c7a94
RS		 4645 SH_PFC_FUNCTION(canfd0),
4646 SH_PFC_FUNCTION(canfd1),
641b0ab8
DB		 4647 SH_PFC_FUNCTION(drif0),
4648 SH_PFC_FUNCTION(drif1),
4649 SH_PFC_FUNCTION(drif2),
4650 SH_PFC_FUNCTION(drif3),
a20a6585 4651 SH_PFC_FUNCTION(du),
7a362e34
WS		 4652 SH_PFC_FUNCTION(hscif0),
4653 SH_PFC_FUNCTION(hscif1),
4654 SH_PFC_FUNCTION(hscif2),
4655 SH_PFC_FUNCTION(hscif3),
4656 SH_PFC_FUNCTION(hscif4),
f62d4c9e
WS		 4657 SH_PFC_FUNCTION(i2c1),
4658 SH_PFC_FUNCTION(i2c2),
4659 SH_PFC_FUNCTION(i2c6),
8480e6ca 4660 SH_PFC_FUNCTION(intc_ex),
3e6c7727
GU		 4661 SH_PFC_FUNCTION(msiof0),
4662 SH_PFC_FUNCTION(msiof1),
4663 SH_PFC_FUNCTION(msiof2),
4664 SH_PFC_FUNCTION(msiof3),
c03a133b
LP		 4665 SH_PFC_FUNCTION(pwm0),
4666 SH_PFC_FUNCTION(pwm1),
4667 SH_PFC_FUNCTION(pwm2),
4668 SH_PFC_FUNCTION(pwm3),
4669 SH_PFC_FUNCTION(pwm4),
4670 SH_PFC_FUNCTION(pwm5),
4671 SH_PFC_FUNCTION(pwm6),
e7ad4d3c
GU		 4672 SH_PFC_FUNCTION(scif0),
4673 SH_PFC_FUNCTION(scif1),
4674 SH_PFC_FUNCTION(scif2),
4675 SH_PFC_FUNCTION(scif3),
4676 SH_PFC_FUNCTION(scif4),
4677 SH_PFC_FUNCTION(scif5),
d14a39ed 4678 SH_PFC_FUNCTION(scif_clk),
9ed13958
TK		 4679 SH_PFC_FUNCTION(sdhi0),
4680 SH_PFC_FUNCTION(sdhi1),
4681 SH_PFC_FUNCTION(sdhi2),
4682 SH_PFC_FUNCTION(sdhi3),
0526234d 4683 SH_PFC_FUNCTION(ssi),
933ddbe5
YS		 4684 SH_PFC_FUNCTION(usb0),
4685 SH_PFC_FUNCTION(usb1),
4686 SH_PFC_FUNCTION(usb2),
4687 SH_PFC_FUNCTION(usb2_ch3),
5ec8a41a 4688 SH_PFC_FUNCTION(usb30),
0b0ffc96
TK		 4689};
4690
4691static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4692#define F_(x, y) FN_##y
4693#define FM(x) FN_##x
4694 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4695 0, 0,
4696 0, 0,
4697 0, 0,
4698 0, 0,
4699 0, 0,
4700 0, 0,
4701 0, 0,
4702 0, 0,
4703 0, 0,
4704 0, 0,
4705 0, 0,
4706 0, 0,
4707 0, 0,
4708 0, 0,
4709 0, 0,
4710 0, 0,
4711 GP_0_15_FN, GPSR0_15,
4712 GP_0_14_FN, GPSR0_14,
4713 GP_0_13_FN, GPSR0_13,
4714 GP_0_12_FN, GPSR0_12,
4715 GP_0_11_FN, GPSR0_11,
4716 GP_0_10_FN, GPSR0_10,
4717 GP_0_9_FN, GPSR0_9,
4718 GP_0_8_FN, GPSR0_8,
4719 GP_0_7_FN, GPSR0_7,
4720 GP_0_6_FN, GPSR0_6,
4721 GP_0_5_FN, GPSR0_5,
4722 GP_0_4_FN, GPSR0_4,
4723 GP_0_3_FN, GPSR0_3,
4724 GP_0_2_FN, GPSR0_2,
4725 GP_0_1_FN, GPSR0_1,
4726 GP_0_0_FN, GPSR0_0, }
4727 },
4728 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4729 0, 0,
4730 0, 0,
4731 0, 0,
82d2de5a 4732 GP_1_28_FN, GPSR1_28,
0b0ffc96
TK		 4733 GP_1_27_FN, GPSR1_27,
4734 GP_1_26_FN, GPSR1_26,
4735 GP_1_25_FN, GPSR1_25,
4736 GP_1_24_FN, GPSR1_24,
4737 GP_1_23_FN, GPSR1_23,
4738 GP_1_22_FN, GPSR1_22,
4739 GP_1_21_FN, GPSR1_21,
4740 GP_1_20_FN, GPSR1_20,
4741 GP_1_19_FN, GPSR1_19,
4742 GP_1_18_FN, GPSR1_18,
4743 GP_1_17_FN, GPSR1_17,
4744 GP_1_16_FN, GPSR1_16,
4745 GP_1_15_FN, GPSR1_15,
4746 GP_1_14_FN, GPSR1_14,
4747 GP_1_13_FN, GPSR1_13,
4748 GP_1_12_FN, GPSR1_12,
4749 GP_1_11_FN, GPSR1_11,
4750 GP_1_10_FN, GPSR1_10,
4751 GP_1_9_FN, GPSR1_9,
4752 GP_1_8_FN, GPSR1_8,
4753 GP_1_7_FN, GPSR1_7,
4754 GP_1_6_FN, GPSR1_6,
4755 GP_1_5_FN, GPSR1_5,
4756 GP_1_4_FN, GPSR1_4,
4757 GP_1_3_FN, GPSR1_3,
4758 GP_1_2_FN, GPSR1_2,
4759 GP_1_1_FN, GPSR1_1,
4760 GP_1_0_FN, GPSR1_0, }
4761 },
4762 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4763 0, 0,
4764 0, 0,
4765 0, 0,
4766 0, 0,
4767 0, 0,
4768 0, 0,
4769 0, 0,
4770 0, 0,
4771 0, 0,
4772 0, 0,
4773 0, 0,
4774 0, 0,
4775 0, 0,
4776 0, 0,
4777 0, 0,
4778 0, 0,
4779 0, 0,
4780 GP_2_14_FN, GPSR2_14,
4781 GP_2_13_FN, GPSR2_13,
4782 GP_2_12_FN, GPSR2_12,
4783 GP_2_11_FN, GPSR2_11,
4784 GP_2_10_FN, GPSR2_10,
4785 GP_2_9_FN, GPSR2_9,
4786 GP_2_8_FN, GPSR2_8,
4787 GP_2_7_FN, GPSR2_7,
4788 GP_2_6_FN, GPSR2_6,
4789 GP_2_5_FN, GPSR2_5,
4790 GP_2_4_FN, GPSR2_4,
4791 GP_2_3_FN, GPSR2_3,
4792 GP_2_2_FN, GPSR2_2,
4793 GP_2_1_FN, GPSR2_1,
4794 GP_2_0_FN, GPSR2_0, }
4795 },
4796 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4797 0, 0,
4798 0, 0,
4799 0, 0,
4800 0, 0,
4801 0, 0,
4802 0, 0,
4803 0, 0,
4804 0, 0,
4805 0, 0,
4806 0, 0,
4807 0, 0,
4808 0, 0,
4809 0, 0,
4810 0, 0,
4811 0, 0,
4812 0, 0,
4813 GP_3_15_FN, GPSR3_15,
4814 GP_3_14_FN, GPSR3_14,
4815 GP_3_13_FN, GPSR3_13,
4816 GP_3_12_FN, GPSR3_12,
4817 GP_3_11_FN, GPSR3_11,
4818 GP_3_10_FN, GPSR3_10,
4819 GP_3_9_FN, GPSR3_9,
4820 GP_3_8_FN, GPSR3_8,
4821 GP_3_7_FN, GPSR3_7,
4822 GP_3_6_FN, GPSR3_6,
4823 GP_3_5_FN, GPSR3_5,
4824 GP_3_4_FN, GPSR3_4,
4825 GP_3_3_FN, GPSR3_3,
4826 GP_3_2_FN, GPSR3_2,
4827 GP_3_1_FN, GPSR3_1,
4828 GP_3_0_FN, GPSR3_0, }
4829 },
4830 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4831 0, 0,
4832 0, 0,
4833 0, 0,
4834 0, 0,
4835 0, 0,
4836 0, 0,
4837 0, 0,
4838 0, 0,
4839 0, 0,
4840 0, 0,
4841 0, 0,
4842 0, 0,
4843 0, 0,
4844 0, 0,
4845 GP_4_17_FN, GPSR4_17,
4846 GP_4_16_FN, GPSR4_16,
4847 GP_4_15_FN, GPSR4_15,
4848 GP_4_14_FN, GPSR4_14,
4849 GP_4_13_FN, GPSR4_13,
4850 GP_4_12_FN, GPSR4_12,
4851 GP_4_11_FN, GPSR4_11,
4852 GP_4_10_FN, GPSR4_10,
4853 GP_4_9_FN, GPSR4_9,
4854 GP_4_8_FN, GPSR4_8,
4855 GP_4_7_FN, GPSR4_7,
4856 GP_4_6_FN, GPSR4_6,
4857 GP_4_5_FN, GPSR4_5,
4858 GP_4_4_FN, GPSR4_4,
4859 GP_4_3_FN, GPSR4_3,
4860 GP_4_2_FN, GPSR4_2,
4861 GP_4_1_FN, GPSR4_1,
4862 GP_4_0_FN, GPSR4_0, }
4863 },
4864 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4865 0, 0,
4866 0, 0,
4867 0, 0,
4868 0, 0,
4869 0, 0,
4870 0, 0,
4871 GP_5_25_FN, GPSR5_25,
4872 GP_5_24_FN, GPSR5_24,
4873 GP_5_23_FN, GPSR5_23,
4874 GP_5_22_FN, GPSR5_22,
4875 GP_5_21_FN, GPSR5_21,
4876 GP_5_20_FN, GPSR5_20,
4877 GP_5_19_FN, GPSR5_19,
4878 GP_5_18_FN, GPSR5_18,
4879 GP_5_17_FN, GPSR5_17,
4880 GP_5_16_FN, GPSR5_16,
4881 GP_5_15_FN, GPSR5_15,
4882 GP_5_14_FN, GPSR5_14,
4883 GP_5_13_FN, GPSR5_13,
4884 GP_5_12_FN, GPSR5_12,
4885 GP_5_11_FN, GPSR5_11,
4886 GP_5_10_FN, GPSR5_10,
4887 GP_5_9_FN, GPSR5_9,
4888 GP_5_8_FN, GPSR5_8,
4889 GP_5_7_FN, GPSR5_7,
4890 GP_5_6_FN, GPSR5_6,
4891 GP_5_5_FN, GPSR5_5,
4892 GP_5_4_FN, GPSR5_4,
4893 GP_5_3_FN, GPSR5_3,
4894 GP_5_2_FN, GPSR5_2,
4895 GP_5_1_FN, GPSR5_1,
4896 GP_5_0_FN, GPSR5_0, }
4897 },
4898 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4899 GP_6_31_FN, GPSR6_31,
4900 GP_6_30_FN, GPSR6_30,
4901 GP_6_29_FN, GPSR6_29,
4902 GP_6_28_FN, GPSR6_28,
4903 GP_6_27_FN, GPSR6_27,
4904 GP_6_26_FN, GPSR6_26,
4905 GP_6_25_FN, GPSR6_25,
4906 GP_6_24_FN, GPSR6_24,
4907 GP_6_23_FN, GPSR6_23,
4908 GP_6_22_FN, GPSR6_22,
4909 GP_6_21_FN, GPSR6_21,
4910 GP_6_20_FN, GPSR6_20,
4911 GP_6_19_FN, GPSR6_19,
4912 GP_6_18_FN, GPSR6_18,
4913 GP_6_17_FN, GPSR6_17,
4914 GP_6_16_FN, GPSR6_16,
4915 GP_6_15_FN, GPSR6_15,
4916 GP_6_14_FN, GPSR6_14,
4917 GP_6_13_FN, GPSR6_13,
4918 GP_6_12_FN, GPSR6_12,
4919 GP_6_11_FN, GPSR6_11,
4920 GP_6_10_FN, GPSR6_10,
4921 GP_6_9_FN, GPSR6_9,
4922 GP_6_8_FN, GPSR6_8,
4923 GP_6_7_FN, GPSR6_7,
4924 GP_6_6_FN, GPSR6_6,
4925 GP_6_5_FN, GPSR6_5,
4926 GP_6_4_FN, GPSR6_4,
4927 GP_6_3_FN, GPSR6_3,
4928 GP_6_2_FN, GPSR6_2,
4929 GP_6_1_FN, GPSR6_1,
4930 GP_6_0_FN, GPSR6_0, }
4931 },
4932 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4933 0, 0,
4934 0, 0,
4935 0, 0,
4936 0, 0,
4937 0, 0,
4938 0, 0,
4939 0, 0,
4940 0, 0,
4941 0, 0,
4942 0, 0,
4943 0, 0,
4944 0, 0,
4945 0, 0,
4946 0, 0,
4947 0, 0,
4948 0, 0,
4949 0, 0,
4950 0, 0,
4951 0, 0,
4952 0, 0,
4953 0, 0,
4954 0, 0,
4955 0, 0,
4956 0, 0,
4957 0, 0,
4958 0, 0,
4959 0, 0,
4960 0, 0,
4961 GP_7_3_FN, GPSR7_3,
4962 GP_7_2_FN, GPSR7_2,
4963 GP_7_1_FN, GPSR7_1,
4964 GP_7_0_FN, GPSR7_0, }
4965 },
4966#undef F_
4967#undef FM
4968
4969#define F_(x, y) x,
4970#define FM(x) FN_##x,
4971 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4972 IP0_31_28
4973 IP0_27_24
4974 IP0_23_20
4975 IP0_19_16
4976 IP0_15_12
4977 IP0_11_8
4978 IP0_7_4
4979 IP0_3_0 }
4980 },
4981 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4982 IP1_31_28
4983 IP1_27_24
4984 IP1_23_20
4985 IP1_19_16
4986 IP1_15_12
4987 IP1_11_8
4988 IP1_7_4
4989 IP1_3_0 }
4990 },
4991 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4992 IP2_31_28
4993 IP2_27_24
4994 IP2_23_20
4995 IP2_19_16
4996 IP2_15_12
4997 IP2_11_8
4998 IP2_7_4
4999 IP2_3_0 }
5000 },
5001 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5002 IP3_31_28
5003 IP3_27_24
5004 IP3_23_20
5005 IP3_19_16
5006 IP3_15_12
5007 IP3_11_8
5008 IP3_7_4
5009 IP3_3_0 }
5010 },
5011 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5012 IP4_31_28
5013 IP4_27_24
5014 IP4_23_20
5015 IP4_19_16
5016 IP4_15_12
5017 IP4_11_8
5018 IP4_7_4
5019 IP4_3_0 }
5020 },
5021 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5022 IP5_31_28
5023 IP5_27_24
5024 IP5_23_20
5025 IP5_19_16
5026 IP5_15_12
5027 IP5_11_8
5028 IP5_7_4
5029 IP5_3_0 }
5030 },
5031 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5032 IP6_31_28
5033 IP6_27_24
5034 IP6_23_20
5035 IP6_19_16
5036 IP6_15_12
5037 IP6_11_8
5038 IP6_7_4
5039 IP6_3_0 }
5040 },
5041 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5042 IP7_31_28
5043 IP7_27_24
5044 IP7_23_20
5045 IP7_19_16
30cd1c46 5046 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5047 IP7_11_8
5048 IP7_7_4
5049 IP7_3_0 }
5050 },
5051 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5052 IP8_31_28
5053 IP8_27_24
5054 IP8_23_20
5055 IP8_19_16
5056 IP8_15_12
5057 IP8_11_8
5058 IP8_7_4
5059 IP8_3_0 }
5060 },
5061 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5062 IP9_31_28
5063 IP9_27_24
5064 IP9_23_20
5065 IP9_19_16
5066 IP9_15_12
5067 IP9_11_8
5068 IP9_7_4
5069 IP9_3_0 }
5070 },
5071 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5072 IP10_31_28
5073 IP10_27_24
5074 IP10_23_20
5075 IP10_19_16
5076 IP10_15_12
5077 IP10_11_8
5078 IP10_7_4
5079 IP10_3_0 }
5080 },
5081 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5082 IP11_31_28
5083 IP11_27_24
5084 IP11_23_20
5085 IP11_19_16
5086 IP11_15_12
5087 IP11_11_8
5088 IP11_7_4
5089 IP11_3_0 }
5090 },
5091 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5092 IP12_31_28
5093 IP12_27_24
5094 IP12_23_20
5095 IP12_19_16
5096 IP12_15_12
5097 IP12_11_8
5098 IP12_7_4
5099 IP12_3_0 }
5100 },
5101 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5102 IP13_31_28
5103 IP13_27_24
5104 IP13_23_20
5105 IP13_19_16
5106 IP13_15_12
5107 IP13_11_8
5108 IP13_7_4
5109 IP13_3_0 }
5110 },
5111 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5112 IP14_31_28
5113 IP14_27_24
5114 IP14_23_20
5115 IP14_19_16
5116 IP14_15_12
5117 IP14_11_8
5118 IP14_7_4
5119 IP14_3_0 }
5120 },
5121 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5122 IP15_31_28
5123 IP15_27_24
5124 IP15_23_20
5125 IP15_19_16
5126 IP15_15_12
5127 IP15_11_8
5128 IP15_7_4
5129 IP15_3_0 }
5130 },
5131 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5132 IP16_31_28
5133 IP16_27_24
5134 IP16_23_20
5135 IP16_19_16
5136 IP16_15_12
5137 IP16_11_8
5138 IP16_7_4
5139 IP16_3_0 }
5140 },
5141 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
b205914c
GU		 5142 IP17_31_28
5143 IP17_27_24
5144 IP17_23_20
5145 IP17_19_16
5146 IP17_15_12
5147 IP17_11_8
0b0ffc96
TK		 5148 IP17_7_4
5149 IP17_3_0 }
5150 },
b205914c
GU		 5151 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5152 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5153 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5154 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5155 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5156 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5157 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5158 IP18_7_4
5159 IP18_3_0 }
5160 },
0b0ffc96
TK		 5161#undef F_
5162#undef FM
5163
5164#define F_(x, y) x,
5165#define FM(x) FN_##x,
5166 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
b205914c
GU		 5167 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5168 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5169 MOD_SEL0_31_30_29
0b0ffc96
TK		 5170 MOD_SEL0_28_27
5171 MOD_SEL0_26_25_24
5172 MOD_SEL0_23
5173 MOD_SEL0_22
b205914c
GU		 5174 MOD_SEL0_21
5175 MOD_SEL0_20
0b0ffc96 5176 MOD_SEL0_19
b205914c
GU		 5177 MOD_SEL0_18_17
5178 MOD_SEL0_16
5179 0, 0, /* RESERVED 15 */
5180 MOD_SEL0_14_13
0b0ffc96
TK		 5181 MOD_SEL0_12
5182 MOD_SEL0_11
5183 MOD_SEL0_10
b205914c 5184 MOD_SEL0_9_8
0b0ffc96 5185 MOD_SEL0_7_6
b205914c
GU		 5186 MOD_SEL0_5
5187 MOD_SEL0_4_3
5188 /* RESERVED 2, 1, 0 */
5189 0, 0, 0, 0, 0, 0, 0, 0 }
0b0ffc96
TK		 5190 },
5191 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5192 2, 3, 1, 2, 3, 1, 1, 2, 1,
5193 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5194 MOD_SEL1_31_30
5195 MOD_SEL1_29_28_27
5196 MOD_SEL1_26
5197 MOD_SEL1_25_24
5198 MOD_SEL1_23_22_21
5199 MOD_SEL1_20
5200 MOD_SEL1_19
5201 MOD_SEL1_18_17
5202 MOD_SEL1_16
5203 MOD_SEL1_15_14
5204 MOD_SEL1_13
5205 MOD_SEL1_12
5206 MOD_SEL1_11
5207 MOD_SEL1_10
5208 MOD_SEL1_9
5209 0, 0, 0, 0, /* RESERVED 8, 7 */
5210 MOD_SEL1_6
5211 MOD_SEL1_5
5212 MOD_SEL1_4
5213 MOD_SEL1_3
5214 MOD_SEL1_2
5215 MOD_SEL1_1
5216 MOD_SEL1_0 }
5217 },
5218 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
b205914c
GU		 5219 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5220 4, 4, 4, 3, 1) {
0b0ffc96
TK		 5221 MOD_SEL2_31
5222 MOD_SEL2_30
5223 MOD_SEL2_29
b205914c
GU		 5224 MOD_SEL2_28_27
5225 MOD_SEL2_26
5226 MOD_SEL2_25_24_23
3c612d2c
TK		 5227 /* RESERVED 22 */
5228 0, 0,
b205914c
GU		 5229 MOD_SEL2_21
5230 MOD_SEL2_20
5231 MOD_SEL2_19
5232 MOD_SEL2_18
5233 MOD_SEL2_17
5234 /* RESERVED 16 */
0b0ffc96 5235 0, 0,
0b0ffc96
TK		 5236 /* RESERVED 15, 14, 13, 12 */
5237 0, 0, 0, 0, 0, 0, 0, 0,
5238 0, 0, 0, 0, 0, 0, 0, 0,
5239 /* RESERVED 11, 10, 9, 8 */
5240 0, 0, 0, 0, 0, 0, 0, 0,
5241 0, 0, 0, 0, 0, 0, 0, 0,
5242 /* RESERVED 7, 6, 5, 4 */
5243 0, 0, 0, 0, 0, 0, 0, 0,
5244 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 5245 /* RESERVED 3, 2, 1 */
5246 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5247 MOD_SEL2_0 }
5248 },
5249 { },
5250};
5251
92e6d9a2 5252static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 5253 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5254 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5255 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5256 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5257 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5258 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5259 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5260 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5261 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5262 } },
5263 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5264 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5265 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5266 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5267 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5268 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5269 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5270 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5271 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5272 } },
5273 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5274 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5275 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5276 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5277 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5278 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5279 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5280 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5281 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5282 } },
92e6d9a2 5283 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 5284 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5285 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5286 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5287 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5288 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5289 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5290 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5291 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 5292 } },
5293 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5294 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5295 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5296 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5297 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5298 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5299 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5300 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5301 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5302 } },
5303 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5304 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5305 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5306 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5307 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5308 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5309 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5310 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5311 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5312 } },
5313 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5314 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5315 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5316 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5317 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5318 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5319 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5320 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5321 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5322 } },
5323 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5324 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5325 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5326 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5327 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5328 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5329 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5330 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5331 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5332 } },
5333 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
82d2de5a 5334 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 5335 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5336 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5337 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5338 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5339 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5340 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5341 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5342 } },
5343 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5344 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 5345 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 5346 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5347 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5348 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5349 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5350 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5351 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5352 } },
5353 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5354 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5355 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5356 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5357 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5358 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5359 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5360 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5361 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5362 } },
5363 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 5364 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5365 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5366 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5367 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5368 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5369 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5370 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5371 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5372 } },
5373 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5374 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5375 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5376 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5377 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 5378 } },
5379 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 5380 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5381 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5382 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5383 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5384 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5385 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5386 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5387 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 5388 } },
5389 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5390 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5391 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5392 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5393 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5394 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5395 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5396 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5397 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5398 } },
5399 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5400 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5401 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5402 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5403 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5404 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5405 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5406 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5407 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5408 } },
5409 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5410 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5411 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5412 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5413 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5414 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5415 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5416 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5417 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5418 } },
5419 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5420 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5421 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5422 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5423 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5424 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5425 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5426 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5427 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5428 } },
5429 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5430 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5431 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5432 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5433 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5434 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5435 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5436 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5437 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5438 } },
5439 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5440 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5441 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5442 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5443 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5444 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5445 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5446 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5447 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5448 } },
5449 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5450 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5451 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5452 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5453 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5454 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5455 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 5456 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 5457 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5458 } },
5459 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5460 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5461 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5462 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5463 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 5464 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5465 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 5466 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5467 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5468 } },
5469 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5470 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5471 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5472 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5473 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5474 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5475 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5476 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5477 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5478 } },
5479 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5480 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5481 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5482 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5483 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5484 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5485 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5486 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5487 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5488 } },
5489 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5490 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5491 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5492 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5493 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5494 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
f9d13080
YS		 5495 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5496 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
92e6d9a2
LP		 5497 } },
5498 { },
5499};
5500
e2aad846
GU		 5501enum ioctrl_regs {
5502 POCCTRL,
5503};
5504
5505static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5506 [POCCTRL] = { 0xe6060380, },
5507 { /* sentinel */ },
5508};
5509
e9eace32
WS		 5510static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5511{
5512 int bit = -EINVAL;
5513
e2aad846 5514 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
e9eace32
WS		 5515
5516 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5517 bit = pin & 0x1f;
5518
5519 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5520 bit = (pin & 0x1f) + 12;
5521
5522 return bit;
5523}
5524
6f4b74f3
GU		 5525static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5526 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5527 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5528 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5529 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5530 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5531 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5532 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5533 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5534 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5535 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5536 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5537 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5538 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5539 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5540 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5541 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5542 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5543 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5544 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5545 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5546 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5547 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5548 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5549 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5550 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5551 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5552 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5553 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5554 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5555 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5556 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5557 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5558 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5559 } },
5560 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5561 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5562 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5563 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5564 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5565 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5566 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5567 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5568 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5569 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5570 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5571 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5572 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5573 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5574 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5575 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5576 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5577 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5578 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5579 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5580 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5581 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5582 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5583 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5584 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5585 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5586 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5587 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5588 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5589 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5590 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5591 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5592 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5593 } },
5594 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
82d2de5a 5595 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6f4b74f3
GU		 5596 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5597 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5598 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5599 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5600 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5601 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5602 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5603 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5604 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5605 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5606 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5607 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5608 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5609 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5610 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5611 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5612 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5613 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5614 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5615 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5616 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5617 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5618 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5619 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5620 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5621 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5622 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5623 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5624 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
5625 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5626 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5627 } },
5628 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5629 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
5630 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
5631 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
5632 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5633 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5634 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5635 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5636 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5637 [ 8] = PIN_NONE,
5638 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5639 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5640 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5641 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5642 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5643 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5644 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5645 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5646 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5647 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5648 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5649 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5650 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5651 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5652 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5653 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5654 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5655 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5656 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5657 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5658 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5659 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5660 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5661 } },
5662 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5663 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5664 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5665 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5666 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5667 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5668 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5669 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5670 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5671 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5672 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5673 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5674 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5675 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5676 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5677 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5678 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5679 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
5680 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5681 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5682 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5683 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
5684 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5685 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5686 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5687 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5688 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5689 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5690 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5691 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5692 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5693 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5694 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5695 } },
5696 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5697 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5698 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5699 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5700 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5701 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5702 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5703 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5704 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5705 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5706 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5707 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5708 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5709 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5710 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5711 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5712 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5713 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5714 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5715 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5716 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5717 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5718 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5719 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5720 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5721 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5722 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5723 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5724 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5725 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5726 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5727 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5728 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5729 } },
5730 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5731 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5732 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5733 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5734 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5735 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5736 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
5737 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
5738 [ 7] = PIN_NONE,
5739 [ 8] = PIN_NONE,
5740 [ 9] = PIN_NONE,
5741 [10] = PIN_NONE,
5742 [11] = PIN_NONE,
5743 [12] = PIN_NONE,
5744 [13] = PIN_NONE,
5745 [14] = PIN_NONE,
5746 [15] = PIN_NONE,
5747 [16] = PIN_NONE,
5748 [17] = PIN_NONE,
5749 [18] = PIN_NONE,
5750 [19] = PIN_NONE,
5751 [20] = PIN_NONE,
5752 [21] = PIN_NONE,
5753 [22] = PIN_NONE,
5754 [23] = PIN_NONE,
5755 [24] = PIN_NONE,
5756 [25] = PIN_NONE,
5757 [26] = PIN_NONE,
5758 [27] = PIN_NONE,
5759 [28] = PIN_NONE,
5760 [29] = PIN_NONE,
5761 [30] = PIN_NONE,
5762 [31] = PIN_NONE,
5763 } },
5764 { /* sentinel */ },
56065524
UH		 5765};
5766
5767static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5768 unsigned int pin)
5769{
6f4b74f3
GU		 5770 const struct pinmux_bias_reg *reg;
5771 unsigned int bit;
56065524 5772
6f4b74f3
GU		 5773 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5774 if (!reg)
56065524
UH		 5775 return PIN_CONFIG_BIAS_DISABLE;
5776
6f4b74f3 5777 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
56065524 5778 return PIN_CONFIG_BIAS_DISABLE;
6f4b74f3 5779 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
42831cf9
NS		 5780 return PIN_CONFIG_BIAS_PULL_UP;
5781 else
5782 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 5783}
5784
5785static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5786 unsigned int bias)
5787{
6f4b74f3 5788 const struct pinmux_bias_reg *reg;
56065524 5789 u32 enable, updown;
6f4b74f3 5790 unsigned int bit;
56065524 5791
6f4b74f3
GU		 5792 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5793 if (!reg)
56065524
UH		 5794 return;
5795
6f4b74f3 5796 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
56065524 5797 if (bias != PIN_CONFIG_BIAS_DISABLE)
6f4b74f3 5798 enable |= BIT(bit);
56065524 5799
6f4b74f3 5800 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
56065524 5801 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6f4b74f3 5802 updown |= BIT(bit);
56065524 5803
6f4b74f3
GU		 5804 sh_pfc_write(pfc, reg->pud, updown);
5805 sh_pfc_write(pfc, reg->puen, enable);
56065524
UH		 5806}
5807
b205914c
GU		 5808static const struct soc_device_attribute r8a7795es1[] = {
5809 { .soc_id = "r8a7795", .revision = "ES1.*" },
5810 { /* sentinel */ }
5811};
5812
5813static int r8a7795_pinmux_init(struct sh_pfc *pfc)
5814{
5815 if (soc_device_match(r8a7795es1))
5816 pfc->info = &r8a7795es1_pinmux_info;
5817
5818 return 0;
5819}
5820
e9eace32 5821static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 5822 .init = r8a7795_pinmux_init,
e9eace32 5823 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 5824 .get_bias = r8a7795_pinmux_get_bias,
5825 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 5826};
5827
0b0ffc96 5828const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 5829 .name = "r8a77951_pfc",
e9eace32 5830 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 5831 .unlock_reg = 0xe6060000, /* PMMR */
5832
5833 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5834
5835 .pins = pinmux_pins,
5836 .nr_pins = ARRAY_SIZE(pinmux_pins),
5837 .groups = pinmux_groups,
5838 .nr_groups = ARRAY_SIZE(pinmux_groups),
5839 .functions = pinmux_functions,
5840 .nr_functions = ARRAY_SIZE(pinmux_functions),
5841
5842 .cfg_regs = pinmux_config_regs,
92e6d9a2 5843 .drive_regs = pinmux_drive_regs,
6f4b74f3 5844 .bias_regs = pinmux_bias_regs,
e2aad846 5845 .ioctrl_regs = pinmux_ioctrl_regs,
0b0ffc96 5846
b8b47d67
GU		 5847 .pinmux_data = pinmux_data,
5848 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 5849};
Linux 6.x block layer and io_uring tree(s)