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pinctrl: sh-pfc: r8a7795-es1: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
CommitLineData
0b0ffc96 1/*
b205914c 2 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 3 *
b205914c 4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
0b0ffc96
TK		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
b205914c 12#include <linux/sys_soc.h>
0b0ffc96
TK		 13
14#include "core.h"
15#include "sh_pfc.h"
16
56065524
UH		 17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
0b0ffc96 21#define CPU_ALL_PORT(fn, sfx) \
56065524 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
82d2de5a 23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
56065524
UH		 24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
82d2de5a 58#define GPSR1_28 FM(CLKOUT)
0b0ffc96
TK		 59#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
60#define GPSR1_26 F_(WE1_N, IP5_7_4)
61#define GPSR1_25 F_(WE0_N, IP5_3_0)
62#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
63#define GPSR1_23 F_(RD_N, IP4_27_24)
64#define GPSR1_22 F_(BS_N, IP4_23_20)
fc8fd9be 65#define GPSR1_21 F_(CS1_N, IP4_19_16)
0b0ffc96
TK		 66#define GPSR1_20 F_(CS0_N, IP4_15_12)
67#define GPSR1_19 F_(A19, IP4_11_8)
68#define GPSR1_18 F_(A18, IP4_7_4)
69#define GPSR1_17 F_(A17, IP4_3_0)
70#define GPSR1_16 F_(A16, IP3_31_28)
71#define GPSR1_15 F_(A15, IP3_27_24)
72#define GPSR1_14 F_(A14, IP3_23_20)
73#define GPSR1_13 F_(A13, IP3_19_16)
74#define GPSR1_12 F_(A12, IP3_15_12)
75#define GPSR1_11 F_(A11, IP3_11_8)
76#define GPSR1_10 F_(A10, IP3_7_4)
77#define GPSR1_9 F_(A9, IP3_3_0)
78#define GPSR1_8 F_(A8, IP2_31_28)
79#define GPSR1_7 F_(A7, IP2_27_24)
80#define GPSR1_6 F_(A6, IP2_23_20)
81#define GPSR1_5 F_(A5, IP2_19_16)
82#define GPSR1_4 F_(A4, IP2_15_12)
83#define GPSR1_3 F_(A3, IP2_11_8)
84#define GPSR1_2 F_(A2, IP2_7_4)
85#define GPSR1_1 F_(A1, IP2_3_0)
86#define GPSR1_0 F_(A0, IP1_31_28)
87
88/* GPSR2 */
89#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
90#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
91#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
92#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
93#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
94#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
95#define GPSR2_8 F_(PWM2_A, IP1_27_24)
96#define GPSR2_7 F_(PWM1_A, IP1_23_20)
97#define GPSR2_6 F_(PWM0, IP1_19_16)
98#define GPSR2_5 F_(IRQ5, IP1_15_12)
99#define GPSR2_4 F_(IRQ4, IP1_11_8)
100#define GPSR2_3 F_(IRQ3, IP1_7_4)
101#define GPSR2_2 F_(IRQ2, IP1_3_0)
102#define GPSR2_1 F_(IRQ1, IP0_31_28)
103#define GPSR2_0 F_(IRQ0, IP0_27_24)
104
105/* GPSR3 */
b205914c
GU		 106#define GPSR3_15 F_(SD1_WP, IP11_23_20)
107#define GPSR3_14 F_(SD1_CD, IP11_19_16)
108#define GPSR3_13 F_(SD0_WP, IP11_15_12)
109#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 110#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
111#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
112#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
113#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
114#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
115#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
116#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
117#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
118#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
119#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
120#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
121#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
122
123/* GPSR4 */
b205914c
GU		 124#define GPSR4_17 F_(SD3_DS, IP11_7_4)
125#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
126#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
127#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
128#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
129#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
130#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
131#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
132#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
133#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
134#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
135#define GPSR4_6 F_(SD2_DS, IP9_27_24)
136#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
137#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
138#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
139#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
140#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 141#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
142
143/* GPSR5 */
b205914c
GU		 144#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
145#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
146#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 147#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 148#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 149#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 150#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
151#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 152#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 153#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
154#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
155#define GPSR5_14 F_(HTX0, IP13_19_16)
156#define GPSR5_13 F_(HRX0, IP13_15_12)
157#define GPSR5_12 F_(HSCK0, IP13_11_8)
158#define GPSR5_11 F_(RX2_A, IP13_7_4)
159#define GPSR5_10 F_(TX2_A, IP13_3_0)
160#define GPSR5_9 F_(SCK2, IP12_31_28)
161#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
162#define GPSR5_7 F_(CTS1_N, IP12_23_20)
163#define GPSR5_6 F_(TX1_A, IP12_19_16)
164#define GPSR5_5 F_(RX1_A, IP12_15_12)
165#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
166#define GPSR5_3 F_(CTS0_N, IP12_7_4)
167#define GPSR5_2 F_(TX0, IP12_3_0)
168#define GPSR5_1 F_(RX0, IP11_31_28)
169#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 170
171/* GPSR6 */
f9d13080
YS		 172#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
173#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
b205914c
GU		 174#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
175#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
176#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
177#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
178#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
179#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
180#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
181#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
182#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
183#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
184#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
185#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
186#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
187#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
188#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
189#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 190#define GPSR6_13 FM(SSI_SDATA5)
191#define GPSR6_12 FM(SSI_WS5)
192#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 193#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
194#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
195#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
196#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 197#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
198#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 199#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
200#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
201#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
202#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
203#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 204
205/* GPSR7 */
206#define GPSR7_3 FM(HDMI1_CEC)
207#define GPSR7_2 FM(HDMI0_CEC)
208#define GPSR7_1 FM(AVS2)
209#define GPSR7_0 FM(AVS1)
210
211
212/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
213#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 217#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96 218#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
e2ab1770
TK		 219#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 221#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 225#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232
233/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
234#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
fc8fd9be 251#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 252#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 274#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 283#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 288#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 306#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 307
308/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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GU		 309#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337
338/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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KM		 342#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 344#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
bad7cc19
TK		 364#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
365#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
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TK		 366
367#define PINMUX_GPSR \
368\
369 GPSR6_31 \
370 GPSR6_30 \
371 GPSR6_29 \
82d2de5a 372 GPSR1_28 GPSR6_28 \
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TK		 373 GPSR1_27 GPSR6_27 \
374 GPSR1_26 GPSR6_26 \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
401
402#define PINMUX_IPSR \
403\
404FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412\
413FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
30cd1c46 416FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
0b0ffc96
TK		 417FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421\
422FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430\
431FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439\
b205914c
GU		 440FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 448
449/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 450#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 451#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 455#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 468
469/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
ae03c4ec 472#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
0b0ffc96
TK		 473#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
eada11ac 483#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
0b0ffc96
TK		 484#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
492
493/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
494#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 497#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 500#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
501#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
502#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
503#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
504#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 505#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
506
b205914c 507#define PINMUX_MOD_SELS \
0b0ffc96 508\
b205914c
GU		 509MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
510 MOD_SEL2_30 \
0b0ffc96 511 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 512MOD_SEL0_28_27 MOD_SEL2_28_27 \
513MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
514 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 515MOD_SEL0_23 MOD_SEL1_23_22_21 \
3c612d2c 516MOD_SEL0_22 \
b205914c
GU		 517MOD_SEL0_21 MOD_SEL2_21 \
518MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
519MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
520MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
521 MOD_SEL2_17 \
522MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 523 MOD_SEL1_15_14 \
b205914c
GU		 524MOD_SEL0_14_13 \
525 MOD_SEL1_13 \
0b0ffc96
TK		 526MOD_SEL0_12 MOD_SEL1_12 \
527MOD_SEL0_11 MOD_SEL1_11 \
528MOD_SEL0_10 MOD_SEL1_10 \
b205914c 529MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 530MOD_SEL0_7_6 \
531 MOD_SEL1_6 \
b205914c
GU		 532MOD_SEL0_5 MOD_SEL1_5 \
533MOD_SEL0_4_3 MOD_SEL1_4 \
534 MOD_SEL1_3 \
535 MOD_SEL1_2 \
0b0ffc96
TK		 536 MOD_SEL1_1 \
537 MOD_SEL1_0 MOD_SEL2_0
538
ea9c7405
NS		 539/*
540 * These pins are not able to be muxed but have other properties
541 * that can be set, such as drive-strength or pull-up/pull-down enable.
542 */
543#define PINMUX_STATIC \
544 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
545 FM(QSPI0_IO2) FM(QSPI0_IO3) \
546 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
547 FM(QSPI1_IO2) FM(QSPI1_IO3) \
548 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
549 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
550 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
551 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
82d2de5a 552 FM(PRESETOUT) \
ea9c7405 553 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 554 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96
TK		 555
556enum {
557 PINMUX_RESERVED = 0,
558
559 PINMUX_DATA_BEGIN,
560 GP_ALL(DATA),
561 PINMUX_DATA_END,
562
563#define F_(x, y)
564#define FM(x) FN_##x,
565 PINMUX_FUNCTION_BEGIN,
566 GP_ALL(FN),
567 PINMUX_GPSR
568 PINMUX_IPSR
569 PINMUX_MOD_SELS
570 PINMUX_FUNCTION_END,
571#undef F_
572#undef FM
573
574#define F_(x, y)
575#define FM(x) x##_MARK,
576 PINMUX_MARK_BEGIN,
577 PINMUX_GPSR
578 PINMUX_IPSR
579 PINMUX_MOD_SELS
ea9c7405 580 PINMUX_STATIC
0b0ffc96
TK		 581 PINMUX_MARK_END,
582#undef F_
583#undef FM
584};
585
586static const u16 pinmux_data[] = {
587 PINMUX_DATA_GP_ALL(),
588
8d4df573
GU		 589 PINMUX_SINGLE(AVS1),
590 PINMUX_SINGLE(AVS2),
82d2de5a 591 PINMUX_SINGLE(CLKOUT),
8d4df573
GU		 592 PINMUX_SINGLE(HDMI0_CEC),
593 PINMUX_SINGLE(HDMI1_CEC),
d07640f5
KM		 594 PINMUX_SINGLE(I2C_SEL_0_1),
595 PINMUX_SINGLE(I2C_SEL_3_1),
596 PINMUX_SINGLE(I2C_SEL_5_1),
8d4df573
GU		 597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
0b0ffc96 604 /* IPSR0 */
e01678e3 605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
e01678e3 608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
e01678e3 612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
e01678e3 616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
b205914c 623 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
0b0ffc96
TK		 624
625 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
626 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
627 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
628
e01678e3
GU		 629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
631 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 632 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 635 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 636
e01678e3
GU		 637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 644
645 /* IPSR1 */
e01678e3
GU		 646 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
647 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
648 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 649 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 651 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 652
e01678e3
GU		 653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
655 PINMUX_IPSR_GPSR(IP1_7_4, A25),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 660
e01678e3
GU		 661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, A24),
664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 668
e01678e3
GU		 669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
671 PINMUX_IPSR_GPSR(IP1_15_12, A23),
672 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 673 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 675 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
676 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 677
e01678e3
GU		 678 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
679 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
680 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 681 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
683
684 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 685 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 686 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
687 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
688 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 691 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 692 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
693 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
694
e01678e3
GU		 695 PINMUX_IPSR_GPSR(IP1_31_28, A0),
696 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 697 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 698 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
699 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 700 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
701
702 /* IPSR2 */
e01678e3
GU		 703 PINMUX_IPSR_GPSR(IP2_3_0, A1),
704 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 705 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 706 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
707 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 708 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
709
e01678e3
GU		 710 PINMUX_IPSR_GPSR(IP2_7_4, A2),
711 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 712 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 713 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
714 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 715 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
716
e01678e3
GU		 717 PINMUX_IPSR_GPSR(IP2_11_8, A3),
718 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 719 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 720 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
721 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 722 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
723
e01678e3
GU		 724 PINMUX_IPSR_GPSR(IP2_15_12, A4),
725 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 726 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 727 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
728 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
729 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 730
e01678e3
GU		 731 PINMUX_IPSR_GPSR(IP2_19_16, A5),
732 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 733 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
734 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 735 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
736 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
737 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 738
e01678e3
GU		 739 PINMUX_IPSR_GPSR(IP2_23_20, A6),
740 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 741 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 743 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
744 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
745 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 746
e01678e3
GU		 747 PINMUX_IPSR_GPSR(IP2_27_24, A7),
748 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 749 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
750 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 751 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
752 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
753 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 754
e01678e3 755 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 756 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
760 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
761 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
762
763 /* IPSR3 */
e01678e3 764 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 765 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 767 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 768
e01678e3 769 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 770 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
771 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 772 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 773
e01678e3 774 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 775 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
776 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
777 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 778 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
779 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 780 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
781 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
782 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
783
e01678e3
GU		 784 PINMUX_IPSR_GPSR(IP3_15_12, A12),
785 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 786 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 788 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
789 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 790
e01678e3
GU		 791 PINMUX_IPSR_GPSR(IP3_19_16, A13),
792 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 793 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 795 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
796 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 797
e01678e3
GU		 798 PINMUX_IPSR_GPSR(IP3_23_20, A14),
799 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 800 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 801 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
802 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
803 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 804
e01678e3
GU		 805 PINMUX_IPSR_GPSR(IP3_27_24, A15),
806 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 807 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 808 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
809 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
810 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 811
e01678e3
GU		 812 PINMUX_IPSR_GPSR(IP3_31_28, A16),
813 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
814 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
815 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 816
817 /* IPSR4 */
e01678e3
GU		 818 PINMUX_IPSR_GPSR(IP4_3_0, A17),
819 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
820 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
822
823 PINMUX_IPSR_GPSR(IP4_7_4, A18),
824 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
825 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
826 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
827
828 PINMUX_IPSR_GPSR(IP4_11_8, A19),
829 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
830 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
831 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
832
833 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
834 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
835
fc8fd9be 836 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
e01678e3 837 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 838 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
839
e01678e3
GU		 840 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
841 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 842 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 843 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
844 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
845 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
846 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 847 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
848
e01678e3 849 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 850 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
851 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
854 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
855
e01678e3 856 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 857 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
858 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
860 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
861 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
862
863 /* IPSR5 */
e01678e3 864 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 865 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 866 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
867 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 868 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 869 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 870 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
871
e01678e3 872 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 873 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 874 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
875 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 876 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 877 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
878 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 879 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
880
881 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 882 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
883 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
884 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 885
e01678e3 886 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 887 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
888 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 889 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
890 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 891
e01678e3 892 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 893 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
894 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 895 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
896 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 897
e01678e3 898 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 899 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 900 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
901 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 902
e01678e3 903 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 904 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 905 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
906 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 907
e01678e3 908 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 909 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 910 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
911 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 912
913 /* IPSR6 */
e01678e3 914 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 915 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 916 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
917 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 918
b205914c
GU		 919 PINMUX_IPSR_GPSR(IP6_7_4, D6),
920 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
922 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 923
b205914c
GU		 924 PINMUX_IPSR_GPSR(IP6_11_8, D7),
925 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
926 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
927 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 928
b205914c
GU		 929 PINMUX_IPSR_GPSR(IP6_15_12, D8),
930 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
931 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
933 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
934 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 935
b205914c
GU		 936 PINMUX_IPSR_GPSR(IP6_19_16, D9),
937 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
938 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
940 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 941
b205914c
GU		 942 PINMUX_IPSR_GPSR(IP6_23_20, D10),
943 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
944 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
945 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
946 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
947 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
948 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 949
b205914c
GU		 950 PINMUX_IPSR_GPSR(IP6_27_24, D11),
951 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
952 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
953 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
954 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
955 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
956 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 957
b205914c
GU		 958 PINMUX_IPSR_GPSR(IP6_31_28, D12),
959 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
960 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
961 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
962 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
963 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 964
b205914c
GU		 965 /* IPSR7 */
966 PINMUX_IPSR_GPSR(IP7_3_0, D13),
967 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
968 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
969 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
970 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
971 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 972
b205914c
GU		 973 PINMUX_IPSR_GPSR(IP7_7_4, D14),
974 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
975 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
976 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
977 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
978 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
979 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 980
b205914c
GU		 981 PINMUX_IPSR_GPSR(IP7_11_8, D15),
982 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
983 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
984 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
985 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
986 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
987 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 988
b205914c
GU		 989 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
990 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
991 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 992
b205914c
GU		 993 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
994 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
995 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 996
b205914c
GU		 997 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
998 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
999 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1000 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 1001
b205914c
GU		 1002 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1004 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1005 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1006
b205914c
GU		 1007 /* IPSR8 */
1008 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1009 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1012
b205914c
GU		 1013 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1014 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1015 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1016 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1017
b205914c
GU		 1018 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1019 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1020 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1021
b205914c
GU		 1022 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1023 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
3c612d2c 1024 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
b205914c
GU		 1025 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1026 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1027
b205914c
GU		 1028 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1029 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1030 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
3c612d2c 1031 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
b205914c
GU		 1032 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1033 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1034
b205914c
GU		 1035 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1036 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1037 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
3c612d2c 1038 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
b205914c
GU		 1039 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1040 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1041
b205914c
GU		 1042 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1043 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1044 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
3c612d2c 1045 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
b205914c
GU		 1046 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1047 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1048
b205914c
GU		 1049 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1050 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1051 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
3c612d2c 1052 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
b205914c
GU		 1053 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1054 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1055
b205914c
GU		 1056 /* IPSR9 */
1057 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1058 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1059
b205914c
GU		 1060 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1061 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1062
b205914c
GU		 1063 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1064 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1065
b205914c
GU		 1066 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1067 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1068
b205914c
GU		 1069 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1070 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1071
b205914c
GU		 1072 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1073 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1074
b205914c
GU		 1075 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1076 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1077 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1078
b205914c
GU		 1079 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1080 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1081
b205914c
GU		 1082 /* IPSR10 */
1083 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1084 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1085
b205914c
GU		 1086 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1087 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1088
b205914c
GU		 1089 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1090 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1091
b205914c
GU		 1092 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1093 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1094
b205914c
GU		 1095 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1096 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1097
b205914c
GU		 1098 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1099 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1100 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1101
b205914c
GU		 1102 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1103 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1104 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1105
b205914c
GU		 1106 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1107 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1108 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1109
b205914c
GU		 1110 /* IPSR11 */
1111 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1112 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1113 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1114
1115 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1116 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1117
1118 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1119 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1120 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1121
1122 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1123 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1124
1125 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1126 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1127
1128 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1129 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1130
1131 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1132 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1136 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1139 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1141
1142 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1143 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1144 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1146 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1147
b205914c
GU		 1148 /* IPSR12 */
1149 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1150 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1151 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1153 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1154
1155 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1156 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1158 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1160 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1161 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1162 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1163
1164 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1165 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1168 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1169 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1170 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1171 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1172
1173 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1177 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1178
1179 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1183 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1184
1185 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1186 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1187 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1188 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1190 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1191 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1192
1193 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1194 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1195 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1196 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1198 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1199 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1200
1201 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
eada11ac 1202 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
b205914c
GU		 1203 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1204 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1206 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1207 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1208
b205914c
GU		 1209 /* IPSR13 */
1210 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1212 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1214 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1215 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1216
1217 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1219 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1221 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1222 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1223
1224 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1226 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1227 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1228 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1231 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1232
1233 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1234 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1236 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1238 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1239
1240 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1241 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1243 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1245 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1246
1247 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1248 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1249 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1251 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1253 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1254 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1255
1256 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1257 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1258 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1260 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1262 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1263
1264 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1265 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1266 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1267 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1268
b205914c
GU		 1269 /* IPSR14 */
1270 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1271 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
3c612d2c 1272 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
b205914c
GU		 1273 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1274 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1275 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1276 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
ae03c4ec 1277 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
b205914c
GU		 1278
1279 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1280 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1282 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1284 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1285 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1286 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1287
1288 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1289 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1290 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1291
1292 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1293 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1294 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1295 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1296
1297 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1298 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1299 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1300
1301 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1302 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1303
1304 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1305 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1306
1307 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1308 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1309
b205914c
GU		 1310 /* IPSR15 */
1311 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1312
1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1314 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1315
68e63892 1316 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1317 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1318 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1319
68e63892 1320 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1321 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1323 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1324
1325 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1326 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1332
1333 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1334 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1340
1341 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1342 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1348
1349 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1350 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1356
b205914c
GU		 1357 /* IPSR16 */
1358 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1359 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1360 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1361
1362 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1363 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1364 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1365
1366 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1367 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1368 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1369
1370 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1371 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1372 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1373 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1375 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1377
1378 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1379 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1380 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1381 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1383 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1385
1386 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1387 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1388 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1389 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1391 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
ae03c4ec 1393 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
b205914c
GU		 1394
1395 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1396 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1397 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1398 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1400 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1402
1403 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1405 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1406 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1408 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1409 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
712f36fb 1410 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
20cacae1 1411
b205914c
GU		 1412 /* IPSR17 */
1413 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1414 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1415
1416 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
eada11ac 1417 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
b205914c
GU		 1418 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1419 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
ae03c4ec 1420 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
b205914c
GU		 1421
1422 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1423 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1424 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1425 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1426 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1427 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1428 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1429
1430 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1431 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1432 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1433 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1434 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1435 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1436
1437 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1438 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1439 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1440 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1441 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1442 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1443 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1444 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1445 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1446
1447 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1448 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1449 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1450 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1451 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1452 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1454 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1455 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1456
1457 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1458 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1459 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1460 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
50d83156 1461 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
b205914c
GU		 1462 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1463 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
ae03c4ec 1464 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
b205914c
GU		 1465 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1466 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1467 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1468
1469 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1470 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1471 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1472 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1473 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1474 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1475 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1476 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1477 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1478
1479 /* IPSR18 */
f9d13080 1480 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
b205914c
GU		 1481 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1482 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1483 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1484 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1485 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1486 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1487 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1488 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1489
f9d13080 1490 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
b205914c
GU		 1491 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1492 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1493 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1494 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1495 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1496 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1497 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1498 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1499
b205914c
GU		 1500/*
1501 * Static pins can not be muxed between different functions but
1502 * still needs a mark entry in the pinmux list. Add each static
1503 * pin to the list without an associated function. The sh-pfc
1504 * core will do the right thing and skip trying to mux then pin
1505 * while still applying configuration to it
1506 */
1507#define FM(x) PINMUX_DATA(x##_MARK, 0),
1508 PINMUX_STATIC
1509#undef FM
9b132ba3
KM		 1510};
1511
b205914c 1512/*
ecd54509 1513 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
b205914c
GU		 1514 * Physical layout rows: A - AW, cols: 1 - 39.
1515 */
1516#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1517#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1518#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
6f4b74f3 1519#define PIN_NONE U16_MAX
b205914c
GU		 1520
1521static const struct sh_pfc_pin pinmux_pins[] = {
1522 PINMUX_GPIO_GP_ALL(),
76250a6c 1523
b205914c
GU		 1524 /*
1525 * Pins not associated with a GPIO port.
1526 *
1527 * The pin positions are different between different r8a7795
1528 * packages, all that is needed for the pfc driver is a unique
1529 * number for each pin. To this end use the pin layout from
1530 * R-Car H3SiP to calculate a unique number for each pin.
1531 */
1532 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1576};
1577
55bfea9f
KM		 1578/* - AUDIO CLOCK ------------------------------------------------------------ */
1579static const unsigned int audio_clk_a_a_pins[] = {
1580 /* CLK A */
1581 RCAR_GP_PIN(6, 22),
1582};
1583static const unsigned int audio_clk_a_a_mux[] = {
1584 AUDIO_CLKA_A_MARK,
1585};
1586static const unsigned int audio_clk_a_b_pins[] = {
1587 /* CLK A */
1588 RCAR_GP_PIN(5, 4),
1589};
1590static const unsigned int audio_clk_a_b_mux[] = {
1591 AUDIO_CLKA_B_MARK,
1592};
1593static const unsigned int audio_clk_a_c_pins[] = {
1594 /* CLK A */
1595 RCAR_GP_PIN(5, 19),
1596};
1597static const unsigned int audio_clk_a_c_mux[] = {
1598 AUDIO_CLKA_C_MARK,
1599};
1600static const unsigned int audio_clk_b_a_pins[] = {
1601 /* CLK B */
1602 RCAR_GP_PIN(5, 12),
1603};
1604static const unsigned int audio_clk_b_a_mux[] = {
1605 AUDIO_CLKB_A_MARK,
1606};
1607static const unsigned int audio_clk_b_b_pins[] = {
1608 /* CLK B */
1609 RCAR_GP_PIN(6, 23),
1610};
1611static const unsigned int audio_clk_b_b_mux[] = {
1612 AUDIO_CLKB_B_MARK,
1613};
1614static const unsigned int audio_clk_c_a_pins[] = {
1615 /* CLK C */
1616 RCAR_GP_PIN(5, 21),
1617};
1618static const unsigned int audio_clk_c_a_mux[] = {
1619 AUDIO_CLKC_A_MARK,
1620};
1621static const unsigned int audio_clk_c_b_pins[] = {
1622 /* CLK C */
1623 RCAR_GP_PIN(5, 0),
1624};
1625static const unsigned int audio_clk_c_b_mux[] = {
1626 AUDIO_CLKC_B_MARK,
1627};
1628static const unsigned int audio_clkout_a_pins[] = {
1629 /* CLKOUT */
1630 RCAR_GP_PIN(5, 18),
1631};
1632static const unsigned int audio_clkout_a_mux[] = {
1633 AUDIO_CLKOUT_A_MARK,
1634};
1635static const unsigned int audio_clkout_b_pins[] = {
1636 /* CLKOUT */
1637 RCAR_GP_PIN(6, 28),
1638};
1639static const unsigned int audio_clkout_b_mux[] = {
1640 AUDIO_CLKOUT_B_MARK,
1641};
1642static const unsigned int audio_clkout_c_pins[] = {
1643 /* CLKOUT */
1644 RCAR_GP_PIN(5, 3),
1645};
1646static const unsigned int audio_clkout_c_mux[] = {
1647 AUDIO_CLKOUT_C_MARK,
1648};
1649static const unsigned int audio_clkout_d_pins[] = {
1650 /* CLKOUT */
1651 RCAR_GP_PIN(5, 21),
1652};
1653static const unsigned int audio_clkout_d_mux[] = {
1654 AUDIO_CLKOUT_D_MARK,
1655};
1656static const unsigned int audio_clkout1_a_pins[] = {
1657 /* CLKOUT1 */
1658 RCAR_GP_PIN(5, 15),
1659};
1660static const unsigned int audio_clkout1_a_mux[] = {
1661 AUDIO_CLKOUT1_A_MARK,
1662};
1663static const unsigned int audio_clkout1_b_pins[] = {
1664 /* CLKOUT1 */
1665 RCAR_GP_PIN(6, 29),
1666};
1667static const unsigned int audio_clkout1_b_mux[] = {
1668 AUDIO_CLKOUT1_B_MARK,
1669};
1670static const unsigned int audio_clkout2_a_pins[] = {
1671 /* CLKOUT2 */
1672 RCAR_GP_PIN(5, 16),
1673};
1674static const unsigned int audio_clkout2_a_mux[] = {
1675 AUDIO_CLKOUT2_A_MARK,
1676};
1677static const unsigned int audio_clkout2_b_pins[] = {
1678 /* CLKOUT2 */
1679 RCAR_GP_PIN(6, 30),
1680};
1681static const unsigned int audio_clkout2_b_mux[] = {
1682 AUDIO_CLKOUT2_B_MARK,
1683};
1684static const unsigned int audio_clkout3_a_pins[] = {
1685 /* CLKOUT3 */
1686 RCAR_GP_PIN(5, 19),
1687};
1688static const unsigned int audio_clkout3_a_mux[] = {
1689 AUDIO_CLKOUT3_A_MARK,
1690};
1691static const unsigned int audio_clkout3_b_pins[] = {
1692 /* CLKOUT3 */
1693 RCAR_GP_PIN(6, 31),
1694};
1695static const unsigned int audio_clkout3_b_mux[] = {
1696 AUDIO_CLKOUT3_B_MARK,
1697};
1698
30c078de
GU		 1699/* - EtherAVB --------------------------------------------------------------- */
1700static const unsigned int avb_link_pins[] = {
1701 /* AVB_LINK */
1702 RCAR_GP_PIN(2, 12),
1703};
1704static const unsigned int avb_link_mux[] = {
1705 AVB_LINK_MARK,
1706};
1707static const unsigned int avb_magic_pins[] = {
1708 /* AVB_MAGIC_ */
1709 RCAR_GP_PIN(2, 10),
1710};
1711static const unsigned int avb_magic_mux[] = {
1712 AVB_MAGIC_MARK,
1713};
1714static const unsigned int avb_phy_int_pins[] = {
1715 /* AVB_PHY_INT */
1716 RCAR_GP_PIN(2, 11),
1717};
1718static const unsigned int avb_phy_int_mux[] = {
1719 AVB_PHY_INT_MARK,
1720};
1721static const unsigned int avb_mdc_pins[] = {
1722 /* AVB_MDC, AVB_MDIO */
1723 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1724};
1725static const unsigned int avb_mdc_mux[] = {
1726 AVB_MDC_MARK, AVB_MDIO_MARK,
1727};
1728static const unsigned int avb_mii_pins[] = {
1729 /*
1730 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1731 * AVB_TD1, AVB_TD2, AVB_TD3,
1732 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1733 * AVB_RD1, AVB_RD2, AVB_RD3,
1734 * AVB_TXCREFCLK
1735 */
1736 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1737 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1738 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1739 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1740 PIN_NUMBER('A', 12),
1741
1742};
1743static const unsigned int avb_mii_mux[] = {
1744 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1745 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1746 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1747 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1748 AVB_TXCREFCLK_MARK,
1749};
1750static const unsigned int avb_avtp_pps_pins[] = {
1751 /* AVB_AVTP_PPS */
1752 RCAR_GP_PIN(2, 6),
1753};
1754static const unsigned int avb_avtp_pps_mux[] = {
1755 AVB_AVTP_PPS_MARK,
1756};
1757static const unsigned int avb_avtp_match_a_pins[] = {
1758 /* AVB_AVTP_MATCH_A */
1759 RCAR_GP_PIN(2, 13),
1760};
1761static const unsigned int avb_avtp_match_a_mux[] = {
1762 AVB_AVTP_MATCH_A_MARK,
1763};
1764static const unsigned int avb_avtp_capture_a_pins[] = {
1765 /* AVB_AVTP_CAPTURE_A */
1766 RCAR_GP_PIN(2, 14),
1767};
1768static const unsigned int avb_avtp_capture_a_mux[] = {
1769 AVB_AVTP_CAPTURE_A_MARK,
1770};
1771static const unsigned int avb_avtp_match_b_pins[] = {
1772 /* AVB_AVTP_MATCH_B */
1773 RCAR_GP_PIN(1, 8),
1774};
1775static const unsigned int avb_avtp_match_b_mux[] = {
1776 AVB_AVTP_MATCH_B_MARK,
1777};
1778static const unsigned int avb_avtp_capture_b_pins[] = {
1779 /* AVB_AVTP_CAPTURE_B */
1780 RCAR_GP_PIN(1, 11),
1781};
1782static const unsigned int avb_avtp_capture_b_mux[] = {
1783 AVB_AVTP_CAPTURE_B_MARK,
1784};
1785
a678abfe
RS		 1786/* - CAN ------------------------------------------------------------------ */
1787static const unsigned int can0_data_a_pins[] = {
1788 /* TX, RX */
1789 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1790};
1791static const unsigned int can0_data_a_mux[] = {
1792 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1793};
1794static const unsigned int can0_data_b_pins[] = {
1795 /* TX, RX */
1796 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1797};
1798static const unsigned int can0_data_b_mux[] = {
1799 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1800};
1801static const unsigned int can1_data_pins[] = {
1802 /* TX, RX */
1803 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1804};
1805static const unsigned int can1_data_mux[] = {
1806 CAN1_TX_MARK, CAN1_RX_MARK,
1807};
1808
1809/* - CAN Clock -------------------------------------------------------------- */
1810static const unsigned int can_clk_pins[] = {
1811 /* CLK */
1812 RCAR_GP_PIN(1, 25),
1813};
1814static const unsigned int can_clk_mux[] = {
1815 CAN_CLK_MARK,
1816};
1817
0e1c7a94
RS		 1818/* - CAN FD --------------------------------------------------------------- */
1819static const unsigned int canfd0_data_a_pins[] = {
1820 /* TX, RX */
1821 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1822};
1823static const unsigned int canfd0_data_a_mux[] = {
1824 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1825};
1826static const unsigned int canfd0_data_b_pins[] = {
1827 /* TX, RX */
1828 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1829};
1830static const unsigned int canfd0_data_b_mux[] = {
1831 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1832};
1833static const unsigned int canfd1_data_pins[] = {
1834 /* TX, RX */
1835 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1836};
1837static const unsigned int canfd1_data_mux[] = {
1838 CANFD1_TX_MARK, CANFD1_RX_MARK,
1839};
1840
641b0ab8
DB		 1841/* - DRIF0 --------------------------------------------------------------- */
1842static const unsigned int drif0_ctrl_a_pins[] = {
1843 /* CLK, SYNC */
1844 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1845};
1846static const unsigned int drif0_ctrl_a_mux[] = {
1847 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1848};
1849static const unsigned int drif0_data0_a_pins[] = {
1850 /* D0 */
1851 RCAR_GP_PIN(6, 10),
1852};
1853static const unsigned int drif0_data0_a_mux[] = {
1854 RIF0_D0_A_MARK,
1855};
1856static const unsigned int drif0_data1_a_pins[] = {
1857 /* D1 */
1858 RCAR_GP_PIN(6, 7),
1859};
1860static const unsigned int drif0_data1_a_mux[] = {
1861 RIF0_D1_A_MARK,
1862};
1863static const unsigned int drif0_ctrl_b_pins[] = {
1864 /* CLK, SYNC */
1865 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1866};
1867static const unsigned int drif0_ctrl_b_mux[] = {
1868 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1869};
1870static const unsigned int drif0_data0_b_pins[] = {
1871 /* D0 */
1872 RCAR_GP_PIN(5, 1),
1873};
1874static const unsigned int drif0_data0_b_mux[] = {
1875 RIF0_D0_B_MARK,
1876};
1877static const unsigned int drif0_data1_b_pins[] = {
1878 /* D1 */
1879 RCAR_GP_PIN(5, 2),
1880};
1881static const unsigned int drif0_data1_b_mux[] = {
1882 RIF0_D1_B_MARK,
1883};
1884static const unsigned int drif0_ctrl_c_pins[] = {
1885 /* CLK, SYNC */
1886 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1887};
1888static const unsigned int drif0_ctrl_c_mux[] = {
1889 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1890};
1891static const unsigned int drif0_data0_c_pins[] = {
1892 /* D0 */
1893 RCAR_GP_PIN(5, 13),
1894};
1895static const unsigned int drif0_data0_c_mux[] = {
1896 RIF0_D0_C_MARK,
1897};
1898static const unsigned int drif0_data1_c_pins[] = {
1899 /* D1 */
1900 RCAR_GP_PIN(5, 14),
1901};
1902static const unsigned int drif0_data1_c_mux[] = {
1903 RIF0_D1_C_MARK,
1904};
1905/* - DRIF1 --------------------------------------------------------------- */
1906static const unsigned int drif1_ctrl_a_pins[] = {
1907 /* CLK, SYNC */
1908 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1909};
1910static const unsigned int drif1_ctrl_a_mux[] = {
1911 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1912};
1913static const unsigned int drif1_data0_a_pins[] = {
1914 /* D0 */
1915 RCAR_GP_PIN(6, 19),
1916};
1917static const unsigned int drif1_data0_a_mux[] = {
1918 RIF1_D0_A_MARK,
1919};
1920static const unsigned int drif1_data1_a_pins[] = {
1921 /* D1 */
1922 RCAR_GP_PIN(6, 20),
1923};
1924static const unsigned int drif1_data1_a_mux[] = {
1925 RIF1_D1_A_MARK,
1926};
1927static const unsigned int drif1_ctrl_b_pins[] = {
1928 /* CLK, SYNC */
1929 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1930};
1931static const unsigned int drif1_ctrl_b_mux[] = {
1932 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1933};
1934static const unsigned int drif1_data0_b_pins[] = {
1935 /* D0 */
1936 RCAR_GP_PIN(5, 7),
1937};
1938static const unsigned int drif1_data0_b_mux[] = {
1939 RIF1_D0_B_MARK,
1940};
1941static const unsigned int drif1_data1_b_pins[] = {
1942 /* D1 */
1943 RCAR_GP_PIN(5, 8),
1944};
1945static const unsigned int drif1_data1_b_mux[] = {
1946 RIF1_D1_B_MARK,
1947};
1948static const unsigned int drif1_ctrl_c_pins[] = {
1949 /* CLK, SYNC */
1950 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1951};
1952static const unsigned int drif1_ctrl_c_mux[] = {
1953 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1954};
1955static const unsigned int drif1_data0_c_pins[] = {
1956 /* D0 */
1957 RCAR_GP_PIN(5, 6),
1958};
1959static const unsigned int drif1_data0_c_mux[] = {
1960 RIF1_D0_C_MARK,
1961};
1962static const unsigned int drif1_data1_c_pins[] = {
1963 /* D1 */
1964 RCAR_GP_PIN(5, 10),
1965};
1966static const unsigned int drif1_data1_c_mux[] = {
1967 RIF1_D1_C_MARK,
1968};
1969/* - DRIF2 --------------------------------------------------------------- */
1970static const unsigned int drif2_ctrl_a_pins[] = {
1971 /* CLK, SYNC */
1972 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1973};
1974static const unsigned int drif2_ctrl_a_mux[] = {
1975 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1976};
1977static const unsigned int drif2_data0_a_pins[] = {
1978 /* D0 */
1979 RCAR_GP_PIN(6, 7),
1980};
1981static const unsigned int drif2_data0_a_mux[] = {
1982 RIF2_D0_A_MARK,
1983};
1984static const unsigned int drif2_data1_a_pins[] = {
1985 /* D1 */
1986 RCAR_GP_PIN(6, 10),
1987};
1988static const unsigned int drif2_data1_a_mux[] = {
1989 RIF2_D1_A_MARK,
1990};
1991static const unsigned int drif2_ctrl_b_pins[] = {
1992 /* CLK, SYNC */
1993 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1994};
1995static const unsigned int drif2_ctrl_b_mux[] = {
1996 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1997};
1998static const unsigned int drif2_data0_b_pins[] = {
1999 /* D0 */
2000 RCAR_GP_PIN(6, 30),
2001};
2002static const unsigned int drif2_data0_b_mux[] = {
2003 RIF2_D0_B_MARK,
2004};
2005static const unsigned int drif2_data1_b_pins[] = {
2006 /* D1 */
2007 RCAR_GP_PIN(6, 31),
2008};
2009static const unsigned int drif2_data1_b_mux[] = {
2010 RIF2_D1_B_MARK,
2011};
2012/* - DRIF3 --------------------------------------------------------------- */
2013static const unsigned int drif3_ctrl_a_pins[] = {
2014 /* CLK, SYNC */
2015 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2016};
2017static const unsigned int drif3_ctrl_a_mux[] = {
2018 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2019};
2020static const unsigned int drif3_data0_a_pins[] = {
2021 /* D0 */
2022 RCAR_GP_PIN(6, 19),
2023};
2024static const unsigned int drif3_data0_a_mux[] = {
2025 RIF3_D0_A_MARK,
2026};
2027static const unsigned int drif3_data1_a_pins[] = {
2028 /* D1 */
2029 RCAR_GP_PIN(6, 20),
2030};
2031static const unsigned int drif3_data1_a_mux[] = {
2032 RIF3_D1_A_MARK,
2033};
2034static const unsigned int drif3_ctrl_b_pins[] = {
2035 /* CLK, SYNC */
2036 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2037};
2038static const unsigned int drif3_ctrl_b_mux[] = {
2039 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2040};
2041static const unsigned int drif3_data0_b_pins[] = {
2042 /* D0 */
2043 RCAR_GP_PIN(6, 28),
2044};
2045static const unsigned int drif3_data0_b_mux[] = {
2046 RIF3_D0_B_MARK,
2047};
2048static const unsigned int drif3_data1_b_pins[] = {
2049 /* D1 */
2050 RCAR_GP_PIN(6, 29),
2051};
2052static const unsigned int drif3_data1_b_mux[] = {
2053 RIF3_D1_B_MARK,
2054};
2055
a20a6585
LP		 2056/* - DU --------------------------------------------------------------------- */
2057static const unsigned int du_rgb666_pins[] = {
2058 /* R[7:2], G[7:2], B[7:2] */
2059 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2060 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2061 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2062 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2063 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2064 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2065};
2066static const unsigned int du_rgb666_mux[] = {
2067 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2068 DU_DR3_MARK, DU_DR2_MARK,
2069 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2070 DU_DG3_MARK, DU_DG2_MARK,
2071 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2072 DU_DB3_MARK, DU_DB2_MARK,
2073};
2074static const unsigned int du_rgb888_pins[] = {
2075 /* R[7:0], G[7:0], B[7:0] */
2076 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2077 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2078 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2079 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2080 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2081 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2082 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2083 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2084 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2085};
2086static const unsigned int du_rgb888_mux[] = {
2087 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2088 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2089 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2090 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2091 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2092 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2093};
2094static const unsigned int du_clk_out_0_pins[] = {
2095 /* CLKOUT */
2096 RCAR_GP_PIN(1, 27),
2097};
2098static const unsigned int du_clk_out_0_mux[] = {
2099 DU_DOTCLKOUT0_MARK
2100};
2101static const unsigned int du_clk_out_1_pins[] = {
2102 /* CLKOUT */
2103 RCAR_GP_PIN(2, 3),
2104};
2105static const unsigned int du_clk_out_1_mux[] = {
2106 DU_DOTCLKOUT1_MARK
2107};
2108static const unsigned int du_sync_pins[] = {
2109 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2110 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2111};
2112static const unsigned int du_sync_mux[] = {
2113 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2114};
2115static const unsigned int du_oddf_pins[] = {
2116 /* EXDISP/EXODDF/EXCDE */
2117 RCAR_GP_PIN(2, 2),
2118};
2119static const unsigned int du_oddf_mux[] = {
2120 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2121};
2122static const unsigned int du_cde_pins[] = {
2123 /* CDE */
2124 RCAR_GP_PIN(2, 0),
2125};
2126static const unsigned int du_cde_mux[] = {
2127 DU_CDE_MARK,
2128};
2129static const unsigned int du_disp_pins[] = {
2130 /* DISP */
2131 RCAR_GP_PIN(2, 1),
2132};
2133static const unsigned int du_disp_mux[] = {
2134 DU_DISP_MARK,
2135};
2136
7a362e34
WS		 2137/* - HSCIF0 ----------------------------------------------------------------- */
2138static const unsigned int hscif0_data_pins[] = {
2139 /* RX, TX */
2140 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2141};
2142static const unsigned int hscif0_data_mux[] = {
2143 HRX0_MARK, HTX0_MARK,
2144};
2145static const unsigned int hscif0_clk_pins[] = {
2146 /* SCK */
2147 RCAR_GP_PIN(5, 12),
2148};
2149static const unsigned int hscif0_clk_mux[] = {
2150 HSCK0_MARK,
2151};
2152static const unsigned int hscif0_ctrl_pins[] = {
2153 /* RTS, CTS */
2154 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2155};
2156static const unsigned int hscif0_ctrl_mux[] = {
2157 HRTS0_N_MARK, HCTS0_N_MARK,
2158};
2159/* - HSCIF1 ----------------------------------------------------------------- */
2160static const unsigned int hscif1_data_a_pins[] = {
2161 /* RX, TX */
2162 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2163};
2164static const unsigned int hscif1_data_a_mux[] = {
2165 HRX1_A_MARK, HTX1_A_MARK,
2166};
2167static const unsigned int hscif1_clk_a_pins[] = {
2168 /* SCK */
2169 RCAR_GP_PIN(6, 21),
2170};
2171static const unsigned int hscif1_clk_a_mux[] = {
2172 HSCK1_A_MARK,
2173};
2174static const unsigned int hscif1_ctrl_a_pins[] = {
2175 /* RTS, CTS */
2176 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2177};
2178static const unsigned int hscif1_ctrl_a_mux[] = {
2179 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2180};
2181
2182static const unsigned int hscif1_data_b_pins[] = {
2183 /* RX, TX */
2184 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2185};
2186static const unsigned int hscif1_data_b_mux[] = {
2187 HRX1_B_MARK, HTX1_B_MARK,
2188};
2189static const unsigned int hscif1_clk_b_pins[] = {
2190 /* SCK */
2191 RCAR_GP_PIN(5, 0),
2192};
2193static const unsigned int hscif1_clk_b_mux[] = {
2194 HSCK1_B_MARK,
2195};
2196static const unsigned int hscif1_ctrl_b_pins[] = {
2197 /* RTS, CTS */
2198 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2199};
2200static const unsigned int hscif1_ctrl_b_mux[] = {
2201 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2202};
2203/* - HSCIF2 ----------------------------------------------------------------- */
2204static const unsigned int hscif2_data_a_pins[] = {
2205 /* RX, TX */
2206 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2207};
2208static const unsigned int hscif2_data_a_mux[] = {
2209 HRX2_A_MARK, HTX2_A_MARK,
2210};
2211static const unsigned int hscif2_clk_a_pins[] = {
2212 /* SCK */
2213 RCAR_GP_PIN(6, 10),
2214};
2215static const unsigned int hscif2_clk_a_mux[] = {
2216 HSCK2_A_MARK,
2217};
2218static const unsigned int hscif2_ctrl_a_pins[] = {
2219 /* RTS, CTS */
2220 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2221};
2222static const unsigned int hscif2_ctrl_a_mux[] = {
2223 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2224};
2225
2226static const unsigned int hscif2_data_b_pins[] = {
2227 /* RX, TX */
2228 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2229};
2230static const unsigned int hscif2_data_b_mux[] = {
2231 HRX2_B_MARK, HTX2_B_MARK,
2232};
2233static const unsigned int hscif2_clk_b_pins[] = {
2234 /* SCK */
2235 RCAR_GP_PIN(6, 21),
2236};
2237static const unsigned int hscif2_clk_b_mux[] = {
2238 HSCK2_B_MARK,
2239};
2240static const unsigned int hscif2_ctrl_b_pins[] = {
2241 /* RTS, CTS */
2242 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2243};
2244static const unsigned int hscif2_ctrl_b_mux[] = {
2245 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2246};
2247
2248static const unsigned int hscif2_data_c_pins[] = {
2249 /* RX, TX */
2250 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2251};
2252static const unsigned int hscif2_data_c_mux[] = {
2253 HRX2_C_MARK, HTX2_C_MARK,
2254};
2255static const unsigned int hscif2_clk_c_pins[] = {
2256 /* SCK */
2257 RCAR_GP_PIN(6, 24),
2258};
2259static const unsigned int hscif2_clk_c_mux[] = {
2260 HSCK2_C_MARK,
2261};
2262static const unsigned int hscif2_ctrl_c_pins[] = {
2263 /* RTS, CTS */
2264 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2265};
2266static const unsigned int hscif2_ctrl_c_mux[] = {
2267 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2268};
2269/* - HSCIF3 ----------------------------------------------------------------- */
2270static const unsigned int hscif3_data_a_pins[] = {
2271 /* RX, TX */
2272 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2273};
2274static const unsigned int hscif3_data_a_mux[] = {
2275 HRX3_A_MARK, HTX3_A_MARK,
2276};
2277static const unsigned int hscif3_clk_pins[] = {
2278 /* SCK */
2279 RCAR_GP_PIN(1, 22),
2280};
2281static const unsigned int hscif3_clk_mux[] = {
2282 HSCK3_MARK,
2283};
2284static const unsigned int hscif3_ctrl_pins[] = {
2285 /* RTS, CTS */
2286 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2287};
2288static const unsigned int hscif3_ctrl_mux[] = {
2289 HRTS3_N_MARK, HCTS3_N_MARK,
2290};
2291
2292static const unsigned int hscif3_data_b_pins[] = {
2293 /* RX, TX */
2294 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2295};
2296static const unsigned int hscif3_data_b_mux[] = {
2297 HRX3_B_MARK, HTX3_B_MARK,
2298};
2299static const unsigned int hscif3_data_c_pins[] = {
2300 /* RX, TX */
2301 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2302};
2303static const unsigned int hscif3_data_c_mux[] = {
2304 HRX3_C_MARK, HTX3_C_MARK,
2305};
2306static const unsigned int hscif3_data_d_pins[] = {
2307 /* RX, TX */
2308 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2309};
2310static const unsigned int hscif3_data_d_mux[] = {
2311 HRX3_D_MARK, HTX3_D_MARK,
2312};
2313/* - HSCIF4 ----------------------------------------------------------------- */
2314static const unsigned int hscif4_data_a_pins[] = {
2315 /* RX, TX */
2316 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2317};
2318static const unsigned int hscif4_data_a_mux[] = {
2319 HRX4_A_MARK, HTX4_A_MARK,
2320};
2321static const unsigned int hscif4_clk_pins[] = {
2322 /* SCK */
2323 RCAR_GP_PIN(1, 11),
2324};
2325static const unsigned int hscif4_clk_mux[] = {
2326 HSCK4_MARK,
2327};
2328static const unsigned int hscif4_ctrl_pins[] = {
2329 /* RTS, CTS */
2330 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2331};
2332static const unsigned int hscif4_ctrl_mux[] = {
2333 HRTS4_N_MARK, HCTS4_N_MARK,
2334};
2335
2336static const unsigned int hscif4_data_b_pins[] = {
2337 /* RX, TX */
2338 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2339};
2340static const unsigned int hscif4_data_b_mux[] = {
2341 HRX4_B_MARK, HTX4_B_MARK,
2342};
2343
f62d4c9e
WS		 2344/* - I2C -------------------------------------------------------------------- */
2345static const unsigned int i2c1_a_pins[] = {
2346 /* SDA, SCL */
2347 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2348};
2349static const unsigned int i2c1_a_mux[] = {
2350 SDA1_A_MARK, SCL1_A_MARK,
2351};
2352static const unsigned int i2c1_b_pins[] = {
2353 /* SDA, SCL */
2354 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2355};
2356static const unsigned int i2c1_b_mux[] = {
2357 SDA1_B_MARK, SCL1_B_MARK,
2358};
2359static const unsigned int i2c2_a_pins[] = {
2360 /* SDA, SCL */
2361 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2362};
2363static const unsigned int i2c2_a_mux[] = {
2364 SDA2_A_MARK, SCL2_A_MARK,
2365};
2366static const unsigned int i2c2_b_pins[] = {
2367 /* SDA, SCL */
2368 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2369};
2370static const unsigned int i2c2_b_mux[] = {
2371 SDA2_B_MARK, SCL2_B_MARK,
2372};
2373static const unsigned int i2c6_a_pins[] = {
2374 /* SDA, SCL */
2375 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2376};
2377static const unsigned int i2c6_a_mux[] = {
2378 SDA6_A_MARK, SCL6_A_MARK,
2379};
2380static const unsigned int i2c6_b_pins[] = {
2381 /* SDA, SCL */
2382 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2383};
2384static const unsigned int i2c6_b_mux[] = {
2385 SDA6_B_MARK, SCL6_B_MARK,
2386};
2387static const unsigned int i2c6_c_pins[] = {
2388 /* SDA, SCL */
2389 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2390};
2391static const unsigned int i2c6_c_mux[] = {
2392 SDA6_C_MARK, SCL6_C_MARK,
2393};
2394
8480e6ca
GU		 2395/* - INTC-EX ---------------------------------------------------------------- */
2396static const unsigned int intc_ex_irq0_pins[] = {
2397 /* IRQ0 */
2398 RCAR_GP_PIN(2, 0),
2399};
2400static const unsigned int intc_ex_irq0_mux[] = {
2401 IRQ0_MARK,
2402};
2403static const unsigned int intc_ex_irq1_pins[] = {
2404 /* IRQ1 */
2405 RCAR_GP_PIN(2, 1),
2406};
2407static const unsigned int intc_ex_irq1_mux[] = {
2408 IRQ1_MARK,
2409};
2410static const unsigned int intc_ex_irq2_pins[] = {
2411 /* IRQ2 */
2412 RCAR_GP_PIN(2, 2),
2413};
2414static const unsigned int intc_ex_irq2_mux[] = {
2415 IRQ2_MARK,
2416};
2417static const unsigned int intc_ex_irq3_pins[] = {
2418 /* IRQ3 */
2419 RCAR_GP_PIN(2, 3),
2420};
2421static const unsigned int intc_ex_irq3_mux[] = {
2422 IRQ3_MARK,
2423};
2424static const unsigned int intc_ex_irq4_pins[] = {
2425 /* IRQ4 */
2426 RCAR_GP_PIN(2, 4),
2427};
2428static const unsigned int intc_ex_irq4_mux[] = {
2429 IRQ4_MARK,
2430};
2431static const unsigned int intc_ex_irq5_pins[] = {
2432 /* IRQ5 */
2433 RCAR_GP_PIN(2, 5),
2434};
2435static const unsigned int intc_ex_irq5_mux[] = {
2436 IRQ5_MARK,
2437};
2438
3e6c7727
GU		 2439/* - MSIOF0 ----------------------------------------------------------------- */
2440static const unsigned int msiof0_clk_pins[] = {
2441 /* SCK */
2442 RCAR_GP_PIN(5, 17),
2443};
2444static const unsigned int msiof0_clk_mux[] = {
2445 MSIOF0_SCK_MARK,
2446};
2447static const unsigned int msiof0_sync_pins[] = {
2448 /* SYNC */
2449 RCAR_GP_PIN(5, 18),
2450};
2451static const unsigned int msiof0_sync_mux[] = {
2452 MSIOF0_SYNC_MARK,
2453};
2454static const unsigned int msiof0_ss1_pins[] = {
2455 /* SS1 */
2456 RCAR_GP_PIN(5, 19),
2457};
2458static const unsigned int msiof0_ss1_mux[] = {
2459 MSIOF0_SS1_MARK,
2460};
2461static const unsigned int msiof0_ss2_pins[] = {
2462 /* SS2 */
2463 RCAR_GP_PIN(5, 21),
2464};
2465static const unsigned int msiof0_ss2_mux[] = {
2466 MSIOF0_SS2_MARK,
2467};
2468static const unsigned int msiof0_txd_pins[] = {
2469 /* TXD */
2470 RCAR_GP_PIN(5, 20),
2471};
2472static const unsigned int msiof0_txd_mux[] = {
2473 MSIOF0_TXD_MARK,
2474};
2475static const unsigned int msiof0_rxd_pins[] = {
2476 /* RXD */
2477 RCAR_GP_PIN(5, 22),
2478};
2479static const unsigned int msiof0_rxd_mux[] = {
2480 MSIOF0_RXD_MARK,
2481};
2482/* - MSIOF1 ----------------------------------------------------------------- */
2483static const unsigned int msiof1_clk_a_pins[] = {
2484 /* SCK */
2485 RCAR_GP_PIN(6, 8),
2486};
2487static const unsigned int msiof1_clk_a_mux[] = {
2488 MSIOF1_SCK_A_MARK,
2489};
2490static const unsigned int msiof1_sync_a_pins[] = {
2491 /* SYNC */
2492 RCAR_GP_PIN(6, 9),
2493};
2494static const unsigned int msiof1_sync_a_mux[] = {
2495 MSIOF1_SYNC_A_MARK,
2496};
2497static const unsigned int msiof1_ss1_a_pins[] = {
2498 /* SS1 */
2499 RCAR_GP_PIN(6, 5),
2500};
2501static const unsigned int msiof1_ss1_a_mux[] = {
2502 MSIOF1_SS1_A_MARK,
2503};
2504static const unsigned int msiof1_ss2_a_pins[] = {
2505 /* SS2 */
2506 RCAR_GP_PIN(6, 6),
2507};
2508static const unsigned int msiof1_ss2_a_mux[] = {
2509 MSIOF1_SS2_A_MARK,
2510};
2511static const unsigned int msiof1_txd_a_pins[] = {
2512 /* TXD */
2513 RCAR_GP_PIN(6, 7),
2514};
2515static const unsigned int msiof1_txd_a_mux[] = {
2516 MSIOF1_TXD_A_MARK,
2517};
2518static const unsigned int msiof1_rxd_a_pins[] = {
2519 /* RXD */
2520 RCAR_GP_PIN(6, 10),
2521};
2522static const unsigned int msiof1_rxd_a_mux[] = {
2523 MSIOF1_RXD_A_MARK,
2524};
2525static const unsigned int msiof1_clk_b_pins[] = {
2526 /* SCK */
2527 RCAR_GP_PIN(5, 9),
2528};
2529static const unsigned int msiof1_clk_b_mux[] = {
2530 MSIOF1_SCK_B_MARK,
2531};
2532static const unsigned int msiof1_sync_b_pins[] = {
2533 /* SYNC */
2534 RCAR_GP_PIN(5, 3),
2535};
2536static const unsigned int msiof1_sync_b_mux[] = {
2537 MSIOF1_SYNC_B_MARK,
2538};
2539static const unsigned int msiof1_ss1_b_pins[] = {
2540 /* SS1 */
2541 RCAR_GP_PIN(5, 4),
2542};
2543static const unsigned int msiof1_ss1_b_mux[] = {
2544 MSIOF1_SS1_B_MARK,
2545};
2546static const unsigned int msiof1_ss2_b_pins[] = {
2547 /* SS2 */
2548 RCAR_GP_PIN(5, 0),
2549};
2550static const unsigned int msiof1_ss2_b_mux[] = {
2551 MSIOF1_SS2_B_MARK,
2552};
2553static const unsigned int msiof1_txd_b_pins[] = {
2554 /* TXD */
2555 RCAR_GP_PIN(5, 8),
2556};
2557static const unsigned int msiof1_txd_b_mux[] = {
2558 MSIOF1_TXD_B_MARK,
2559};
2560static const unsigned int msiof1_rxd_b_pins[] = {
2561 /* RXD */
2562 RCAR_GP_PIN(5, 7),
2563};
2564static const unsigned int msiof1_rxd_b_mux[] = {
2565 MSIOF1_RXD_B_MARK,
2566};
2567static const unsigned int msiof1_clk_c_pins[] = {
2568 /* SCK */
2569 RCAR_GP_PIN(6, 17),
2570};
2571static const unsigned int msiof1_clk_c_mux[] = {
2572 MSIOF1_SCK_C_MARK,
2573};
2574static const unsigned int msiof1_sync_c_pins[] = {
2575 /* SYNC */
2576 RCAR_GP_PIN(6, 18),
2577};
2578static const unsigned int msiof1_sync_c_mux[] = {
2579 MSIOF1_SYNC_C_MARK,
2580};
2581static const unsigned int msiof1_ss1_c_pins[] = {
2582 /* SS1 */
2583 RCAR_GP_PIN(6, 21),
2584};
2585static const unsigned int msiof1_ss1_c_mux[] = {
2586 MSIOF1_SS1_C_MARK,
2587};
2588static const unsigned int msiof1_ss2_c_pins[] = {
2589 /* SS2 */
2590 RCAR_GP_PIN(6, 27),
2591};
2592static const unsigned int msiof1_ss2_c_mux[] = {
2593 MSIOF1_SS2_C_MARK,
2594};
2595static const unsigned int msiof1_txd_c_pins[] = {
2596 /* TXD */
2597 RCAR_GP_PIN(6, 20),
2598};
2599static const unsigned int msiof1_txd_c_mux[] = {
2600 MSIOF1_TXD_C_MARK,
2601};
2602static const unsigned int msiof1_rxd_c_pins[] = {
2603 /* RXD */
2604 RCAR_GP_PIN(6, 19),
2605};
2606static const unsigned int msiof1_rxd_c_mux[] = {
2607 MSIOF1_RXD_C_MARK,
2608};
2609static const unsigned int msiof1_clk_d_pins[] = {
2610 /* SCK */
2611 RCAR_GP_PIN(5, 12),
2612};
2613static const unsigned int msiof1_clk_d_mux[] = {
2614 MSIOF1_SCK_D_MARK,
2615};
2616static const unsigned int msiof1_sync_d_pins[] = {
2617 /* SYNC */
2618 RCAR_GP_PIN(5, 15),
2619};
2620static const unsigned int msiof1_sync_d_mux[] = {
2621 MSIOF1_SYNC_D_MARK,
2622};
2623static const unsigned int msiof1_ss1_d_pins[] = {
2624 /* SS1 */
2625 RCAR_GP_PIN(5, 16),
2626};
2627static const unsigned int msiof1_ss1_d_mux[] = {
2628 MSIOF1_SS1_D_MARK,
2629};
2630static const unsigned int msiof1_ss2_d_pins[] = {
2631 /* SS2 */
2632 RCAR_GP_PIN(5, 21),
2633};
2634static const unsigned int msiof1_ss2_d_mux[] = {
2635 MSIOF1_SS2_D_MARK,
2636};
2637static const unsigned int msiof1_txd_d_pins[] = {
2638 /* TXD */
2639 RCAR_GP_PIN(5, 14),
2640};
2641static const unsigned int msiof1_txd_d_mux[] = {
2642 MSIOF1_TXD_D_MARK,
2643};
2644static const unsigned int msiof1_rxd_d_pins[] = {
2645 /* RXD */
2646 RCAR_GP_PIN(5, 13),
2647};
2648static const unsigned int msiof1_rxd_d_mux[] = {
2649 MSIOF1_RXD_D_MARK,
2650};
2651static const unsigned int msiof1_clk_e_pins[] = {
2652 /* SCK */
2653 RCAR_GP_PIN(3, 0),
2654};
2655static const unsigned int msiof1_clk_e_mux[] = {
2656 MSIOF1_SCK_E_MARK,
2657};
2658static const unsigned int msiof1_sync_e_pins[] = {
2659 /* SYNC */
2660 RCAR_GP_PIN(3, 1),
2661};
2662static const unsigned int msiof1_sync_e_mux[] = {
2663 MSIOF1_SYNC_E_MARK,
2664};
2665static const unsigned int msiof1_ss1_e_pins[] = {
2666 /* SS1 */
2667 RCAR_GP_PIN(3, 4),
2668};
2669static const unsigned int msiof1_ss1_e_mux[] = {
2670 MSIOF1_SS1_E_MARK,
2671};
2672static const unsigned int msiof1_ss2_e_pins[] = {
2673 /* SS2 */
2674 RCAR_GP_PIN(3, 5),
2675};
2676static const unsigned int msiof1_ss2_e_mux[] = {
2677 MSIOF1_SS2_E_MARK,
2678};
2679static const unsigned int msiof1_txd_e_pins[] = {
2680 /* TXD */
2681 RCAR_GP_PIN(3, 3),
2682};
2683static const unsigned int msiof1_txd_e_mux[] = {
2684 MSIOF1_TXD_E_MARK,
2685};
2686static const unsigned int msiof1_rxd_e_pins[] = {
2687 /* RXD */
2688 RCAR_GP_PIN(3, 2),
2689};
2690static const unsigned int msiof1_rxd_e_mux[] = {
2691 MSIOF1_RXD_E_MARK,
2692};
2693static const unsigned int msiof1_clk_f_pins[] = {
2694 /* SCK */
2695 RCAR_GP_PIN(5, 23),
2696};
2697static const unsigned int msiof1_clk_f_mux[] = {
2698 MSIOF1_SCK_F_MARK,
2699};
2700static const unsigned int msiof1_sync_f_pins[] = {
2701 /* SYNC */
2702 RCAR_GP_PIN(5, 24),
2703};
2704static const unsigned int msiof1_sync_f_mux[] = {
2705 MSIOF1_SYNC_F_MARK,
2706};
2707static const unsigned int msiof1_ss1_f_pins[] = {
2708 /* SS1 */
2709 RCAR_GP_PIN(6, 1),
2710};
2711static const unsigned int msiof1_ss1_f_mux[] = {
2712 MSIOF1_SS1_F_MARK,
2713};
2714static const unsigned int msiof1_ss2_f_pins[] = {
2715 /* SS2 */
2716 RCAR_GP_PIN(6, 2),
2717};
2718static const unsigned int msiof1_ss2_f_mux[] = {
2719 MSIOF1_SS2_F_MARK,
2720};
2721static const unsigned int msiof1_txd_f_pins[] = {
2722 /* TXD */
2723 RCAR_GP_PIN(6, 0),
2724};
2725static const unsigned int msiof1_txd_f_mux[] = {
2726 MSIOF1_TXD_F_MARK,
2727};
2728static const unsigned int msiof1_rxd_f_pins[] = {
2729 /* RXD */
2730 RCAR_GP_PIN(5, 25),
2731};
2732static const unsigned int msiof1_rxd_f_mux[] = {
2733 MSIOF1_RXD_F_MARK,
2734};
2735static const unsigned int msiof1_clk_g_pins[] = {
2736 /* SCK */
2737 RCAR_GP_PIN(3, 6),
2738};
2739static const unsigned int msiof1_clk_g_mux[] = {
2740 MSIOF1_SCK_G_MARK,
2741};
2742static const unsigned int msiof1_sync_g_pins[] = {
2743 /* SYNC */
2744 RCAR_GP_PIN(3, 7),
2745};
2746static const unsigned int msiof1_sync_g_mux[] = {
2747 MSIOF1_SYNC_G_MARK,
2748};
2749static const unsigned int msiof1_ss1_g_pins[] = {
2750 /* SS1 */
2751 RCAR_GP_PIN(3, 10),
2752};
2753static const unsigned int msiof1_ss1_g_mux[] = {
2754 MSIOF1_SS1_G_MARK,
2755};
2756static const unsigned int msiof1_ss2_g_pins[] = {
2757 /* SS2 */
2758 RCAR_GP_PIN(3, 11),
2759};
2760static const unsigned int msiof1_ss2_g_mux[] = {
2761 MSIOF1_SS2_G_MARK,
2762};
2763static const unsigned int msiof1_txd_g_pins[] = {
2764 /* TXD */
2765 RCAR_GP_PIN(3, 9),
2766};
2767static const unsigned int msiof1_txd_g_mux[] = {
2768 MSIOF1_TXD_G_MARK,
2769};
2770static const unsigned int msiof1_rxd_g_pins[] = {
2771 /* RXD */
2772 RCAR_GP_PIN(3, 8),
2773};
2774static const unsigned int msiof1_rxd_g_mux[] = {
2775 MSIOF1_RXD_G_MARK,
2776};
2777/* - MSIOF2 ----------------------------------------------------------------- */
2778static const unsigned int msiof2_clk_a_pins[] = {
2779 /* SCK */
2780 RCAR_GP_PIN(1, 9),
2781};
2782static const unsigned int msiof2_clk_a_mux[] = {
2783 MSIOF2_SCK_A_MARK,
2784};
2785static const unsigned int msiof2_sync_a_pins[] = {
2786 /* SYNC */
2787 RCAR_GP_PIN(1, 8),
2788};
2789static const unsigned int msiof2_sync_a_mux[] = {
2790 MSIOF2_SYNC_A_MARK,
2791};
2792static const unsigned int msiof2_ss1_a_pins[] = {
2793 /* SS1 */
2794 RCAR_GP_PIN(1, 6),
2795};
2796static const unsigned int msiof2_ss1_a_mux[] = {
2797 MSIOF2_SS1_A_MARK,
2798};
2799static const unsigned int msiof2_ss2_a_pins[] = {
2800 /* SS2 */
2801 RCAR_GP_PIN(1, 7),
2802};
2803static const unsigned int msiof2_ss2_a_mux[] = {
2804 MSIOF2_SS2_A_MARK,
2805};
2806static const unsigned int msiof2_txd_a_pins[] = {
2807 /* TXD */
2808 RCAR_GP_PIN(1, 11),
2809};
2810static const unsigned int msiof2_txd_a_mux[] = {
2811 MSIOF2_TXD_A_MARK,
2812};
2813static const unsigned int msiof2_rxd_a_pins[] = {
2814 /* RXD */
2815 RCAR_GP_PIN(1, 10),
2816};
2817static const unsigned int msiof2_rxd_a_mux[] = {
2818 MSIOF2_RXD_A_MARK,
2819};
2820static const unsigned int msiof2_clk_b_pins[] = {
2821 /* SCK */
2822 RCAR_GP_PIN(0, 4),
2823};
2824static const unsigned int msiof2_clk_b_mux[] = {
2825 MSIOF2_SCK_B_MARK,
2826};
2827static const unsigned int msiof2_sync_b_pins[] = {
2828 /* SYNC */
2829 RCAR_GP_PIN(0, 5),
2830};
2831static const unsigned int msiof2_sync_b_mux[] = {
2832 MSIOF2_SYNC_B_MARK,
2833};
2834static const unsigned int msiof2_ss1_b_pins[] = {
2835 /* SS1 */
2836 RCAR_GP_PIN(0, 0),
2837};
2838static const unsigned int msiof2_ss1_b_mux[] = {
2839 MSIOF2_SS1_B_MARK,
2840};
2841static const unsigned int msiof2_ss2_b_pins[] = {
2842 /* SS2 */
2843 RCAR_GP_PIN(0, 1),
2844};
2845static const unsigned int msiof2_ss2_b_mux[] = {
2846 MSIOF2_SS2_B_MARK,
2847};
2848static const unsigned int msiof2_txd_b_pins[] = {
2849 /* TXD */
2850 RCAR_GP_PIN(0, 7),
2851};
2852static const unsigned int msiof2_txd_b_mux[] = {
2853 MSIOF2_TXD_B_MARK,
2854};
2855static const unsigned int msiof2_rxd_b_pins[] = {
2856 /* RXD */
2857 RCAR_GP_PIN(0, 6),
2858};
2859static const unsigned int msiof2_rxd_b_mux[] = {
2860 MSIOF2_RXD_B_MARK,
2861};
2862static const unsigned int msiof2_clk_c_pins[] = {
2863 /* SCK */
2864 RCAR_GP_PIN(2, 12),
2865};
2866static const unsigned int msiof2_clk_c_mux[] = {
2867 MSIOF2_SCK_C_MARK,
2868};
2869static const unsigned int msiof2_sync_c_pins[] = {
2870 /* SYNC */
2871 RCAR_GP_PIN(2, 11),
2872};
2873static const unsigned int msiof2_sync_c_mux[] = {
2874 MSIOF2_SYNC_C_MARK,
2875};
2876static const unsigned int msiof2_ss1_c_pins[] = {
2877 /* SS1 */
2878 RCAR_GP_PIN(2, 10),
2879};
2880static const unsigned int msiof2_ss1_c_mux[] = {
2881 MSIOF2_SS1_C_MARK,
2882};
2883static const unsigned int msiof2_ss2_c_pins[] = {
2884 /* SS2 */
2885 RCAR_GP_PIN(2, 9),
2886};
2887static const unsigned int msiof2_ss2_c_mux[] = {
2888 MSIOF2_SS2_C_MARK,
2889};
2890static const unsigned int msiof2_txd_c_pins[] = {
2891 /* TXD */
2892 RCAR_GP_PIN(2, 14),
2893};
2894static const unsigned int msiof2_txd_c_mux[] = {
2895 MSIOF2_TXD_C_MARK,
2896};
2897static const unsigned int msiof2_rxd_c_pins[] = {
2898 /* RXD */
2899 RCAR_GP_PIN(2, 13),
2900};
2901static const unsigned int msiof2_rxd_c_mux[] = {
2902 MSIOF2_RXD_C_MARK,
2903};
2904static const unsigned int msiof2_clk_d_pins[] = {
2905 /* SCK */
2906 RCAR_GP_PIN(0, 8),
2907};
2908static const unsigned int msiof2_clk_d_mux[] = {
2909 MSIOF2_SCK_D_MARK,
2910};
2911static const unsigned int msiof2_sync_d_pins[] = {
2912 /* SYNC */
2913 RCAR_GP_PIN(0, 9),
2914};
2915static const unsigned int msiof2_sync_d_mux[] = {
2916 MSIOF2_SYNC_D_MARK,
2917};
2918static const unsigned int msiof2_ss1_d_pins[] = {
2919 /* SS1 */
2920 RCAR_GP_PIN(0, 12),
2921};
2922static const unsigned int msiof2_ss1_d_mux[] = {
2923 MSIOF2_SS1_D_MARK,
2924};
2925static const unsigned int msiof2_ss2_d_pins[] = {
2926 /* SS2 */
2927 RCAR_GP_PIN(0, 13),
2928};
2929static const unsigned int msiof2_ss2_d_mux[] = {
2930 MSIOF2_SS2_D_MARK,
2931};
2932static const unsigned int msiof2_txd_d_pins[] = {
2933 /* TXD */
2934 RCAR_GP_PIN(0, 11),
2935};
2936static const unsigned int msiof2_txd_d_mux[] = {
2937 MSIOF2_TXD_D_MARK,
2938};
2939static const unsigned int msiof2_rxd_d_pins[] = {
2940 /* RXD */
2941 RCAR_GP_PIN(0, 10),
2942};
2943static const unsigned int msiof2_rxd_d_mux[] = {
2944 MSIOF2_RXD_D_MARK,
2945};
2946/* - MSIOF3 ----------------------------------------------------------------- */
2947static const unsigned int msiof3_clk_a_pins[] = {
2948 /* SCK */
2949 RCAR_GP_PIN(0, 0),
2950};
2951static const unsigned int msiof3_clk_a_mux[] = {
2952 MSIOF3_SCK_A_MARK,
2953};
2954static const unsigned int msiof3_sync_a_pins[] = {
2955 /* SYNC */
2956 RCAR_GP_PIN(0, 1),
2957};
2958static const unsigned int msiof3_sync_a_mux[] = {
2959 MSIOF3_SYNC_A_MARK,
2960};
2961static const unsigned int msiof3_ss1_a_pins[] = {
2962 /* SS1 */
2963 RCAR_GP_PIN(0, 14),
2964};
2965static const unsigned int msiof3_ss1_a_mux[] = {
2966 MSIOF3_SS1_A_MARK,
2967};
2968static const unsigned int msiof3_ss2_a_pins[] = {
2969 /* SS2 */
2970 RCAR_GP_PIN(0, 15),
2971};
2972static const unsigned int msiof3_ss2_a_mux[] = {
2973 MSIOF3_SS2_A_MARK,
2974};
2975static const unsigned int msiof3_txd_a_pins[] = {
2976 /* TXD */
2977 RCAR_GP_PIN(0, 3),
2978};
2979static const unsigned int msiof3_txd_a_mux[] = {
2980 MSIOF3_TXD_A_MARK,
2981};
2982static const unsigned int msiof3_rxd_a_pins[] = {
2983 /* RXD */
2984 RCAR_GP_PIN(0, 2),
2985};
2986static const unsigned int msiof3_rxd_a_mux[] = {
2987 MSIOF3_RXD_A_MARK,
2988};
2989static const unsigned int msiof3_clk_b_pins[] = {
2990 /* SCK */
2991 RCAR_GP_PIN(1, 2),
2992};
2993static const unsigned int msiof3_clk_b_mux[] = {
2994 MSIOF3_SCK_B_MARK,
2995};
2996static const unsigned int msiof3_sync_b_pins[] = {
2997 /* SYNC */
2998 RCAR_GP_PIN(1, 0),
2999};
3000static const unsigned int msiof3_sync_b_mux[] = {
3001 MSIOF3_SYNC_B_MARK,
3002};
3003static const unsigned int msiof3_ss1_b_pins[] = {
3004 /* SS1 */
3005 RCAR_GP_PIN(1, 4),
3006};
3007static const unsigned int msiof3_ss1_b_mux[] = {
3008 MSIOF3_SS1_B_MARK,
3009};
3010static const unsigned int msiof3_ss2_b_pins[] = {
3011 /* SS2 */
3012 RCAR_GP_PIN(1, 5),
3013};
3014static const unsigned int msiof3_ss2_b_mux[] = {
3015 MSIOF3_SS2_B_MARK,
3016};
3017static const unsigned int msiof3_txd_b_pins[] = {
3018 /* TXD */
3019 RCAR_GP_PIN(1, 1),
3020};
3021static const unsigned int msiof3_txd_b_mux[] = {
3022 MSIOF3_TXD_B_MARK,
3023};
3024static const unsigned int msiof3_rxd_b_pins[] = {
3025 /* RXD */
3026 RCAR_GP_PIN(1, 3),
3027};
3028static const unsigned int msiof3_rxd_b_mux[] = {
3029 MSIOF3_RXD_B_MARK,
3030};
3031static const unsigned int msiof3_clk_c_pins[] = {
3032 /* SCK */
3033 RCAR_GP_PIN(1, 12),
3034};
3035static const unsigned int msiof3_clk_c_mux[] = {
3036 MSIOF3_SCK_C_MARK,
3037};
3038static const unsigned int msiof3_sync_c_pins[] = {
3039 /* SYNC */
3040 RCAR_GP_PIN(1, 13),
3041};
3042static const unsigned int msiof3_sync_c_mux[] = {
3043 MSIOF3_SYNC_C_MARK,
3044};
3045static const unsigned int msiof3_txd_c_pins[] = {
3046 /* TXD */
3047 RCAR_GP_PIN(1, 15),
3048};
3049static const unsigned int msiof3_txd_c_mux[] = {
3050 MSIOF3_TXD_C_MARK,
3051};
3052static const unsigned int msiof3_rxd_c_pins[] = {
3053 /* RXD */
3054 RCAR_GP_PIN(1, 14),
3055};
3056static const unsigned int msiof3_rxd_c_mux[] = {
3057 MSIOF3_RXD_C_MARK,
3058};
3059static const unsigned int msiof3_clk_d_pins[] = {
3060 /* SCK */
3061 RCAR_GP_PIN(1, 22),
3062};
3063static const unsigned int msiof3_clk_d_mux[] = {
3064 MSIOF3_SCK_D_MARK,
3065};
3066static const unsigned int msiof3_sync_d_pins[] = {
3067 /* SYNC */
3068 RCAR_GP_PIN(1, 23),
3069};
3070static const unsigned int msiof3_sync_d_mux[] = {
3071 MSIOF3_SYNC_D_MARK,
3072};
3073static const unsigned int msiof3_ss1_d_pins[] = {
3074 /* SS1 */
3075 RCAR_GP_PIN(1, 26),
3076};
3077static const unsigned int msiof3_ss1_d_mux[] = {
3078 MSIOF3_SS1_D_MARK,
3079};
3080static const unsigned int msiof3_txd_d_pins[] = {
3081 /* TXD */
3082 RCAR_GP_PIN(1, 25),
3083};
3084static const unsigned int msiof3_txd_d_mux[] = {
3085 MSIOF3_TXD_D_MARK,
3086};
3087static const unsigned int msiof3_rxd_d_pins[] = {
3088 /* RXD */
3089 RCAR_GP_PIN(1, 24),
3090};
3091static const unsigned int msiof3_rxd_d_mux[] = {
3092 MSIOF3_RXD_D_MARK,
3093};
3094static const unsigned int msiof3_clk_e_pins[] = {
3095 /* SCK */
3096 RCAR_GP_PIN(2, 3),
3097};
3098static const unsigned int msiof3_clk_e_mux[] = {
3099 MSIOF3_SCK_E_MARK,
3100};
3101static const unsigned int msiof3_sync_e_pins[] = {
3102 /* SYNC */
3103 RCAR_GP_PIN(2, 2),
3104};
3105static const unsigned int msiof3_sync_e_mux[] = {
3106 MSIOF3_SYNC_E_MARK,
3107};
3108static const unsigned int msiof3_ss1_e_pins[] = {
3109 /* SS1 */
3110 RCAR_GP_PIN(2, 1),
3111};
3112static const unsigned int msiof3_ss1_e_mux[] = {
3113 MSIOF3_SS1_E_MARK,
3114};
3115static const unsigned int msiof3_ss2_e_pins[] = {
3116 /* SS1 */
3117 RCAR_GP_PIN(2, 0),
3118};
3119static const unsigned int msiof3_ss2_e_mux[] = {
3120 MSIOF3_SS2_E_MARK,
3121};
3122static const unsigned int msiof3_txd_e_pins[] = {
3123 /* TXD */
3124 RCAR_GP_PIN(2, 5),
3125};
3126static const unsigned int msiof3_txd_e_mux[] = {
3127 MSIOF3_TXD_E_MARK,
3128};
3129static const unsigned int msiof3_rxd_e_pins[] = {
3130 /* RXD */
3131 RCAR_GP_PIN(2, 4),
3132};
3133static const unsigned int msiof3_rxd_e_mux[] = {
3134 MSIOF3_RXD_E_MARK,
3135};
3136
c03a133b
LP		 3137/* - PWM0 --------------------------------------------------------------------*/
3138static const unsigned int pwm0_pins[] = {
3139 /* PWM */
3140 RCAR_GP_PIN(2, 6),
3141};
3142static const unsigned int pwm0_mux[] = {
3143 PWM0_MARK,
3144};
3145/* - PWM1 --------------------------------------------------------------------*/
3146static const unsigned int pwm1_a_pins[] = {
3147 /* PWM */
3148 RCAR_GP_PIN(2, 7),
3149};
3150static const unsigned int pwm1_a_mux[] = {
3151 PWM1_A_MARK,
3152};
3153static const unsigned int pwm1_b_pins[] = {
3154 /* PWM */
3155 RCAR_GP_PIN(1, 8),
3156};
3157static const unsigned int pwm1_b_mux[] = {
3158 PWM1_B_MARK,
3159};
3160/* - PWM2 --------------------------------------------------------------------*/
3161static const unsigned int pwm2_a_pins[] = {
3162 /* PWM */
3163 RCAR_GP_PIN(2, 8),
3164};
3165static const unsigned int pwm2_a_mux[] = {
3166 PWM2_A_MARK,
3167};
3168static const unsigned int pwm2_b_pins[] = {
3169 /* PWM */
3170 RCAR_GP_PIN(1, 11),
3171};
3172static const unsigned int pwm2_b_mux[] = {
3173 PWM2_B_MARK,
3174};
3175/* - PWM3 --------------------------------------------------------------------*/
3176static const unsigned int pwm3_a_pins[] = {
3177 /* PWM */
3178 RCAR_GP_PIN(1, 0),
3179};
3180static const unsigned int pwm3_a_mux[] = {
3181 PWM3_A_MARK,
3182};
3183static const unsigned int pwm3_b_pins[] = {
3184 /* PWM */
3185 RCAR_GP_PIN(2, 2),
3186};
3187static const unsigned int pwm3_b_mux[] = {
3188 PWM3_B_MARK,
3189};
3190/* - PWM4 --------------------------------------------------------------------*/
3191static const unsigned int pwm4_a_pins[] = {
3192 /* PWM */
3193 RCAR_GP_PIN(1, 1),
3194};
3195static const unsigned int pwm4_a_mux[] = {
3196 PWM4_A_MARK,
3197};
3198static const unsigned int pwm4_b_pins[] = {
3199 /* PWM */
3200 RCAR_GP_PIN(2, 3),
3201};
3202static const unsigned int pwm4_b_mux[] = {
3203 PWM4_B_MARK,
3204};
3205/* - PWM5 --------------------------------------------------------------------*/
3206static const unsigned int pwm5_a_pins[] = {
3207 /* PWM */
3208 RCAR_GP_PIN(1, 2),
3209};
3210static const unsigned int pwm5_a_mux[] = {
3211 PWM5_A_MARK,
3212};
3213static const unsigned int pwm5_b_pins[] = {
3214 /* PWM */
3215 RCAR_GP_PIN(2, 4),
3216};
3217static const unsigned int pwm5_b_mux[] = {
3218 PWM5_B_MARK,
3219};
3220/* - PWM6 --------------------------------------------------------------------*/
3221static const unsigned int pwm6_a_pins[] = {
3222 /* PWM */
3223 RCAR_GP_PIN(1, 3),
3224};
3225static const unsigned int pwm6_a_mux[] = {
3226 PWM6_A_MARK,
3227};
3228static const unsigned int pwm6_b_pins[] = {
3229 /* PWM */
3230 RCAR_GP_PIN(2, 5),
3231};
3232static const unsigned int pwm6_b_mux[] = {
3233 PWM6_B_MARK,
3234};
3235
e7ad4d3c
GU		 3236/* - SCIF0 ------------------------------------------------------------------ */
3237static const unsigned int scif0_data_pins[] = {
3238 /* RX, TX */
3239 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3240};
3241static const unsigned int scif0_data_mux[] = {
3242 RX0_MARK, TX0_MARK,
3243};
3244static const unsigned int scif0_clk_pins[] = {
3245 /* SCK */
3246 RCAR_GP_PIN(5, 0),
3247};
3248static const unsigned int scif0_clk_mux[] = {
3249 SCK0_MARK,
3250};
3251static const unsigned int scif0_ctrl_pins[] = {
3252 /* RTS, CTS */
3253 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3254};
3255static const unsigned int scif0_ctrl_mux[] = {
3256 RTS0_N_TANS_MARK, CTS0_N_MARK,
3257};
3258/* - SCIF1 ------------------------------------------------------------------ */
3259static const unsigned int scif1_data_a_pins[] = {
3260 /* RX, TX */
3261 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3262};
3263static const unsigned int scif1_data_a_mux[] = {
3264 RX1_A_MARK, TX1_A_MARK,
3265};
3266static const unsigned int scif1_clk_pins[] = {
3267 /* SCK */
3268 RCAR_GP_PIN(6, 21),
3269};
3270static const unsigned int scif1_clk_mux[] = {
3271 SCK1_MARK,
3272};
3273static const unsigned int scif1_ctrl_pins[] = {
3274 /* RTS, CTS */
3275 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3276};
3277static const unsigned int scif1_ctrl_mux[] = {
3278 RTS1_N_TANS_MARK, CTS1_N_MARK,
3279};
3280
3281static const unsigned int scif1_data_b_pins[] = {
3282 /* RX, TX */
3283 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3284};
3285static const unsigned int scif1_data_b_mux[] = {
3286 RX1_B_MARK, TX1_B_MARK,
3287};
3288/* - SCIF2 ------------------------------------------------------------------ */
3289static const unsigned int scif2_data_a_pins[] = {
3290 /* RX, TX */
3291 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3292};
3293static const unsigned int scif2_data_a_mux[] = {
3294 RX2_A_MARK, TX2_A_MARK,
3295};
3296static const unsigned int scif2_clk_pins[] = {
3297 /* SCK */
3298 RCAR_GP_PIN(5, 9),
3299};
3300static const unsigned int scif2_clk_mux[] = {
3301 SCK2_MARK,
3302};
3303static const unsigned int scif2_data_b_pins[] = {
3304 /* RX, TX */
3305 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3306};
3307static const unsigned int scif2_data_b_mux[] = {
3308 RX2_B_MARK, TX2_B_MARK,
3309};
3310/* - SCIF3 ------------------------------------------------------------------ */
3311static const unsigned int scif3_data_a_pins[] = {
3312 /* RX, TX */
3313 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3314};
3315static const unsigned int scif3_data_a_mux[] = {
3316 RX3_A_MARK, TX3_A_MARK,
3317};
3318static const unsigned int scif3_clk_pins[] = {
3319 /* SCK */
3320 RCAR_GP_PIN(1, 22),
3321};
3322static const unsigned int scif3_clk_mux[] = {
3323 SCK3_MARK,
3324};
3325static const unsigned int scif3_ctrl_pins[] = {
3326 /* RTS, CTS */
3327 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3328};
3329static const unsigned int scif3_ctrl_mux[] = {
3330 RTS3_N_TANS_MARK, CTS3_N_MARK,
3331};
3332static const unsigned int scif3_data_b_pins[] = {
3333 /* RX, TX */
3334 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3335};
3336static const unsigned int scif3_data_b_mux[] = {
3337 RX3_B_MARK, TX3_B_MARK,
3338};
3339/* - SCIF4 ------------------------------------------------------------------ */
3340static const unsigned int scif4_data_a_pins[] = {
3341 /* RX, TX */
3342 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3343};
3344static const unsigned int scif4_data_a_mux[] = {
3345 RX4_A_MARK, TX4_A_MARK,
3346};
3347static const unsigned int scif4_clk_a_pins[] = {
3348 /* SCK */
3349 RCAR_GP_PIN(2, 10),
3350};
3351static const unsigned int scif4_clk_a_mux[] = {
3352 SCK4_A_MARK,
3353};
3354static const unsigned int scif4_ctrl_a_pins[] = {
3355 /* RTS, CTS */
3356 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3357};
3358static const unsigned int scif4_ctrl_a_mux[] = {
3359 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3360};
3361static const unsigned int scif4_data_b_pins[] = {
3362 /* RX, TX */
3363 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3364};
3365static const unsigned int scif4_data_b_mux[] = {
3366 RX4_B_MARK, TX4_B_MARK,
3367};
3368static const unsigned int scif4_clk_b_pins[] = {
3369 /* SCK */
3370 RCAR_GP_PIN(1, 5),
3371};
3372static const unsigned int scif4_clk_b_mux[] = {
3373 SCK4_B_MARK,
3374};
3375static const unsigned int scif4_ctrl_b_pins[] = {
3376 /* RTS, CTS */
3377 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3378};
3379static const unsigned int scif4_ctrl_b_mux[] = {
3380 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3381};
3382static const unsigned int scif4_data_c_pins[] = {
3383 /* RX, TX */
3384 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3385};
3386static const unsigned int scif4_data_c_mux[] = {
3387 RX4_C_MARK, TX4_C_MARK,
3388};
3389static const unsigned int scif4_clk_c_pins[] = {
3390 /* SCK */
3391 RCAR_GP_PIN(0, 8),
3392};
3393static const unsigned int scif4_clk_c_mux[] = {
3394 SCK4_C_MARK,
3395};
3396static const unsigned int scif4_ctrl_c_pins[] = {
3397 /* RTS, CTS */
3398 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3399};
3400static const unsigned int scif4_ctrl_c_mux[] = {
3401 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3402};
3403/* - SCIF5 ------------------------------------------------------------------ */
3404static const unsigned int scif5_data_a_pins[] = {
3405 /* RX, TX */
3406 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3407};
3408static const unsigned int scif5_data_a_mux[] = {
3409 RX5_A_MARK, TX5_A_MARK,
3410};
3411static const unsigned int scif5_clk_a_pins[] = {
3412 /* SCK */
3413 RCAR_GP_PIN(6, 21),
3414};
3415static const unsigned int scif5_clk_a_mux[] = {
3416 SCK5_A_MARK,
3417};
3418static const unsigned int scif5_data_b_pins[] = {
3419 /* RX, TX */
3420 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3421};
3422static const unsigned int scif5_data_b_mux[] = {
3423 RX5_B_MARK, TX5_B_MARK,
3424};
3425static const unsigned int scif5_clk_b_pins[] = {
3426 /* SCK */
3427 RCAR_GP_PIN(5, 0),
3428};
3429static const unsigned int scif5_clk_b_mux[] = {
3430 SCK5_B_MARK,
3431};
3432
b4062b46
GU		 3433/* - SCIF Clock ------------------------------------------------------------- */
3434static const unsigned int scif_clk_a_pins[] = {
3435 /* SCIF_CLK */
3436 RCAR_GP_PIN(6, 23),
3437};
3438static const unsigned int scif_clk_a_mux[] = {
3439 SCIF_CLK_A_MARK,
3440};
3441static const unsigned int scif_clk_b_pins[] = {
3442 /* SCIF_CLK */
3443 RCAR_GP_PIN(5, 9),
3444};
3445static const unsigned int scif_clk_b_mux[] = {
3446 SCIF_CLK_B_MARK,
3447};
3448
9ed13958
TK		 3449/* - SDHI0 ------------------------------------------------------------------ */
3450static const unsigned int sdhi0_data1_pins[] = {
3451 /* D0 */
3452 RCAR_GP_PIN(3, 2),
3453};
3454static const unsigned int sdhi0_data1_mux[] = {
3455 SD0_DAT0_MARK,
3456};
3457static const unsigned int sdhi0_data4_pins[] = {
3458 /* D[0:3] */
3459 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3460 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3461};
3462static const unsigned int sdhi0_data4_mux[] = {
3463 SD0_DAT0_MARK, SD0_DAT1_MARK,
3464 SD0_DAT2_MARK, SD0_DAT3_MARK,
3465};
3466static const unsigned int sdhi0_ctrl_pins[] = {
3467 /* CLK, CMD */
3468 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3469};
3470static const unsigned int sdhi0_ctrl_mux[] = {
3471 SD0_CLK_MARK, SD0_CMD_MARK,
3472};
3473static const unsigned int sdhi0_cd_pins[] = {
3474 /* CD */
3475 RCAR_GP_PIN(3, 12),
3476};
3477static const unsigned int sdhi0_cd_mux[] = {
3478 SD0_CD_MARK,
3479};
3480static const unsigned int sdhi0_wp_pins[] = {
3481 /* WP */
3482 RCAR_GP_PIN(3, 13),
3483};
3484static const unsigned int sdhi0_wp_mux[] = {
3485 SD0_WP_MARK,
3486};
3487/* - SDHI1 ------------------------------------------------------------------ */
3488static const unsigned int sdhi1_data1_pins[] = {
3489 /* D0 */
3490 RCAR_GP_PIN(3, 8),
3491};
3492static const unsigned int sdhi1_data1_mux[] = {
3493 SD1_DAT0_MARK,
3494};
3495static const unsigned int sdhi1_data4_pins[] = {
3496 /* D[0:3] */
3497 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3498 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3499};
3500static const unsigned int sdhi1_data4_mux[] = {
3501 SD1_DAT0_MARK, SD1_DAT1_MARK,
3502 SD1_DAT2_MARK, SD1_DAT3_MARK,
3503};
3504static const unsigned int sdhi1_ctrl_pins[] = {
3505 /* CLK, CMD */
3506 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3507};
3508static const unsigned int sdhi1_ctrl_mux[] = {
3509 SD1_CLK_MARK, SD1_CMD_MARK,
3510};
3511static const unsigned int sdhi1_cd_pins[] = {
3512 /* CD */
3513 RCAR_GP_PIN(3, 14),
3514};
3515static const unsigned int sdhi1_cd_mux[] = {
3516 SD1_CD_MARK,
3517};
3518static const unsigned int sdhi1_wp_pins[] = {
3519 /* WP */
3520 RCAR_GP_PIN(3, 15),
3521};
3522static const unsigned int sdhi1_wp_mux[] = {
3523 SD1_WP_MARK,
3524};
3525/* - SDHI2 ------------------------------------------------------------------ */
3526static const unsigned int sdhi2_data1_pins[] = {
3527 /* D0 */
3528 RCAR_GP_PIN(4, 2),
3529};
3530static const unsigned int sdhi2_data1_mux[] = {
3531 SD2_DAT0_MARK,
3532};
3533static const unsigned int sdhi2_data4_pins[] = {
3534 /* D[0:3] */
3535 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3536 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3537};
3538static const unsigned int sdhi2_data4_mux[] = {
3539 SD2_DAT0_MARK, SD2_DAT1_MARK,
3540 SD2_DAT2_MARK, SD2_DAT3_MARK,
3541};
3542static const unsigned int sdhi2_data8_pins[] = {
3543 /* D[0:7] */
3544 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3545 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3546 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3547 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3548};
3549static const unsigned int sdhi2_data8_mux[] = {
3550 SD2_DAT0_MARK, SD2_DAT1_MARK,
3551 SD2_DAT2_MARK, SD2_DAT3_MARK,
3552 SD2_DAT4_MARK, SD2_DAT5_MARK,
3553 SD2_DAT6_MARK, SD2_DAT7_MARK,
3554};
3555static const unsigned int sdhi2_ctrl_pins[] = {
3556 /* CLK, CMD */
3557 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3558};
3559static const unsigned int sdhi2_ctrl_mux[] = {
3560 SD2_CLK_MARK, SD2_CMD_MARK,
3561};
3562static const unsigned int sdhi2_cd_a_pins[] = {
3563 /* CD */
3564 RCAR_GP_PIN(4, 13),
3565};
3566static const unsigned int sdhi2_cd_a_mux[] = {
3567 SD2_CD_A_MARK,
3568};
3569static const unsigned int sdhi2_cd_b_pins[] = {
3570 /* CD */
3571 RCAR_GP_PIN(5, 10),
3572};
3573static const unsigned int sdhi2_cd_b_mux[] = {
3574 SD2_CD_B_MARK,
3575};
3576static const unsigned int sdhi2_wp_a_pins[] = {
3577 /* WP */
3578 RCAR_GP_PIN(4, 14),
3579};
3580static const unsigned int sdhi2_wp_a_mux[] = {
3581 SD2_WP_A_MARK,
3582};
3583static const unsigned int sdhi2_wp_b_pins[] = {
3584 /* WP */
3585 RCAR_GP_PIN(5, 11),
3586};
3587static const unsigned int sdhi2_wp_b_mux[] = {
3588 SD2_WP_B_MARK,
3589};
3590static const unsigned int sdhi2_ds_pins[] = {
3591 /* DS */
3592 RCAR_GP_PIN(4, 6),
3593};
3594static const unsigned int sdhi2_ds_mux[] = {
3595 SD2_DS_MARK,
3596};
3597/* - SDHI3 ------------------------------------------------------------------ */
3598static const unsigned int sdhi3_data1_pins[] = {
3599 /* D0 */
3600 RCAR_GP_PIN(4, 9),
3601};
3602static const unsigned int sdhi3_data1_mux[] = {
3603 SD3_DAT0_MARK,
3604};
3605static const unsigned int sdhi3_data4_pins[] = {
3606 /* D[0:3] */
3607 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3608 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3609};
3610static const unsigned int sdhi3_data4_mux[] = {
3611 SD3_DAT0_MARK, SD3_DAT1_MARK,
3612 SD3_DAT2_MARK, SD3_DAT3_MARK,
3613};
3614static const unsigned int sdhi3_data8_pins[] = {
3615 /* D[0:7] */
3616 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3617 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3618 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3619 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3620};
3621static const unsigned int sdhi3_data8_mux[] = {
3622 SD3_DAT0_MARK, SD3_DAT1_MARK,
3623 SD3_DAT2_MARK, SD3_DAT3_MARK,
3624 SD3_DAT4_MARK, SD3_DAT5_MARK,
3625 SD3_DAT6_MARK, SD3_DAT7_MARK,
3626};
3627static const unsigned int sdhi3_ctrl_pins[] = {
3628 /* CLK, CMD */
3629 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3630};
3631static const unsigned int sdhi3_ctrl_mux[] = {
3632 SD3_CLK_MARK, SD3_CMD_MARK,
3633};
3634static const unsigned int sdhi3_cd_pins[] = {
3635 /* CD */
3636 RCAR_GP_PIN(4, 15),
3637};
3638static const unsigned int sdhi3_cd_mux[] = {
3639 SD3_CD_MARK,
3640};
3641static const unsigned int sdhi3_wp_pins[] = {
3642 /* WP */
3643 RCAR_GP_PIN(4, 16),
3644};
3645static const unsigned int sdhi3_wp_mux[] = {
3646 SD3_WP_MARK,
3647};
3648static const unsigned int sdhi3_ds_pins[] = {
3649 /* DS */
3650 RCAR_GP_PIN(4, 17),
3651};
3652static const unsigned int sdhi3_ds_mux[] = {
3653 SD3_DS_MARK,
3654};
3655
0526234d
KM		 3656/* - SSI -------------------------------------------------------------------- */
3657static const unsigned int ssi0_data_pins[] = {
3658 /* SDATA */
3659 RCAR_GP_PIN(6, 2),
3660};
3661static const unsigned int ssi0_data_mux[] = {
3662 SSI_SDATA0_MARK,
3663};
3664static const unsigned int ssi01239_ctrl_pins[] = {
3665 /* SCK, WS */
3666 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3667};
3668static const unsigned int ssi01239_ctrl_mux[] = {
3669 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3670};
3671static const unsigned int ssi1_data_a_pins[] = {
3672 /* SDATA */
3673 RCAR_GP_PIN(6, 3),
3674};
3675static const unsigned int ssi1_data_a_mux[] = {
3676 SSI_SDATA1_A_MARK,
3677};
3678static const unsigned int ssi1_data_b_pins[] = {
3679 /* SDATA */
3680 RCAR_GP_PIN(5, 12),
3681};
3682static const unsigned int ssi1_data_b_mux[] = {
3683 SSI_SDATA1_B_MARK,
3684};
3685static const unsigned int ssi1_ctrl_a_pins[] = {
3686 /* SCK, WS */
3687 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3688};
3689static const unsigned int ssi1_ctrl_a_mux[] = {
3690 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3691};
3692static const unsigned int ssi1_ctrl_b_pins[] = {
3693 /* SCK, WS */
3694 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3695};
3696static const unsigned int ssi1_ctrl_b_mux[] = {
3697 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3698};
3699static const unsigned int ssi2_data_a_pins[] = {
3700 /* SDATA */
3701 RCAR_GP_PIN(6, 4),
3702};
3703static const unsigned int ssi2_data_a_mux[] = {
3704 SSI_SDATA2_A_MARK,
3705};
3706static const unsigned int ssi2_data_b_pins[] = {
3707 /* SDATA */
3708 RCAR_GP_PIN(5, 13),
3709};
3710static const unsigned int ssi2_data_b_mux[] = {
3711 SSI_SDATA2_B_MARK,
3712};
3713static const unsigned int ssi2_ctrl_a_pins[] = {
3714 /* SCK, WS */
3715 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3716};
3717static const unsigned int ssi2_ctrl_a_mux[] = {
3718 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3719};
3720static const unsigned int ssi2_ctrl_b_pins[] = {
3721 /* SCK, WS */
3722 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3723};
3724static const unsigned int ssi2_ctrl_b_mux[] = {
3725 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3726};
3727static const unsigned int ssi3_data_pins[] = {
3728 /* SDATA */
3729 RCAR_GP_PIN(6, 7),
3730};
3731static const unsigned int ssi3_data_mux[] = {
3732 SSI_SDATA3_MARK,
3733};
3734static const unsigned int ssi349_ctrl_pins[] = {
3735 /* SCK, WS */
3736 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3737};
3738static const unsigned int ssi349_ctrl_mux[] = {
3739 SSI_SCK349_MARK, SSI_WS349_MARK,
3740};
3741static const unsigned int ssi4_data_pins[] = {
3742 /* SDATA */
3743 RCAR_GP_PIN(6, 10),
3744};
3745static const unsigned int ssi4_data_mux[] = {
3746 SSI_SDATA4_MARK,
3747};
3748static const unsigned int ssi4_ctrl_pins[] = {
3749 /* SCK, WS */
3750 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3751};
3752static const unsigned int ssi4_ctrl_mux[] = {
3753 SSI_SCK4_MARK, SSI_WS4_MARK,
3754};
3755static const unsigned int ssi5_data_pins[] = {
3756 /* SDATA */
3757 RCAR_GP_PIN(6, 13),
3758};
3759static const unsigned int ssi5_data_mux[] = {
3760 SSI_SDATA5_MARK,
3761};
3762static const unsigned int ssi5_ctrl_pins[] = {
3763 /* SCK, WS */
3764 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3765};
3766static const unsigned int ssi5_ctrl_mux[] = {
3767 SSI_SCK5_MARK, SSI_WS5_MARK,
3768};
3769static const unsigned int ssi6_data_pins[] = {
3770 /* SDATA */
3771 RCAR_GP_PIN(6, 16),
3772};
3773static const unsigned int ssi6_data_mux[] = {
3774 SSI_SDATA6_MARK,
3775};
3776static const unsigned int ssi6_ctrl_pins[] = {
3777 /* SCK, WS */
3778 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3779};
3780static const unsigned int ssi6_ctrl_mux[] = {
3781 SSI_SCK6_MARK, SSI_WS6_MARK,
3782};
3783static const unsigned int ssi7_data_pins[] = {
3784 /* SDATA */
3785 RCAR_GP_PIN(6, 19),
3786};
3787static const unsigned int ssi7_data_mux[] = {
3788 SSI_SDATA7_MARK,
3789};
3790static const unsigned int ssi78_ctrl_pins[] = {
3791 /* SCK, WS */
3792 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3793};
3794static const unsigned int ssi78_ctrl_mux[] = {
3795 SSI_SCK78_MARK, SSI_WS78_MARK,
3796};
3797static const unsigned int ssi8_data_pins[] = {
3798 /* SDATA */
3799 RCAR_GP_PIN(6, 20),
3800};
3801static const unsigned int ssi8_data_mux[] = {
3802 SSI_SDATA8_MARK,
3803};
3804static const unsigned int ssi9_data_a_pins[] = {
3805 /* SDATA */
3806 RCAR_GP_PIN(6, 21),
3807};
3808static const unsigned int ssi9_data_a_mux[] = {
3809 SSI_SDATA9_A_MARK,
3810};
3811static const unsigned int ssi9_data_b_pins[] = {
3812 /* SDATA */
3813 RCAR_GP_PIN(5, 14),
3814};
3815static const unsigned int ssi9_data_b_mux[] = {
3816 SSI_SDATA9_B_MARK,
3817};
3818static const unsigned int ssi9_ctrl_a_pins[] = {
3819 /* SCK, WS */
3820 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3821};
3822static const unsigned int ssi9_ctrl_a_mux[] = {
3823 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3824};
3825static const unsigned int ssi9_ctrl_b_pins[] = {
3826 /* SCK, WS */
3827 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3828};
3829static const unsigned int ssi9_ctrl_b_mux[] = {
3830 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3831};
3832
933ddbe5
YS		 3833/* - USB0 ------------------------------------------------------------------- */
3834static const unsigned int usb0_pins[] = {
3835 /* PWEN, OVC */
3836 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3837};
3838static const unsigned int usb0_mux[] = {
3839 USB0_PWEN_MARK, USB0_OVC_MARK,
3840};
3841/* - USB1 ------------------------------------------------------------------- */
3842static const unsigned int usb1_pins[] = {
3843 /* PWEN, OVC */
3844 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3845};
3846static const unsigned int usb1_mux[] = {
3847 USB1_PWEN_MARK, USB1_OVC_MARK,
3848};
3849/* - USB2 ------------------------------------------------------------------- */
3850static const unsigned int usb2_pins[] = {
3851 /* PWEN, OVC */
3852 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3853};
3854static const unsigned int usb2_mux[] = {
3855 USB2_PWEN_MARK, USB2_OVC_MARK,
3856};
3857/* - USB2_CH3 --------------------------------------------------------------- */
3858static const unsigned int usb2_ch3_pins[] = {
3859 /* PWEN, OVC */
3860 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3861};
3862static const unsigned int usb2_ch3_mux[] = {
3863 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3864};
3865
5ec8a41a
TK		 3866/* - USB30 ------------------------------------------------------------------ */
3867static const unsigned int usb30_pins[] = {
3868 /* PWEN, OVC */
3869 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3870};
3871static const unsigned int usb30_mux[] = {
3872 USB30_PWEN_MARK, USB30_OVC_MARK,
3873};
3874
b205914c 3875static const struct sh_pfc_pin_group pinmux_groups[] = {
55bfea9f
KM		 3876 SH_PFC_PIN_GROUP(audio_clk_a_a),
3877 SH_PFC_PIN_GROUP(audio_clk_a_b),
3878 SH_PFC_PIN_GROUP(audio_clk_a_c),
3879 SH_PFC_PIN_GROUP(audio_clk_b_a),
3880 SH_PFC_PIN_GROUP(audio_clk_b_b),
3881 SH_PFC_PIN_GROUP(audio_clk_c_a),
3882 SH_PFC_PIN_GROUP(audio_clk_c_b),
3883 SH_PFC_PIN_GROUP(audio_clkout_a),
3884 SH_PFC_PIN_GROUP(audio_clkout_b),
3885 SH_PFC_PIN_GROUP(audio_clkout_c),
3886 SH_PFC_PIN_GROUP(audio_clkout_d),
3887 SH_PFC_PIN_GROUP(audio_clkout1_a),
3888 SH_PFC_PIN_GROUP(audio_clkout1_b),
3889 SH_PFC_PIN_GROUP(audio_clkout2_a),
3890 SH_PFC_PIN_GROUP(audio_clkout2_b),
3891 SH_PFC_PIN_GROUP(audio_clkout3_a),
3892 SH_PFC_PIN_GROUP(audio_clkout3_b),
30c078de
GU		 3893 SH_PFC_PIN_GROUP(avb_link),
3894 SH_PFC_PIN_GROUP(avb_magic),
3895 SH_PFC_PIN_GROUP(avb_phy_int),
3896 SH_PFC_PIN_GROUP(avb_mdc),
3897 SH_PFC_PIN_GROUP(avb_mii),
3898 SH_PFC_PIN_GROUP(avb_avtp_pps),
3899 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3900 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3901 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3902 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a678abfe
RS		 3903 SH_PFC_PIN_GROUP(can0_data_a),
3904 SH_PFC_PIN_GROUP(can0_data_b),
3905 SH_PFC_PIN_GROUP(can1_data),
3906 SH_PFC_PIN_GROUP(can_clk),
0e1c7a94
RS		 3907 SH_PFC_PIN_GROUP(canfd0_data_a),
3908 SH_PFC_PIN_GROUP(canfd0_data_b),
3909 SH_PFC_PIN_GROUP(canfd1_data),
641b0ab8
DB		 3910 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3911 SH_PFC_PIN_GROUP(drif0_data0_a),
3912 SH_PFC_PIN_GROUP(drif0_data1_a),
3913 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3914 SH_PFC_PIN_GROUP(drif0_data0_b),
3915 SH_PFC_PIN_GROUP(drif0_data1_b),
3916 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3917 SH_PFC_PIN_GROUP(drif0_data0_c),
3918 SH_PFC_PIN_GROUP(drif0_data1_c),
3919 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3920 SH_PFC_PIN_GROUP(drif1_data0_a),
3921 SH_PFC_PIN_GROUP(drif1_data1_a),
3922 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3923 SH_PFC_PIN_GROUP(drif1_data0_b),
3924 SH_PFC_PIN_GROUP(drif1_data1_b),
3925 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3926 SH_PFC_PIN_GROUP(drif1_data0_c),
3927 SH_PFC_PIN_GROUP(drif1_data1_c),
3928 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3929 SH_PFC_PIN_GROUP(drif2_data0_a),
3930 SH_PFC_PIN_GROUP(drif2_data1_a),
3931 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3932 SH_PFC_PIN_GROUP(drif2_data0_b),
3933 SH_PFC_PIN_GROUP(drif2_data1_b),
3934 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3935 SH_PFC_PIN_GROUP(drif3_data0_a),
3936 SH_PFC_PIN_GROUP(drif3_data1_a),
3937 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3938 SH_PFC_PIN_GROUP(drif3_data0_b),
3939 SH_PFC_PIN_GROUP(drif3_data1_b),
a20a6585
LP		 3940 SH_PFC_PIN_GROUP(du_rgb666),
3941 SH_PFC_PIN_GROUP(du_rgb888),
3942 SH_PFC_PIN_GROUP(du_clk_out_0),
3943 SH_PFC_PIN_GROUP(du_clk_out_1),
3944 SH_PFC_PIN_GROUP(du_sync),
3945 SH_PFC_PIN_GROUP(du_oddf),
3946 SH_PFC_PIN_GROUP(du_cde),
3947 SH_PFC_PIN_GROUP(du_disp),
7a362e34
WS		 3948 SH_PFC_PIN_GROUP(hscif0_data),
3949 SH_PFC_PIN_GROUP(hscif0_clk),
3950 SH_PFC_PIN_GROUP(hscif0_ctrl),
3951 SH_PFC_PIN_GROUP(hscif1_data_a),
3952 SH_PFC_PIN_GROUP(hscif1_clk_a),
3953 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3954 SH_PFC_PIN_GROUP(hscif1_data_b),
3955 SH_PFC_PIN_GROUP(hscif1_clk_b),
3956 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3957 SH_PFC_PIN_GROUP(hscif2_data_a),
3958 SH_PFC_PIN_GROUP(hscif2_clk_a),
3959 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3960 SH_PFC_PIN_GROUP(hscif2_data_b),
3961 SH_PFC_PIN_GROUP(hscif2_clk_b),
3962 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3963 SH_PFC_PIN_GROUP(hscif2_data_c),
3964 SH_PFC_PIN_GROUP(hscif2_clk_c),
3965 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3966 SH_PFC_PIN_GROUP(hscif3_data_a),
3967 SH_PFC_PIN_GROUP(hscif3_clk),
3968 SH_PFC_PIN_GROUP(hscif3_ctrl),
3969 SH_PFC_PIN_GROUP(hscif3_data_b),
3970 SH_PFC_PIN_GROUP(hscif3_data_c),
3971 SH_PFC_PIN_GROUP(hscif3_data_d),
3972 SH_PFC_PIN_GROUP(hscif4_data_a),
3973 SH_PFC_PIN_GROUP(hscif4_clk),
3974 SH_PFC_PIN_GROUP(hscif4_ctrl),
3975 SH_PFC_PIN_GROUP(hscif4_data_b),
f62d4c9e
WS		 3976 SH_PFC_PIN_GROUP(i2c1_a),
3977 SH_PFC_PIN_GROUP(i2c1_b),
3978 SH_PFC_PIN_GROUP(i2c2_a),
3979 SH_PFC_PIN_GROUP(i2c2_b),
3980 SH_PFC_PIN_GROUP(i2c6_a),
3981 SH_PFC_PIN_GROUP(i2c6_b),
3982 SH_PFC_PIN_GROUP(i2c6_c),
8480e6ca
GU		 3983 SH_PFC_PIN_GROUP(intc_ex_irq0),
3984 SH_PFC_PIN_GROUP(intc_ex_irq1),
3985 SH_PFC_PIN_GROUP(intc_ex_irq2),
3986 SH_PFC_PIN_GROUP(intc_ex_irq3),
3987 SH_PFC_PIN_GROUP(intc_ex_irq4),
3988 SH_PFC_PIN_GROUP(intc_ex_irq5),
3e6c7727
GU		 3989 SH_PFC_PIN_GROUP(msiof0_clk),
3990 SH_PFC_PIN_GROUP(msiof0_sync),
3991 SH_PFC_PIN_GROUP(msiof0_ss1),
3992 SH_PFC_PIN_GROUP(msiof0_ss2),
3993 SH_PFC_PIN_GROUP(msiof0_txd),
3994 SH_PFC_PIN_GROUP(msiof0_rxd),
3995 SH_PFC_PIN_GROUP(msiof1_clk_a),
3996 SH_PFC_PIN_GROUP(msiof1_sync_a),
3997 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3998 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3999 SH_PFC_PIN_GROUP(msiof1_txd_a),
4000 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4001 SH_PFC_PIN_GROUP(msiof1_clk_b),
4002 SH_PFC_PIN_GROUP(msiof1_sync_b),
4003 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4004 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4005 SH_PFC_PIN_GROUP(msiof1_txd_b),
4006 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4007 SH_PFC_PIN_GROUP(msiof1_clk_c),
4008 SH_PFC_PIN_GROUP(msiof1_sync_c),
4009 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4010 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4011 SH_PFC_PIN_GROUP(msiof1_txd_c),
4012 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4013 SH_PFC_PIN_GROUP(msiof1_clk_d),
4014 SH_PFC_PIN_GROUP(msiof1_sync_d),
4015 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4016 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4017 SH_PFC_PIN_GROUP(msiof1_txd_d),
4018 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4019 SH_PFC_PIN_GROUP(msiof1_clk_e),
4020 SH_PFC_PIN_GROUP(msiof1_sync_e),
4021 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4022 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4023 SH_PFC_PIN_GROUP(msiof1_txd_e),
4024 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4025 SH_PFC_PIN_GROUP(msiof1_clk_f),
4026 SH_PFC_PIN_GROUP(msiof1_sync_f),
4027 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4028 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4029 SH_PFC_PIN_GROUP(msiof1_txd_f),
4030 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4031 SH_PFC_PIN_GROUP(msiof1_clk_g),
4032 SH_PFC_PIN_GROUP(msiof1_sync_g),
4033 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4034 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4035 SH_PFC_PIN_GROUP(msiof1_txd_g),
4036 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4037 SH_PFC_PIN_GROUP(msiof2_clk_a),
4038 SH_PFC_PIN_GROUP(msiof2_sync_a),
4039 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4040 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4041 SH_PFC_PIN_GROUP(msiof2_txd_a),
4042 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4043 SH_PFC_PIN_GROUP(msiof2_clk_b),
4044 SH_PFC_PIN_GROUP(msiof2_sync_b),
4045 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4046 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4047 SH_PFC_PIN_GROUP(msiof2_txd_b),
4048 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4049 SH_PFC_PIN_GROUP(msiof2_clk_c),
4050 SH_PFC_PIN_GROUP(msiof2_sync_c),
4051 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4052 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4053 SH_PFC_PIN_GROUP(msiof2_txd_c),
4054 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4055 SH_PFC_PIN_GROUP(msiof2_clk_d),
4056 SH_PFC_PIN_GROUP(msiof2_sync_d),
4057 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4058 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4059 SH_PFC_PIN_GROUP(msiof2_txd_d),
4060 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4061 SH_PFC_PIN_GROUP(msiof3_clk_a),
4062 SH_PFC_PIN_GROUP(msiof3_sync_a),
4063 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4064 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4065 SH_PFC_PIN_GROUP(msiof3_txd_a),
4066 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4067 SH_PFC_PIN_GROUP(msiof3_clk_b),
4068 SH_PFC_PIN_GROUP(msiof3_sync_b),
4069 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4070 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4071 SH_PFC_PIN_GROUP(msiof3_txd_b),
4072 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4073 SH_PFC_PIN_GROUP(msiof3_clk_c),
4074 SH_PFC_PIN_GROUP(msiof3_sync_c),
4075 SH_PFC_PIN_GROUP(msiof3_txd_c),
4076 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4077 SH_PFC_PIN_GROUP(msiof3_clk_d),
4078 SH_PFC_PIN_GROUP(msiof3_sync_d),
4079 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4080 SH_PFC_PIN_GROUP(msiof3_txd_d),
4081 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4082 SH_PFC_PIN_GROUP(msiof3_clk_e),
4083 SH_PFC_PIN_GROUP(msiof3_sync_e),
4084 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4085 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4086 SH_PFC_PIN_GROUP(msiof3_txd_e),
4087 SH_PFC_PIN_GROUP(msiof3_rxd_e),
c03a133b
LP		 4088 SH_PFC_PIN_GROUP(pwm0),
4089 SH_PFC_PIN_GROUP(pwm1_a),
4090 SH_PFC_PIN_GROUP(pwm1_b),
4091 SH_PFC_PIN_GROUP(pwm2_a),
4092 SH_PFC_PIN_GROUP(pwm2_b),
4093 SH_PFC_PIN_GROUP(pwm3_a),
4094 SH_PFC_PIN_GROUP(pwm3_b),
4095 SH_PFC_PIN_GROUP(pwm4_a),
4096 SH_PFC_PIN_GROUP(pwm4_b),
4097 SH_PFC_PIN_GROUP(pwm5_a),
4098 SH_PFC_PIN_GROUP(pwm5_b),
4099 SH_PFC_PIN_GROUP(pwm6_a),
4100 SH_PFC_PIN_GROUP(pwm6_b),
e7ad4d3c
GU		 4101 SH_PFC_PIN_GROUP(scif0_data),
4102 SH_PFC_PIN_GROUP(scif0_clk),
4103 SH_PFC_PIN_GROUP(scif0_ctrl),
4104 SH_PFC_PIN_GROUP(scif1_data_a),
4105 SH_PFC_PIN_GROUP(scif1_clk),
4106 SH_PFC_PIN_GROUP(scif1_ctrl),
4107 SH_PFC_PIN_GROUP(scif1_data_b),
4108 SH_PFC_PIN_GROUP(scif2_data_a),
4109 SH_PFC_PIN_GROUP(scif2_clk),
4110 SH_PFC_PIN_GROUP(scif2_data_b),
4111 SH_PFC_PIN_GROUP(scif3_data_a),
4112 SH_PFC_PIN_GROUP(scif3_clk),
4113 SH_PFC_PIN_GROUP(scif3_ctrl),
4114 SH_PFC_PIN_GROUP(scif3_data_b),
4115 SH_PFC_PIN_GROUP(scif4_data_a),
4116 SH_PFC_PIN_GROUP(scif4_clk_a),
4117 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4118 SH_PFC_PIN_GROUP(scif4_data_b),
4119 SH_PFC_PIN_GROUP(scif4_clk_b),
4120 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4121 SH_PFC_PIN_GROUP(scif4_data_c),
4122 SH_PFC_PIN_GROUP(scif4_clk_c),
4123 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4124 SH_PFC_PIN_GROUP(scif5_data_a),
4125 SH_PFC_PIN_GROUP(scif5_clk_a),
4126 SH_PFC_PIN_GROUP(scif5_data_b),
4127 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 4128 SH_PFC_PIN_GROUP(scif_clk_a),
4129 SH_PFC_PIN_GROUP(scif_clk_b),
9ed13958
TK		 4130 SH_PFC_PIN_GROUP(sdhi0_data1),
4131 SH_PFC_PIN_GROUP(sdhi0_data4),
4132 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4133 SH_PFC_PIN_GROUP(sdhi0_cd),
4134 SH_PFC_PIN_GROUP(sdhi0_wp),
4135 SH_PFC_PIN_GROUP(sdhi1_data1),
4136 SH_PFC_PIN_GROUP(sdhi1_data4),
4137 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4138 SH_PFC_PIN_GROUP(sdhi1_cd),
4139 SH_PFC_PIN_GROUP(sdhi1_wp),
4140 SH_PFC_PIN_GROUP(sdhi2_data1),
4141 SH_PFC_PIN_GROUP(sdhi2_data4),
4142 SH_PFC_PIN_GROUP(sdhi2_data8),
4143 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4144 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4145 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4146 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4147 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4148 SH_PFC_PIN_GROUP(sdhi2_ds),
4149 SH_PFC_PIN_GROUP(sdhi3_data1),
4150 SH_PFC_PIN_GROUP(sdhi3_data4),
4151 SH_PFC_PIN_GROUP(sdhi3_data8),
4152 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4153 SH_PFC_PIN_GROUP(sdhi3_cd),
4154 SH_PFC_PIN_GROUP(sdhi3_wp),
4155 SH_PFC_PIN_GROUP(sdhi3_ds),
0526234d
KM		 4156 SH_PFC_PIN_GROUP(ssi0_data),
4157 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4158 SH_PFC_PIN_GROUP(ssi1_data_a),
4159 SH_PFC_PIN_GROUP(ssi1_data_b),
4160 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4161 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4162 SH_PFC_PIN_GROUP(ssi2_data_a),
4163 SH_PFC_PIN_GROUP(ssi2_data_b),
4164 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4165 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4166 SH_PFC_PIN_GROUP(ssi3_data),
4167 SH_PFC_PIN_GROUP(ssi349_ctrl),
4168 SH_PFC_PIN_GROUP(ssi4_data),
4169 SH_PFC_PIN_GROUP(ssi4_ctrl),
4170 SH_PFC_PIN_GROUP(ssi5_data),
4171 SH_PFC_PIN_GROUP(ssi5_ctrl),
4172 SH_PFC_PIN_GROUP(ssi6_data),
4173 SH_PFC_PIN_GROUP(ssi6_ctrl),
4174 SH_PFC_PIN_GROUP(ssi7_data),
4175 SH_PFC_PIN_GROUP(ssi78_ctrl),
4176 SH_PFC_PIN_GROUP(ssi8_data),
4177 SH_PFC_PIN_GROUP(ssi9_data_a),
4178 SH_PFC_PIN_GROUP(ssi9_data_b),
4179 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4180 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
933ddbe5
YS		 4181 SH_PFC_PIN_GROUP(usb0),
4182 SH_PFC_PIN_GROUP(usb1),
4183 SH_PFC_PIN_GROUP(usb2),
4184 SH_PFC_PIN_GROUP(usb2_ch3),
5ec8a41a 4185 SH_PFC_PIN_GROUP(usb30),
e7ad4d3c
GU		 4186};
4187
55bfea9f
KM		 4188static const char * const audio_clk_groups[] = {
4189 "audio_clk_a_a",
4190 "audio_clk_a_b",
4191 "audio_clk_a_c",
4192 "audio_clk_b_a",
4193 "audio_clk_b_b",
4194 "audio_clk_c_a",
4195 "audio_clk_c_b",
4196 "audio_clkout_a",
4197 "audio_clkout_b",
4198 "audio_clkout_c",
4199 "audio_clkout_d",
4200 "audio_clkout1_a",
4201 "audio_clkout1_b",
4202 "audio_clkout2_a",
4203 "audio_clkout2_b",
4204 "audio_clkout3_a",
4205 "audio_clkout3_b",
4206};
4207
30c078de
GU		 4208static const char * const avb_groups[] = {
4209 "avb_link",
4210 "avb_magic",
4211 "avb_phy_int",
4212 "avb_mdc",
4213 "avb_mii",
4214 "avb_avtp_pps",
4215 "avb_avtp_match_a",
4216 "avb_avtp_capture_a",
4217 "avb_avtp_match_b",
4218 "avb_avtp_capture_b",
4219};
4220
a678abfe
RS		 4221static const char * const can0_groups[] = {
4222 "can0_data_a",
4223 "can0_data_b",
4224};
4225
4226static const char * const can1_groups[] = {
4227 "can1_data",
4228};
4229
4230static const char * const can_clk_groups[] = {
4231 "can_clk",
4232};
4233
0e1c7a94
RS		 4234static const char * const canfd0_groups[] = {
4235 "canfd0_data_a",
4236 "canfd0_data_b",
4237};
4238
4239static const char * const canfd1_groups[] = {
4240 "canfd1_data",
4241};
4242
641b0ab8
DB		 4243static const char * const drif0_groups[] = {
4244 "drif0_ctrl_a",
4245 "drif0_data0_a",
4246 "drif0_data1_a",
4247 "drif0_ctrl_b",
4248 "drif0_data0_b",
4249 "drif0_data1_b",
4250 "drif0_ctrl_c",
4251 "drif0_data0_c",
4252 "drif0_data1_c",
4253};
4254
4255static const char * const drif1_groups[] = {
4256 "drif1_ctrl_a",
4257 "drif1_data0_a",
4258 "drif1_data1_a",
4259 "drif1_ctrl_b",
4260 "drif1_data0_b",
4261 "drif1_data1_b",
4262 "drif1_ctrl_c",
4263 "drif1_data0_c",
4264 "drif1_data1_c",
4265};
4266
4267static const char * const drif2_groups[] = {
4268 "drif2_ctrl_a",
4269 "drif2_data0_a",
4270 "drif2_data1_a",
4271 "drif2_ctrl_b",
4272 "drif2_data0_b",
4273 "drif2_data1_b",
4274};
4275
4276static const char * const drif3_groups[] = {
4277 "drif3_ctrl_a",
4278 "drif3_data0_a",
4279 "drif3_data1_a",
4280 "drif3_ctrl_b",
4281 "drif3_data0_b",
4282 "drif3_data1_b",
4283};
4284
a20a6585
LP		 4285static const char * const du_groups[] = {
4286 "du_rgb666",
4287 "du_rgb888",
4288 "du_clk_out_0",
4289 "du_clk_out_1",
4290 "du_sync",
4291 "du_oddf",
4292 "du_cde",
4293 "du_disp",
4294};
4295
7a362e34
WS		 4296static const char * const hscif0_groups[] = {
4297 "hscif0_data",
4298 "hscif0_clk",
4299 "hscif0_ctrl",
4300};
4301
4302static const char * const hscif1_groups[] = {
4303 "hscif1_data_a",
4304 "hscif1_clk_a",
4305 "hscif1_ctrl_a",
4306 "hscif1_data_b",
4307 "hscif1_clk_b",
4308 "hscif1_ctrl_b",
4309};
4310
4311static const char * const hscif2_groups[] = {
4312 "hscif2_data_a",
4313 "hscif2_clk_a",
4314 "hscif2_ctrl_a",
4315 "hscif2_data_b",
4316 "hscif2_clk_b",
4317 "hscif2_ctrl_b",
4318 "hscif2_data_c",
4319 "hscif2_clk_c",
4320 "hscif2_ctrl_c",
4321};
4322
4323static const char * const hscif3_groups[] = {
4324 "hscif3_data_a",
4325 "hscif3_clk",
4326 "hscif3_ctrl",
4327 "hscif3_data_b",
4328 "hscif3_data_c",
4329 "hscif3_data_d",
4330};
4331
4332static const char * const hscif4_groups[] = {
4333 "hscif4_data_a",
4334 "hscif4_clk",
4335 "hscif4_ctrl",
4336 "hscif4_data_b",
4337};
4338
f62d4c9e
WS		 4339static const char * const i2c1_groups[] = {
4340 "i2c1_a",
4341 "i2c1_b",
4342};
4343
4344static const char * const i2c2_groups[] = {
4345 "i2c2_a",
4346 "i2c2_b",
4347};
4348
4349static const char * const i2c6_groups[] = {
4350 "i2c6_a",
4351 "i2c6_b",
4352 "i2c6_c",
4353};
4354
8480e6ca
GU		 4355static const char * const intc_ex_groups[] = {
4356 "intc_ex_irq0",
4357 "intc_ex_irq1",
4358 "intc_ex_irq2",
4359 "intc_ex_irq3",
4360 "intc_ex_irq4",
4361 "intc_ex_irq5",
4362};
4363
3e6c7727
GU		 4364static const char * const msiof0_groups[] = {
4365 "msiof0_clk",
4366 "msiof0_sync",
4367 "msiof0_ss1",
4368 "msiof0_ss2",
4369 "msiof0_txd",
4370 "msiof0_rxd",
4371};
4372
4373static const char * const msiof1_groups[] = {
4374 "msiof1_clk_a",
4375 "msiof1_sync_a",
4376 "msiof1_ss1_a",
4377 "msiof1_ss2_a",
4378 "msiof1_txd_a",
4379 "msiof1_rxd_a",
4380 "msiof1_clk_b",
4381 "msiof1_sync_b",
4382 "msiof1_ss1_b",
4383 "msiof1_ss2_b",
4384 "msiof1_txd_b",
4385 "msiof1_rxd_b",
4386 "msiof1_clk_c",
4387 "msiof1_sync_c",
4388 "msiof1_ss1_c",
4389 "msiof1_ss2_c",
4390 "msiof1_txd_c",
4391 "msiof1_rxd_c",
4392 "msiof1_clk_d",
4393 "msiof1_sync_d",
4394 "msiof1_ss1_d",
4395 "msiof1_ss2_d",
4396 "msiof1_txd_d",
4397 "msiof1_rxd_d",
4398 "msiof1_clk_e",
4399 "msiof1_sync_e",
4400 "msiof1_ss1_e",
4401 "msiof1_ss2_e",
4402 "msiof1_txd_e",
4403 "msiof1_rxd_e",
4404 "msiof1_clk_f",
4405 "msiof1_sync_f",
4406 "msiof1_ss1_f",
4407 "msiof1_ss2_f",
4408 "msiof1_txd_f",
4409 "msiof1_rxd_f",
4410 "msiof1_clk_g",
4411 "msiof1_sync_g",
4412 "msiof1_ss1_g",
4413 "msiof1_ss2_g",
4414 "msiof1_txd_g",
4415 "msiof1_rxd_g",
4416};
4417
4418static const char * const msiof2_groups[] = {
4419 "msiof2_clk_a",
4420 "msiof2_sync_a",
4421 "msiof2_ss1_a",
4422 "msiof2_ss2_a",
4423 "msiof2_txd_a",
4424 "msiof2_rxd_a",
4425 "msiof2_clk_b",
4426 "msiof2_sync_b",
4427 "msiof2_ss1_b",
4428 "msiof2_ss2_b",
4429 "msiof2_txd_b",
4430 "msiof2_rxd_b",
4431 "msiof2_clk_c",
4432 "msiof2_sync_c",
4433 "msiof2_ss1_c",
4434 "msiof2_ss2_c",
4435 "msiof2_txd_c",
4436 "msiof2_rxd_c",
4437 "msiof2_clk_d",
4438 "msiof2_sync_d",
4439 "msiof2_ss1_d",
4440 "msiof2_ss2_d",
4441 "msiof2_txd_d",
4442 "msiof2_rxd_d",
4443};
4444
4445static const char * const msiof3_groups[] = {
4446 "msiof3_clk_a",
4447 "msiof3_sync_a",
4448 "msiof3_ss1_a",
4449 "msiof3_ss2_a",
4450 "msiof3_txd_a",
4451 "msiof3_rxd_a",
4452 "msiof3_clk_b",
4453 "msiof3_sync_b",
4454 "msiof3_ss1_b",
4455 "msiof3_ss2_b",
4456 "msiof3_txd_b",
4457 "msiof3_rxd_b",
4458 "msiof3_clk_c",
4459 "msiof3_sync_c",
4460 "msiof3_txd_c",
4461 "msiof3_rxd_c",
4462 "msiof3_clk_d",
4463 "msiof3_sync_d",
4464 "msiof3_ss1_d",
4465 "msiof3_txd_d",
4466 "msiof3_rxd_d",
4467 "msiof3_clk_e",
4468 "msiof3_sync_e",
4469 "msiof3_ss1_e",
4470 "msiof3_ss2_e",
4471 "msiof3_txd_e",
4472 "msiof3_rxd_e",
4473};
4474
c03a133b
LP		 4475static const char * const pwm0_groups[] = {
4476 "pwm0",
4477};
4478
4479static const char * const pwm1_groups[] = {
4480 "pwm1_a",
4481 "pwm1_b",
4482};
4483
4484static const char * const pwm2_groups[] = {
4485 "pwm2_a",
4486 "pwm2_b",
4487};
4488
4489static const char * const pwm3_groups[] = {
4490 "pwm3_a",
4491 "pwm3_b",
4492};
4493
4494static const char * const pwm4_groups[] = {
4495 "pwm4_a",
4496 "pwm4_b",
4497};
4498
4499static const char * const pwm5_groups[] = {
4500 "pwm5_a",
4501 "pwm5_b",
4502};
4503
4504static const char * const pwm6_groups[] = {
4505 "pwm6_a",
4506 "pwm6_b",
4507};
4508
e7ad4d3c
GU		 4509static const char * const scif0_groups[] = {
4510 "scif0_data",
4511 "scif0_clk",
4512 "scif0_ctrl",
4513};
4514
4515static const char * const scif1_groups[] = {
4516 "scif1_data_a",
4517 "scif1_clk",
4518 "scif1_ctrl",
4519 "scif1_data_b",
4520};
4521
4522static const char * const scif2_groups[] = {
4523 "scif2_data_a",
4524 "scif2_clk",
4525 "scif2_data_b",
4526};
4527
4528static const char * const scif3_groups[] = {
4529 "scif3_data_a",
4530 "scif3_clk",
4531 "scif3_ctrl",
4532 "scif3_data_b",
4533};
4534
4535static const char * const scif4_groups[] = {
4536 "scif4_data_a",
4537 "scif4_clk_a",
4538 "scif4_ctrl_a",
4539 "scif4_data_b",
4540 "scif4_clk_b",
4541 "scif4_ctrl_b",
4542 "scif4_data_c",
4543 "scif4_clk_c",
4544 "scif4_ctrl_c",
4545};
4546
4547static const char * const scif5_groups[] = {
4548 "scif5_data_a",
4549 "scif5_clk_a",
4550 "scif5_data_b",
4551 "scif5_clk_b",
76250a6c
TK		 4552};
4553
d14a39ed
GU		 4554static const char * const scif_clk_groups[] = {
4555 "scif_clk_a",
4556 "scif_clk_b",
4557};
4558
9ed13958
TK		 4559static const char * const sdhi0_groups[] = {
4560 "sdhi0_data1",
4561 "sdhi0_data4",
4562 "sdhi0_ctrl",
4563 "sdhi0_cd",
4564 "sdhi0_wp",
4565};
4566
4567static const char * const sdhi1_groups[] = {
4568 "sdhi1_data1",
4569 "sdhi1_data4",
4570 "sdhi1_ctrl",
4571 "sdhi1_cd",
4572 "sdhi1_wp",
4573};
4574
4575static const char * const sdhi2_groups[] = {
4576 "sdhi2_data1",
4577 "sdhi2_data4",
4578 "sdhi2_data8",
4579 "sdhi2_ctrl",
4580 "sdhi2_cd_a",
4581 "sdhi2_wp_a",
4582 "sdhi2_cd_b",
4583 "sdhi2_wp_b",
4584 "sdhi2_ds",
4585};
4586
4587static const char * const sdhi3_groups[] = {
4588 "sdhi3_data1",
4589 "sdhi3_data4",
4590 "sdhi3_data8",
4591 "sdhi3_ctrl",
4592 "sdhi3_cd",
4593 "sdhi3_wp",
4594 "sdhi3_ds",
4595};
4596
0526234d
KM		 4597static const char * const ssi_groups[] = {
4598 "ssi0_data",
4599 "ssi01239_ctrl",
4600 "ssi1_data_a",
4601 "ssi1_data_b",
4602 "ssi1_ctrl_a",
4603 "ssi1_ctrl_b",
4604 "ssi2_data_a",
4605 "ssi2_data_b",
4606 "ssi2_ctrl_a",
4607 "ssi2_ctrl_b",
4608 "ssi3_data",
4609 "ssi349_ctrl",
4610 "ssi4_data",
4611 "ssi4_ctrl",
4612 "ssi5_data",
4613 "ssi5_ctrl",
4614 "ssi6_data",
4615 "ssi6_ctrl",
4616 "ssi7_data",
4617 "ssi78_ctrl",
4618 "ssi8_data",
4619 "ssi9_data_a",
4620 "ssi9_data_b",
4621 "ssi9_ctrl_a",
4622 "ssi9_ctrl_b",
4623};
4624
933ddbe5
YS		 4625static const char * const usb0_groups[] = {
4626 "usb0",
4627};
4628
4629static const char * const usb1_groups[] = {
4630 "usb1",
4631};
4632
4633static const char * const usb2_groups[] = {
4634 "usb2",
4635};
4636
4637static const char * const usb2_ch3_groups[] = {
4638 "usb2_ch3",
4639};
4640
5ec8a41a
TK		 4641static const char * const usb30_groups[] = {
4642 "usb30",
4643};
4644
0b0ffc96 4645static const struct sh_pfc_function pinmux_functions[] = {
55bfea9f 4646 SH_PFC_FUNCTION(audio_clk),
30c078de 4647 SH_PFC_FUNCTION(avb),
a678abfe
RS		 4648 SH_PFC_FUNCTION(can0),
4649 SH_PFC_FUNCTION(can1),
4650 SH_PFC_FUNCTION(can_clk),
0e1c7a94
RS		 4651 SH_PFC_FUNCTION(canfd0),
4652 SH_PFC_FUNCTION(canfd1),
641b0ab8
DB		 4653 SH_PFC_FUNCTION(drif0),
4654 SH_PFC_FUNCTION(drif1),
4655 SH_PFC_FUNCTION(drif2),
4656 SH_PFC_FUNCTION(drif3),
a20a6585 4657 SH_PFC_FUNCTION(du),
7a362e34
WS		 4658 SH_PFC_FUNCTION(hscif0),
4659 SH_PFC_FUNCTION(hscif1),
4660 SH_PFC_FUNCTION(hscif2),
4661 SH_PFC_FUNCTION(hscif3),
4662 SH_PFC_FUNCTION(hscif4),
f62d4c9e
WS		 4663 SH_PFC_FUNCTION(i2c1),
4664 SH_PFC_FUNCTION(i2c2),
4665 SH_PFC_FUNCTION(i2c6),
8480e6ca 4666 SH_PFC_FUNCTION(intc_ex),
3e6c7727
GU		 4667 SH_PFC_FUNCTION(msiof0),
4668 SH_PFC_FUNCTION(msiof1),
4669 SH_PFC_FUNCTION(msiof2),
4670 SH_PFC_FUNCTION(msiof3),
c03a133b
LP		 4671 SH_PFC_FUNCTION(pwm0),
4672 SH_PFC_FUNCTION(pwm1),
4673 SH_PFC_FUNCTION(pwm2),
4674 SH_PFC_FUNCTION(pwm3),
4675 SH_PFC_FUNCTION(pwm4),
4676 SH_PFC_FUNCTION(pwm5),
4677 SH_PFC_FUNCTION(pwm6),
e7ad4d3c
GU		 4678 SH_PFC_FUNCTION(scif0),
4679 SH_PFC_FUNCTION(scif1),
4680 SH_PFC_FUNCTION(scif2),
4681 SH_PFC_FUNCTION(scif3),
4682 SH_PFC_FUNCTION(scif4),
4683 SH_PFC_FUNCTION(scif5),
d14a39ed 4684 SH_PFC_FUNCTION(scif_clk),
9ed13958
TK		 4685 SH_PFC_FUNCTION(sdhi0),
4686 SH_PFC_FUNCTION(sdhi1),
4687 SH_PFC_FUNCTION(sdhi2),
4688 SH_PFC_FUNCTION(sdhi3),
0526234d 4689 SH_PFC_FUNCTION(ssi),
933ddbe5
YS		 4690 SH_PFC_FUNCTION(usb0),
4691 SH_PFC_FUNCTION(usb1),
4692 SH_PFC_FUNCTION(usb2),
4693 SH_PFC_FUNCTION(usb2_ch3),
5ec8a41a 4694 SH_PFC_FUNCTION(usb30),
0b0ffc96
TK		 4695};
4696
4697static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4698#define F_(x, y) FN_##y
4699#define FM(x) FN_##x
4700 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4701 0, 0,
4702 0, 0,
4703 0, 0,
4704 0, 0,
4705 0, 0,
4706 0, 0,
4707 0, 0,
4708 0, 0,
4709 0, 0,
4710 0, 0,
4711 0, 0,
4712 0, 0,
4713 0, 0,
4714 0, 0,
4715 0, 0,
4716 0, 0,
4717 GP_0_15_FN, GPSR0_15,
4718 GP_0_14_FN, GPSR0_14,
4719 GP_0_13_FN, GPSR0_13,
4720 GP_0_12_FN, GPSR0_12,
4721 GP_0_11_FN, GPSR0_11,
4722 GP_0_10_FN, GPSR0_10,
4723 GP_0_9_FN, GPSR0_9,
4724 GP_0_8_FN, GPSR0_8,
4725 GP_0_7_FN, GPSR0_7,
4726 GP_0_6_FN, GPSR0_6,
4727 GP_0_5_FN, GPSR0_5,
4728 GP_0_4_FN, GPSR0_4,
4729 GP_0_3_FN, GPSR0_3,
4730 GP_0_2_FN, GPSR0_2,
4731 GP_0_1_FN, GPSR0_1,
4732 GP_0_0_FN, GPSR0_0, }
4733 },
4734 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4735 0, 0,
4736 0, 0,
4737 0, 0,
82d2de5a 4738 GP_1_28_FN, GPSR1_28,
0b0ffc96
TK		 4739 GP_1_27_FN, GPSR1_27,
4740 GP_1_26_FN, GPSR1_26,
4741 GP_1_25_FN, GPSR1_25,
4742 GP_1_24_FN, GPSR1_24,
4743 GP_1_23_FN, GPSR1_23,
4744 GP_1_22_FN, GPSR1_22,
4745 GP_1_21_FN, GPSR1_21,
4746 GP_1_20_FN, GPSR1_20,
4747 GP_1_19_FN, GPSR1_19,
4748 GP_1_18_FN, GPSR1_18,
4749 GP_1_17_FN, GPSR1_17,
4750 GP_1_16_FN, GPSR1_16,
4751 GP_1_15_FN, GPSR1_15,
4752 GP_1_14_FN, GPSR1_14,
4753 GP_1_13_FN, GPSR1_13,
4754 GP_1_12_FN, GPSR1_12,
4755 GP_1_11_FN, GPSR1_11,
4756 GP_1_10_FN, GPSR1_10,
4757 GP_1_9_FN, GPSR1_9,
4758 GP_1_8_FN, GPSR1_8,
4759 GP_1_7_FN, GPSR1_7,
4760 GP_1_6_FN, GPSR1_6,
4761 GP_1_5_FN, GPSR1_5,
4762 GP_1_4_FN, GPSR1_4,
4763 GP_1_3_FN, GPSR1_3,
4764 GP_1_2_FN, GPSR1_2,
4765 GP_1_1_FN, GPSR1_1,
4766 GP_1_0_FN, GPSR1_0, }
4767 },
4768 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4769 0, 0,
4770 0, 0,
4771 0, 0,
4772 0, 0,
4773 0, 0,
4774 0, 0,
4775 0, 0,
4776 0, 0,
4777 0, 0,
4778 0, 0,
4779 0, 0,
4780 0, 0,
4781 0, 0,
4782 0, 0,
4783 0, 0,
4784 0, 0,
4785 0, 0,
4786 GP_2_14_FN, GPSR2_14,
4787 GP_2_13_FN, GPSR2_13,
4788 GP_2_12_FN, GPSR2_12,
4789 GP_2_11_FN, GPSR2_11,
4790 GP_2_10_FN, GPSR2_10,
4791 GP_2_9_FN, GPSR2_9,
4792 GP_2_8_FN, GPSR2_8,
4793 GP_2_7_FN, GPSR2_7,
4794 GP_2_6_FN, GPSR2_6,
4795 GP_2_5_FN, GPSR2_5,
4796 GP_2_4_FN, GPSR2_4,
4797 GP_2_3_FN, GPSR2_3,
4798 GP_2_2_FN, GPSR2_2,
4799 GP_2_1_FN, GPSR2_1,
4800 GP_2_0_FN, GPSR2_0, }
4801 },
4802 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4803 0, 0,
4804 0, 0,
4805 0, 0,
4806 0, 0,
4807 0, 0,
4808 0, 0,
4809 0, 0,
4810 0, 0,
4811 0, 0,
4812 0, 0,
4813 0, 0,
4814 0, 0,
4815 0, 0,
4816 0, 0,
4817 0, 0,
4818 0, 0,
4819 GP_3_15_FN, GPSR3_15,
4820 GP_3_14_FN, GPSR3_14,
4821 GP_3_13_FN, GPSR3_13,
4822 GP_3_12_FN, GPSR3_12,
4823 GP_3_11_FN, GPSR3_11,
4824 GP_3_10_FN, GPSR3_10,
4825 GP_3_9_FN, GPSR3_9,
4826 GP_3_8_FN, GPSR3_8,
4827 GP_3_7_FN, GPSR3_7,
4828 GP_3_6_FN, GPSR3_6,
4829 GP_3_5_FN, GPSR3_5,
4830 GP_3_4_FN, GPSR3_4,
4831 GP_3_3_FN, GPSR3_3,
4832 GP_3_2_FN, GPSR3_2,
4833 GP_3_1_FN, GPSR3_1,
4834 GP_3_0_FN, GPSR3_0, }
4835 },
4836 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4837 0, 0,
4838 0, 0,
4839 0, 0,
4840 0, 0,
4841 0, 0,
4842 0, 0,
4843 0, 0,
4844 0, 0,
4845 0, 0,
4846 0, 0,
4847 0, 0,
4848 0, 0,
4849 0, 0,
4850 0, 0,
4851 GP_4_17_FN, GPSR4_17,
4852 GP_4_16_FN, GPSR4_16,
4853 GP_4_15_FN, GPSR4_15,
4854 GP_4_14_FN, GPSR4_14,
4855 GP_4_13_FN, GPSR4_13,
4856 GP_4_12_FN, GPSR4_12,
4857 GP_4_11_FN, GPSR4_11,
4858 GP_4_10_FN, GPSR4_10,
4859 GP_4_9_FN, GPSR4_9,
4860 GP_4_8_FN, GPSR4_8,
4861 GP_4_7_FN, GPSR4_7,
4862 GP_4_6_FN, GPSR4_6,
4863 GP_4_5_FN, GPSR4_5,
4864 GP_4_4_FN, GPSR4_4,
4865 GP_4_3_FN, GPSR4_3,
4866 GP_4_2_FN, GPSR4_2,
4867 GP_4_1_FN, GPSR4_1,
4868 GP_4_0_FN, GPSR4_0, }
4869 },
4870 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4871 0, 0,
4872 0, 0,
4873 0, 0,
4874 0, 0,
4875 0, 0,
4876 0, 0,
4877 GP_5_25_FN, GPSR5_25,
4878 GP_5_24_FN, GPSR5_24,
4879 GP_5_23_FN, GPSR5_23,
4880 GP_5_22_FN, GPSR5_22,
4881 GP_5_21_FN, GPSR5_21,
4882 GP_5_20_FN, GPSR5_20,
4883 GP_5_19_FN, GPSR5_19,
4884 GP_5_18_FN, GPSR5_18,
4885 GP_5_17_FN, GPSR5_17,
4886 GP_5_16_FN, GPSR5_16,
4887 GP_5_15_FN, GPSR5_15,
4888 GP_5_14_FN, GPSR5_14,
4889 GP_5_13_FN, GPSR5_13,
4890 GP_5_12_FN, GPSR5_12,
4891 GP_5_11_FN, GPSR5_11,
4892 GP_5_10_FN, GPSR5_10,
4893 GP_5_9_FN, GPSR5_9,
4894 GP_5_8_FN, GPSR5_8,
4895 GP_5_7_FN, GPSR5_7,
4896 GP_5_6_FN, GPSR5_6,
4897 GP_5_5_FN, GPSR5_5,
4898 GP_5_4_FN, GPSR5_4,
4899 GP_5_3_FN, GPSR5_3,
4900 GP_5_2_FN, GPSR5_2,
4901 GP_5_1_FN, GPSR5_1,
4902 GP_5_0_FN, GPSR5_0, }
4903 },
4904 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4905 GP_6_31_FN, GPSR6_31,
4906 GP_6_30_FN, GPSR6_30,
4907 GP_6_29_FN, GPSR6_29,
4908 GP_6_28_FN, GPSR6_28,
4909 GP_6_27_FN, GPSR6_27,
4910 GP_6_26_FN, GPSR6_26,
4911 GP_6_25_FN, GPSR6_25,
4912 GP_6_24_FN, GPSR6_24,
4913 GP_6_23_FN, GPSR6_23,
4914 GP_6_22_FN, GPSR6_22,
4915 GP_6_21_FN, GPSR6_21,
4916 GP_6_20_FN, GPSR6_20,
4917 GP_6_19_FN, GPSR6_19,
4918 GP_6_18_FN, GPSR6_18,
4919 GP_6_17_FN, GPSR6_17,
4920 GP_6_16_FN, GPSR6_16,
4921 GP_6_15_FN, GPSR6_15,
4922 GP_6_14_FN, GPSR6_14,
4923 GP_6_13_FN, GPSR6_13,
4924 GP_6_12_FN, GPSR6_12,
4925 GP_6_11_FN, GPSR6_11,
4926 GP_6_10_FN, GPSR6_10,
4927 GP_6_9_FN, GPSR6_9,
4928 GP_6_8_FN, GPSR6_8,
4929 GP_6_7_FN, GPSR6_7,
4930 GP_6_6_FN, GPSR6_6,
4931 GP_6_5_FN, GPSR6_5,
4932 GP_6_4_FN, GPSR6_4,
4933 GP_6_3_FN, GPSR6_3,
4934 GP_6_2_FN, GPSR6_2,
4935 GP_6_1_FN, GPSR6_1,
4936 GP_6_0_FN, GPSR6_0, }
4937 },
4938 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4939 0, 0,
4940 0, 0,
4941 0, 0,
4942 0, 0,
4943 0, 0,
4944 0, 0,
4945 0, 0,
4946 0, 0,
4947 0, 0,
4948 0, 0,
4949 0, 0,
4950 0, 0,
4951 0, 0,
4952 0, 0,
4953 0, 0,
4954 0, 0,
4955 0, 0,
4956 0, 0,
4957 0, 0,
4958 0, 0,
4959 0, 0,
4960 0, 0,
4961 0, 0,
4962 0, 0,
4963 0, 0,
4964 0, 0,
4965 0, 0,
4966 0, 0,
4967 GP_7_3_FN, GPSR7_3,
4968 GP_7_2_FN, GPSR7_2,
4969 GP_7_1_FN, GPSR7_1,
4970 GP_7_0_FN, GPSR7_0, }
4971 },
4972#undef F_
4973#undef FM
4974
4975#define F_(x, y) x,
4976#define FM(x) FN_##x,
4977 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4978 IP0_31_28
4979 IP0_27_24
4980 IP0_23_20
4981 IP0_19_16
4982 IP0_15_12
4983 IP0_11_8
4984 IP0_7_4
4985 IP0_3_0 }
4986 },
4987 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4988 IP1_31_28
4989 IP1_27_24
4990 IP1_23_20
4991 IP1_19_16
4992 IP1_15_12
4993 IP1_11_8
4994 IP1_7_4
4995 IP1_3_0 }
4996 },
4997 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4998 IP2_31_28
4999 IP2_27_24
5000 IP2_23_20
5001 IP2_19_16
5002 IP2_15_12
5003 IP2_11_8
5004 IP2_7_4
5005 IP2_3_0 }
5006 },
5007 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5008 IP3_31_28
5009 IP3_27_24
5010 IP3_23_20
5011 IP3_19_16
5012 IP3_15_12
5013 IP3_11_8
5014 IP3_7_4
5015 IP3_3_0 }
5016 },
5017 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5018 IP4_31_28
5019 IP4_27_24
5020 IP4_23_20
5021 IP4_19_16
5022 IP4_15_12
5023 IP4_11_8
5024 IP4_7_4
5025 IP4_3_0 }
5026 },
5027 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5028 IP5_31_28
5029 IP5_27_24
5030 IP5_23_20
5031 IP5_19_16
5032 IP5_15_12
5033 IP5_11_8
5034 IP5_7_4
5035 IP5_3_0 }
5036 },
5037 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5038 IP6_31_28
5039 IP6_27_24
5040 IP6_23_20
5041 IP6_19_16
5042 IP6_15_12
5043 IP6_11_8
5044 IP6_7_4
5045 IP6_3_0 }
5046 },
5047 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5048 IP7_31_28
5049 IP7_27_24
5050 IP7_23_20
5051 IP7_19_16
30cd1c46 5052 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5053 IP7_11_8
5054 IP7_7_4
5055 IP7_3_0 }
5056 },
5057 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5058 IP8_31_28
5059 IP8_27_24
5060 IP8_23_20
5061 IP8_19_16
5062 IP8_15_12
5063 IP8_11_8
5064 IP8_7_4
5065 IP8_3_0 }
5066 },
5067 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5068 IP9_31_28
5069 IP9_27_24
5070 IP9_23_20
5071 IP9_19_16
5072 IP9_15_12
5073 IP9_11_8
5074 IP9_7_4
5075 IP9_3_0 }
5076 },
5077 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5078 IP10_31_28
5079 IP10_27_24
5080 IP10_23_20
5081 IP10_19_16
5082 IP10_15_12
5083 IP10_11_8
5084 IP10_7_4
5085 IP10_3_0 }
5086 },
5087 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5088 IP11_31_28
5089 IP11_27_24
5090 IP11_23_20
5091 IP11_19_16
5092 IP11_15_12
5093 IP11_11_8
5094 IP11_7_4
5095 IP11_3_0 }
5096 },
5097 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5098 IP12_31_28
5099 IP12_27_24
5100 IP12_23_20
5101 IP12_19_16
5102 IP12_15_12
5103 IP12_11_8
5104 IP12_7_4
5105 IP12_3_0 }
5106 },
5107 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5108 IP13_31_28
5109 IP13_27_24
5110 IP13_23_20
5111 IP13_19_16
5112 IP13_15_12
5113 IP13_11_8
5114 IP13_7_4
5115 IP13_3_0 }
5116 },
5117 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5118 IP14_31_28
5119 IP14_27_24
5120 IP14_23_20
5121 IP14_19_16
5122 IP14_15_12
5123 IP14_11_8
5124 IP14_7_4
5125 IP14_3_0 }
5126 },
5127 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5128 IP15_31_28
5129 IP15_27_24
5130 IP15_23_20
5131 IP15_19_16
5132 IP15_15_12
5133 IP15_11_8
5134 IP15_7_4
5135 IP15_3_0 }
5136 },
5137 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5138 IP16_31_28
5139 IP16_27_24
5140 IP16_23_20
5141 IP16_19_16
5142 IP16_15_12
5143 IP16_11_8
5144 IP16_7_4
5145 IP16_3_0 }
5146 },
5147 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
b205914c
GU		 5148 IP17_31_28
5149 IP17_27_24
5150 IP17_23_20
5151 IP17_19_16
5152 IP17_15_12
5153 IP17_11_8
0b0ffc96
TK		 5154 IP17_7_4
5155 IP17_3_0 }
5156 },
b205914c
GU		 5157 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5158 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5159 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5160 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5161 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5162 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5163 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5164 IP18_7_4
5165 IP18_3_0 }
5166 },
0b0ffc96
TK		 5167#undef F_
5168#undef FM
5169
5170#define F_(x, y) x,
5171#define FM(x) FN_##x,
5172 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
b205914c
GU		 5173 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5174 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5175 MOD_SEL0_31_30_29
0b0ffc96
TK		 5176 MOD_SEL0_28_27
5177 MOD_SEL0_26_25_24
5178 MOD_SEL0_23
5179 MOD_SEL0_22
b205914c
GU		 5180 MOD_SEL0_21
5181 MOD_SEL0_20
0b0ffc96 5182 MOD_SEL0_19
b205914c
GU		 5183 MOD_SEL0_18_17
5184 MOD_SEL0_16
5185 0, 0, /* RESERVED 15 */
5186 MOD_SEL0_14_13
0b0ffc96
TK		 5187 MOD_SEL0_12
5188 MOD_SEL0_11
5189 MOD_SEL0_10
b205914c 5190 MOD_SEL0_9_8
0b0ffc96 5191 MOD_SEL0_7_6
b205914c
GU		 5192 MOD_SEL0_5
5193 MOD_SEL0_4_3
5194 /* RESERVED 2, 1, 0 */
5195 0, 0, 0, 0, 0, 0, 0, 0 }
0b0ffc96
TK		 5196 },
5197 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5198 2, 3, 1, 2, 3, 1, 1, 2, 1,
5199 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5200 MOD_SEL1_31_30
5201 MOD_SEL1_29_28_27
5202 MOD_SEL1_26
5203 MOD_SEL1_25_24
5204 MOD_SEL1_23_22_21
5205 MOD_SEL1_20
5206 MOD_SEL1_19
5207 MOD_SEL1_18_17
5208 MOD_SEL1_16
5209 MOD_SEL1_15_14
5210 MOD_SEL1_13
5211 MOD_SEL1_12
5212 MOD_SEL1_11
5213 MOD_SEL1_10
5214 MOD_SEL1_9
5215 0, 0, 0, 0, /* RESERVED 8, 7 */
5216 MOD_SEL1_6
5217 MOD_SEL1_5
5218 MOD_SEL1_4
5219 MOD_SEL1_3
5220 MOD_SEL1_2
5221 MOD_SEL1_1
5222 MOD_SEL1_0 }
5223 },
5224 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
b205914c
GU		 5225 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5226 4, 4, 4, 3, 1) {
0b0ffc96
TK		 5227 MOD_SEL2_31
5228 MOD_SEL2_30
5229 MOD_SEL2_29
b205914c
GU		 5230 MOD_SEL2_28_27
5231 MOD_SEL2_26
5232 MOD_SEL2_25_24_23
3c612d2c
TK		 5233 /* RESERVED 22 */
5234 0, 0,
b205914c
GU		 5235 MOD_SEL2_21
5236 MOD_SEL2_20
5237 MOD_SEL2_19
5238 MOD_SEL2_18
5239 MOD_SEL2_17
5240 /* RESERVED 16 */
0b0ffc96 5241 0, 0,
0b0ffc96
TK		 5242 /* RESERVED 15, 14, 13, 12 */
5243 0, 0, 0, 0, 0, 0, 0, 0,
5244 0, 0, 0, 0, 0, 0, 0, 0,
5245 /* RESERVED 11, 10, 9, 8 */
5246 0, 0, 0, 0, 0, 0, 0, 0,
5247 0, 0, 0, 0, 0, 0, 0, 0,
5248 /* RESERVED 7, 6, 5, 4 */
5249 0, 0, 0, 0, 0, 0, 0, 0,
5250 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 5251 /* RESERVED 3, 2, 1 */
5252 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5253 MOD_SEL2_0 }
5254 },
5255 { },
5256};
5257
92e6d9a2 5258static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 5259 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5260 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5261 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5262 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5263 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5264 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5265 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5266 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5267 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5268 } },
5269 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5270 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5271 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5272 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5273 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5274 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5275 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5276 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5277 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5278 } },
5279 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5280 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5281 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5282 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5283 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5284 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5285 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5286 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5287 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5288 } },
92e6d9a2 5289 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 5290 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5291 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5292 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5293 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5294 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5295 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5296 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5297 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 5298 } },
5299 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5300 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5301 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5302 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5303 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5304 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5305 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5306 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5307 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5308 } },
5309 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5310 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5311 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5312 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5313 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5314 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5315 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5316 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5317 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5318 } },
5319 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5320 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5321 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5322 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5323 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5324 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5325 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5326 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5327 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5328 } },
5329 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5330 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5331 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5332 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5333 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5334 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5335 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5336 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5337 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5338 } },
5339 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
82d2de5a 5340 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 5341 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5342 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5343 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5344 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5345 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5346 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5347 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5348 } },
5349 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5350 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 5351 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 5352 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5353 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5354 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5355 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5356 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5357 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5358 } },
5359 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5360 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5361 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5362 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5363 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5364 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5365 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5366 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5367 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5368 } },
5369 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 5370 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5371 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5372 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5373 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5374 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5375 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5376 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5377 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5378 } },
5379 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5380 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5381 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5382 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5383 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 5384 } },
5385 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 5386 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5387 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5388 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5389 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5390 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5391 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5392 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5393 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 5394 } },
5395 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5396 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5397 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5398 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5399 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5400 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5401 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5402 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5403 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5404 } },
5405 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5406 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5407 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5408 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5409 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5410 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5411 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5412 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5413 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5414 } },
5415 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5416 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5417 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5418 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5419 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5420 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5421 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5422 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5423 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5424 } },
5425 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5426 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5427 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5428 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5429 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5430 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5431 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5432 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5433 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5434 } },
5435 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5436 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5437 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5438 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5439 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5440 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5441 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5442 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5443 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5444 } },
5445 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5446 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5447 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5448 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5449 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5450 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5451 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5452 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5453 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5454 } },
5455 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5456 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5457 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5458 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5459 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5460 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5461 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 5462 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 5463 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5464 } },
5465 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5466 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5467 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5468 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5469 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 5470 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5471 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 5472 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5473 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5474 } },
5475 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5476 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5477 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5478 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5479 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5480 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5481 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5482 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5483 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5484 } },
5485 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5486 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5487 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5488 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5489 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5490 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5491 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5492 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5493 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5494 } },
5495 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5496 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5497 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5498 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5499 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5500 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
f9d13080
YS		 5501 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5502 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
92e6d9a2
LP		 5503 } },
5504 { },
5505};
5506
e2aad846
GU		 5507enum ioctrl_regs {
5508 POCCTRL,
5509};
5510
5511static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5512 [POCCTRL] = { 0xe6060380, },
5513 { /* sentinel */ },
5514};
5515
e9eace32
WS		 5516static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5517{
5518 int bit = -EINVAL;
5519
e2aad846 5520 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
e9eace32
WS		 5521
5522 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5523 bit = pin & 0x1f;
5524
5525 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5526 bit = (pin & 0x1f) + 12;
5527
5528 return bit;
5529}
5530
6f4b74f3
GU		 5531static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5532 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5533 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5534 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5535 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5536 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5537 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5538 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5539 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5540 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5541 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5542 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5543 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5544 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5545 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5546 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5547 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5548 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5549 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5550 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5551 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5552 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5553 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5554 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5555 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5556 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5557 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5558 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5559 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5560 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5561 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5562 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5563 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5564 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5565 } },
5566 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5567 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5568 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5569 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5570 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5571 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5572 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5573 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5574 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5575 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5576 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5577 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5578 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5579 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5580 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5581 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5582 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5583 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5584 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5585 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5586 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5587 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5588 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5589 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5590 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5591 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5592 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5593 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5594 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5595 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5596 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5597 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5598 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5599 } },
5600 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
82d2de5a 5601 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6f4b74f3
GU		 5602 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5603 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5604 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5605 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5606 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5607 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5608 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5609 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5610 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5611 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5612 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5613 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5614 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5615 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5616 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5617 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5618 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5619 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5620 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5621 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5622 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5623 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5624 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5625 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5626 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5627 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5628 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5629 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5630 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
5631 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5632 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5633 } },
5634 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5635 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
5636 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
5637 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
5638 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5639 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5640 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5641 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5642 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5643 [ 8] = PIN_NONE,
5644 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5645 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5646 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5647 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5648 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5649 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5650 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5651 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5652 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5653 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5654 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5655 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5656 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5657 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5658 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5659 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5660 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5661 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5662 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5663 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5664 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5665 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5666 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5667 } },
5668 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5669 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5670 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5671 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5672 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5673 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5674 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5675 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5676 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5677 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5678 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5679 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5680 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5681 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5682 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5683 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5684 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5685 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
5686 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5687 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5688 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5689 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
5690 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5691 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5692 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5693 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5694 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5695 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5696 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5697 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5698 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5699 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5700 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5701 } },
5702 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5703 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5704 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5705 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5706 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5707 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5708 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5709 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5710 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5711 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5712 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5713 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5714 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5715 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5716 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5717 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5718 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5719 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5720 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5721 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5722 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5723 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5724 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5725 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5726 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5727 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5728 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5729 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5730 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5731 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5732 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5733 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5734 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5735 } },
5736 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5737 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5738 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5739 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5740 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5741 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5742 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
5743 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
5744 [ 7] = PIN_NONE,
5745 [ 8] = PIN_NONE,
5746 [ 9] = PIN_NONE,
5747 [10] = PIN_NONE,
5748 [11] = PIN_NONE,
5749 [12] = PIN_NONE,
5750 [13] = PIN_NONE,
5751 [14] = PIN_NONE,
5752 [15] = PIN_NONE,
5753 [16] = PIN_NONE,
5754 [17] = PIN_NONE,
5755 [18] = PIN_NONE,
5756 [19] = PIN_NONE,
5757 [20] = PIN_NONE,
5758 [21] = PIN_NONE,
5759 [22] = PIN_NONE,
5760 [23] = PIN_NONE,
5761 [24] = PIN_NONE,
5762 [25] = PIN_NONE,
5763 [26] = PIN_NONE,
5764 [27] = PIN_NONE,
5765 [28] = PIN_NONE,
5766 [29] = PIN_NONE,
5767 [30] = PIN_NONE,
5768 [31] = PIN_NONE,
5769 } },
5770 { /* sentinel */ },
56065524
UH		 5771};
5772
5773static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5774 unsigned int pin)
5775{
6f4b74f3
GU		 5776 const struct pinmux_bias_reg *reg;
5777 unsigned int bit;
56065524 5778
6f4b74f3
GU		 5779 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5780 if (!reg)
56065524
UH		 5781 return PIN_CONFIG_BIAS_DISABLE;
5782
6f4b74f3 5783 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
56065524 5784 return PIN_CONFIG_BIAS_DISABLE;
6f4b74f3 5785 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
42831cf9
NS		 5786 return PIN_CONFIG_BIAS_PULL_UP;
5787 else
5788 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 5789}
5790
5791static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5792 unsigned int bias)
5793{
6f4b74f3 5794 const struct pinmux_bias_reg *reg;
56065524 5795 u32 enable, updown;
6f4b74f3 5796 unsigned int bit;
56065524 5797
6f4b74f3
GU		 5798 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5799 if (!reg)
56065524
UH		 5800 return;
5801
6f4b74f3 5802 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
56065524 5803 if (bias != PIN_CONFIG_BIAS_DISABLE)
6f4b74f3 5804 enable |= BIT(bit);
56065524 5805
6f4b74f3 5806 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
56065524 5807 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6f4b74f3 5808 updown |= BIT(bit);
56065524 5809
6f4b74f3
GU		 5810 sh_pfc_write(pfc, reg->pud, updown);
5811 sh_pfc_write(pfc, reg->puen, enable);
56065524
UH		 5812}
5813
b205914c
GU		 5814static const struct soc_device_attribute r8a7795es1[] = {
5815 { .soc_id = "r8a7795", .revision = "ES1.*" },
5816 { /* sentinel */ }
5817};
5818
5819static int r8a7795_pinmux_init(struct sh_pfc *pfc)
5820{
5821 if (soc_device_match(r8a7795es1))
5822 pfc->info = &r8a7795es1_pinmux_info;
5823
5824 return 0;
5825}
5826
e9eace32 5827static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 5828 .init = r8a7795_pinmux_init,
e9eace32 5829 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 5830 .get_bias = r8a7795_pinmux_get_bias,
5831 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 5832};
5833
0b0ffc96 5834const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 5835 .name = "r8a77951_pfc",
e9eace32 5836 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 5837 .unlock_reg = 0xe6060000, /* PMMR */
5838
5839 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5840
5841 .pins = pinmux_pins,
5842 .nr_pins = ARRAY_SIZE(pinmux_pins),
5843 .groups = pinmux_groups,
5844 .nr_groups = ARRAY_SIZE(pinmux_groups),
5845 .functions = pinmux_functions,
5846 .nr_functions = ARRAY_SIZE(pinmux_functions),
5847
5848 .cfg_regs = pinmux_config_regs,
92e6d9a2 5849 .drive_regs = pinmux_drive_regs,
6f4b74f3 5850 .bias_regs = pinmux_bias_regs,
e2aad846 5851 .ioctrl_regs = pinmux_ioctrl_regs,
0b0ffc96 5852
b8b47d67
GU		 5853 .pinmux_data = pinmux_data,
5854 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 5855};
Linux 6.x block layer and io_uring tree(s)