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pinctrl: sh-pfc: r8a7795: Add SDHI0-3 support
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
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0b0ffc96 1/*
b205914c 2 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 3 *
b205914c 4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
0b0ffc96
TK		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
b205914c 12#include <linux/sys_soc.h>
0b0ffc96
TK		 13
14#include "core.h"
15#include "sh_pfc.h"
16
56065524
UH		 17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
0b0ffc96 21#define CPU_ALL_PORT(fn, sfx) \
56065524
UH		 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
fc8fd9be 64#define GPSR1_21 F_(CS1_N, IP4_19_16)
0b0ffc96
TK		 65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
b205914c
GU		 105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
b205914c
GU		 123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
b205914c
GU		 143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 146#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 148#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 151#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
160#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
164#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 169
170/* GPSR6 */
f9d13080
YS		 171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
b205914c
GU		 173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 203
204/* GPSR7 */
205#define GPSR7_3 FM(HDMI1_CEC)
206#define GPSR7_2 FM(HDMI0_CEC)
207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96 217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
e2ab1770
TK		 218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
fc8fd9be 250#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 273#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 282#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 287#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 305#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 306
307/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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GU		 308#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
337/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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KM		 341#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 343#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
bad7cc19
TK		 363#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
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TK		 365
366#define PINMUX_GPSR \
367\
368 GPSR6_31 \
369 GPSR6_30 \
370 GPSR6_29 \
371 GPSR6_28 \
372 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
400
401#define PINMUX_IPSR \
402\
403FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
411\
412FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
30cd1c46 415FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
0b0ffc96
TK		 416FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
420\
421FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
429\
430FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
438\
b205914c
GU		 439FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 447
448/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 449#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 450#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 454#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
466#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 467
468/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
ae03c4ec 471#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
0b0ffc96
TK		 472#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
474#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
475#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
eada11ac 482#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
0b0ffc96
TK		 483#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
491
492/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 496#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 499#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
502#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
503#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 504#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
505
b205914c 506#define PINMUX_MOD_SELS \
0b0ffc96 507\
b205914c
GU		 508MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
509 MOD_SEL2_30 \
0b0ffc96 510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 511MOD_SEL0_28_27 MOD_SEL2_28_27 \
512MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 514MOD_SEL0_23 MOD_SEL1_23_22_21 \
3c612d2c 515MOD_SEL0_22 \
b205914c
GU		 516MOD_SEL0_21 MOD_SEL2_21 \
517MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
520 MOD_SEL2_17 \
521MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 522 MOD_SEL1_15_14 \
b205914c
GU		 523MOD_SEL0_14_13 \
524 MOD_SEL1_13 \
0b0ffc96
TK		 525MOD_SEL0_12 MOD_SEL1_12 \
526MOD_SEL0_11 MOD_SEL1_11 \
527MOD_SEL0_10 MOD_SEL1_10 \
b205914c 528MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 529MOD_SEL0_7_6 \
530 MOD_SEL1_6 \
b205914c
GU		 531MOD_SEL0_5 MOD_SEL1_5 \
532MOD_SEL0_4_3 MOD_SEL1_4 \
533 MOD_SEL1_3 \
534 MOD_SEL1_2 \
0b0ffc96
TK		 535 MOD_SEL1_1 \
536 MOD_SEL1_0 MOD_SEL2_0
537
ea9c7405
NS		 538/*
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
541 */
542#define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
551 FM(CLKOUT) FM(PRESETOUT) \
552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96
TK		 554
555enum {
556 PINMUX_RESERVED = 0,
557
558 PINMUX_DATA_BEGIN,
559 GP_ALL(DATA),
560 PINMUX_DATA_END,
561
562#define F_(x, y)
563#define FM(x) FN_##x,
564 PINMUX_FUNCTION_BEGIN,
565 GP_ALL(FN),
566 PINMUX_GPSR
567 PINMUX_IPSR
568 PINMUX_MOD_SELS
569 PINMUX_FUNCTION_END,
570#undef F_
571#undef FM
572
573#define F_(x, y)
574#define FM(x) x##_MARK,
575 PINMUX_MARK_BEGIN,
576 PINMUX_GPSR
577 PINMUX_IPSR
578 PINMUX_MOD_SELS
ea9c7405 579 PINMUX_STATIC
0b0ffc96
TK		 580 PINMUX_MARK_END,
581#undef F_
582#undef FM
583};
584
585static const u16 pinmux_data[] = {
586 PINMUX_DATA_GP_ALL(),
587
8d4df573
GU		 588 PINMUX_SINGLE(AVS1),
589 PINMUX_SINGLE(AVS2),
590 PINMUX_SINGLE(HDMI0_CEC),
591 PINMUX_SINGLE(HDMI1_CEC),
d07640f5
KM		 592 PINMUX_SINGLE(I2C_SEL_0_1),
593 PINMUX_SINGLE(I2C_SEL_3_1),
594 PINMUX_SINGLE(I2C_SEL_5_1),
8d4df573
GU		 595 PINMUX_SINGLE(MSIOF0_RXD),
596 PINMUX_SINGLE(MSIOF0_SCK),
597 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 598 PINMUX_SINGLE(SSI_SCK5),
599 PINMUX_SINGLE(SSI_SDATA5),
600 PINMUX_SINGLE(SSI_WS5),
601
0b0ffc96 602 /* IPSR0 */
e01678e3 603 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 604 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
605
e01678e3 606 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 607 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
609
e01678e3 610 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 611 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
613
e01678e3 614 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 615 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
617
618 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
619 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
620 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
b205914c 621 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
0b0ffc96
TK		 622
623 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
626
e01678e3
GU		 627 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
628 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
629 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 630 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
631 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
632 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 633 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 634
e01678e3
GU		 635 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
636 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
637 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 638 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
639 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 641 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 642
643 /* IPSR1 */
e01678e3
GU		 644 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
645 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
646 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 647 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
648 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 649 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 650
e01678e3
GU		 651 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
652 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
653 PINMUX_IPSR_GPSR(IP1_7_4, A25),
654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 657 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 658
e01678e3
GU		 659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
661 PINMUX_IPSR_GPSR(IP1_11_8, A24),
662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 665 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 666
e01678e3
GU		 667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
669 PINMUX_IPSR_GPSR(IP1_15_12, A23),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 675
e01678e3
GU		 676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 679 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
680 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
681
682 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 683 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 684 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
685 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
687
688 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 689 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 690 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
691 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
692
e01678e3
GU		 693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
694 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 695 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 696 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
697 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 698 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
699
700 /* IPSR2 */
e01678e3
GU		 701 PINMUX_IPSR_GPSR(IP2_3_0, A1),
702 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 703 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 704 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
705 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 706 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
707
e01678e3
GU		 708 PINMUX_IPSR_GPSR(IP2_7_4, A2),
709 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 710 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 711 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
712 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 713 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
714
e01678e3
GU		 715 PINMUX_IPSR_GPSR(IP2_11_8, A3),
716 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 717 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 718 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
719 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 720 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
721
e01678e3
GU		 722 PINMUX_IPSR_GPSR(IP2_15_12, A4),
723 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 724 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 725 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
727 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 728
e01678e3
GU		 729 PINMUX_IPSR_GPSR(IP2_19_16, A5),
730 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 731 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 733 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
735 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 736
e01678e3
GU		 737 PINMUX_IPSR_GPSR(IP2_23_20, A6),
738 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 739 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 741 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
743 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 744
e01678e3
GU		 745 PINMUX_IPSR_GPSR(IP2_27_24, A7),
746 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 747 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 749 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
751 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 752
e01678e3 753 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 754 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
760
761 /* IPSR3 */
e01678e3 762 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 763 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 765 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 766
e01678e3 767 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 771
e01678e3 772 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 773 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 776 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
777 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 778 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
781
e01678e3
GU		 782 PINMUX_IPSR_GPSR(IP3_15_12, A12),
783 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 784 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
785 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 786 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
787 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 788
e01678e3
GU		 789 PINMUX_IPSR_GPSR(IP3_19_16, A13),
790 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 791 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
792 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 793 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
794 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 795
e01678e3
GU		 796 PINMUX_IPSR_GPSR(IP3_23_20, A14),
797 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 798 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 799 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
800 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
801 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 802
e01678e3
GU		 803 PINMUX_IPSR_GPSR(IP3_27_24, A15),
804 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 805 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 806 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
807 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
808 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 809
e01678e3
GU		 810 PINMUX_IPSR_GPSR(IP3_31_28, A16),
811 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
812 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
813 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 814
815 /* IPSR4 */
e01678e3
GU		 816 PINMUX_IPSR_GPSR(IP4_3_0, A17),
817 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
818 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
820
821 PINMUX_IPSR_GPSR(IP4_7_4, A18),
822 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
823 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
825
826 PINMUX_IPSR_GPSR(IP4_11_8, A19),
827 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
828 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
830
831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
833
fc8fd9be 834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
e01678e3 835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
837
e01678e3
GU		 838 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
839 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 840 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 841 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
843 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
844 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 845 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
846
e01678e3 847 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 848 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
853
e01678e3 854 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 855 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
860
861 /* IPSR5 */
e01678e3 862 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 863 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 864 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
865 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 866 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 867 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 868 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
869
e01678e3 870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
876 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 877 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
878
879 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 880 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
882 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 883
e01678e3 884 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 887 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
888 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 889
e01678e3 890 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 893 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
894 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 895
e01678e3 896 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 897 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 898 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
899 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 900
e01678e3 901 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 902 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 903 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
904 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 905
e01678e3 906 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 907 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 908 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
909 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 910
911 /* IPSR6 */
e01678e3 912 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 913 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 914 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
915 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 916
b205914c
GU		 917 PINMUX_IPSR_GPSR(IP6_7_4, D6),
918 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
920 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 921
b205914c
GU		 922 PINMUX_IPSR_GPSR(IP6_11_8, D7),
923 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
925 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 926
b205914c
GU		 927 PINMUX_IPSR_GPSR(IP6_15_12, D8),
928 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
929 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
930 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
931 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 933
b205914c
GU		 934 PINMUX_IPSR_GPSR(IP6_19_16, D9),
935 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
936 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 939
b205914c
GU		 940 PINMUX_IPSR_GPSR(IP6_23_20, D10),
941 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
942 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
944 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
945 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
946 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 947
b205914c
GU		 948 PINMUX_IPSR_GPSR(IP6_27_24, D11),
949 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 955
b205914c
GU		 956 PINMUX_IPSR_GPSR(IP6_31_28, D12),
957 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
958 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
960 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
961 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 962
b205914c
GU		 963 /* IPSR7 */
964 PINMUX_IPSR_GPSR(IP7_3_0, D13),
965 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
966 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 970
b205914c
GU		 971 PINMUX_IPSR_GPSR(IP7_7_4, D14),
972 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
973 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
974 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
975 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
977 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 978
b205914c
GU		 979 PINMUX_IPSR_GPSR(IP7_11_8, D15),
980 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
981 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 986
b205914c
GU		 987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 990
b205914c
GU		 991 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
992 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 994
b205914c
GU		 995 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
996 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 999
b205914c
GU		 1000 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1004
b205914c
GU		 1005 /* IPSR8 */
1006 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1007 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1010
b205914c
GU		 1011 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1012 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1015
b205914c
GU		 1016 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1017 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1019
b205914c
GU		 1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
3c612d2c 1022 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
b205914c
GU		 1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1025
b205914c
GU		 1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
3c612d2c 1029 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
b205914c
GU		 1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1032
b205914c
GU		 1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
3c612d2c 1036 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
b205914c
GU		 1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1039
b205914c
GU		 1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
3c612d2c 1043 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
b205914c
GU		 1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1046
b205914c
GU		 1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
3c612d2c 1050 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
b205914c
GU		 1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1053
b205914c
GU		 1054 /* IPSR9 */
1055 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1056 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1057
b205914c
GU		 1058 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1059 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1060
b205914c
GU		 1061 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1062 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1063
b205914c
GU		 1064 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1065 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1066
b205914c
GU		 1067 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1068 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1069
b205914c
GU		 1070 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1071 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1072
b205914c
GU		 1073 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1074 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1075 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1076
b205914c
GU		 1077 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1078 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1079
b205914c
GU		 1080 /* IPSR10 */
1081 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1082 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1083
b205914c
GU		 1084 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1085 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1086
b205914c
GU		 1087 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1088 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1089
b205914c
GU		 1090 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1091 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1092
b205914c
GU		 1093 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1094 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1095
b205914c
GU		 1096 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1097 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1099
b205914c
GU		 1100 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1101 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1103
b205914c
GU		 1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1105 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1106 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1107
b205914c
GU		 1108 /* IPSR11 */
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1110 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1111 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1112
1113 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1114 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1115
1116 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1117 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1118 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1119
1120 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1121 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1122
1123 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1128
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1139
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1141 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1142 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1143 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1145
b205914c
GU		 1146 /* IPSR12 */
1147 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1148 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1152
1153 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1154 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1155 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1157 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161
1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1169 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1170
1171 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1172 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1174 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1176
1177 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1178 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1182
1183 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1184 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1185 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1187 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190
1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1198
1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
eada11ac 1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
b205914c
GU		 1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1206
b205914c
GU		 1207 /* IPSR13 */
1208 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1213 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1214
1215 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1220 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1221
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1232 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1233 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1234 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1237
1238 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1239 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1240 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1241 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1244
1245 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1248 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1249 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1252 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1253
1254 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1255 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1256 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1257 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1258 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1260 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1263 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1264 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1265 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1266
b205914c
GU		 1267 /* IPSR14 */
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
3c612d2c 1270 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
b205914c
GU		 1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
ae03c4ec 1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
b205914c
GU		 1276
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1287 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1291 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1294
1295 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1296 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1297 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1298
1299 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1300 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1301
1302 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1303 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1304
1305 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1306 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1307
b205914c
GU		 1308 /* IPSR15 */
1309 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1310
1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1313
68e63892 1314 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1315 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1317
68e63892 1318 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1319 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1322
1323 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1324 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1332 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1340 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1348 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1354
b205914c
GU		 1355 /* IPSR16 */
1356 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1357 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1362 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1365 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1366 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1367
1368 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1369 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1371 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1375
1376 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1377 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1378 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1379 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1383
1384 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1385 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1386 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1387 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
ae03c4ec 1391 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
b205914c
GU		 1392
1393 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1394 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1395 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1396 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1400
1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1402 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1406 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
712f36fb 1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
20cacae1 1409
b205914c
GU		 1410 /* IPSR17 */
1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1413
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
eada11ac 1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
b205914c
GU		 1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
ae03c4ec 1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
b205914c
GU		 1419
1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1427
1428 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1429 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1430 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1434
1435 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1438 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1444
1445 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1446 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1447 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1448 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1454
1455 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
50d83156 1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
b205914c
GU		 1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
ae03c4ec 1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
b205914c
GU		 1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1466
1467 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1468 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1469 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1470 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1476
1477 /* IPSR18 */
f9d13080 1478 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
b205914c
GU		 1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1487
f9d13080 1488 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
b205914c
GU		 1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1497
b205914c
GU		 1498/*
1499 * Static pins can not be muxed between different functions but
1500 * still needs a mark entry in the pinmux list. Add each static
1501 * pin to the list without an associated function. The sh-pfc
1502 * core will do the right thing and skip trying to mux then pin
1503 * while still applying configuration to it
1504 */
1505#define FM(x) PINMUX_DATA(x##_MARK, 0),
1506 PINMUX_STATIC
1507#undef FM
9b132ba3
KM		 1508};
1509
b205914c
GU		 1510/*
1511 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1512 * Physical layout rows: A - AW, cols: 1 - 39.
1513 */
1514#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1517
1518static const struct sh_pfc_pin pinmux_pins[] = {
1519 PINMUX_GPIO_GP_ALL(),
76250a6c 1520
b205914c
GU		 1521 /*
1522 * Pins not associated with a GPIO port.
1523 *
1524 * The pin positions are different between different r8a7795
1525 * packages, all that is needed for the pfc driver is a unique
1526 * number for each pin. To this end use the pin layout from
1527 * R-Car H3SiP to calculate a unique number for each pin.
1528 */
1529 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1573};
1574
30c078de
GU		 1575/* - EtherAVB --------------------------------------------------------------- */
1576static const unsigned int avb_link_pins[] = {
1577 /* AVB_LINK */
1578 RCAR_GP_PIN(2, 12),
1579};
1580static const unsigned int avb_link_mux[] = {
1581 AVB_LINK_MARK,
1582};
1583static const unsigned int avb_magic_pins[] = {
1584 /* AVB_MAGIC_ */
1585 RCAR_GP_PIN(2, 10),
1586};
1587static const unsigned int avb_magic_mux[] = {
1588 AVB_MAGIC_MARK,
1589};
1590static const unsigned int avb_phy_int_pins[] = {
1591 /* AVB_PHY_INT */
1592 RCAR_GP_PIN(2, 11),
1593};
1594static const unsigned int avb_phy_int_mux[] = {
1595 AVB_PHY_INT_MARK,
1596};
1597static const unsigned int avb_mdc_pins[] = {
1598 /* AVB_MDC, AVB_MDIO */
1599 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1600};
1601static const unsigned int avb_mdc_mux[] = {
1602 AVB_MDC_MARK, AVB_MDIO_MARK,
1603};
1604static const unsigned int avb_mii_pins[] = {
1605 /*
1606 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1607 * AVB_TD1, AVB_TD2, AVB_TD3,
1608 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1609 * AVB_RD1, AVB_RD2, AVB_RD3,
1610 * AVB_TXCREFCLK
1611 */
1612 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1613 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1614 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1615 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1616 PIN_NUMBER('A', 12),
1617
1618};
1619static const unsigned int avb_mii_mux[] = {
1620 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1621 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1622 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1623 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1624 AVB_TXCREFCLK_MARK,
1625};
1626static const unsigned int avb_avtp_pps_pins[] = {
1627 /* AVB_AVTP_PPS */
1628 RCAR_GP_PIN(2, 6),
1629};
1630static const unsigned int avb_avtp_pps_mux[] = {
1631 AVB_AVTP_PPS_MARK,
1632};
1633static const unsigned int avb_avtp_match_a_pins[] = {
1634 /* AVB_AVTP_MATCH_A */
1635 RCAR_GP_PIN(2, 13),
1636};
1637static const unsigned int avb_avtp_match_a_mux[] = {
1638 AVB_AVTP_MATCH_A_MARK,
1639};
1640static const unsigned int avb_avtp_capture_a_pins[] = {
1641 /* AVB_AVTP_CAPTURE_A */
1642 RCAR_GP_PIN(2, 14),
1643};
1644static const unsigned int avb_avtp_capture_a_mux[] = {
1645 AVB_AVTP_CAPTURE_A_MARK,
1646};
1647static const unsigned int avb_avtp_match_b_pins[] = {
1648 /* AVB_AVTP_MATCH_B */
1649 RCAR_GP_PIN(1, 8),
1650};
1651static const unsigned int avb_avtp_match_b_mux[] = {
1652 AVB_AVTP_MATCH_B_MARK,
1653};
1654static const unsigned int avb_avtp_capture_b_pins[] = {
1655 /* AVB_AVTP_CAPTURE_B */
1656 RCAR_GP_PIN(1, 11),
1657};
1658static const unsigned int avb_avtp_capture_b_mux[] = {
1659 AVB_AVTP_CAPTURE_B_MARK,
1660};
1661
a20a6585
LP		 1662/* - DU --------------------------------------------------------------------- */
1663static const unsigned int du_rgb666_pins[] = {
1664 /* R[7:2], G[7:2], B[7:2] */
1665 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1666 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1667 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1668 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1669 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1670 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1671};
1672static const unsigned int du_rgb666_mux[] = {
1673 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1674 DU_DR3_MARK, DU_DR2_MARK,
1675 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1676 DU_DG3_MARK, DU_DG2_MARK,
1677 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1678 DU_DB3_MARK, DU_DB2_MARK,
1679};
1680static const unsigned int du_rgb888_pins[] = {
1681 /* R[7:0], G[7:0], B[7:0] */
1682 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1683 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1684 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1685 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1686 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1687 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1688 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1689 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1690 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1691};
1692static const unsigned int du_rgb888_mux[] = {
1693 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1694 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1695 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1696 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1697 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1698 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1699};
1700static const unsigned int du_clk_out_0_pins[] = {
1701 /* CLKOUT */
1702 RCAR_GP_PIN(1, 27),
1703};
1704static const unsigned int du_clk_out_0_mux[] = {
1705 DU_DOTCLKOUT0_MARK
1706};
1707static const unsigned int du_clk_out_1_pins[] = {
1708 /* CLKOUT */
1709 RCAR_GP_PIN(2, 3),
1710};
1711static const unsigned int du_clk_out_1_mux[] = {
1712 DU_DOTCLKOUT1_MARK
1713};
1714static const unsigned int du_sync_pins[] = {
1715 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1716 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1717};
1718static const unsigned int du_sync_mux[] = {
1719 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1720};
1721static const unsigned int du_oddf_pins[] = {
1722 /* EXDISP/EXODDF/EXCDE */
1723 RCAR_GP_PIN(2, 2),
1724};
1725static const unsigned int du_oddf_mux[] = {
1726 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1727};
1728static const unsigned int du_cde_pins[] = {
1729 /* CDE */
1730 RCAR_GP_PIN(2, 0),
1731};
1732static const unsigned int du_cde_mux[] = {
1733 DU_CDE_MARK,
1734};
1735static const unsigned int du_disp_pins[] = {
1736 /* DISP */
1737 RCAR_GP_PIN(2, 1),
1738};
1739static const unsigned int du_disp_mux[] = {
1740 DU_DISP_MARK,
1741};
1742
3e6c7727
GU		 1743/* - MSIOF0 ----------------------------------------------------------------- */
1744static const unsigned int msiof0_clk_pins[] = {
1745 /* SCK */
1746 RCAR_GP_PIN(5, 17),
1747};
1748static const unsigned int msiof0_clk_mux[] = {
1749 MSIOF0_SCK_MARK,
1750};
1751static const unsigned int msiof0_sync_pins[] = {
1752 /* SYNC */
1753 RCAR_GP_PIN(5, 18),
1754};
1755static const unsigned int msiof0_sync_mux[] = {
1756 MSIOF0_SYNC_MARK,
1757};
1758static const unsigned int msiof0_ss1_pins[] = {
1759 /* SS1 */
1760 RCAR_GP_PIN(5, 19),
1761};
1762static const unsigned int msiof0_ss1_mux[] = {
1763 MSIOF0_SS1_MARK,
1764};
1765static const unsigned int msiof0_ss2_pins[] = {
1766 /* SS2 */
1767 RCAR_GP_PIN(5, 21),
1768};
1769static const unsigned int msiof0_ss2_mux[] = {
1770 MSIOF0_SS2_MARK,
1771};
1772static const unsigned int msiof0_txd_pins[] = {
1773 /* TXD */
1774 RCAR_GP_PIN(5, 20),
1775};
1776static const unsigned int msiof0_txd_mux[] = {
1777 MSIOF0_TXD_MARK,
1778};
1779static const unsigned int msiof0_rxd_pins[] = {
1780 /* RXD */
1781 RCAR_GP_PIN(5, 22),
1782};
1783static const unsigned int msiof0_rxd_mux[] = {
1784 MSIOF0_RXD_MARK,
1785};
1786/* - MSIOF1 ----------------------------------------------------------------- */
1787static const unsigned int msiof1_clk_a_pins[] = {
1788 /* SCK */
1789 RCAR_GP_PIN(6, 8),
1790};
1791static const unsigned int msiof1_clk_a_mux[] = {
1792 MSIOF1_SCK_A_MARK,
1793};
1794static const unsigned int msiof1_sync_a_pins[] = {
1795 /* SYNC */
1796 RCAR_GP_PIN(6, 9),
1797};
1798static const unsigned int msiof1_sync_a_mux[] = {
1799 MSIOF1_SYNC_A_MARK,
1800};
1801static const unsigned int msiof1_ss1_a_pins[] = {
1802 /* SS1 */
1803 RCAR_GP_PIN(6, 5),
1804};
1805static const unsigned int msiof1_ss1_a_mux[] = {
1806 MSIOF1_SS1_A_MARK,
1807};
1808static const unsigned int msiof1_ss2_a_pins[] = {
1809 /* SS2 */
1810 RCAR_GP_PIN(6, 6),
1811};
1812static const unsigned int msiof1_ss2_a_mux[] = {
1813 MSIOF1_SS2_A_MARK,
1814};
1815static const unsigned int msiof1_txd_a_pins[] = {
1816 /* TXD */
1817 RCAR_GP_PIN(6, 7),
1818};
1819static const unsigned int msiof1_txd_a_mux[] = {
1820 MSIOF1_TXD_A_MARK,
1821};
1822static const unsigned int msiof1_rxd_a_pins[] = {
1823 /* RXD */
1824 RCAR_GP_PIN(6, 10),
1825};
1826static const unsigned int msiof1_rxd_a_mux[] = {
1827 MSIOF1_RXD_A_MARK,
1828};
1829static const unsigned int msiof1_clk_b_pins[] = {
1830 /* SCK */
1831 RCAR_GP_PIN(5, 9),
1832};
1833static const unsigned int msiof1_clk_b_mux[] = {
1834 MSIOF1_SCK_B_MARK,
1835};
1836static const unsigned int msiof1_sync_b_pins[] = {
1837 /* SYNC */
1838 RCAR_GP_PIN(5, 3),
1839};
1840static const unsigned int msiof1_sync_b_mux[] = {
1841 MSIOF1_SYNC_B_MARK,
1842};
1843static const unsigned int msiof1_ss1_b_pins[] = {
1844 /* SS1 */
1845 RCAR_GP_PIN(5, 4),
1846};
1847static const unsigned int msiof1_ss1_b_mux[] = {
1848 MSIOF1_SS1_B_MARK,
1849};
1850static const unsigned int msiof1_ss2_b_pins[] = {
1851 /* SS2 */
1852 RCAR_GP_PIN(5, 0),
1853};
1854static const unsigned int msiof1_ss2_b_mux[] = {
1855 MSIOF1_SS2_B_MARK,
1856};
1857static const unsigned int msiof1_txd_b_pins[] = {
1858 /* TXD */
1859 RCAR_GP_PIN(5, 8),
1860};
1861static const unsigned int msiof1_txd_b_mux[] = {
1862 MSIOF1_TXD_B_MARK,
1863};
1864static const unsigned int msiof1_rxd_b_pins[] = {
1865 /* RXD */
1866 RCAR_GP_PIN(5, 7),
1867};
1868static const unsigned int msiof1_rxd_b_mux[] = {
1869 MSIOF1_RXD_B_MARK,
1870};
1871static const unsigned int msiof1_clk_c_pins[] = {
1872 /* SCK */
1873 RCAR_GP_PIN(6, 17),
1874};
1875static const unsigned int msiof1_clk_c_mux[] = {
1876 MSIOF1_SCK_C_MARK,
1877};
1878static const unsigned int msiof1_sync_c_pins[] = {
1879 /* SYNC */
1880 RCAR_GP_PIN(6, 18),
1881};
1882static const unsigned int msiof1_sync_c_mux[] = {
1883 MSIOF1_SYNC_C_MARK,
1884};
1885static const unsigned int msiof1_ss1_c_pins[] = {
1886 /* SS1 */
1887 RCAR_GP_PIN(6, 21),
1888};
1889static const unsigned int msiof1_ss1_c_mux[] = {
1890 MSIOF1_SS1_C_MARK,
1891};
1892static const unsigned int msiof1_ss2_c_pins[] = {
1893 /* SS2 */
1894 RCAR_GP_PIN(6, 27),
1895};
1896static const unsigned int msiof1_ss2_c_mux[] = {
1897 MSIOF1_SS2_C_MARK,
1898};
1899static const unsigned int msiof1_txd_c_pins[] = {
1900 /* TXD */
1901 RCAR_GP_PIN(6, 20),
1902};
1903static const unsigned int msiof1_txd_c_mux[] = {
1904 MSIOF1_TXD_C_MARK,
1905};
1906static const unsigned int msiof1_rxd_c_pins[] = {
1907 /* RXD */
1908 RCAR_GP_PIN(6, 19),
1909};
1910static const unsigned int msiof1_rxd_c_mux[] = {
1911 MSIOF1_RXD_C_MARK,
1912};
1913static const unsigned int msiof1_clk_d_pins[] = {
1914 /* SCK */
1915 RCAR_GP_PIN(5, 12),
1916};
1917static const unsigned int msiof1_clk_d_mux[] = {
1918 MSIOF1_SCK_D_MARK,
1919};
1920static const unsigned int msiof1_sync_d_pins[] = {
1921 /* SYNC */
1922 RCAR_GP_PIN(5, 15),
1923};
1924static const unsigned int msiof1_sync_d_mux[] = {
1925 MSIOF1_SYNC_D_MARK,
1926};
1927static const unsigned int msiof1_ss1_d_pins[] = {
1928 /* SS1 */
1929 RCAR_GP_PIN(5, 16),
1930};
1931static const unsigned int msiof1_ss1_d_mux[] = {
1932 MSIOF1_SS1_D_MARK,
1933};
1934static const unsigned int msiof1_ss2_d_pins[] = {
1935 /* SS2 */
1936 RCAR_GP_PIN(5, 21),
1937};
1938static const unsigned int msiof1_ss2_d_mux[] = {
1939 MSIOF1_SS2_D_MARK,
1940};
1941static const unsigned int msiof1_txd_d_pins[] = {
1942 /* TXD */
1943 RCAR_GP_PIN(5, 14),
1944};
1945static const unsigned int msiof1_txd_d_mux[] = {
1946 MSIOF1_TXD_D_MARK,
1947};
1948static const unsigned int msiof1_rxd_d_pins[] = {
1949 /* RXD */
1950 RCAR_GP_PIN(5, 13),
1951};
1952static const unsigned int msiof1_rxd_d_mux[] = {
1953 MSIOF1_RXD_D_MARK,
1954};
1955static const unsigned int msiof1_clk_e_pins[] = {
1956 /* SCK */
1957 RCAR_GP_PIN(3, 0),
1958};
1959static const unsigned int msiof1_clk_e_mux[] = {
1960 MSIOF1_SCK_E_MARK,
1961};
1962static const unsigned int msiof1_sync_e_pins[] = {
1963 /* SYNC */
1964 RCAR_GP_PIN(3, 1),
1965};
1966static const unsigned int msiof1_sync_e_mux[] = {
1967 MSIOF1_SYNC_E_MARK,
1968};
1969static const unsigned int msiof1_ss1_e_pins[] = {
1970 /* SS1 */
1971 RCAR_GP_PIN(3, 4),
1972};
1973static const unsigned int msiof1_ss1_e_mux[] = {
1974 MSIOF1_SS1_E_MARK,
1975};
1976static const unsigned int msiof1_ss2_e_pins[] = {
1977 /* SS2 */
1978 RCAR_GP_PIN(3, 5),
1979};
1980static const unsigned int msiof1_ss2_e_mux[] = {
1981 MSIOF1_SS2_E_MARK,
1982};
1983static const unsigned int msiof1_txd_e_pins[] = {
1984 /* TXD */
1985 RCAR_GP_PIN(3, 3),
1986};
1987static const unsigned int msiof1_txd_e_mux[] = {
1988 MSIOF1_TXD_E_MARK,
1989};
1990static const unsigned int msiof1_rxd_e_pins[] = {
1991 /* RXD */
1992 RCAR_GP_PIN(3, 2),
1993};
1994static const unsigned int msiof1_rxd_e_mux[] = {
1995 MSIOF1_RXD_E_MARK,
1996};
1997static const unsigned int msiof1_clk_f_pins[] = {
1998 /* SCK */
1999 RCAR_GP_PIN(5, 23),
2000};
2001static const unsigned int msiof1_clk_f_mux[] = {
2002 MSIOF1_SCK_F_MARK,
2003};
2004static const unsigned int msiof1_sync_f_pins[] = {
2005 /* SYNC */
2006 RCAR_GP_PIN(5, 24),
2007};
2008static const unsigned int msiof1_sync_f_mux[] = {
2009 MSIOF1_SYNC_F_MARK,
2010};
2011static const unsigned int msiof1_ss1_f_pins[] = {
2012 /* SS1 */
2013 RCAR_GP_PIN(6, 1),
2014};
2015static const unsigned int msiof1_ss1_f_mux[] = {
2016 MSIOF1_SS1_F_MARK,
2017};
2018static const unsigned int msiof1_ss2_f_pins[] = {
2019 /* SS2 */
2020 RCAR_GP_PIN(6, 2),
2021};
2022static const unsigned int msiof1_ss2_f_mux[] = {
2023 MSIOF1_SS2_F_MARK,
2024};
2025static const unsigned int msiof1_txd_f_pins[] = {
2026 /* TXD */
2027 RCAR_GP_PIN(6, 0),
2028};
2029static const unsigned int msiof1_txd_f_mux[] = {
2030 MSIOF1_TXD_F_MARK,
2031};
2032static const unsigned int msiof1_rxd_f_pins[] = {
2033 /* RXD */
2034 RCAR_GP_PIN(5, 25),
2035};
2036static const unsigned int msiof1_rxd_f_mux[] = {
2037 MSIOF1_RXD_F_MARK,
2038};
2039static const unsigned int msiof1_clk_g_pins[] = {
2040 /* SCK */
2041 RCAR_GP_PIN(3, 6),
2042};
2043static const unsigned int msiof1_clk_g_mux[] = {
2044 MSIOF1_SCK_G_MARK,
2045};
2046static const unsigned int msiof1_sync_g_pins[] = {
2047 /* SYNC */
2048 RCAR_GP_PIN(3, 7),
2049};
2050static const unsigned int msiof1_sync_g_mux[] = {
2051 MSIOF1_SYNC_G_MARK,
2052};
2053static const unsigned int msiof1_ss1_g_pins[] = {
2054 /* SS1 */
2055 RCAR_GP_PIN(3, 10),
2056};
2057static const unsigned int msiof1_ss1_g_mux[] = {
2058 MSIOF1_SS1_G_MARK,
2059};
2060static const unsigned int msiof1_ss2_g_pins[] = {
2061 /* SS2 */
2062 RCAR_GP_PIN(3, 11),
2063};
2064static const unsigned int msiof1_ss2_g_mux[] = {
2065 MSIOF1_SS2_G_MARK,
2066};
2067static const unsigned int msiof1_txd_g_pins[] = {
2068 /* TXD */
2069 RCAR_GP_PIN(3, 9),
2070};
2071static const unsigned int msiof1_txd_g_mux[] = {
2072 MSIOF1_TXD_G_MARK,
2073};
2074static const unsigned int msiof1_rxd_g_pins[] = {
2075 /* RXD */
2076 RCAR_GP_PIN(3, 8),
2077};
2078static const unsigned int msiof1_rxd_g_mux[] = {
2079 MSIOF1_RXD_G_MARK,
2080};
2081/* - MSIOF2 ----------------------------------------------------------------- */
2082static const unsigned int msiof2_clk_a_pins[] = {
2083 /* SCK */
2084 RCAR_GP_PIN(1, 9),
2085};
2086static const unsigned int msiof2_clk_a_mux[] = {
2087 MSIOF2_SCK_A_MARK,
2088};
2089static const unsigned int msiof2_sync_a_pins[] = {
2090 /* SYNC */
2091 RCAR_GP_PIN(1, 8),
2092};
2093static const unsigned int msiof2_sync_a_mux[] = {
2094 MSIOF2_SYNC_A_MARK,
2095};
2096static const unsigned int msiof2_ss1_a_pins[] = {
2097 /* SS1 */
2098 RCAR_GP_PIN(1, 6),
2099};
2100static const unsigned int msiof2_ss1_a_mux[] = {
2101 MSIOF2_SS1_A_MARK,
2102};
2103static const unsigned int msiof2_ss2_a_pins[] = {
2104 /* SS2 */
2105 RCAR_GP_PIN(1, 7),
2106};
2107static const unsigned int msiof2_ss2_a_mux[] = {
2108 MSIOF2_SS2_A_MARK,
2109};
2110static const unsigned int msiof2_txd_a_pins[] = {
2111 /* TXD */
2112 RCAR_GP_PIN(1, 11),
2113};
2114static const unsigned int msiof2_txd_a_mux[] = {
2115 MSIOF2_TXD_A_MARK,
2116};
2117static const unsigned int msiof2_rxd_a_pins[] = {
2118 /* RXD */
2119 RCAR_GP_PIN(1, 10),
2120};
2121static const unsigned int msiof2_rxd_a_mux[] = {
2122 MSIOF2_RXD_A_MARK,
2123};
2124static const unsigned int msiof2_clk_b_pins[] = {
2125 /* SCK */
2126 RCAR_GP_PIN(0, 4),
2127};
2128static const unsigned int msiof2_clk_b_mux[] = {
2129 MSIOF2_SCK_B_MARK,
2130};
2131static const unsigned int msiof2_sync_b_pins[] = {
2132 /* SYNC */
2133 RCAR_GP_PIN(0, 5),
2134};
2135static const unsigned int msiof2_sync_b_mux[] = {
2136 MSIOF2_SYNC_B_MARK,
2137};
2138static const unsigned int msiof2_ss1_b_pins[] = {
2139 /* SS1 */
2140 RCAR_GP_PIN(0, 0),
2141};
2142static const unsigned int msiof2_ss1_b_mux[] = {
2143 MSIOF2_SS1_B_MARK,
2144};
2145static const unsigned int msiof2_ss2_b_pins[] = {
2146 /* SS2 */
2147 RCAR_GP_PIN(0, 1),
2148};
2149static const unsigned int msiof2_ss2_b_mux[] = {
2150 MSIOF2_SS2_B_MARK,
2151};
2152static const unsigned int msiof2_txd_b_pins[] = {
2153 /* TXD */
2154 RCAR_GP_PIN(0, 7),
2155};
2156static const unsigned int msiof2_txd_b_mux[] = {
2157 MSIOF2_TXD_B_MARK,
2158};
2159static const unsigned int msiof2_rxd_b_pins[] = {
2160 /* RXD */
2161 RCAR_GP_PIN(0, 6),
2162};
2163static const unsigned int msiof2_rxd_b_mux[] = {
2164 MSIOF2_RXD_B_MARK,
2165};
2166static const unsigned int msiof2_clk_c_pins[] = {
2167 /* SCK */
2168 RCAR_GP_PIN(2, 12),
2169};
2170static const unsigned int msiof2_clk_c_mux[] = {
2171 MSIOF2_SCK_C_MARK,
2172};
2173static const unsigned int msiof2_sync_c_pins[] = {
2174 /* SYNC */
2175 RCAR_GP_PIN(2, 11),
2176};
2177static const unsigned int msiof2_sync_c_mux[] = {
2178 MSIOF2_SYNC_C_MARK,
2179};
2180static const unsigned int msiof2_ss1_c_pins[] = {
2181 /* SS1 */
2182 RCAR_GP_PIN(2, 10),
2183};
2184static const unsigned int msiof2_ss1_c_mux[] = {
2185 MSIOF2_SS1_C_MARK,
2186};
2187static const unsigned int msiof2_ss2_c_pins[] = {
2188 /* SS2 */
2189 RCAR_GP_PIN(2, 9),
2190};
2191static const unsigned int msiof2_ss2_c_mux[] = {
2192 MSIOF2_SS2_C_MARK,
2193};
2194static const unsigned int msiof2_txd_c_pins[] = {
2195 /* TXD */
2196 RCAR_GP_PIN(2, 14),
2197};
2198static const unsigned int msiof2_txd_c_mux[] = {
2199 MSIOF2_TXD_C_MARK,
2200};
2201static const unsigned int msiof2_rxd_c_pins[] = {
2202 /* RXD */
2203 RCAR_GP_PIN(2, 13),
2204};
2205static const unsigned int msiof2_rxd_c_mux[] = {
2206 MSIOF2_RXD_C_MARK,
2207};
2208static const unsigned int msiof2_clk_d_pins[] = {
2209 /* SCK */
2210 RCAR_GP_PIN(0, 8),
2211};
2212static const unsigned int msiof2_clk_d_mux[] = {
2213 MSIOF2_SCK_D_MARK,
2214};
2215static const unsigned int msiof2_sync_d_pins[] = {
2216 /* SYNC */
2217 RCAR_GP_PIN(0, 9),
2218};
2219static const unsigned int msiof2_sync_d_mux[] = {
2220 MSIOF2_SYNC_D_MARK,
2221};
2222static const unsigned int msiof2_ss1_d_pins[] = {
2223 /* SS1 */
2224 RCAR_GP_PIN(0, 12),
2225};
2226static const unsigned int msiof2_ss1_d_mux[] = {
2227 MSIOF2_SS1_D_MARK,
2228};
2229static const unsigned int msiof2_ss2_d_pins[] = {
2230 /* SS2 */
2231 RCAR_GP_PIN(0, 13),
2232};
2233static const unsigned int msiof2_ss2_d_mux[] = {
2234 MSIOF2_SS2_D_MARK,
2235};
2236static const unsigned int msiof2_txd_d_pins[] = {
2237 /* TXD */
2238 RCAR_GP_PIN(0, 11),
2239};
2240static const unsigned int msiof2_txd_d_mux[] = {
2241 MSIOF2_TXD_D_MARK,
2242};
2243static const unsigned int msiof2_rxd_d_pins[] = {
2244 /* RXD */
2245 RCAR_GP_PIN(0, 10),
2246};
2247static const unsigned int msiof2_rxd_d_mux[] = {
2248 MSIOF2_RXD_D_MARK,
2249};
2250/* - MSIOF3 ----------------------------------------------------------------- */
2251static const unsigned int msiof3_clk_a_pins[] = {
2252 /* SCK */
2253 RCAR_GP_PIN(0, 0),
2254};
2255static const unsigned int msiof3_clk_a_mux[] = {
2256 MSIOF3_SCK_A_MARK,
2257};
2258static const unsigned int msiof3_sync_a_pins[] = {
2259 /* SYNC */
2260 RCAR_GP_PIN(0, 1),
2261};
2262static const unsigned int msiof3_sync_a_mux[] = {
2263 MSIOF3_SYNC_A_MARK,
2264};
2265static const unsigned int msiof3_ss1_a_pins[] = {
2266 /* SS1 */
2267 RCAR_GP_PIN(0, 14),
2268};
2269static const unsigned int msiof3_ss1_a_mux[] = {
2270 MSIOF3_SS1_A_MARK,
2271};
2272static const unsigned int msiof3_ss2_a_pins[] = {
2273 /* SS2 */
2274 RCAR_GP_PIN(0, 15),
2275};
2276static const unsigned int msiof3_ss2_a_mux[] = {
2277 MSIOF3_SS2_A_MARK,
2278};
2279static const unsigned int msiof3_txd_a_pins[] = {
2280 /* TXD */
2281 RCAR_GP_PIN(0, 3),
2282};
2283static const unsigned int msiof3_txd_a_mux[] = {
2284 MSIOF3_TXD_A_MARK,
2285};
2286static const unsigned int msiof3_rxd_a_pins[] = {
2287 /* RXD */
2288 RCAR_GP_PIN(0, 2),
2289};
2290static const unsigned int msiof3_rxd_a_mux[] = {
2291 MSIOF3_RXD_A_MARK,
2292};
2293static const unsigned int msiof3_clk_b_pins[] = {
2294 /* SCK */
2295 RCAR_GP_PIN(1, 2),
2296};
2297static const unsigned int msiof3_clk_b_mux[] = {
2298 MSIOF3_SCK_B_MARK,
2299};
2300static const unsigned int msiof3_sync_b_pins[] = {
2301 /* SYNC */
2302 RCAR_GP_PIN(1, 0),
2303};
2304static const unsigned int msiof3_sync_b_mux[] = {
2305 MSIOF3_SYNC_B_MARK,
2306};
2307static const unsigned int msiof3_ss1_b_pins[] = {
2308 /* SS1 */
2309 RCAR_GP_PIN(1, 4),
2310};
2311static const unsigned int msiof3_ss1_b_mux[] = {
2312 MSIOF3_SS1_B_MARK,
2313};
2314static const unsigned int msiof3_ss2_b_pins[] = {
2315 /* SS2 */
2316 RCAR_GP_PIN(1, 5),
2317};
2318static const unsigned int msiof3_ss2_b_mux[] = {
2319 MSIOF3_SS2_B_MARK,
2320};
2321static const unsigned int msiof3_txd_b_pins[] = {
2322 /* TXD */
2323 RCAR_GP_PIN(1, 1),
2324};
2325static const unsigned int msiof3_txd_b_mux[] = {
2326 MSIOF3_TXD_B_MARK,
2327};
2328static const unsigned int msiof3_rxd_b_pins[] = {
2329 /* RXD */
2330 RCAR_GP_PIN(1, 3),
2331};
2332static const unsigned int msiof3_rxd_b_mux[] = {
2333 MSIOF3_RXD_B_MARK,
2334};
2335static const unsigned int msiof3_clk_c_pins[] = {
2336 /* SCK */
2337 RCAR_GP_PIN(1, 12),
2338};
2339static const unsigned int msiof3_clk_c_mux[] = {
2340 MSIOF3_SCK_C_MARK,
2341};
2342static const unsigned int msiof3_sync_c_pins[] = {
2343 /* SYNC */
2344 RCAR_GP_PIN(1, 13),
2345};
2346static const unsigned int msiof3_sync_c_mux[] = {
2347 MSIOF3_SYNC_C_MARK,
2348};
2349static const unsigned int msiof3_txd_c_pins[] = {
2350 /* TXD */
2351 RCAR_GP_PIN(1, 15),
2352};
2353static const unsigned int msiof3_txd_c_mux[] = {
2354 MSIOF3_TXD_C_MARK,
2355};
2356static const unsigned int msiof3_rxd_c_pins[] = {
2357 /* RXD */
2358 RCAR_GP_PIN(1, 14),
2359};
2360static const unsigned int msiof3_rxd_c_mux[] = {
2361 MSIOF3_RXD_C_MARK,
2362};
2363static const unsigned int msiof3_clk_d_pins[] = {
2364 /* SCK */
2365 RCAR_GP_PIN(1, 22),
2366};
2367static const unsigned int msiof3_clk_d_mux[] = {
2368 MSIOF3_SCK_D_MARK,
2369};
2370static const unsigned int msiof3_sync_d_pins[] = {
2371 /* SYNC */
2372 RCAR_GP_PIN(1, 23),
2373};
2374static const unsigned int msiof3_sync_d_mux[] = {
2375 MSIOF3_SYNC_D_MARK,
2376};
2377static const unsigned int msiof3_ss1_d_pins[] = {
2378 /* SS1 */
2379 RCAR_GP_PIN(1, 26),
2380};
2381static const unsigned int msiof3_ss1_d_mux[] = {
2382 MSIOF3_SS1_D_MARK,
2383};
2384static const unsigned int msiof3_txd_d_pins[] = {
2385 /* TXD */
2386 RCAR_GP_PIN(1, 25),
2387};
2388static const unsigned int msiof3_txd_d_mux[] = {
2389 MSIOF3_TXD_D_MARK,
2390};
2391static const unsigned int msiof3_rxd_d_pins[] = {
2392 /* RXD */
2393 RCAR_GP_PIN(1, 24),
2394};
2395static const unsigned int msiof3_rxd_d_mux[] = {
2396 MSIOF3_RXD_D_MARK,
2397};
2398static const unsigned int msiof3_clk_e_pins[] = {
2399 /* SCK */
2400 RCAR_GP_PIN(2, 3),
2401};
2402static const unsigned int msiof3_clk_e_mux[] = {
2403 MSIOF3_SCK_E_MARK,
2404};
2405static const unsigned int msiof3_sync_e_pins[] = {
2406 /* SYNC */
2407 RCAR_GP_PIN(2, 2),
2408};
2409static const unsigned int msiof3_sync_e_mux[] = {
2410 MSIOF3_SYNC_E_MARK,
2411};
2412static const unsigned int msiof3_ss1_e_pins[] = {
2413 /* SS1 */
2414 RCAR_GP_PIN(2, 1),
2415};
2416static const unsigned int msiof3_ss1_e_mux[] = {
2417 MSIOF3_SS1_E_MARK,
2418};
2419static const unsigned int msiof3_ss2_e_pins[] = {
2420 /* SS1 */
2421 RCAR_GP_PIN(2, 0),
2422};
2423static const unsigned int msiof3_ss2_e_mux[] = {
2424 MSIOF3_SS2_E_MARK,
2425};
2426static const unsigned int msiof3_txd_e_pins[] = {
2427 /* TXD */
2428 RCAR_GP_PIN(2, 5),
2429};
2430static const unsigned int msiof3_txd_e_mux[] = {
2431 MSIOF3_TXD_E_MARK,
2432};
2433static const unsigned int msiof3_rxd_e_pins[] = {
2434 /* RXD */
2435 RCAR_GP_PIN(2, 4),
2436};
2437static const unsigned int msiof3_rxd_e_mux[] = {
2438 MSIOF3_RXD_E_MARK,
2439};
2440
c03a133b
LP		 2441/* - PWM0 --------------------------------------------------------------------*/
2442static const unsigned int pwm0_pins[] = {
2443 /* PWM */
2444 RCAR_GP_PIN(2, 6),
2445};
2446static const unsigned int pwm0_mux[] = {
2447 PWM0_MARK,
2448};
2449/* - PWM1 --------------------------------------------------------------------*/
2450static const unsigned int pwm1_a_pins[] = {
2451 /* PWM */
2452 RCAR_GP_PIN(2, 7),
2453};
2454static const unsigned int pwm1_a_mux[] = {
2455 PWM1_A_MARK,
2456};
2457static const unsigned int pwm1_b_pins[] = {
2458 /* PWM */
2459 RCAR_GP_PIN(1, 8),
2460};
2461static const unsigned int pwm1_b_mux[] = {
2462 PWM1_B_MARK,
2463};
2464/* - PWM2 --------------------------------------------------------------------*/
2465static const unsigned int pwm2_a_pins[] = {
2466 /* PWM */
2467 RCAR_GP_PIN(2, 8),
2468};
2469static const unsigned int pwm2_a_mux[] = {
2470 PWM2_A_MARK,
2471};
2472static const unsigned int pwm2_b_pins[] = {
2473 /* PWM */
2474 RCAR_GP_PIN(1, 11),
2475};
2476static const unsigned int pwm2_b_mux[] = {
2477 PWM2_B_MARK,
2478};
2479/* - PWM3 --------------------------------------------------------------------*/
2480static const unsigned int pwm3_a_pins[] = {
2481 /* PWM */
2482 RCAR_GP_PIN(1, 0),
2483};
2484static const unsigned int pwm3_a_mux[] = {
2485 PWM3_A_MARK,
2486};
2487static const unsigned int pwm3_b_pins[] = {
2488 /* PWM */
2489 RCAR_GP_PIN(2, 2),
2490};
2491static const unsigned int pwm3_b_mux[] = {
2492 PWM3_B_MARK,
2493};
2494/* - PWM4 --------------------------------------------------------------------*/
2495static const unsigned int pwm4_a_pins[] = {
2496 /* PWM */
2497 RCAR_GP_PIN(1, 1),
2498};
2499static const unsigned int pwm4_a_mux[] = {
2500 PWM4_A_MARK,
2501};
2502static const unsigned int pwm4_b_pins[] = {
2503 /* PWM */
2504 RCAR_GP_PIN(2, 3),
2505};
2506static const unsigned int pwm4_b_mux[] = {
2507 PWM4_B_MARK,
2508};
2509/* - PWM5 --------------------------------------------------------------------*/
2510static const unsigned int pwm5_a_pins[] = {
2511 /* PWM */
2512 RCAR_GP_PIN(1, 2),
2513};
2514static const unsigned int pwm5_a_mux[] = {
2515 PWM5_A_MARK,
2516};
2517static const unsigned int pwm5_b_pins[] = {
2518 /* PWM */
2519 RCAR_GP_PIN(2, 4),
2520};
2521static const unsigned int pwm5_b_mux[] = {
2522 PWM5_B_MARK,
2523};
2524/* - PWM6 --------------------------------------------------------------------*/
2525static const unsigned int pwm6_a_pins[] = {
2526 /* PWM */
2527 RCAR_GP_PIN(1, 3),
2528};
2529static const unsigned int pwm6_a_mux[] = {
2530 PWM6_A_MARK,
2531};
2532static const unsigned int pwm6_b_pins[] = {
2533 /* PWM */
2534 RCAR_GP_PIN(2, 5),
2535};
2536static const unsigned int pwm6_b_mux[] = {
2537 PWM6_B_MARK,
2538};
2539
e7ad4d3c
GU		 2540/* - SCIF0 ------------------------------------------------------------------ */
2541static const unsigned int scif0_data_pins[] = {
2542 /* RX, TX */
2543 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2544};
2545static const unsigned int scif0_data_mux[] = {
2546 RX0_MARK, TX0_MARK,
2547};
2548static const unsigned int scif0_clk_pins[] = {
2549 /* SCK */
2550 RCAR_GP_PIN(5, 0),
2551};
2552static const unsigned int scif0_clk_mux[] = {
2553 SCK0_MARK,
2554};
2555static const unsigned int scif0_ctrl_pins[] = {
2556 /* RTS, CTS */
2557 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2558};
2559static const unsigned int scif0_ctrl_mux[] = {
2560 RTS0_N_TANS_MARK, CTS0_N_MARK,
2561};
2562/* - SCIF1 ------------------------------------------------------------------ */
2563static const unsigned int scif1_data_a_pins[] = {
2564 /* RX, TX */
2565 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2566};
2567static const unsigned int scif1_data_a_mux[] = {
2568 RX1_A_MARK, TX1_A_MARK,
2569};
2570static const unsigned int scif1_clk_pins[] = {
2571 /* SCK */
2572 RCAR_GP_PIN(6, 21),
2573};
2574static const unsigned int scif1_clk_mux[] = {
2575 SCK1_MARK,
2576};
2577static const unsigned int scif1_ctrl_pins[] = {
2578 /* RTS, CTS */
2579 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2580};
2581static const unsigned int scif1_ctrl_mux[] = {
2582 RTS1_N_TANS_MARK, CTS1_N_MARK,
2583};
2584
2585static const unsigned int scif1_data_b_pins[] = {
2586 /* RX, TX */
2587 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2588};
2589static const unsigned int scif1_data_b_mux[] = {
2590 RX1_B_MARK, TX1_B_MARK,
2591};
2592/* - SCIF2 ------------------------------------------------------------------ */
2593static const unsigned int scif2_data_a_pins[] = {
2594 /* RX, TX */
2595 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2596};
2597static const unsigned int scif2_data_a_mux[] = {
2598 RX2_A_MARK, TX2_A_MARK,
2599};
2600static const unsigned int scif2_clk_pins[] = {
2601 /* SCK */
2602 RCAR_GP_PIN(5, 9),
2603};
2604static const unsigned int scif2_clk_mux[] = {
2605 SCK2_MARK,
2606};
2607static const unsigned int scif2_data_b_pins[] = {
2608 /* RX, TX */
2609 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2610};
2611static const unsigned int scif2_data_b_mux[] = {
2612 RX2_B_MARK, TX2_B_MARK,
2613};
2614/* - SCIF3 ------------------------------------------------------------------ */
2615static const unsigned int scif3_data_a_pins[] = {
2616 /* RX, TX */
2617 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2618};
2619static const unsigned int scif3_data_a_mux[] = {
2620 RX3_A_MARK, TX3_A_MARK,
2621};
2622static const unsigned int scif3_clk_pins[] = {
2623 /* SCK */
2624 RCAR_GP_PIN(1, 22),
2625};
2626static const unsigned int scif3_clk_mux[] = {
2627 SCK3_MARK,
2628};
2629static const unsigned int scif3_ctrl_pins[] = {
2630 /* RTS, CTS */
2631 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2632};
2633static const unsigned int scif3_ctrl_mux[] = {
2634 RTS3_N_TANS_MARK, CTS3_N_MARK,
2635};
2636static const unsigned int scif3_data_b_pins[] = {
2637 /* RX, TX */
2638 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2639};
2640static const unsigned int scif3_data_b_mux[] = {
2641 RX3_B_MARK, TX3_B_MARK,
2642};
2643/* - SCIF4 ------------------------------------------------------------------ */
2644static const unsigned int scif4_data_a_pins[] = {
2645 /* RX, TX */
2646 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2647};
2648static const unsigned int scif4_data_a_mux[] = {
2649 RX4_A_MARK, TX4_A_MARK,
2650};
2651static const unsigned int scif4_clk_a_pins[] = {
2652 /* SCK */
2653 RCAR_GP_PIN(2, 10),
2654};
2655static const unsigned int scif4_clk_a_mux[] = {
2656 SCK4_A_MARK,
2657};
2658static const unsigned int scif4_ctrl_a_pins[] = {
2659 /* RTS, CTS */
2660 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2661};
2662static const unsigned int scif4_ctrl_a_mux[] = {
2663 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2664};
2665static const unsigned int scif4_data_b_pins[] = {
2666 /* RX, TX */
2667 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2668};
2669static const unsigned int scif4_data_b_mux[] = {
2670 RX4_B_MARK, TX4_B_MARK,
2671};
2672static const unsigned int scif4_clk_b_pins[] = {
2673 /* SCK */
2674 RCAR_GP_PIN(1, 5),
2675};
2676static const unsigned int scif4_clk_b_mux[] = {
2677 SCK4_B_MARK,
2678};
2679static const unsigned int scif4_ctrl_b_pins[] = {
2680 /* RTS, CTS */
2681 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2682};
2683static const unsigned int scif4_ctrl_b_mux[] = {
2684 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
2685};
2686static const unsigned int scif4_data_c_pins[] = {
2687 /* RX, TX */
2688 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2689};
2690static const unsigned int scif4_data_c_mux[] = {
2691 RX4_C_MARK, TX4_C_MARK,
2692};
2693static const unsigned int scif4_clk_c_pins[] = {
2694 /* SCK */
2695 RCAR_GP_PIN(0, 8),
2696};
2697static const unsigned int scif4_clk_c_mux[] = {
2698 SCK4_C_MARK,
2699};
2700static const unsigned int scif4_ctrl_c_pins[] = {
2701 /* RTS, CTS */
2702 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2703};
2704static const unsigned int scif4_ctrl_c_mux[] = {
2705 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2706};
2707/* - SCIF5 ------------------------------------------------------------------ */
2708static const unsigned int scif5_data_a_pins[] = {
2709 /* RX, TX */
2710 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2711};
2712static const unsigned int scif5_data_a_mux[] = {
2713 RX5_A_MARK, TX5_A_MARK,
2714};
2715static const unsigned int scif5_clk_a_pins[] = {
2716 /* SCK */
2717 RCAR_GP_PIN(6, 21),
2718};
2719static const unsigned int scif5_clk_a_mux[] = {
2720 SCK5_A_MARK,
2721};
2722static const unsigned int scif5_data_b_pins[] = {
2723 /* RX, TX */
2724 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
2725};
2726static const unsigned int scif5_data_b_mux[] = {
2727 RX5_B_MARK, TX5_B_MARK,
2728};
2729static const unsigned int scif5_clk_b_pins[] = {
2730 /* SCK */
2731 RCAR_GP_PIN(5, 0),
2732};
2733static const unsigned int scif5_clk_b_mux[] = {
2734 SCK5_B_MARK,
2735};
2736
9ed13958
TK		 2737/* - SDHI0 ------------------------------------------------------------------ */
2738static const unsigned int sdhi0_data1_pins[] = {
2739 /* D0 */
2740 RCAR_GP_PIN(3, 2),
2741};
2742static const unsigned int sdhi0_data1_mux[] = {
2743 SD0_DAT0_MARK,
2744};
2745static const unsigned int sdhi0_data4_pins[] = {
2746 /* D[0:3] */
2747 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2748 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2749};
2750static const unsigned int sdhi0_data4_mux[] = {
2751 SD0_DAT0_MARK, SD0_DAT1_MARK,
2752 SD0_DAT2_MARK, SD0_DAT3_MARK,
2753};
2754static const unsigned int sdhi0_ctrl_pins[] = {
2755 /* CLK, CMD */
2756 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2757};
2758static const unsigned int sdhi0_ctrl_mux[] = {
2759 SD0_CLK_MARK, SD0_CMD_MARK,
2760};
2761static const unsigned int sdhi0_cd_pins[] = {
2762 /* CD */
2763 RCAR_GP_PIN(3, 12),
2764};
2765static const unsigned int sdhi0_cd_mux[] = {
2766 SD0_CD_MARK,
2767};
2768static const unsigned int sdhi0_wp_pins[] = {
2769 /* WP */
2770 RCAR_GP_PIN(3, 13),
2771};
2772static const unsigned int sdhi0_wp_mux[] = {
2773 SD0_WP_MARK,
2774};
2775/* - SDHI1 ------------------------------------------------------------------ */
2776static const unsigned int sdhi1_data1_pins[] = {
2777 /* D0 */
2778 RCAR_GP_PIN(3, 8),
2779};
2780static const unsigned int sdhi1_data1_mux[] = {
2781 SD1_DAT0_MARK,
2782};
2783static const unsigned int sdhi1_data4_pins[] = {
2784 /* D[0:3] */
2785 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2786 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2787};
2788static const unsigned int sdhi1_data4_mux[] = {
2789 SD1_DAT0_MARK, SD1_DAT1_MARK,
2790 SD1_DAT2_MARK, SD1_DAT3_MARK,
2791};
2792static const unsigned int sdhi1_ctrl_pins[] = {
2793 /* CLK, CMD */
2794 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2795};
2796static const unsigned int sdhi1_ctrl_mux[] = {
2797 SD1_CLK_MARK, SD1_CMD_MARK,
2798};
2799static const unsigned int sdhi1_cd_pins[] = {
2800 /* CD */
2801 RCAR_GP_PIN(3, 14),
2802};
2803static const unsigned int sdhi1_cd_mux[] = {
2804 SD1_CD_MARK,
2805};
2806static const unsigned int sdhi1_wp_pins[] = {
2807 /* WP */
2808 RCAR_GP_PIN(3, 15),
2809};
2810static const unsigned int sdhi1_wp_mux[] = {
2811 SD1_WP_MARK,
2812};
2813/* - SDHI2 ------------------------------------------------------------------ */
2814static const unsigned int sdhi2_data1_pins[] = {
2815 /* D0 */
2816 RCAR_GP_PIN(4, 2),
2817};
2818static const unsigned int sdhi2_data1_mux[] = {
2819 SD2_DAT0_MARK,
2820};
2821static const unsigned int sdhi2_data4_pins[] = {
2822 /* D[0:3] */
2823 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2824 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2825};
2826static const unsigned int sdhi2_data4_mux[] = {
2827 SD2_DAT0_MARK, SD2_DAT1_MARK,
2828 SD2_DAT2_MARK, SD2_DAT3_MARK,
2829};
2830static const unsigned int sdhi2_data8_pins[] = {
2831 /* D[0:7] */
2832 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2833 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2834 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2835 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2836};
2837static const unsigned int sdhi2_data8_mux[] = {
2838 SD2_DAT0_MARK, SD2_DAT1_MARK,
2839 SD2_DAT2_MARK, SD2_DAT3_MARK,
2840 SD2_DAT4_MARK, SD2_DAT5_MARK,
2841 SD2_DAT6_MARK, SD2_DAT7_MARK,
2842};
2843static const unsigned int sdhi2_ctrl_pins[] = {
2844 /* CLK, CMD */
2845 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2846};
2847static const unsigned int sdhi2_ctrl_mux[] = {
2848 SD2_CLK_MARK, SD2_CMD_MARK,
2849};
2850static const unsigned int sdhi2_cd_a_pins[] = {
2851 /* CD */
2852 RCAR_GP_PIN(4, 13),
2853};
2854static const unsigned int sdhi2_cd_a_mux[] = {
2855 SD2_CD_A_MARK,
2856};
2857static const unsigned int sdhi2_cd_b_pins[] = {
2858 /* CD */
2859 RCAR_GP_PIN(5, 10),
2860};
2861static const unsigned int sdhi2_cd_b_mux[] = {
2862 SD2_CD_B_MARK,
2863};
2864static const unsigned int sdhi2_wp_a_pins[] = {
2865 /* WP */
2866 RCAR_GP_PIN(4, 14),
2867};
2868static const unsigned int sdhi2_wp_a_mux[] = {
2869 SD2_WP_A_MARK,
2870};
2871static const unsigned int sdhi2_wp_b_pins[] = {
2872 /* WP */
2873 RCAR_GP_PIN(5, 11),
2874};
2875static const unsigned int sdhi2_wp_b_mux[] = {
2876 SD2_WP_B_MARK,
2877};
2878static const unsigned int sdhi2_ds_pins[] = {
2879 /* DS */
2880 RCAR_GP_PIN(4, 6),
2881};
2882static const unsigned int sdhi2_ds_mux[] = {
2883 SD2_DS_MARK,
2884};
2885/* - SDHI3 ------------------------------------------------------------------ */
2886static const unsigned int sdhi3_data1_pins[] = {
2887 /* D0 */
2888 RCAR_GP_PIN(4, 9),
2889};
2890static const unsigned int sdhi3_data1_mux[] = {
2891 SD3_DAT0_MARK,
2892};
2893static const unsigned int sdhi3_data4_pins[] = {
2894 /* D[0:3] */
2895 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2896 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2897};
2898static const unsigned int sdhi3_data4_mux[] = {
2899 SD3_DAT0_MARK, SD3_DAT1_MARK,
2900 SD3_DAT2_MARK, SD3_DAT3_MARK,
2901};
2902static const unsigned int sdhi3_data8_pins[] = {
2903 /* D[0:7] */
2904 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2905 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2906 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2907 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2908};
2909static const unsigned int sdhi3_data8_mux[] = {
2910 SD3_DAT0_MARK, SD3_DAT1_MARK,
2911 SD3_DAT2_MARK, SD3_DAT3_MARK,
2912 SD3_DAT4_MARK, SD3_DAT5_MARK,
2913 SD3_DAT6_MARK, SD3_DAT7_MARK,
2914};
2915static const unsigned int sdhi3_ctrl_pins[] = {
2916 /* CLK, CMD */
2917 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
2918};
2919static const unsigned int sdhi3_ctrl_mux[] = {
2920 SD3_CLK_MARK, SD3_CMD_MARK,
2921};
2922static const unsigned int sdhi3_cd_pins[] = {
2923 /* CD */
2924 RCAR_GP_PIN(4, 15),
2925};
2926static const unsigned int sdhi3_cd_mux[] = {
2927 SD3_CD_MARK,
2928};
2929static const unsigned int sdhi3_wp_pins[] = {
2930 /* WP */
2931 RCAR_GP_PIN(4, 16),
2932};
2933static const unsigned int sdhi3_wp_mux[] = {
2934 SD3_WP_MARK,
2935};
2936static const unsigned int sdhi3_ds_pins[] = {
2937 /* DS */
2938 RCAR_GP_PIN(4, 17),
2939};
2940static const unsigned int sdhi3_ds_mux[] = {
2941 SD3_DS_MARK,
2942};
2943
d14a39ed
GU		 2944/* - SCIF Clock ------------------------------------------------------------- */
2945static const unsigned int scif_clk_a_pins[] = {
2946 /* SCIF_CLK */
2947 RCAR_GP_PIN(6, 23),
2948};
2949static const unsigned int scif_clk_a_mux[] = {
2950 SCIF_CLK_A_MARK,
2951};
2952static const unsigned int scif_clk_b_pins[] = {
2953 /* SCIF_CLK */
2954 RCAR_GP_PIN(5, 9),
2955};
2956static const unsigned int scif_clk_b_mux[] = {
2957 SCIF_CLK_B_MARK,
2958};
2959
933ddbe5
YS		 2960/* - USB0 ------------------------------------------------------------------- */
2961static const unsigned int usb0_pins[] = {
2962 /* PWEN, OVC */
2963 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2964};
2965static const unsigned int usb0_mux[] = {
2966 USB0_PWEN_MARK, USB0_OVC_MARK,
2967};
2968/* - USB1 ------------------------------------------------------------------- */
2969static const unsigned int usb1_pins[] = {
2970 /* PWEN, OVC */
2971 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2972};
2973static const unsigned int usb1_mux[] = {
2974 USB1_PWEN_MARK, USB1_OVC_MARK,
2975};
2976/* - USB2 ------------------------------------------------------------------- */
2977static const unsigned int usb2_pins[] = {
2978 /* PWEN, OVC */
2979 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2980};
2981static const unsigned int usb2_mux[] = {
2982 USB2_PWEN_MARK, USB2_OVC_MARK,
2983};
2984/* - USB2_CH3 --------------------------------------------------------------- */
2985static const unsigned int usb2_ch3_pins[] = {
2986 /* PWEN, OVC */
2987 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
2988};
2989static const unsigned int usb2_ch3_mux[] = {
2990 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
2991};
2992
b205914c 2993static const struct sh_pfc_pin_group pinmux_groups[] = {
30c078de
GU		 2994 SH_PFC_PIN_GROUP(avb_link),
2995 SH_PFC_PIN_GROUP(avb_magic),
2996 SH_PFC_PIN_GROUP(avb_phy_int),
2997 SH_PFC_PIN_GROUP(avb_mdc),
2998 SH_PFC_PIN_GROUP(avb_mii),
2999 SH_PFC_PIN_GROUP(avb_avtp_pps),
3000 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3001 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3002 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3003 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a20a6585
LP		 3004 SH_PFC_PIN_GROUP(du_rgb666),
3005 SH_PFC_PIN_GROUP(du_rgb888),
3006 SH_PFC_PIN_GROUP(du_clk_out_0),
3007 SH_PFC_PIN_GROUP(du_clk_out_1),
3008 SH_PFC_PIN_GROUP(du_sync),
3009 SH_PFC_PIN_GROUP(du_oddf),
3010 SH_PFC_PIN_GROUP(du_cde),
3011 SH_PFC_PIN_GROUP(du_disp),
3e6c7727
GU		 3012 SH_PFC_PIN_GROUP(msiof0_clk),
3013 SH_PFC_PIN_GROUP(msiof0_sync),
3014 SH_PFC_PIN_GROUP(msiof0_ss1),
3015 SH_PFC_PIN_GROUP(msiof0_ss2),
3016 SH_PFC_PIN_GROUP(msiof0_txd),
3017 SH_PFC_PIN_GROUP(msiof0_rxd),
3018 SH_PFC_PIN_GROUP(msiof1_clk_a),
3019 SH_PFC_PIN_GROUP(msiof1_sync_a),
3020 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3021 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3022 SH_PFC_PIN_GROUP(msiof1_txd_a),
3023 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3024 SH_PFC_PIN_GROUP(msiof1_clk_b),
3025 SH_PFC_PIN_GROUP(msiof1_sync_b),
3026 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3027 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3028 SH_PFC_PIN_GROUP(msiof1_txd_b),
3029 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3030 SH_PFC_PIN_GROUP(msiof1_clk_c),
3031 SH_PFC_PIN_GROUP(msiof1_sync_c),
3032 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3033 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3034 SH_PFC_PIN_GROUP(msiof1_txd_c),
3035 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3036 SH_PFC_PIN_GROUP(msiof1_clk_d),
3037 SH_PFC_PIN_GROUP(msiof1_sync_d),
3038 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3039 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3040 SH_PFC_PIN_GROUP(msiof1_txd_d),
3041 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3042 SH_PFC_PIN_GROUP(msiof1_clk_e),
3043 SH_PFC_PIN_GROUP(msiof1_sync_e),
3044 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3045 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3046 SH_PFC_PIN_GROUP(msiof1_txd_e),
3047 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3048 SH_PFC_PIN_GROUP(msiof1_clk_f),
3049 SH_PFC_PIN_GROUP(msiof1_sync_f),
3050 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3051 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3052 SH_PFC_PIN_GROUP(msiof1_txd_f),
3053 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3054 SH_PFC_PIN_GROUP(msiof1_clk_g),
3055 SH_PFC_PIN_GROUP(msiof1_sync_g),
3056 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3057 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3058 SH_PFC_PIN_GROUP(msiof1_txd_g),
3059 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3060 SH_PFC_PIN_GROUP(msiof2_clk_a),
3061 SH_PFC_PIN_GROUP(msiof2_sync_a),
3062 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3063 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3064 SH_PFC_PIN_GROUP(msiof2_txd_a),
3065 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3066 SH_PFC_PIN_GROUP(msiof2_clk_b),
3067 SH_PFC_PIN_GROUP(msiof2_sync_b),
3068 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3069 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3070 SH_PFC_PIN_GROUP(msiof2_txd_b),
3071 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3072 SH_PFC_PIN_GROUP(msiof2_clk_c),
3073 SH_PFC_PIN_GROUP(msiof2_sync_c),
3074 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3075 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3076 SH_PFC_PIN_GROUP(msiof2_txd_c),
3077 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3078 SH_PFC_PIN_GROUP(msiof2_clk_d),
3079 SH_PFC_PIN_GROUP(msiof2_sync_d),
3080 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3081 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3082 SH_PFC_PIN_GROUP(msiof2_txd_d),
3083 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3084 SH_PFC_PIN_GROUP(msiof3_clk_a),
3085 SH_PFC_PIN_GROUP(msiof3_sync_a),
3086 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3087 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3088 SH_PFC_PIN_GROUP(msiof3_txd_a),
3089 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3090 SH_PFC_PIN_GROUP(msiof3_clk_b),
3091 SH_PFC_PIN_GROUP(msiof3_sync_b),
3092 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3093 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3094 SH_PFC_PIN_GROUP(msiof3_txd_b),
3095 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3096 SH_PFC_PIN_GROUP(msiof3_clk_c),
3097 SH_PFC_PIN_GROUP(msiof3_sync_c),
3098 SH_PFC_PIN_GROUP(msiof3_txd_c),
3099 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3100 SH_PFC_PIN_GROUP(msiof3_clk_d),
3101 SH_PFC_PIN_GROUP(msiof3_sync_d),
3102 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3103 SH_PFC_PIN_GROUP(msiof3_txd_d),
3104 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3105 SH_PFC_PIN_GROUP(msiof3_clk_e),
3106 SH_PFC_PIN_GROUP(msiof3_sync_e),
3107 SH_PFC_PIN_GROUP(msiof3_ss1_e),
3108 SH_PFC_PIN_GROUP(msiof3_ss2_e),
3109 SH_PFC_PIN_GROUP(msiof3_txd_e),
3110 SH_PFC_PIN_GROUP(msiof3_rxd_e),
c03a133b
LP		 3111 SH_PFC_PIN_GROUP(pwm0),
3112 SH_PFC_PIN_GROUP(pwm1_a),
3113 SH_PFC_PIN_GROUP(pwm1_b),
3114 SH_PFC_PIN_GROUP(pwm2_a),
3115 SH_PFC_PIN_GROUP(pwm2_b),
3116 SH_PFC_PIN_GROUP(pwm3_a),
3117 SH_PFC_PIN_GROUP(pwm3_b),
3118 SH_PFC_PIN_GROUP(pwm4_a),
3119 SH_PFC_PIN_GROUP(pwm4_b),
3120 SH_PFC_PIN_GROUP(pwm5_a),
3121 SH_PFC_PIN_GROUP(pwm5_b),
3122 SH_PFC_PIN_GROUP(pwm6_a),
3123 SH_PFC_PIN_GROUP(pwm6_b),
e7ad4d3c
GU		 3124 SH_PFC_PIN_GROUP(scif0_data),
3125 SH_PFC_PIN_GROUP(scif0_clk),
3126 SH_PFC_PIN_GROUP(scif0_ctrl),
3127 SH_PFC_PIN_GROUP(scif1_data_a),
3128 SH_PFC_PIN_GROUP(scif1_clk),
3129 SH_PFC_PIN_GROUP(scif1_ctrl),
3130 SH_PFC_PIN_GROUP(scif1_data_b),
3131 SH_PFC_PIN_GROUP(scif2_data_a),
3132 SH_PFC_PIN_GROUP(scif2_clk),
3133 SH_PFC_PIN_GROUP(scif2_data_b),
3134 SH_PFC_PIN_GROUP(scif3_data_a),
3135 SH_PFC_PIN_GROUP(scif3_clk),
3136 SH_PFC_PIN_GROUP(scif3_ctrl),
3137 SH_PFC_PIN_GROUP(scif3_data_b),
3138 SH_PFC_PIN_GROUP(scif4_data_a),
3139 SH_PFC_PIN_GROUP(scif4_clk_a),
3140 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3141 SH_PFC_PIN_GROUP(scif4_data_b),
3142 SH_PFC_PIN_GROUP(scif4_clk_b),
3143 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3144 SH_PFC_PIN_GROUP(scif4_data_c),
3145 SH_PFC_PIN_GROUP(scif4_clk_c),
3146 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3147 SH_PFC_PIN_GROUP(scif5_data_a),
3148 SH_PFC_PIN_GROUP(scif5_clk_a),
3149 SH_PFC_PIN_GROUP(scif5_data_b),
3150 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 3151 SH_PFC_PIN_GROUP(scif_clk_a),
3152 SH_PFC_PIN_GROUP(scif_clk_b),
9ed13958
TK		 3153 SH_PFC_PIN_GROUP(sdhi0_data1),
3154 SH_PFC_PIN_GROUP(sdhi0_data4),
3155 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3156 SH_PFC_PIN_GROUP(sdhi0_cd),
3157 SH_PFC_PIN_GROUP(sdhi0_wp),
3158 SH_PFC_PIN_GROUP(sdhi1_data1),
3159 SH_PFC_PIN_GROUP(sdhi1_data4),
3160 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3161 SH_PFC_PIN_GROUP(sdhi1_cd),
3162 SH_PFC_PIN_GROUP(sdhi1_wp),
3163 SH_PFC_PIN_GROUP(sdhi2_data1),
3164 SH_PFC_PIN_GROUP(sdhi2_data4),
3165 SH_PFC_PIN_GROUP(sdhi2_data8),
3166 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3167 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3168 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3169 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3170 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3171 SH_PFC_PIN_GROUP(sdhi2_ds),
3172 SH_PFC_PIN_GROUP(sdhi3_data1),
3173 SH_PFC_PIN_GROUP(sdhi3_data4),
3174 SH_PFC_PIN_GROUP(sdhi3_data8),
3175 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3176 SH_PFC_PIN_GROUP(sdhi3_cd),
3177 SH_PFC_PIN_GROUP(sdhi3_wp),
3178 SH_PFC_PIN_GROUP(sdhi3_ds),
933ddbe5
YS		 3179 SH_PFC_PIN_GROUP(usb0),
3180 SH_PFC_PIN_GROUP(usb1),
3181 SH_PFC_PIN_GROUP(usb2),
3182 SH_PFC_PIN_GROUP(usb2_ch3),
e7ad4d3c
GU		 3183};
3184
30c078de
GU		 3185static const char * const avb_groups[] = {
3186 "avb_link",
3187 "avb_magic",
3188 "avb_phy_int",
3189 "avb_mdc",
3190 "avb_mii",
3191 "avb_avtp_pps",
3192 "avb_avtp_match_a",
3193 "avb_avtp_capture_a",
3194 "avb_avtp_match_b",
3195 "avb_avtp_capture_b",
3196};
3197
a20a6585
LP		 3198static const char * const du_groups[] = {
3199 "du_rgb666",
3200 "du_rgb888",
3201 "du_clk_out_0",
3202 "du_clk_out_1",
3203 "du_sync",
3204 "du_oddf",
3205 "du_cde",
3206 "du_disp",
3207};
3208
3e6c7727
GU		 3209static const char * const msiof0_groups[] = {
3210 "msiof0_clk",
3211 "msiof0_sync",
3212 "msiof0_ss1",
3213 "msiof0_ss2",
3214 "msiof0_txd",
3215 "msiof0_rxd",
3216};
3217
3218static const char * const msiof1_groups[] = {
3219 "msiof1_clk_a",
3220 "msiof1_sync_a",
3221 "msiof1_ss1_a",
3222 "msiof1_ss2_a",
3223 "msiof1_txd_a",
3224 "msiof1_rxd_a",
3225 "msiof1_clk_b",
3226 "msiof1_sync_b",
3227 "msiof1_ss1_b",
3228 "msiof1_ss2_b",
3229 "msiof1_txd_b",
3230 "msiof1_rxd_b",
3231 "msiof1_clk_c",
3232 "msiof1_sync_c",
3233 "msiof1_ss1_c",
3234 "msiof1_ss2_c",
3235 "msiof1_txd_c",
3236 "msiof1_rxd_c",
3237 "msiof1_clk_d",
3238 "msiof1_sync_d",
3239 "msiof1_ss1_d",
3240 "msiof1_ss2_d",
3241 "msiof1_txd_d",
3242 "msiof1_rxd_d",
3243 "msiof1_clk_e",
3244 "msiof1_sync_e",
3245 "msiof1_ss1_e",
3246 "msiof1_ss2_e",
3247 "msiof1_txd_e",
3248 "msiof1_rxd_e",
3249 "msiof1_clk_f",
3250 "msiof1_sync_f",
3251 "msiof1_ss1_f",
3252 "msiof1_ss2_f",
3253 "msiof1_txd_f",
3254 "msiof1_rxd_f",
3255 "msiof1_clk_g",
3256 "msiof1_sync_g",
3257 "msiof1_ss1_g",
3258 "msiof1_ss2_g",
3259 "msiof1_txd_g",
3260 "msiof1_rxd_g",
3261};
3262
3263static const char * const msiof2_groups[] = {
3264 "msiof2_clk_a",
3265 "msiof2_sync_a",
3266 "msiof2_ss1_a",
3267 "msiof2_ss2_a",
3268 "msiof2_txd_a",
3269 "msiof2_rxd_a",
3270 "msiof2_clk_b",
3271 "msiof2_sync_b",
3272 "msiof2_ss1_b",
3273 "msiof2_ss2_b",
3274 "msiof2_txd_b",
3275 "msiof2_rxd_b",
3276 "msiof2_clk_c",
3277 "msiof2_sync_c",
3278 "msiof2_ss1_c",
3279 "msiof2_ss2_c",
3280 "msiof2_txd_c",
3281 "msiof2_rxd_c",
3282 "msiof2_clk_d",
3283 "msiof2_sync_d",
3284 "msiof2_ss1_d",
3285 "msiof2_ss2_d",
3286 "msiof2_txd_d",
3287 "msiof2_rxd_d",
3288};
3289
3290static const char * const msiof3_groups[] = {
3291 "msiof3_clk_a",
3292 "msiof3_sync_a",
3293 "msiof3_ss1_a",
3294 "msiof3_ss2_a",
3295 "msiof3_txd_a",
3296 "msiof3_rxd_a",
3297 "msiof3_clk_b",
3298 "msiof3_sync_b",
3299 "msiof3_ss1_b",
3300 "msiof3_ss2_b",
3301 "msiof3_txd_b",
3302 "msiof3_rxd_b",
3303 "msiof3_clk_c",
3304 "msiof3_sync_c",
3305 "msiof3_txd_c",
3306 "msiof3_rxd_c",
3307 "msiof3_clk_d",
3308 "msiof3_sync_d",
3309 "msiof3_ss1_d",
3310 "msiof3_txd_d",
3311 "msiof3_rxd_d",
3312 "msiof3_clk_e",
3313 "msiof3_sync_e",
3314 "msiof3_ss1_e",
3315 "msiof3_ss2_e",
3316 "msiof3_txd_e",
3317 "msiof3_rxd_e",
3318};
3319
c03a133b
LP		 3320static const char * const pwm0_groups[] = {
3321 "pwm0",
3322};
3323
3324static const char * const pwm1_groups[] = {
3325 "pwm1_a",
3326 "pwm1_b",
3327};
3328
3329static const char * const pwm2_groups[] = {
3330 "pwm2_a",
3331 "pwm2_b",
3332};
3333
3334static const char * const pwm3_groups[] = {
3335 "pwm3_a",
3336 "pwm3_b",
3337};
3338
3339static const char * const pwm4_groups[] = {
3340 "pwm4_a",
3341 "pwm4_b",
3342};
3343
3344static const char * const pwm5_groups[] = {
3345 "pwm5_a",
3346 "pwm5_b",
3347};
3348
3349static const char * const pwm6_groups[] = {
3350 "pwm6_a",
3351 "pwm6_b",
3352};
3353
e7ad4d3c
GU		 3354static const char * const scif0_groups[] = {
3355 "scif0_data",
3356 "scif0_clk",
3357 "scif0_ctrl",
3358};
3359
3360static const char * const scif1_groups[] = {
3361 "scif1_data_a",
3362 "scif1_clk",
3363 "scif1_ctrl",
3364 "scif1_data_b",
3365};
3366
3367static const char * const scif2_groups[] = {
3368 "scif2_data_a",
3369 "scif2_clk",
3370 "scif2_data_b",
3371};
3372
3373static const char * const scif3_groups[] = {
3374 "scif3_data_a",
3375 "scif3_clk",
3376 "scif3_ctrl",
3377 "scif3_data_b",
3378};
3379
3380static const char * const scif4_groups[] = {
3381 "scif4_data_a",
3382 "scif4_clk_a",
3383 "scif4_ctrl_a",
3384 "scif4_data_b",
3385 "scif4_clk_b",
3386 "scif4_ctrl_b",
3387 "scif4_data_c",
3388 "scif4_clk_c",
3389 "scif4_ctrl_c",
3390};
3391
3392static const char * const scif5_groups[] = {
3393 "scif5_data_a",
3394 "scif5_clk_a",
3395 "scif5_data_b",
3396 "scif5_clk_b",
76250a6c
TK		 3397};
3398
d14a39ed
GU		 3399static const char * const scif_clk_groups[] = {
3400 "scif_clk_a",
3401 "scif_clk_b",
3402};
3403
9ed13958
TK		 3404static const char * const sdhi0_groups[] = {
3405 "sdhi0_data1",
3406 "sdhi0_data4",
3407 "sdhi0_ctrl",
3408 "sdhi0_cd",
3409 "sdhi0_wp",
3410};
3411
3412static const char * const sdhi1_groups[] = {
3413 "sdhi1_data1",
3414 "sdhi1_data4",
3415 "sdhi1_ctrl",
3416 "sdhi1_cd",
3417 "sdhi1_wp",
3418};
3419
3420static const char * const sdhi2_groups[] = {
3421 "sdhi2_data1",
3422 "sdhi2_data4",
3423 "sdhi2_data8",
3424 "sdhi2_ctrl",
3425 "sdhi2_cd_a",
3426 "sdhi2_wp_a",
3427 "sdhi2_cd_b",
3428 "sdhi2_wp_b",
3429 "sdhi2_ds",
3430};
3431
3432static const char * const sdhi3_groups[] = {
3433 "sdhi3_data1",
3434 "sdhi3_data4",
3435 "sdhi3_data8",
3436 "sdhi3_ctrl",
3437 "sdhi3_cd",
3438 "sdhi3_wp",
3439 "sdhi3_ds",
3440};
3441
933ddbe5
YS		 3442static const char * const usb0_groups[] = {
3443 "usb0",
3444};
3445
3446static const char * const usb1_groups[] = {
3447 "usb1",
3448};
3449
3450static const char * const usb2_groups[] = {
3451 "usb2",
3452};
3453
3454static const char * const usb2_ch3_groups[] = {
3455 "usb2_ch3",
3456};
3457
0b0ffc96 3458static const struct sh_pfc_function pinmux_functions[] = {
30c078de 3459 SH_PFC_FUNCTION(avb),
a20a6585 3460 SH_PFC_FUNCTION(du),
3e6c7727
GU		 3461 SH_PFC_FUNCTION(msiof0),
3462 SH_PFC_FUNCTION(msiof1),
3463 SH_PFC_FUNCTION(msiof2),
3464 SH_PFC_FUNCTION(msiof3),
c03a133b
LP		 3465 SH_PFC_FUNCTION(pwm0),
3466 SH_PFC_FUNCTION(pwm1),
3467 SH_PFC_FUNCTION(pwm2),
3468 SH_PFC_FUNCTION(pwm3),
3469 SH_PFC_FUNCTION(pwm4),
3470 SH_PFC_FUNCTION(pwm5),
3471 SH_PFC_FUNCTION(pwm6),
e7ad4d3c
GU		 3472 SH_PFC_FUNCTION(scif0),
3473 SH_PFC_FUNCTION(scif1),
3474 SH_PFC_FUNCTION(scif2),
3475 SH_PFC_FUNCTION(scif3),
3476 SH_PFC_FUNCTION(scif4),
3477 SH_PFC_FUNCTION(scif5),
d14a39ed 3478 SH_PFC_FUNCTION(scif_clk),
9ed13958
TK		 3479 SH_PFC_FUNCTION(sdhi0),
3480 SH_PFC_FUNCTION(sdhi1),
3481 SH_PFC_FUNCTION(sdhi2),
3482 SH_PFC_FUNCTION(sdhi3),
933ddbe5
YS		 3483 SH_PFC_FUNCTION(usb0),
3484 SH_PFC_FUNCTION(usb1),
3485 SH_PFC_FUNCTION(usb2),
3486 SH_PFC_FUNCTION(usb2_ch3),
0b0ffc96
TK		 3487};
3488
3489static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3490#define F_(x, y) FN_##y
3491#define FM(x) FN_##x
3492 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
3493 0, 0,
3494 0, 0,
3495 0, 0,
3496 0, 0,
3497 0, 0,
3498 0, 0,
3499 0, 0,
3500 0, 0,
3501 0, 0,
3502 0, 0,
3503 0, 0,
3504 0, 0,
3505 0, 0,
3506 0, 0,
3507 0, 0,
3508 0, 0,
3509 GP_0_15_FN, GPSR0_15,
3510 GP_0_14_FN, GPSR0_14,
3511 GP_0_13_FN, GPSR0_13,
3512 GP_0_12_FN, GPSR0_12,
3513 GP_0_11_FN, GPSR0_11,
3514 GP_0_10_FN, GPSR0_10,
3515 GP_0_9_FN, GPSR0_9,
3516 GP_0_8_FN, GPSR0_8,
3517 GP_0_7_FN, GPSR0_7,
3518 GP_0_6_FN, GPSR0_6,
3519 GP_0_5_FN, GPSR0_5,
3520 GP_0_4_FN, GPSR0_4,
3521 GP_0_3_FN, GPSR0_3,
3522 GP_0_2_FN, GPSR0_2,
3523 GP_0_1_FN, GPSR0_1,
3524 GP_0_0_FN, GPSR0_0, }
3525 },
3526 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
3527 0, 0,
3528 0, 0,
3529 0, 0,
3530 0, 0,
3531 GP_1_27_FN, GPSR1_27,
3532 GP_1_26_FN, GPSR1_26,
3533 GP_1_25_FN, GPSR1_25,
3534 GP_1_24_FN, GPSR1_24,
3535 GP_1_23_FN, GPSR1_23,
3536 GP_1_22_FN, GPSR1_22,
3537 GP_1_21_FN, GPSR1_21,
3538 GP_1_20_FN, GPSR1_20,
3539 GP_1_19_FN, GPSR1_19,
3540 GP_1_18_FN, GPSR1_18,
3541 GP_1_17_FN, GPSR1_17,
3542 GP_1_16_FN, GPSR1_16,
3543 GP_1_15_FN, GPSR1_15,
3544 GP_1_14_FN, GPSR1_14,
3545 GP_1_13_FN, GPSR1_13,
3546 GP_1_12_FN, GPSR1_12,
3547 GP_1_11_FN, GPSR1_11,
3548 GP_1_10_FN, GPSR1_10,
3549 GP_1_9_FN, GPSR1_9,
3550 GP_1_8_FN, GPSR1_8,
3551 GP_1_7_FN, GPSR1_7,
3552 GP_1_6_FN, GPSR1_6,
3553 GP_1_5_FN, GPSR1_5,
3554 GP_1_4_FN, GPSR1_4,
3555 GP_1_3_FN, GPSR1_3,
3556 GP_1_2_FN, GPSR1_2,
3557 GP_1_1_FN, GPSR1_1,
3558 GP_1_0_FN, GPSR1_0, }
3559 },
3560 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
3561 0, 0,
3562 0, 0,
3563 0, 0,
3564 0, 0,
3565 0, 0,
3566 0, 0,
3567 0, 0,
3568 0, 0,
3569 0, 0,
3570 0, 0,
3571 0, 0,
3572 0, 0,
3573 0, 0,
3574 0, 0,
3575 0, 0,
3576 0, 0,
3577 0, 0,
3578 GP_2_14_FN, GPSR2_14,
3579 GP_2_13_FN, GPSR2_13,
3580 GP_2_12_FN, GPSR2_12,
3581 GP_2_11_FN, GPSR2_11,
3582 GP_2_10_FN, GPSR2_10,
3583 GP_2_9_FN, GPSR2_9,
3584 GP_2_8_FN, GPSR2_8,
3585 GP_2_7_FN, GPSR2_7,
3586 GP_2_6_FN, GPSR2_6,
3587 GP_2_5_FN, GPSR2_5,
3588 GP_2_4_FN, GPSR2_4,
3589 GP_2_3_FN, GPSR2_3,
3590 GP_2_2_FN, GPSR2_2,
3591 GP_2_1_FN, GPSR2_1,
3592 GP_2_0_FN, GPSR2_0, }
3593 },
3594 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
3595 0, 0,
3596 0, 0,
3597 0, 0,
3598 0, 0,
3599 0, 0,
3600 0, 0,
3601 0, 0,
3602 0, 0,
3603 0, 0,
3604 0, 0,
3605 0, 0,
3606 0, 0,
3607 0, 0,
3608 0, 0,
3609 0, 0,
3610 0, 0,
3611 GP_3_15_FN, GPSR3_15,
3612 GP_3_14_FN, GPSR3_14,
3613 GP_3_13_FN, GPSR3_13,
3614 GP_3_12_FN, GPSR3_12,
3615 GP_3_11_FN, GPSR3_11,
3616 GP_3_10_FN, GPSR3_10,
3617 GP_3_9_FN, GPSR3_9,
3618 GP_3_8_FN, GPSR3_8,
3619 GP_3_7_FN, GPSR3_7,
3620 GP_3_6_FN, GPSR3_6,
3621 GP_3_5_FN, GPSR3_5,
3622 GP_3_4_FN, GPSR3_4,
3623 GP_3_3_FN, GPSR3_3,
3624 GP_3_2_FN, GPSR3_2,
3625 GP_3_1_FN, GPSR3_1,
3626 GP_3_0_FN, GPSR3_0, }
3627 },
3628 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
3629 0, 0,
3630 0, 0,
3631 0, 0,
3632 0, 0,
3633 0, 0,
3634 0, 0,
3635 0, 0,
3636 0, 0,
3637 0, 0,
3638 0, 0,
3639 0, 0,
3640 0, 0,
3641 0, 0,
3642 0, 0,
3643 GP_4_17_FN, GPSR4_17,
3644 GP_4_16_FN, GPSR4_16,
3645 GP_4_15_FN, GPSR4_15,
3646 GP_4_14_FN, GPSR4_14,
3647 GP_4_13_FN, GPSR4_13,
3648 GP_4_12_FN, GPSR4_12,
3649 GP_4_11_FN, GPSR4_11,
3650 GP_4_10_FN, GPSR4_10,
3651 GP_4_9_FN, GPSR4_9,
3652 GP_4_8_FN, GPSR4_8,
3653 GP_4_7_FN, GPSR4_7,
3654 GP_4_6_FN, GPSR4_6,
3655 GP_4_5_FN, GPSR4_5,
3656 GP_4_4_FN, GPSR4_4,
3657 GP_4_3_FN, GPSR4_3,
3658 GP_4_2_FN, GPSR4_2,
3659 GP_4_1_FN, GPSR4_1,
3660 GP_4_0_FN, GPSR4_0, }
3661 },
3662 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
3663 0, 0,
3664 0, 0,
3665 0, 0,
3666 0, 0,
3667 0, 0,
3668 0, 0,
3669 GP_5_25_FN, GPSR5_25,
3670 GP_5_24_FN, GPSR5_24,
3671 GP_5_23_FN, GPSR5_23,
3672 GP_5_22_FN, GPSR5_22,
3673 GP_5_21_FN, GPSR5_21,
3674 GP_5_20_FN, GPSR5_20,
3675 GP_5_19_FN, GPSR5_19,
3676 GP_5_18_FN, GPSR5_18,
3677 GP_5_17_FN, GPSR5_17,
3678 GP_5_16_FN, GPSR5_16,
3679 GP_5_15_FN, GPSR5_15,
3680 GP_5_14_FN, GPSR5_14,
3681 GP_5_13_FN, GPSR5_13,
3682 GP_5_12_FN, GPSR5_12,
3683 GP_5_11_FN, GPSR5_11,
3684 GP_5_10_FN, GPSR5_10,
3685 GP_5_9_FN, GPSR5_9,
3686 GP_5_8_FN, GPSR5_8,
3687 GP_5_7_FN, GPSR5_7,
3688 GP_5_6_FN, GPSR5_6,
3689 GP_5_5_FN, GPSR5_5,
3690 GP_5_4_FN, GPSR5_4,
3691 GP_5_3_FN, GPSR5_3,
3692 GP_5_2_FN, GPSR5_2,
3693 GP_5_1_FN, GPSR5_1,
3694 GP_5_0_FN, GPSR5_0, }
3695 },
3696 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
3697 GP_6_31_FN, GPSR6_31,
3698 GP_6_30_FN, GPSR6_30,
3699 GP_6_29_FN, GPSR6_29,
3700 GP_6_28_FN, GPSR6_28,
3701 GP_6_27_FN, GPSR6_27,
3702 GP_6_26_FN, GPSR6_26,
3703 GP_6_25_FN, GPSR6_25,
3704 GP_6_24_FN, GPSR6_24,
3705 GP_6_23_FN, GPSR6_23,
3706 GP_6_22_FN, GPSR6_22,
3707 GP_6_21_FN, GPSR6_21,
3708 GP_6_20_FN, GPSR6_20,
3709 GP_6_19_FN, GPSR6_19,
3710 GP_6_18_FN, GPSR6_18,
3711 GP_6_17_FN, GPSR6_17,
3712 GP_6_16_FN, GPSR6_16,
3713 GP_6_15_FN, GPSR6_15,
3714 GP_6_14_FN, GPSR6_14,
3715 GP_6_13_FN, GPSR6_13,
3716 GP_6_12_FN, GPSR6_12,
3717 GP_6_11_FN, GPSR6_11,
3718 GP_6_10_FN, GPSR6_10,
3719 GP_6_9_FN, GPSR6_9,
3720 GP_6_8_FN, GPSR6_8,
3721 GP_6_7_FN, GPSR6_7,
3722 GP_6_6_FN, GPSR6_6,
3723 GP_6_5_FN, GPSR6_5,
3724 GP_6_4_FN, GPSR6_4,
3725 GP_6_3_FN, GPSR6_3,
3726 GP_6_2_FN, GPSR6_2,
3727 GP_6_1_FN, GPSR6_1,
3728 GP_6_0_FN, GPSR6_0, }
3729 },
3730 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
3731 0, 0,
3732 0, 0,
3733 0, 0,
3734 0, 0,
3735 0, 0,
3736 0, 0,
3737 0, 0,
3738 0, 0,
3739 0, 0,
3740 0, 0,
3741 0, 0,
3742 0, 0,
3743 0, 0,
3744 0, 0,
3745 0, 0,
3746 0, 0,
3747 0, 0,
3748 0, 0,
3749 0, 0,
3750 0, 0,
3751 0, 0,
3752 0, 0,
3753 0, 0,
3754 0, 0,
3755 0, 0,
3756 0, 0,
3757 0, 0,
3758 0, 0,
3759 GP_7_3_FN, GPSR7_3,
3760 GP_7_2_FN, GPSR7_2,
3761 GP_7_1_FN, GPSR7_1,
3762 GP_7_0_FN, GPSR7_0, }
3763 },
3764#undef F_
3765#undef FM
3766
3767#define F_(x, y) x,
3768#define FM(x) FN_##x,
3769 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
3770 IP0_31_28
3771 IP0_27_24
3772 IP0_23_20
3773 IP0_19_16
3774 IP0_15_12
3775 IP0_11_8
3776 IP0_7_4
3777 IP0_3_0 }
3778 },
3779 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
3780 IP1_31_28
3781 IP1_27_24
3782 IP1_23_20
3783 IP1_19_16
3784 IP1_15_12
3785 IP1_11_8
3786 IP1_7_4
3787 IP1_3_0 }
3788 },
3789 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
3790 IP2_31_28
3791 IP2_27_24
3792 IP2_23_20
3793 IP2_19_16
3794 IP2_15_12
3795 IP2_11_8
3796 IP2_7_4
3797 IP2_3_0 }
3798 },
3799 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
3800 IP3_31_28
3801 IP3_27_24
3802 IP3_23_20
3803 IP3_19_16
3804 IP3_15_12
3805 IP3_11_8
3806 IP3_7_4
3807 IP3_3_0 }
3808 },
3809 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
3810 IP4_31_28
3811 IP4_27_24
3812 IP4_23_20
3813 IP4_19_16
3814 IP4_15_12
3815 IP4_11_8
3816 IP4_7_4
3817 IP4_3_0 }
3818 },
3819 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
3820 IP5_31_28
3821 IP5_27_24
3822 IP5_23_20
3823 IP5_19_16
3824 IP5_15_12
3825 IP5_11_8
3826 IP5_7_4
3827 IP5_3_0 }
3828 },
3829 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
3830 IP6_31_28
3831 IP6_27_24
3832 IP6_23_20
3833 IP6_19_16
3834 IP6_15_12
3835 IP6_11_8
3836 IP6_7_4
3837 IP6_3_0 }
3838 },
3839 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
3840 IP7_31_28
3841 IP7_27_24
3842 IP7_23_20
3843 IP7_19_16
30cd1c46 3844 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 3845 IP7_11_8
3846 IP7_7_4
3847 IP7_3_0 }
3848 },
3849 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
3850 IP8_31_28
3851 IP8_27_24
3852 IP8_23_20
3853 IP8_19_16
3854 IP8_15_12
3855 IP8_11_8
3856 IP8_7_4
3857 IP8_3_0 }
3858 },
3859 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
3860 IP9_31_28
3861 IP9_27_24
3862 IP9_23_20
3863 IP9_19_16
3864 IP9_15_12
3865 IP9_11_8
3866 IP9_7_4
3867 IP9_3_0 }
3868 },
3869 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
3870 IP10_31_28
3871 IP10_27_24
3872 IP10_23_20
3873 IP10_19_16
3874 IP10_15_12
3875 IP10_11_8
3876 IP10_7_4
3877 IP10_3_0 }
3878 },
3879 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
3880 IP11_31_28
3881 IP11_27_24
3882 IP11_23_20
3883 IP11_19_16
3884 IP11_15_12
3885 IP11_11_8
3886 IP11_7_4
3887 IP11_3_0 }
3888 },
3889 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
3890 IP12_31_28
3891 IP12_27_24
3892 IP12_23_20
3893 IP12_19_16
3894 IP12_15_12
3895 IP12_11_8
3896 IP12_7_4
3897 IP12_3_0 }
3898 },
3899 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
3900 IP13_31_28
3901 IP13_27_24
3902 IP13_23_20
3903 IP13_19_16
3904 IP13_15_12
3905 IP13_11_8
3906 IP13_7_4
3907 IP13_3_0 }
3908 },
3909 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
3910 IP14_31_28
3911 IP14_27_24
3912 IP14_23_20
3913 IP14_19_16
3914 IP14_15_12
3915 IP14_11_8
3916 IP14_7_4
3917 IP14_3_0 }
3918 },
3919 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
3920 IP15_31_28
3921 IP15_27_24
3922 IP15_23_20
3923 IP15_19_16
3924 IP15_15_12
3925 IP15_11_8
3926 IP15_7_4
3927 IP15_3_0 }
3928 },
3929 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
3930 IP16_31_28
3931 IP16_27_24
3932 IP16_23_20
3933 IP16_19_16
3934 IP16_15_12
3935 IP16_11_8
3936 IP16_7_4
3937 IP16_3_0 }
3938 },
3939 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
b205914c
GU		 3940 IP17_31_28
3941 IP17_27_24
3942 IP17_23_20
3943 IP17_19_16
3944 IP17_15_12
3945 IP17_11_8
0b0ffc96
TK		 3946 IP17_7_4
3947 IP17_3_0 }
3948 },
b205914c
GU		 3949 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
3950 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3951 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3952 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3953 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3954 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3955 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3956 IP18_7_4
3957 IP18_3_0 }
3958 },
0b0ffc96
TK		 3959#undef F_
3960#undef FM
3961
3962#define F_(x, y) x,
3963#define FM(x) FN_##x,
3964 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
b205914c
GU		 3965 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
3966 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
3967 MOD_SEL0_31_30_29
0b0ffc96
TK		 3968 MOD_SEL0_28_27
3969 MOD_SEL0_26_25_24
3970 MOD_SEL0_23
3971 MOD_SEL0_22
b205914c
GU		 3972 MOD_SEL0_21
3973 MOD_SEL0_20
0b0ffc96 3974 MOD_SEL0_19
b205914c
GU		 3975 MOD_SEL0_18_17
3976 MOD_SEL0_16
3977 0, 0, /* RESERVED 15 */
3978 MOD_SEL0_14_13
0b0ffc96
TK		 3979 MOD_SEL0_12
3980 MOD_SEL0_11
3981 MOD_SEL0_10
b205914c 3982 MOD_SEL0_9_8
0b0ffc96 3983 MOD_SEL0_7_6
b205914c
GU		 3984 MOD_SEL0_5
3985 MOD_SEL0_4_3
3986 /* RESERVED 2, 1, 0 */
3987 0, 0, 0, 0, 0, 0, 0, 0 }
0b0ffc96
TK		 3988 },
3989 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
3990 2, 3, 1, 2, 3, 1, 1, 2, 1,
3991 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
3992 MOD_SEL1_31_30
3993 MOD_SEL1_29_28_27
3994 MOD_SEL1_26
3995 MOD_SEL1_25_24
3996 MOD_SEL1_23_22_21
3997 MOD_SEL1_20
3998 MOD_SEL1_19
3999 MOD_SEL1_18_17
4000 MOD_SEL1_16
4001 MOD_SEL1_15_14
4002 MOD_SEL1_13
4003 MOD_SEL1_12
4004 MOD_SEL1_11
4005 MOD_SEL1_10
4006 MOD_SEL1_9
4007 0, 0, 0, 0, /* RESERVED 8, 7 */
4008 MOD_SEL1_6
4009 MOD_SEL1_5
4010 MOD_SEL1_4
4011 MOD_SEL1_3
4012 MOD_SEL1_2
4013 MOD_SEL1_1
4014 MOD_SEL1_0 }
4015 },
4016 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
b205914c
GU		 4017 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4018 4, 4, 4, 3, 1) {
0b0ffc96
TK		 4019 MOD_SEL2_31
4020 MOD_SEL2_30
4021 MOD_SEL2_29
b205914c
GU		 4022 MOD_SEL2_28_27
4023 MOD_SEL2_26
4024 MOD_SEL2_25_24_23
3c612d2c
TK		 4025 /* RESERVED 22 */
4026 0, 0,
b205914c
GU		 4027 MOD_SEL2_21
4028 MOD_SEL2_20
4029 MOD_SEL2_19
4030 MOD_SEL2_18
4031 MOD_SEL2_17
4032 /* RESERVED 16 */
0b0ffc96 4033 0, 0,
0b0ffc96
TK		 4034 /* RESERVED 15, 14, 13, 12 */
4035 0, 0, 0, 0, 0, 0, 0, 0,
4036 0, 0, 0, 0, 0, 0, 0, 0,
4037 /* RESERVED 11, 10, 9, 8 */
4038 0, 0, 0, 0, 0, 0, 0, 0,
4039 0, 0, 0, 0, 0, 0, 0, 0,
4040 /* RESERVED 7, 6, 5, 4 */
4041 0, 0, 0, 0, 0, 0, 0, 0,
4042 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 4043 /* RESERVED 3, 2, 1 */
4044 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 4045 MOD_SEL2_0 }
4046 },
4047 { },
4048};
4049
92e6d9a2 4050static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 4051 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
4052 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
4053 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
4054 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
4055 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
4056 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
4057 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
4058 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
4059 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
4060 } },
4061 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
4062 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
4063 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
4064 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
4065 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
4066 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
4067 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
4068 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
4069 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
4070 } },
4071 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
4072 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
4073 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
4074 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
4075 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
4076 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
4077 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
4078 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
4079 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
4080 } },
92e6d9a2 4081 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 4082 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
4083 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
4084 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
4085 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
4086 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
4087 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4088 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4089 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 4090 } },
4091 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4092 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4093 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4094 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4095 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4096 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4097 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4098 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4099 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4100 } },
4101 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4102 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4103 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4104 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4105 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4106 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4107 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4108 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4109 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4110 } },
4111 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4112 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4113 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4114 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4115 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4116 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4117 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4118 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4119 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4120 } },
4121 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4122 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4123 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4124 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4125 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4126 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4127 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4128 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4129 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4130 } },
4131 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
ea9c7405 4132 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 4133 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4134 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4135 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4136 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4137 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4138 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4139 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4140 } },
4141 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4142 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 4143 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 4144 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4145 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4146 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4147 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4148 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4149 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4150 } },
4151 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4152 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4153 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4154 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4155 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4156 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4157 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4158 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4159 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4160 } },
4161 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 4162 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4163 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4164 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4165 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4166 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4167 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
4168 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
4169 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
4170 } },
4171 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
4172 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
4173 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
4174 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
4175 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 4176 } },
4177 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 4178 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
4179 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
4180 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4181 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4182 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4183 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4184 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4185 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 4186 } },
4187 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4188 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4189 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4190 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4191 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4192 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4193 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4194 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4195 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4196 } },
4197 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4198 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4199 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4200 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4201 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4202 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4203 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4204 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4205 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4206 } },
4207 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4208 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4209 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4210 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4211 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4212 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4213 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4214 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4215 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4216 } },
4217 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4218 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4219 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4220 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4221 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4222 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4223 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4224 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4225 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4226 } },
4227 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4228 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
4229 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4230 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4231 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4232 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
4233 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4234 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4235 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4236 } },
4237 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4238 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
4239 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
4240 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
4241 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
4242 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
4243 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
4244 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
4245 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
4246 } },
4247 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4248 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
4249 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
4250 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
4251 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
4252 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
4253 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 4254 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 4255 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
4256 } },
4257 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4258 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
4259 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
4260 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
4261 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 4262 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
4263 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 4264 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
4265 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
4266 } },
4267 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4268 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
4269 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
4270 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
4271 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4272 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4273 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4274 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4275 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4276 } },
4277 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4278 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4279 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4280 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4281 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4282 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4283 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4284 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4285 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4286 } },
4287 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4288 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4289 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4290 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4291 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4292 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
f9d13080
YS		 4293 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
4294 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
92e6d9a2
LP		 4295 } },
4296 { },
4297};
4298
e9eace32
WS		 4299static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4300{
4301 int bit = -EINVAL;
4302
4303 *pocctrl = 0xe6060380;
4304
4305 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4306 bit = pin & 0x1f;
4307
4308 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4309 bit = (pin & 0x1f) + 12;
4310
4311 return bit;
4312}
4313
56065524
UH		 4314#define PUEN 0xe6060400
4315#define PUD 0xe6060440
4316
4317#define PU0 0x00
4318#define PU1 0x04
4319#define PU2 0x08
4320#define PU3 0x0c
4321#define PU4 0x10
4322#define PU5 0x14
4323#define PU6 0x18
4324
d3b861bc 4325static const struct sh_pfc_bias_info bias_info[] = {
4c2fb44d
NS		 4326 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
4327 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
4328 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
4329 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
4330 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
4331 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
4332 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
4333 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
4334 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
4335 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
4336 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
4337 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
4338 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
4339 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
4340 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
4341 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
4342 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
4343 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
4344 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
4345 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
4346 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
4347 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
4348 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
4349 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
4350 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
4351 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
4352 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
4353 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
4354 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
4355 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
4356 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
4357 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
4358
4359 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
4360 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
4361 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
4362 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
4363 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
4364 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
4365 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
4366 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
4367 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
4368 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
4369 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
4370 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
4371 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
4372 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
4373 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
4374 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
4375 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
4376 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
4377 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
4378 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
4379 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
4380 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
4381 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
4382 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
4383 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
4384 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
4385 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
4386 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
4387 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
4388 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
4389 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
4390 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
4391
4392 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
4393 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
4394 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
4395 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
4396 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
4397 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
4398 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
4399 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
4400 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
4401 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
4402 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
4403 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
4404 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
4405 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
4406 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
4407 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
4408 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
4409 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
4410 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
4411 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
4412 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
4413 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
4414 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
4415 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
4416 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
4417 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
4418 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
4419 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
4420 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
fc8fd9be 4421 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
4c2fb44d
NS		 4422 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
4423 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
4424
4425 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
4426 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
4427 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
4428 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
4429 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
4430 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
4431 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
4432 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
4433 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
4434 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
4435 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
4436 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
4437 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
4438 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
4439 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
4440 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
4441 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
4442 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
4443 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
4444 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
4445 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
4446 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
4447 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
4448 /* bit 8 n/a */
4449 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
4450 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
4451 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
4452 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
4453 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
4454 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
4455 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
4456 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
4457
4458 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
4459 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
4460 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
4461 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
4462 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
4463 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
4464 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
4465 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
4466 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
4467 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
4468 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
4469 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
4470 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
4471 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
4472 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
4473 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
4474 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
4475 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
4476 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
4477 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
4478 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
4479 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
4480 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
4481 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
4482 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
4483 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
4484 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
4485 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
4486 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
4487 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
4488 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
4489 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
4490
4491 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
4492 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
4493 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
4494 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
4495 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
4496 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
4497 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
4498 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
4499 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
4500 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
4501 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
4502 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
4503 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
4504 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
4505 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
4506 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
4507 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
4508 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
68e63892
KM		 4509 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
4510 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
4c2fb44d
NS		 4511 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
4512 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
4513 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
4514 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
4515 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
4516 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
4517 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
4518 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
4519 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
4520 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
4521 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
4522 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
4523
f9d13080
YS		 4524 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */
4525 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */
4c2fb44d
NS		 4526 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
4527 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
4528 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
4529 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
4530 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
56065524
UH		 4531};
4532
4533static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
4534 unsigned int pin)
4535{
d3b861bc 4536 const struct sh_pfc_bias_info *info;
56065524
UH		 4537 u32 reg;
4538 u32 bit;
4539
d3b861bc
NS		 4540 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
4541 if (!info)
56065524
UH		 4542 return PIN_CONFIG_BIAS_DISABLE;
4543
d3b861bc
NS		 4544 reg = info->reg;
4545 bit = BIT(info->bit);
56065524 4546
42831cf9 4547 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
56065524 4548 return PIN_CONFIG_BIAS_DISABLE;
42831cf9
NS		 4549 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
4550 return PIN_CONFIG_BIAS_PULL_UP;
4551 else
4552 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 4553}
4554
4555static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4556 unsigned int bias)
4557{
d3b861bc 4558 const struct sh_pfc_bias_info *info;
56065524
UH		 4559 u32 enable, updown;
4560 u32 reg;
4561 u32 bit;
4562
d3b861bc
NS		 4563 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
4564 if (!info)
56065524
UH		 4565 return;
4566
d3b861bc
NS		 4567 reg = info->reg;
4568 bit = BIT(info->bit);
56065524
UH		 4569
4570 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
4571 if (bias != PIN_CONFIG_BIAS_DISABLE)
4572 enable |= bit;
4573
4574 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
4575 if (bias == PIN_CONFIG_BIAS_PULL_UP)
4576 updown |= bit;
4577
4578 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
4579 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
4580}
4581
b205914c
GU		 4582static const struct soc_device_attribute r8a7795es1[] = {
4583 { .soc_id = "r8a7795", .revision = "ES1.*" },
4584 { /* sentinel */ }
4585};
4586
4587static int r8a7795_pinmux_init(struct sh_pfc *pfc)
4588{
4589 if (soc_device_match(r8a7795es1))
4590 pfc->info = &r8a7795es1_pinmux_info;
4591
4592 return 0;
4593}
4594
e9eace32 4595static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 4596 .init = r8a7795_pinmux_init,
e9eace32 4597 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 4598 .get_bias = r8a7795_pinmux_get_bias,
4599 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 4600};
4601
0b0ffc96 4602const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 4603 .name = "r8a77951_pfc",
e9eace32 4604 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 4605 .unlock_reg = 0xe6060000, /* PMMR */
4606
4607 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4608
4609 .pins = pinmux_pins,
4610 .nr_pins = ARRAY_SIZE(pinmux_pins),
4611 .groups = pinmux_groups,
4612 .nr_groups = ARRAY_SIZE(pinmux_groups),
4613 .functions = pinmux_functions,
4614 .nr_functions = ARRAY_SIZE(pinmux_functions),
4615
4616 .cfg_regs = pinmux_config_regs,
92e6d9a2 4617 .drive_regs = pinmux_drive_regs,
0b0ffc96 4618
b8b47d67
GU		 4619 .pinmux_data = pinmux_data,
4620 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 4621};
Linux 6.x block layer and io_uring tree(s)