projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
CommitLineData
0b0ffc96 1/*
b205914c 2 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 3 *
b205914c 4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
0b0ffc96
TK		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
b205914c 12#include <linux/sys_soc.h>
0b0ffc96
TK		 13
14#include "core.h"
15#include "sh_pfc.h"
16
56065524
UH		 17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
0b0ffc96 21#define CPU_ALL_PORT(fn, sfx) \
56065524
UH		 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
64#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
b205914c
GU		 105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
b205914c
GU		 123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
b205914c
GU		 143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 146#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 148#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 151#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
160#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
164#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 169
170/* GPSR6 */
f9d13080
YS		 171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
b205914c
GU		 173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 203
204/* GPSR7 */
205#define GPSR7_3 FM(HDMI1_CEC)
206#define GPSR7_2 FM(HDMI0_CEC)
207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96 217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
e2ab1770
TK		 218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 283#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 307
308/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
b205914c
GU		 309#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337
338/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
68e63892
KM		 342#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 344#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
f9d13080
YS		 364#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
365#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
0b0ffc96
TK		 366
367#define PINMUX_GPSR \
368\
369 GPSR6_31 \
370 GPSR6_30 \
371 GPSR6_29 \
372 GPSR6_28 \
373 GPSR1_27 GPSR6_27 \
374 GPSR1_26 GPSR6_26 \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
401
402#define PINMUX_IPSR \
403\
404FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412\
413FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
416FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
417FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421\
422FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430\
431FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439\
b205914c
GU		 440FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 448
449/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 450#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 451#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 455#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 468
469/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
473#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
fd1aa743 483#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
0b0ffc96
TK		 484#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
492
493/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
494#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 497#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
501#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
502#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
503#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
504#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
505#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 506#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
507
b205914c 508#define PINMUX_MOD_SELS \
0b0ffc96 509\
b205914c
GU		 510MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
511 MOD_SEL2_30 \
0b0ffc96 512 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 513MOD_SEL0_28_27 MOD_SEL2_28_27 \
514MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
515 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 516MOD_SEL0_23 MOD_SEL1_23_22_21 \
b205914c
GU		 517MOD_SEL0_22 MOD_SEL2_22 \
518MOD_SEL0_21 MOD_SEL2_21 \
519MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
520MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
521MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
522 MOD_SEL2_17 \
523MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 524 MOD_SEL1_15_14 \
b205914c
GU		 525MOD_SEL0_14_13 \
526 MOD_SEL1_13 \
0b0ffc96
TK		 527MOD_SEL0_12 MOD_SEL1_12 \
528MOD_SEL0_11 MOD_SEL1_11 \
529MOD_SEL0_10 MOD_SEL1_10 \
b205914c 530MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 531MOD_SEL0_7_6 \
532 MOD_SEL1_6 \
b205914c
GU		 533MOD_SEL0_5 MOD_SEL1_5 \
534MOD_SEL0_4_3 MOD_SEL1_4 \
535 MOD_SEL1_3 \
536 MOD_SEL1_2 \
0b0ffc96
TK		 537 MOD_SEL1_1 \
538 MOD_SEL1_0 MOD_SEL2_0
539
ea9c7405
NS		 540/*
541 * These pins are not able to be muxed but have other properties
542 * that can be set, such as drive-strength or pull-up/pull-down enable.
543 */
544#define PINMUX_STATIC \
545 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
546 FM(QSPI0_IO2) FM(QSPI0_IO3) \
547 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
548 FM(QSPI1_IO2) FM(QSPI1_IO3) \
549 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
550 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
551 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
552 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
553 FM(CLKOUT) FM(PRESETOUT) \
554 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 555 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96
TK		 556
557enum {
558 PINMUX_RESERVED = 0,
559
560 PINMUX_DATA_BEGIN,
561 GP_ALL(DATA),
562 PINMUX_DATA_END,
563
564#define F_(x, y)
565#define FM(x) FN_##x,
566 PINMUX_FUNCTION_BEGIN,
567 GP_ALL(FN),
568 PINMUX_GPSR
569 PINMUX_IPSR
570 PINMUX_MOD_SELS
571 PINMUX_FUNCTION_END,
572#undef F_
573#undef FM
574
575#define F_(x, y)
576#define FM(x) x##_MARK,
577 PINMUX_MARK_BEGIN,
578 PINMUX_GPSR
579 PINMUX_IPSR
580 PINMUX_MOD_SELS
ea9c7405 581 PINMUX_STATIC
0b0ffc96
TK		 582 PINMUX_MARK_END,
583#undef F_
584#undef FM
585};
586
587static const u16 pinmux_data[] = {
588 PINMUX_DATA_GP_ALL(),
589
8d4df573
GU		 590 PINMUX_SINGLE(AVS1),
591 PINMUX_SINGLE(AVS2),
592 PINMUX_SINGLE(HDMI0_CEC),
593 PINMUX_SINGLE(HDMI1_CEC),
d07640f5
KM		 594 PINMUX_SINGLE(I2C_SEL_0_1),
595 PINMUX_SINGLE(I2C_SEL_3_1),
596 PINMUX_SINGLE(I2C_SEL_5_1),
8d4df573
GU		 597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
0b0ffc96 604 /* IPSR0 */
e01678e3 605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
e01678e3 608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
e01678e3 612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
e01678e3 616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
b205914c 623 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
0b0ffc96
TK		 624
625 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
626 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
627 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
628
e01678e3
GU		 629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
631 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 632 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 635 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 636
e01678e3
GU		 637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 644
645 /* IPSR1 */
e01678e3
GU		 646 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
647 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
648 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 649 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 651 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 652
e01678e3
GU		 653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
655 PINMUX_IPSR_GPSR(IP1_7_4, A25),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 660
e01678e3
GU		 661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, A24),
664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 668
e01678e3
GU		 669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
671 PINMUX_IPSR_GPSR(IP1_15_12, A23),
672 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 673 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 675 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
676 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 677
e01678e3
GU		 678 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
679 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
680 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 681 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
683
684 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 685 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 686 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
687 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
688 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 691 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 692 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
693 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
694
e01678e3
GU		 695 PINMUX_IPSR_GPSR(IP1_31_28, A0),
696 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 697 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 698 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
699 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 700 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
701
702 /* IPSR2 */
e01678e3
GU		 703 PINMUX_IPSR_GPSR(IP2_3_0, A1),
704 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 705 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 706 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
707 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 708 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
709
e01678e3
GU		 710 PINMUX_IPSR_GPSR(IP2_7_4, A2),
711 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 712 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 713 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
714 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 715 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
716
e01678e3
GU		 717 PINMUX_IPSR_GPSR(IP2_11_8, A3),
718 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 719 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 720 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
721 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 722 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
723
e01678e3
GU		 724 PINMUX_IPSR_GPSR(IP2_15_12, A4),
725 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 726 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 727 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
728 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
729 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 730
e01678e3
GU		 731 PINMUX_IPSR_GPSR(IP2_19_16, A5),
732 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 733 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
734 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 735 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
736 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
737 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 738
e01678e3
GU		 739 PINMUX_IPSR_GPSR(IP2_23_20, A6),
740 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 741 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 743 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
744 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
745 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 746
e01678e3
GU		 747 PINMUX_IPSR_GPSR(IP2_27_24, A7),
748 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 749 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
750 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 751 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
752 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
753 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 754
e01678e3 755 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 756 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
760 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
761 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
762
763 /* IPSR3 */
e01678e3 764 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 765 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 767 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 768
e01678e3 769 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 770 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
771 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 772 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 773
e01678e3 774 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 775 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
776 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
777 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 778 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
779 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 780 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
781 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
782 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
783
e01678e3
GU		 784 PINMUX_IPSR_GPSR(IP3_15_12, A12),
785 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 786 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 788 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
789 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 790
e01678e3
GU		 791 PINMUX_IPSR_GPSR(IP3_19_16, A13),
792 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 793 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 795 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
796 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 797
e01678e3
GU		 798 PINMUX_IPSR_GPSR(IP3_23_20, A14),
799 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 800 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 801 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
802 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
803 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 804
e01678e3
GU		 805 PINMUX_IPSR_GPSR(IP3_27_24, A15),
806 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 807 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 808 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
809 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
810 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 811
e01678e3
GU		 812 PINMUX_IPSR_GPSR(IP3_31_28, A16),
813 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
814 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
815 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 816
817 /* IPSR4 */
e01678e3
GU		 818 PINMUX_IPSR_GPSR(IP4_3_0, A17),
819 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
820 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
822
823 PINMUX_IPSR_GPSR(IP4_7_4, A18),
824 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
825 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
826 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
827
828 PINMUX_IPSR_GPSR(IP4_11_8, A19),
829 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
830 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
831 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
832
833 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
834 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
835
836 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
837 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 838 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
839
e01678e3
GU		 840 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
841 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 842 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 843 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
844 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
845 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
846 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 847 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
848
e01678e3 849 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 850 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
851 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
854 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
855
e01678e3 856 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 857 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
858 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
860 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
861 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
862
863 /* IPSR5 */
e01678e3 864 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 865 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 866 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
867 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 868 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 869 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 870 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
871
e01678e3 872 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 873 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 874 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
875 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 876 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 877 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
878 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 879 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
880
881 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 882 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
883 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
884 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 885
e01678e3 886 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 887 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
888 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 889 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
890 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 891
e01678e3 892 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 893 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
894 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 895 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
896 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 897
e01678e3 898 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 899 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 900 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
901 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 902
e01678e3 903 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 904 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 905 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
906 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 907
e01678e3 908 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 909 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 910 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
911 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 912
913 /* IPSR6 */
e01678e3 914 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 915 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 916 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
917 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 918
b205914c
GU		 919 PINMUX_IPSR_GPSR(IP6_7_4, D6),
920 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
922 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 923
b205914c
GU		 924 PINMUX_IPSR_GPSR(IP6_11_8, D7),
925 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
926 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
927 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 928
b205914c
GU		 929 PINMUX_IPSR_GPSR(IP6_15_12, D8),
930 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
931 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
933 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
934 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 935
b205914c
GU		 936 PINMUX_IPSR_GPSR(IP6_19_16, D9),
937 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
938 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
940 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 941
b205914c
GU		 942 PINMUX_IPSR_GPSR(IP6_23_20, D10),
943 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
944 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
945 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
946 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
947 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
948 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 949
b205914c
GU		 950 PINMUX_IPSR_GPSR(IP6_27_24, D11),
951 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
952 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
953 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
954 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
955 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
956 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 957
b205914c
GU		 958 PINMUX_IPSR_GPSR(IP6_31_28, D12),
959 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
960 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
961 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
962 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
963 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 964
b205914c
GU		 965 /* IPSR7 */
966 PINMUX_IPSR_GPSR(IP7_3_0, D13),
967 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
968 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
969 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
970 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
971 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 972
b205914c
GU		 973 PINMUX_IPSR_GPSR(IP7_7_4, D14),
974 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
975 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
976 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
977 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
978 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
979 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 980
b205914c
GU		 981 PINMUX_IPSR_GPSR(IP7_11_8, D15),
982 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
983 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
984 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
985 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
986 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
987 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 988
b205914c 989 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
2d775831 990
b205914c
GU		 991 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
992 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 994
b205914c
GU		 995 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
996 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 998
b205914c
GU		 999 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1000 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1002 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 1003
b205914c
GU		 1004 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1005 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1006 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1007 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1008
b205914c
GU		 1009 /* IPSR8 */
1010 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1011 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1012 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1013 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1014
b205914c
GU		 1015 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1016 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1017 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1018 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1019
b205914c
GU		 1020 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1021 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1023
b205914c
GU		 1024 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1025 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1027 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1028 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1029
b205914c
GU		 1030 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1031 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1032 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1034 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1036
b205914c
GU		 1037 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1038 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1039 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1041 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1043
b205914c
GU		 1044 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1045 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1046 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1048 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1050
b205914c
GU		 1051 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1052 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1053 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1054 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1055 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1056 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1057
b205914c
GU		 1058 /* IPSR9 */
1059 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1060 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1061
b205914c
GU		 1062 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1063 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1064
b205914c
GU		 1065 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1066 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1067
b205914c
GU		 1068 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1069 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1070
b205914c
GU		 1071 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1072 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1073
b205914c
GU		 1074 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1075 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1076
b205914c
GU		 1077 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1078 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1079 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1080
b205914c
GU		 1081 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1082 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1083
b205914c
GU		 1084 /* IPSR10 */
1085 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1086 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1087
b205914c
GU		 1088 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1089 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1090
b205914c
GU		 1091 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1092 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1093
b205914c
GU		 1094 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1095 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1096
b205914c
GU		 1097 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1098 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1099
b205914c
GU		 1100 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1101 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1103
b205914c
GU		 1104 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1105 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1106 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1107
b205914c
GU		 1108 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1109 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1110 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1111
b205914c
GU		 1112 /* IPSR11 */
1113 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1114 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1115 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1116
1117 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1118 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1119
1120 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1121 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1122 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1123
1124 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1125 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1126
1127 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1128 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1129
1130 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1131 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1132
1133 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1139 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1141 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1142 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1143
1144 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1145 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1146 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1147 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1148 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1149
b205914c
GU		 1150 /* IPSR12 */
1151 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1152 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1153 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1154 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1155 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1156
1157 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1158 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1159 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1160 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1161 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1162 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1163 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1164 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1165
1166 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1167 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1168 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1169 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1170 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1171 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1172 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1173 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1174
1175 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1176 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1177 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1178 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1179 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1180
1181 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1182 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1183 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1184 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1185 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1186
1187 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1188 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1190 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1191 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1192 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1193 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1194
1195 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1196 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1197 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1198 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1199 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1200 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1201 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1202
1203 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1205 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1206 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1208 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1209 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1210
b205914c
GU		 1211 /* IPSR13 */
1212 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1214 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1215 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1216 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1217 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1218
1219 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1221 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1222 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1223 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1224 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1225
1226 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1227 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1229 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1230 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1231 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1232 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1233 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1234
1235 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1236 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1238 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1239 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1240 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1241
1242 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1243 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1245 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1246 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1247 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1248
1249 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1250 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1251 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1253 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1254 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1255 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1256 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1257
1258 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1259 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1260 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1262 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1263 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1264 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1265
1266 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1267 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1268 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1269 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1270
b205914c
GU		 1271 /* IPSR14 */
1272 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1273 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1275 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1276 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1277 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1278 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1279 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1280
1281 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1282 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1284 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1286 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1287 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1288 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1291 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1292 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1293
1294 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1295 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1296 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1297 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1298
1299 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1300 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1301 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1302
1303 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1304 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1305
1306 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1307 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1308
1309 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1310 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1311
b205914c
GU		 1312 /* IPSR15 */
1313 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1314
1315 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1316 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1317
68e63892 1318 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1319 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1320 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1321
68e63892 1322 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1323 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1324 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1325 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1326
1327 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1328 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1332 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1333 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1334
1335 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1336 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1340 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1342
1343 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1344 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1348 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1350
1351 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1352 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1356 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1357 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1358
b205914c
GU		 1359 /* IPSR16 */
1360 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1361 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1362 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1365 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1366 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1367
1368 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1369 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1370 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1371
1372 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1373 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1374 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1375 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1377 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1378 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1379
1380 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1381 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1385 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1386 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1387
1388 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1389 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1396
1397 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1398 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1399 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1400 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1402 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1403 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1404
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1406 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1408 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1409 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1410 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1411 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1412 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
20cacae1 1413
b205914c
GU		 1414 /* IPSR17 */
1415 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1416 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1417
1418 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1419 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1420 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1421 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1422 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1423
1424 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1425 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1426 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1427 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1429 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1430 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1431
1432 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1433 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1434 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1435 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1436 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1437 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1438
1439 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1440 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1443 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1444 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1445 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1446 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1447 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1448
1449 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1450 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1451 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1452 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1453 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1454 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1455 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1456 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1457 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1458
1459 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1460 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1461 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
50d83156 1463 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
b205914c
GU		 1464 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1465 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1466 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1467 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1468 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1469 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1470
1471 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1472 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1473 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1474 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1477 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1479 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1480
1481 /* IPSR18 */
f9d13080 1482 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
b205914c
GU		 1483 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1484 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1485 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1486 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1487 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1488 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1489 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1490 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1491
f9d13080 1492 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
b205914c
GU		 1493 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1494 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1495 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1496 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1497 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1498 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1499 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1500 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1501
b205914c
GU		 1502/*
1503 * Static pins can not be muxed between different functions but
1504 * still needs a mark entry in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux then pin
1507 * while still applying configuration to it
1508 */
1509#define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511#undef FM
9b132ba3
KM		 1512};
1513
b205914c
GU		 1514/*
1515 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521
1522static const struct sh_pfc_pin pinmux_pins[] = {
1523 PINMUX_GPIO_GP_ALL(),
76250a6c 1524
b205914c
GU		 1525 /*
1526 * Pins not associated with a GPIO port.
1527 *
1528 * The pin positions are different between different r8a7795
1529 * packages, all that is needed for the pfc driver is a unique
1530 * number for each pin. To this end use the pin layout from
1531 * R-Car H3SiP to calculate a unique number for each pin.
1532 */
1533 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1577};
1578
30c078de
GU		 1579/* - EtherAVB --------------------------------------------------------------- */
1580static const unsigned int avb_link_pins[] = {
1581 /* AVB_LINK */
1582 RCAR_GP_PIN(2, 12),
1583};
1584static const unsigned int avb_link_mux[] = {
1585 AVB_LINK_MARK,
1586};
1587static const unsigned int avb_magic_pins[] = {
1588 /* AVB_MAGIC_ */
1589 RCAR_GP_PIN(2, 10),
1590};
1591static const unsigned int avb_magic_mux[] = {
1592 AVB_MAGIC_MARK,
1593};
1594static const unsigned int avb_phy_int_pins[] = {
1595 /* AVB_PHY_INT */
1596 RCAR_GP_PIN(2, 11),
1597};
1598static const unsigned int avb_phy_int_mux[] = {
1599 AVB_PHY_INT_MARK,
1600};
1601static const unsigned int avb_mdc_pins[] = {
1602 /* AVB_MDC, AVB_MDIO */
1603 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1604};
1605static const unsigned int avb_mdc_mux[] = {
1606 AVB_MDC_MARK, AVB_MDIO_MARK,
1607};
1608static const unsigned int avb_mii_pins[] = {
1609 /*
1610 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1611 * AVB_TD1, AVB_TD2, AVB_TD3,
1612 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1613 * AVB_RD1, AVB_RD2, AVB_RD3,
1614 * AVB_TXCREFCLK
1615 */
1616 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1617 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1618 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1619 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1620 PIN_NUMBER('A', 12),
1621
1622};
1623static const unsigned int avb_mii_mux[] = {
1624 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1625 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1626 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1627 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1628 AVB_TXCREFCLK_MARK,
1629};
1630static const unsigned int avb_avtp_pps_pins[] = {
1631 /* AVB_AVTP_PPS */
1632 RCAR_GP_PIN(2, 6),
1633};
1634static const unsigned int avb_avtp_pps_mux[] = {
1635 AVB_AVTP_PPS_MARK,
1636};
1637static const unsigned int avb_avtp_match_a_pins[] = {
1638 /* AVB_AVTP_MATCH_A */
1639 RCAR_GP_PIN(2, 13),
1640};
1641static const unsigned int avb_avtp_match_a_mux[] = {
1642 AVB_AVTP_MATCH_A_MARK,
1643};
1644static const unsigned int avb_avtp_capture_a_pins[] = {
1645 /* AVB_AVTP_CAPTURE_A */
1646 RCAR_GP_PIN(2, 14),
1647};
1648static const unsigned int avb_avtp_capture_a_mux[] = {
1649 AVB_AVTP_CAPTURE_A_MARK,
1650};
1651static const unsigned int avb_avtp_match_b_pins[] = {
1652 /* AVB_AVTP_MATCH_B */
1653 RCAR_GP_PIN(1, 8),
1654};
1655static const unsigned int avb_avtp_match_b_mux[] = {
1656 AVB_AVTP_MATCH_B_MARK,
1657};
1658static const unsigned int avb_avtp_capture_b_pins[] = {
1659 /* AVB_AVTP_CAPTURE_B */
1660 RCAR_GP_PIN(1, 11),
1661};
1662static const unsigned int avb_avtp_capture_b_mux[] = {
1663 AVB_AVTP_CAPTURE_B_MARK,
1664};
1665
a20a6585
LP		 1666/* - DU --------------------------------------------------------------------- */
1667static const unsigned int du_rgb666_pins[] = {
1668 /* R[7:2], G[7:2], B[7:2] */
1669 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1670 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1671 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1672 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1673 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1674 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1675};
1676static const unsigned int du_rgb666_mux[] = {
1677 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1678 DU_DR3_MARK, DU_DR2_MARK,
1679 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1680 DU_DG3_MARK, DU_DG2_MARK,
1681 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1682 DU_DB3_MARK, DU_DB2_MARK,
1683};
1684static const unsigned int du_rgb888_pins[] = {
1685 /* R[7:0], G[7:0], B[7:0] */
1686 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1687 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1688 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1689 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1690 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1691 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1692 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1693 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1694 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1695};
1696static const unsigned int du_rgb888_mux[] = {
1697 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1698 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1699 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1700 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1701 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1702 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1703};
1704static const unsigned int du_clk_out_0_pins[] = {
1705 /* CLKOUT */
1706 RCAR_GP_PIN(1, 27),
1707};
1708static const unsigned int du_clk_out_0_mux[] = {
1709 DU_DOTCLKOUT0_MARK
1710};
1711static const unsigned int du_clk_out_1_pins[] = {
1712 /* CLKOUT */
1713 RCAR_GP_PIN(2, 3),
1714};
1715static const unsigned int du_clk_out_1_mux[] = {
1716 DU_DOTCLKOUT1_MARK
1717};
1718static const unsigned int du_sync_pins[] = {
1719 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1720 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1721};
1722static const unsigned int du_sync_mux[] = {
1723 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1724};
1725static const unsigned int du_oddf_pins[] = {
1726 /* EXDISP/EXODDF/EXCDE */
1727 RCAR_GP_PIN(2, 2),
1728};
1729static const unsigned int du_oddf_mux[] = {
1730 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1731};
1732static const unsigned int du_cde_pins[] = {
1733 /* CDE */
1734 RCAR_GP_PIN(2, 0),
1735};
1736static const unsigned int du_cde_mux[] = {
1737 DU_CDE_MARK,
1738};
1739static const unsigned int du_disp_pins[] = {
1740 /* DISP */
1741 RCAR_GP_PIN(2, 1),
1742};
1743static const unsigned int du_disp_mux[] = {
1744 DU_DISP_MARK,
1745};
1746
3e6c7727
GU		 1747/* - MSIOF0 ----------------------------------------------------------------- */
1748static const unsigned int msiof0_clk_pins[] = {
1749 /* SCK */
1750 RCAR_GP_PIN(5, 17),
1751};
1752static const unsigned int msiof0_clk_mux[] = {
1753 MSIOF0_SCK_MARK,
1754};
1755static const unsigned int msiof0_sync_pins[] = {
1756 /* SYNC */
1757 RCAR_GP_PIN(5, 18),
1758};
1759static const unsigned int msiof0_sync_mux[] = {
1760 MSIOF0_SYNC_MARK,
1761};
1762static const unsigned int msiof0_ss1_pins[] = {
1763 /* SS1 */
1764 RCAR_GP_PIN(5, 19),
1765};
1766static const unsigned int msiof0_ss1_mux[] = {
1767 MSIOF0_SS1_MARK,
1768};
1769static const unsigned int msiof0_ss2_pins[] = {
1770 /* SS2 */
1771 RCAR_GP_PIN(5, 21),
1772};
1773static const unsigned int msiof0_ss2_mux[] = {
1774 MSIOF0_SS2_MARK,
1775};
1776static const unsigned int msiof0_txd_pins[] = {
1777 /* TXD */
1778 RCAR_GP_PIN(5, 20),
1779};
1780static const unsigned int msiof0_txd_mux[] = {
1781 MSIOF0_TXD_MARK,
1782};
1783static const unsigned int msiof0_rxd_pins[] = {
1784 /* RXD */
1785 RCAR_GP_PIN(5, 22),
1786};
1787static const unsigned int msiof0_rxd_mux[] = {
1788 MSIOF0_RXD_MARK,
1789};
1790/* - MSIOF1 ----------------------------------------------------------------- */
1791static const unsigned int msiof1_clk_a_pins[] = {
1792 /* SCK */
1793 RCAR_GP_PIN(6, 8),
1794};
1795static const unsigned int msiof1_clk_a_mux[] = {
1796 MSIOF1_SCK_A_MARK,
1797};
1798static const unsigned int msiof1_sync_a_pins[] = {
1799 /* SYNC */
1800 RCAR_GP_PIN(6, 9),
1801};
1802static const unsigned int msiof1_sync_a_mux[] = {
1803 MSIOF1_SYNC_A_MARK,
1804};
1805static const unsigned int msiof1_ss1_a_pins[] = {
1806 /* SS1 */
1807 RCAR_GP_PIN(6, 5),
1808};
1809static const unsigned int msiof1_ss1_a_mux[] = {
1810 MSIOF1_SS1_A_MARK,
1811};
1812static const unsigned int msiof1_ss2_a_pins[] = {
1813 /* SS2 */
1814 RCAR_GP_PIN(6, 6),
1815};
1816static const unsigned int msiof1_ss2_a_mux[] = {
1817 MSIOF1_SS2_A_MARK,
1818};
1819static const unsigned int msiof1_txd_a_pins[] = {
1820 /* TXD */
1821 RCAR_GP_PIN(6, 7),
1822};
1823static const unsigned int msiof1_txd_a_mux[] = {
1824 MSIOF1_TXD_A_MARK,
1825};
1826static const unsigned int msiof1_rxd_a_pins[] = {
1827 /* RXD */
1828 RCAR_GP_PIN(6, 10),
1829};
1830static const unsigned int msiof1_rxd_a_mux[] = {
1831 MSIOF1_RXD_A_MARK,
1832};
1833static const unsigned int msiof1_clk_b_pins[] = {
1834 /* SCK */
1835 RCAR_GP_PIN(5, 9),
1836};
1837static const unsigned int msiof1_clk_b_mux[] = {
1838 MSIOF1_SCK_B_MARK,
1839};
1840static const unsigned int msiof1_sync_b_pins[] = {
1841 /* SYNC */
1842 RCAR_GP_PIN(5, 3),
1843};
1844static const unsigned int msiof1_sync_b_mux[] = {
1845 MSIOF1_SYNC_B_MARK,
1846};
1847static const unsigned int msiof1_ss1_b_pins[] = {
1848 /* SS1 */
1849 RCAR_GP_PIN(5, 4),
1850};
1851static const unsigned int msiof1_ss1_b_mux[] = {
1852 MSIOF1_SS1_B_MARK,
1853};
1854static const unsigned int msiof1_ss2_b_pins[] = {
1855 /* SS2 */
1856 RCAR_GP_PIN(5, 0),
1857};
1858static const unsigned int msiof1_ss2_b_mux[] = {
1859 MSIOF1_SS2_B_MARK,
1860};
1861static const unsigned int msiof1_txd_b_pins[] = {
1862 /* TXD */
1863 RCAR_GP_PIN(5, 8),
1864};
1865static const unsigned int msiof1_txd_b_mux[] = {
1866 MSIOF1_TXD_B_MARK,
1867};
1868static const unsigned int msiof1_rxd_b_pins[] = {
1869 /* RXD */
1870 RCAR_GP_PIN(5, 7),
1871};
1872static const unsigned int msiof1_rxd_b_mux[] = {
1873 MSIOF1_RXD_B_MARK,
1874};
1875static const unsigned int msiof1_clk_c_pins[] = {
1876 /* SCK */
1877 RCAR_GP_PIN(6, 17),
1878};
1879static const unsigned int msiof1_clk_c_mux[] = {
1880 MSIOF1_SCK_C_MARK,
1881};
1882static const unsigned int msiof1_sync_c_pins[] = {
1883 /* SYNC */
1884 RCAR_GP_PIN(6, 18),
1885};
1886static const unsigned int msiof1_sync_c_mux[] = {
1887 MSIOF1_SYNC_C_MARK,
1888};
1889static const unsigned int msiof1_ss1_c_pins[] = {
1890 /* SS1 */
1891 RCAR_GP_PIN(6, 21),
1892};
1893static const unsigned int msiof1_ss1_c_mux[] = {
1894 MSIOF1_SS1_C_MARK,
1895};
1896static const unsigned int msiof1_ss2_c_pins[] = {
1897 /* SS2 */
1898 RCAR_GP_PIN(6, 27),
1899};
1900static const unsigned int msiof1_ss2_c_mux[] = {
1901 MSIOF1_SS2_C_MARK,
1902};
1903static const unsigned int msiof1_txd_c_pins[] = {
1904 /* TXD */
1905 RCAR_GP_PIN(6, 20),
1906};
1907static const unsigned int msiof1_txd_c_mux[] = {
1908 MSIOF1_TXD_C_MARK,
1909};
1910static const unsigned int msiof1_rxd_c_pins[] = {
1911 /* RXD */
1912 RCAR_GP_PIN(6, 19),
1913};
1914static const unsigned int msiof1_rxd_c_mux[] = {
1915 MSIOF1_RXD_C_MARK,
1916};
1917static const unsigned int msiof1_clk_d_pins[] = {
1918 /* SCK */
1919 RCAR_GP_PIN(5, 12),
1920};
1921static const unsigned int msiof1_clk_d_mux[] = {
1922 MSIOF1_SCK_D_MARK,
1923};
1924static const unsigned int msiof1_sync_d_pins[] = {
1925 /* SYNC */
1926 RCAR_GP_PIN(5, 15),
1927};
1928static const unsigned int msiof1_sync_d_mux[] = {
1929 MSIOF1_SYNC_D_MARK,
1930};
1931static const unsigned int msiof1_ss1_d_pins[] = {
1932 /* SS1 */
1933 RCAR_GP_PIN(5, 16),
1934};
1935static const unsigned int msiof1_ss1_d_mux[] = {
1936 MSIOF1_SS1_D_MARK,
1937};
1938static const unsigned int msiof1_ss2_d_pins[] = {
1939 /* SS2 */
1940 RCAR_GP_PIN(5, 21),
1941};
1942static const unsigned int msiof1_ss2_d_mux[] = {
1943 MSIOF1_SS2_D_MARK,
1944};
1945static const unsigned int msiof1_txd_d_pins[] = {
1946 /* TXD */
1947 RCAR_GP_PIN(5, 14),
1948};
1949static const unsigned int msiof1_txd_d_mux[] = {
1950 MSIOF1_TXD_D_MARK,
1951};
1952static const unsigned int msiof1_rxd_d_pins[] = {
1953 /* RXD */
1954 RCAR_GP_PIN(5, 13),
1955};
1956static const unsigned int msiof1_rxd_d_mux[] = {
1957 MSIOF1_RXD_D_MARK,
1958};
1959static const unsigned int msiof1_clk_e_pins[] = {
1960 /* SCK */
1961 RCAR_GP_PIN(3, 0),
1962};
1963static const unsigned int msiof1_clk_e_mux[] = {
1964 MSIOF1_SCK_E_MARK,
1965};
1966static const unsigned int msiof1_sync_e_pins[] = {
1967 /* SYNC */
1968 RCAR_GP_PIN(3, 1),
1969};
1970static const unsigned int msiof1_sync_e_mux[] = {
1971 MSIOF1_SYNC_E_MARK,
1972};
1973static const unsigned int msiof1_ss1_e_pins[] = {
1974 /* SS1 */
1975 RCAR_GP_PIN(3, 4),
1976};
1977static const unsigned int msiof1_ss1_e_mux[] = {
1978 MSIOF1_SS1_E_MARK,
1979};
1980static const unsigned int msiof1_ss2_e_pins[] = {
1981 /* SS2 */
1982 RCAR_GP_PIN(3, 5),
1983};
1984static const unsigned int msiof1_ss2_e_mux[] = {
1985 MSIOF1_SS2_E_MARK,
1986};
1987static const unsigned int msiof1_txd_e_pins[] = {
1988 /* TXD */
1989 RCAR_GP_PIN(3, 3),
1990};
1991static const unsigned int msiof1_txd_e_mux[] = {
1992 MSIOF1_TXD_E_MARK,
1993};
1994static const unsigned int msiof1_rxd_e_pins[] = {
1995 /* RXD */
1996 RCAR_GP_PIN(3, 2),
1997};
1998static const unsigned int msiof1_rxd_e_mux[] = {
1999 MSIOF1_RXD_E_MARK,
2000};
2001static const unsigned int msiof1_clk_f_pins[] = {
2002 /* SCK */
2003 RCAR_GP_PIN(5, 23),
2004};
2005static const unsigned int msiof1_clk_f_mux[] = {
2006 MSIOF1_SCK_F_MARK,
2007};
2008static const unsigned int msiof1_sync_f_pins[] = {
2009 /* SYNC */
2010 RCAR_GP_PIN(5, 24),
2011};
2012static const unsigned int msiof1_sync_f_mux[] = {
2013 MSIOF1_SYNC_F_MARK,
2014};
2015static const unsigned int msiof1_ss1_f_pins[] = {
2016 /* SS1 */
2017 RCAR_GP_PIN(6, 1),
2018};
2019static const unsigned int msiof1_ss1_f_mux[] = {
2020 MSIOF1_SS1_F_MARK,
2021};
2022static const unsigned int msiof1_ss2_f_pins[] = {
2023 /* SS2 */
2024 RCAR_GP_PIN(6, 2),
2025};
2026static const unsigned int msiof1_ss2_f_mux[] = {
2027 MSIOF1_SS2_F_MARK,
2028};
2029static const unsigned int msiof1_txd_f_pins[] = {
2030 /* TXD */
2031 RCAR_GP_PIN(6, 0),
2032};
2033static const unsigned int msiof1_txd_f_mux[] = {
2034 MSIOF1_TXD_F_MARK,
2035};
2036static const unsigned int msiof1_rxd_f_pins[] = {
2037 /* RXD */
2038 RCAR_GP_PIN(5, 25),
2039};
2040static const unsigned int msiof1_rxd_f_mux[] = {
2041 MSIOF1_RXD_F_MARK,
2042};
2043static const unsigned int msiof1_clk_g_pins[] = {
2044 /* SCK */
2045 RCAR_GP_PIN(3, 6),
2046};
2047static const unsigned int msiof1_clk_g_mux[] = {
2048 MSIOF1_SCK_G_MARK,
2049};
2050static const unsigned int msiof1_sync_g_pins[] = {
2051 /* SYNC */
2052 RCAR_GP_PIN(3, 7),
2053};
2054static const unsigned int msiof1_sync_g_mux[] = {
2055 MSIOF1_SYNC_G_MARK,
2056};
2057static const unsigned int msiof1_ss1_g_pins[] = {
2058 /* SS1 */
2059 RCAR_GP_PIN(3, 10),
2060};
2061static const unsigned int msiof1_ss1_g_mux[] = {
2062 MSIOF1_SS1_G_MARK,
2063};
2064static const unsigned int msiof1_ss2_g_pins[] = {
2065 /* SS2 */
2066 RCAR_GP_PIN(3, 11),
2067};
2068static const unsigned int msiof1_ss2_g_mux[] = {
2069 MSIOF1_SS2_G_MARK,
2070};
2071static const unsigned int msiof1_txd_g_pins[] = {
2072 /* TXD */
2073 RCAR_GP_PIN(3, 9),
2074};
2075static const unsigned int msiof1_txd_g_mux[] = {
2076 MSIOF1_TXD_G_MARK,
2077};
2078static const unsigned int msiof1_rxd_g_pins[] = {
2079 /* RXD */
2080 RCAR_GP_PIN(3, 8),
2081};
2082static const unsigned int msiof1_rxd_g_mux[] = {
2083 MSIOF1_RXD_G_MARK,
2084};
2085/* - MSIOF2 ----------------------------------------------------------------- */
2086static const unsigned int msiof2_clk_a_pins[] = {
2087 /* SCK */
2088 RCAR_GP_PIN(1, 9),
2089};
2090static const unsigned int msiof2_clk_a_mux[] = {
2091 MSIOF2_SCK_A_MARK,
2092};
2093static const unsigned int msiof2_sync_a_pins[] = {
2094 /* SYNC */
2095 RCAR_GP_PIN(1, 8),
2096};
2097static const unsigned int msiof2_sync_a_mux[] = {
2098 MSIOF2_SYNC_A_MARK,
2099};
2100static const unsigned int msiof2_ss1_a_pins[] = {
2101 /* SS1 */
2102 RCAR_GP_PIN(1, 6),
2103};
2104static const unsigned int msiof2_ss1_a_mux[] = {
2105 MSIOF2_SS1_A_MARK,
2106};
2107static const unsigned int msiof2_ss2_a_pins[] = {
2108 /* SS2 */
2109 RCAR_GP_PIN(1, 7),
2110};
2111static const unsigned int msiof2_ss2_a_mux[] = {
2112 MSIOF2_SS2_A_MARK,
2113};
2114static const unsigned int msiof2_txd_a_pins[] = {
2115 /* TXD */
2116 RCAR_GP_PIN(1, 11),
2117};
2118static const unsigned int msiof2_txd_a_mux[] = {
2119 MSIOF2_TXD_A_MARK,
2120};
2121static const unsigned int msiof2_rxd_a_pins[] = {
2122 /* RXD */
2123 RCAR_GP_PIN(1, 10),
2124};
2125static const unsigned int msiof2_rxd_a_mux[] = {
2126 MSIOF2_RXD_A_MARK,
2127};
2128static const unsigned int msiof2_clk_b_pins[] = {
2129 /* SCK */
2130 RCAR_GP_PIN(0, 4),
2131};
2132static const unsigned int msiof2_clk_b_mux[] = {
2133 MSIOF2_SCK_B_MARK,
2134};
2135static const unsigned int msiof2_sync_b_pins[] = {
2136 /* SYNC */
2137 RCAR_GP_PIN(0, 5),
2138};
2139static const unsigned int msiof2_sync_b_mux[] = {
2140 MSIOF2_SYNC_B_MARK,
2141};
2142static const unsigned int msiof2_ss1_b_pins[] = {
2143 /* SS1 */
2144 RCAR_GP_PIN(0, 0),
2145};
2146static const unsigned int msiof2_ss1_b_mux[] = {
2147 MSIOF2_SS1_B_MARK,
2148};
2149static const unsigned int msiof2_ss2_b_pins[] = {
2150 /* SS2 */
2151 RCAR_GP_PIN(0, 1),
2152};
2153static const unsigned int msiof2_ss2_b_mux[] = {
2154 MSIOF2_SS2_B_MARK,
2155};
2156static const unsigned int msiof2_txd_b_pins[] = {
2157 /* TXD */
2158 RCAR_GP_PIN(0, 7),
2159};
2160static const unsigned int msiof2_txd_b_mux[] = {
2161 MSIOF2_TXD_B_MARK,
2162};
2163static const unsigned int msiof2_rxd_b_pins[] = {
2164 /* RXD */
2165 RCAR_GP_PIN(0, 6),
2166};
2167static const unsigned int msiof2_rxd_b_mux[] = {
2168 MSIOF2_RXD_B_MARK,
2169};
2170static const unsigned int msiof2_clk_c_pins[] = {
2171 /* SCK */
2172 RCAR_GP_PIN(2, 12),
2173};
2174static const unsigned int msiof2_clk_c_mux[] = {
2175 MSIOF2_SCK_C_MARK,
2176};
2177static const unsigned int msiof2_sync_c_pins[] = {
2178 /* SYNC */
2179 RCAR_GP_PIN(2, 11),
2180};
2181static const unsigned int msiof2_sync_c_mux[] = {
2182 MSIOF2_SYNC_C_MARK,
2183};
2184static const unsigned int msiof2_ss1_c_pins[] = {
2185 /* SS1 */
2186 RCAR_GP_PIN(2, 10),
2187};
2188static const unsigned int msiof2_ss1_c_mux[] = {
2189 MSIOF2_SS1_C_MARK,
2190};
2191static const unsigned int msiof2_ss2_c_pins[] = {
2192 /* SS2 */
2193 RCAR_GP_PIN(2, 9),
2194};
2195static const unsigned int msiof2_ss2_c_mux[] = {
2196 MSIOF2_SS2_C_MARK,
2197};
2198static const unsigned int msiof2_txd_c_pins[] = {
2199 /* TXD */
2200 RCAR_GP_PIN(2, 14),
2201};
2202static const unsigned int msiof2_txd_c_mux[] = {
2203 MSIOF2_TXD_C_MARK,
2204};
2205static const unsigned int msiof2_rxd_c_pins[] = {
2206 /* RXD */
2207 RCAR_GP_PIN(2, 13),
2208};
2209static const unsigned int msiof2_rxd_c_mux[] = {
2210 MSIOF2_RXD_C_MARK,
2211};
2212static const unsigned int msiof2_clk_d_pins[] = {
2213 /* SCK */
2214 RCAR_GP_PIN(0, 8),
2215};
2216static const unsigned int msiof2_clk_d_mux[] = {
2217 MSIOF2_SCK_D_MARK,
2218};
2219static const unsigned int msiof2_sync_d_pins[] = {
2220 /* SYNC */
2221 RCAR_GP_PIN(0, 9),
2222};
2223static const unsigned int msiof2_sync_d_mux[] = {
2224 MSIOF2_SYNC_D_MARK,
2225};
2226static const unsigned int msiof2_ss1_d_pins[] = {
2227 /* SS1 */
2228 RCAR_GP_PIN(0, 12),
2229};
2230static const unsigned int msiof2_ss1_d_mux[] = {
2231 MSIOF2_SS1_D_MARK,
2232};
2233static const unsigned int msiof2_ss2_d_pins[] = {
2234 /* SS2 */
2235 RCAR_GP_PIN(0, 13),
2236};
2237static const unsigned int msiof2_ss2_d_mux[] = {
2238 MSIOF2_SS2_D_MARK,
2239};
2240static const unsigned int msiof2_txd_d_pins[] = {
2241 /* TXD */
2242 RCAR_GP_PIN(0, 11),
2243};
2244static const unsigned int msiof2_txd_d_mux[] = {
2245 MSIOF2_TXD_D_MARK,
2246};
2247static const unsigned int msiof2_rxd_d_pins[] = {
2248 /* RXD */
2249 RCAR_GP_PIN(0, 10),
2250};
2251static const unsigned int msiof2_rxd_d_mux[] = {
2252 MSIOF2_RXD_D_MARK,
2253};
2254/* - MSIOF3 ----------------------------------------------------------------- */
2255static const unsigned int msiof3_clk_a_pins[] = {
2256 /* SCK */
2257 RCAR_GP_PIN(0, 0),
2258};
2259static const unsigned int msiof3_clk_a_mux[] = {
2260 MSIOF3_SCK_A_MARK,
2261};
2262static const unsigned int msiof3_sync_a_pins[] = {
2263 /* SYNC */
2264 RCAR_GP_PIN(0, 1),
2265};
2266static const unsigned int msiof3_sync_a_mux[] = {
2267 MSIOF3_SYNC_A_MARK,
2268};
2269static const unsigned int msiof3_ss1_a_pins[] = {
2270 /* SS1 */
2271 RCAR_GP_PIN(0, 14),
2272};
2273static const unsigned int msiof3_ss1_a_mux[] = {
2274 MSIOF3_SS1_A_MARK,
2275};
2276static const unsigned int msiof3_ss2_a_pins[] = {
2277 /* SS2 */
2278 RCAR_GP_PIN(0, 15),
2279};
2280static const unsigned int msiof3_ss2_a_mux[] = {
2281 MSIOF3_SS2_A_MARK,
2282};
2283static const unsigned int msiof3_txd_a_pins[] = {
2284 /* TXD */
2285 RCAR_GP_PIN(0, 3),
2286};
2287static const unsigned int msiof3_txd_a_mux[] = {
2288 MSIOF3_TXD_A_MARK,
2289};
2290static const unsigned int msiof3_rxd_a_pins[] = {
2291 /* RXD */
2292 RCAR_GP_PIN(0, 2),
2293};
2294static const unsigned int msiof3_rxd_a_mux[] = {
2295 MSIOF3_RXD_A_MARK,
2296};
2297static const unsigned int msiof3_clk_b_pins[] = {
2298 /* SCK */
2299 RCAR_GP_PIN(1, 2),
2300};
2301static const unsigned int msiof3_clk_b_mux[] = {
2302 MSIOF3_SCK_B_MARK,
2303};
2304static const unsigned int msiof3_sync_b_pins[] = {
2305 /* SYNC */
2306 RCAR_GP_PIN(1, 0),
2307};
2308static const unsigned int msiof3_sync_b_mux[] = {
2309 MSIOF3_SYNC_B_MARK,
2310};
2311static const unsigned int msiof3_ss1_b_pins[] = {
2312 /* SS1 */
2313 RCAR_GP_PIN(1, 4),
2314};
2315static const unsigned int msiof3_ss1_b_mux[] = {
2316 MSIOF3_SS1_B_MARK,
2317};
2318static const unsigned int msiof3_ss2_b_pins[] = {
2319 /* SS2 */
2320 RCAR_GP_PIN(1, 5),
2321};
2322static const unsigned int msiof3_ss2_b_mux[] = {
2323 MSIOF3_SS2_B_MARK,
2324};
2325static const unsigned int msiof3_txd_b_pins[] = {
2326 /* TXD */
2327 RCAR_GP_PIN(1, 1),
2328};
2329static const unsigned int msiof3_txd_b_mux[] = {
2330 MSIOF3_TXD_B_MARK,
2331};
2332static const unsigned int msiof3_rxd_b_pins[] = {
2333 /* RXD */
2334 RCAR_GP_PIN(1, 3),
2335};
2336static const unsigned int msiof3_rxd_b_mux[] = {
2337 MSIOF3_RXD_B_MARK,
2338};
2339static const unsigned int msiof3_clk_c_pins[] = {
2340 /* SCK */
2341 RCAR_GP_PIN(1, 12),
2342};
2343static const unsigned int msiof3_clk_c_mux[] = {
2344 MSIOF3_SCK_C_MARK,
2345};
2346static const unsigned int msiof3_sync_c_pins[] = {
2347 /* SYNC */
2348 RCAR_GP_PIN(1, 13),
2349};
2350static const unsigned int msiof3_sync_c_mux[] = {
2351 MSIOF3_SYNC_C_MARK,
2352};
2353static const unsigned int msiof3_txd_c_pins[] = {
2354 /* TXD */
2355 RCAR_GP_PIN(1, 15),
2356};
2357static const unsigned int msiof3_txd_c_mux[] = {
2358 MSIOF3_TXD_C_MARK,
2359};
2360static const unsigned int msiof3_rxd_c_pins[] = {
2361 /* RXD */
2362 RCAR_GP_PIN(1, 14),
2363};
2364static const unsigned int msiof3_rxd_c_mux[] = {
2365 MSIOF3_RXD_C_MARK,
2366};
2367static const unsigned int msiof3_clk_d_pins[] = {
2368 /* SCK */
2369 RCAR_GP_PIN(1, 22),
2370};
2371static const unsigned int msiof3_clk_d_mux[] = {
2372 MSIOF3_SCK_D_MARK,
2373};
2374static const unsigned int msiof3_sync_d_pins[] = {
2375 /* SYNC */
2376 RCAR_GP_PIN(1, 23),
2377};
2378static const unsigned int msiof3_sync_d_mux[] = {
2379 MSIOF3_SYNC_D_MARK,
2380};
2381static const unsigned int msiof3_ss1_d_pins[] = {
2382 /* SS1 */
2383 RCAR_GP_PIN(1, 26),
2384};
2385static const unsigned int msiof3_ss1_d_mux[] = {
2386 MSIOF3_SS1_D_MARK,
2387};
2388static const unsigned int msiof3_txd_d_pins[] = {
2389 /* TXD */
2390 RCAR_GP_PIN(1, 25),
2391};
2392static const unsigned int msiof3_txd_d_mux[] = {
2393 MSIOF3_TXD_D_MARK,
2394};
2395static const unsigned int msiof3_rxd_d_pins[] = {
2396 /* RXD */
2397 RCAR_GP_PIN(1, 24),
2398};
2399static const unsigned int msiof3_rxd_d_mux[] = {
2400 MSIOF3_RXD_D_MARK,
2401};
2402static const unsigned int msiof3_clk_e_pins[] = {
2403 /* SCK */
2404 RCAR_GP_PIN(2, 3),
2405};
2406static const unsigned int msiof3_clk_e_mux[] = {
2407 MSIOF3_SCK_E_MARK,
2408};
2409static const unsigned int msiof3_sync_e_pins[] = {
2410 /* SYNC */
2411 RCAR_GP_PIN(2, 2),
2412};
2413static const unsigned int msiof3_sync_e_mux[] = {
2414 MSIOF3_SYNC_E_MARK,
2415};
2416static const unsigned int msiof3_ss1_e_pins[] = {
2417 /* SS1 */
2418 RCAR_GP_PIN(2, 1),
2419};
2420static const unsigned int msiof3_ss1_e_mux[] = {
2421 MSIOF3_SS1_E_MARK,
2422};
2423static const unsigned int msiof3_ss2_e_pins[] = {
2424 /* SS1 */
2425 RCAR_GP_PIN(2, 0),
2426};
2427static const unsigned int msiof3_ss2_e_mux[] = {
2428 MSIOF3_SS2_E_MARK,
2429};
2430static const unsigned int msiof3_txd_e_pins[] = {
2431 /* TXD */
2432 RCAR_GP_PIN(2, 5),
2433};
2434static const unsigned int msiof3_txd_e_mux[] = {
2435 MSIOF3_TXD_E_MARK,
2436};
2437static const unsigned int msiof3_rxd_e_pins[] = {
2438 /* RXD */
2439 RCAR_GP_PIN(2, 4),
2440};
2441static const unsigned int msiof3_rxd_e_mux[] = {
2442 MSIOF3_RXD_E_MARK,
2443};
2444
c03a133b
LP		 2445/* - PWM0 --------------------------------------------------------------------*/
2446static const unsigned int pwm0_pins[] = {
2447 /* PWM */
2448 RCAR_GP_PIN(2, 6),
2449};
2450static const unsigned int pwm0_mux[] = {
2451 PWM0_MARK,
2452};
2453/* - PWM1 --------------------------------------------------------------------*/
2454static const unsigned int pwm1_a_pins[] = {
2455 /* PWM */
2456 RCAR_GP_PIN(2, 7),
2457};
2458static const unsigned int pwm1_a_mux[] = {
2459 PWM1_A_MARK,
2460};
2461static const unsigned int pwm1_b_pins[] = {
2462 /* PWM */
2463 RCAR_GP_PIN(1, 8),
2464};
2465static const unsigned int pwm1_b_mux[] = {
2466 PWM1_B_MARK,
2467};
2468/* - PWM2 --------------------------------------------------------------------*/
2469static const unsigned int pwm2_a_pins[] = {
2470 /* PWM */
2471 RCAR_GP_PIN(2, 8),
2472};
2473static const unsigned int pwm2_a_mux[] = {
2474 PWM2_A_MARK,
2475};
2476static const unsigned int pwm2_b_pins[] = {
2477 /* PWM */
2478 RCAR_GP_PIN(1, 11),
2479};
2480static const unsigned int pwm2_b_mux[] = {
2481 PWM2_B_MARK,
2482};
2483/* - PWM3 --------------------------------------------------------------------*/
2484static const unsigned int pwm3_a_pins[] = {
2485 /* PWM */
2486 RCAR_GP_PIN(1, 0),
2487};
2488static const unsigned int pwm3_a_mux[] = {
2489 PWM3_A_MARK,
2490};
2491static const unsigned int pwm3_b_pins[] = {
2492 /* PWM */
2493 RCAR_GP_PIN(2, 2),
2494};
2495static const unsigned int pwm3_b_mux[] = {
2496 PWM3_B_MARK,
2497};
2498/* - PWM4 --------------------------------------------------------------------*/
2499static const unsigned int pwm4_a_pins[] = {
2500 /* PWM */
2501 RCAR_GP_PIN(1, 1),
2502};
2503static const unsigned int pwm4_a_mux[] = {
2504 PWM4_A_MARK,
2505};
2506static const unsigned int pwm4_b_pins[] = {
2507 /* PWM */
2508 RCAR_GP_PIN(2, 3),
2509};
2510static const unsigned int pwm4_b_mux[] = {
2511 PWM4_B_MARK,
2512};
2513/* - PWM5 --------------------------------------------------------------------*/
2514static const unsigned int pwm5_a_pins[] = {
2515 /* PWM */
2516 RCAR_GP_PIN(1, 2),
2517};
2518static const unsigned int pwm5_a_mux[] = {
2519 PWM5_A_MARK,
2520};
2521static const unsigned int pwm5_b_pins[] = {
2522 /* PWM */
2523 RCAR_GP_PIN(2, 4),
2524};
2525static const unsigned int pwm5_b_mux[] = {
2526 PWM5_B_MARK,
2527};
2528/* - PWM6 --------------------------------------------------------------------*/
2529static const unsigned int pwm6_a_pins[] = {
2530 /* PWM */
2531 RCAR_GP_PIN(1, 3),
2532};
2533static const unsigned int pwm6_a_mux[] = {
2534 PWM6_A_MARK,
2535};
2536static const unsigned int pwm6_b_pins[] = {
2537 /* PWM */
2538 RCAR_GP_PIN(2, 5),
2539};
2540static const unsigned int pwm6_b_mux[] = {
2541 PWM6_B_MARK,
2542};
2543
e7ad4d3c
GU		 2544/* - SCIF0 ------------------------------------------------------------------ */
2545static const unsigned int scif0_data_pins[] = {
2546 /* RX, TX */
2547 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2548};
2549static const unsigned int scif0_data_mux[] = {
2550 RX0_MARK, TX0_MARK,
2551};
2552static const unsigned int scif0_clk_pins[] = {
2553 /* SCK */
2554 RCAR_GP_PIN(5, 0),
2555};
2556static const unsigned int scif0_clk_mux[] = {
2557 SCK0_MARK,
2558};
2559static const unsigned int scif0_ctrl_pins[] = {
2560 /* RTS, CTS */
2561 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2562};
2563static const unsigned int scif0_ctrl_mux[] = {
2564 RTS0_N_TANS_MARK, CTS0_N_MARK,
2565};
2566/* - SCIF1 ------------------------------------------------------------------ */
2567static const unsigned int scif1_data_a_pins[] = {
2568 /* RX, TX */
2569 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2570};
2571static const unsigned int scif1_data_a_mux[] = {
2572 RX1_A_MARK, TX1_A_MARK,
2573};
2574static const unsigned int scif1_clk_pins[] = {
2575 /* SCK */
2576 RCAR_GP_PIN(6, 21),
2577};
2578static const unsigned int scif1_clk_mux[] = {
2579 SCK1_MARK,
2580};
2581static const unsigned int scif1_ctrl_pins[] = {
2582 /* RTS, CTS */
2583 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2584};
2585static const unsigned int scif1_ctrl_mux[] = {
2586 RTS1_N_TANS_MARK, CTS1_N_MARK,
2587};
2588
2589static const unsigned int scif1_data_b_pins[] = {
2590 /* RX, TX */
2591 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2592};
2593static const unsigned int scif1_data_b_mux[] = {
2594 RX1_B_MARK, TX1_B_MARK,
2595};
2596/* - SCIF2 ------------------------------------------------------------------ */
2597static const unsigned int scif2_data_a_pins[] = {
2598 /* RX, TX */
2599 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2600};
2601static const unsigned int scif2_data_a_mux[] = {
2602 RX2_A_MARK, TX2_A_MARK,
2603};
2604static const unsigned int scif2_clk_pins[] = {
2605 /* SCK */
2606 RCAR_GP_PIN(5, 9),
2607};
2608static const unsigned int scif2_clk_mux[] = {
2609 SCK2_MARK,
2610};
2611static const unsigned int scif2_data_b_pins[] = {
2612 /* RX, TX */
2613 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2614};
2615static const unsigned int scif2_data_b_mux[] = {
2616 RX2_B_MARK, TX2_B_MARK,
2617};
2618/* - SCIF3 ------------------------------------------------------------------ */
2619static const unsigned int scif3_data_a_pins[] = {
2620 /* RX, TX */
2621 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2622};
2623static const unsigned int scif3_data_a_mux[] = {
2624 RX3_A_MARK, TX3_A_MARK,
2625};
2626static const unsigned int scif3_clk_pins[] = {
2627 /* SCK */
2628 RCAR_GP_PIN(1, 22),
2629};
2630static const unsigned int scif3_clk_mux[] = {
2631 SCK3_MARK,
2632};
2633static const unsigned int scif3_ctrl_pins[] = {
2634 /* RTS, CTS */
2635 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2636};
2637static const unsigned int scif3_ctrl_mux[] = {
2638 RTS3_N_TANS_MARK, CTS3_N_MARK,
2639};
2640static const unsigned int scif3_data_b_pins[] = {
2641 /* RX, TX */
2642 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2643};
2644static const unsigned int scif3_data_b_mux[] = {
2645 RX3_B_MARK, TX3_B_MARK,
2646};
2647/* - SCIF4 ------------------------------------------------------------------ */
2648static const unsigned int scif4_data_a_pins[] = {
2649 /* RX, TX */
2650 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2651};
2652static const unsigned int scif4_data_a_mux[] = {
2653 RX4_A_MARK, TX4_A_MARK,
2654};
2655static const unsigned int scif4_clk_a_pins[] = {
2656 /* SCK */
2657 RCAR_GP_PIN(2, 10),
2658};
2659static const unsigned int scif4_clk_a_mux[] = {
2660 SCK4_A_MARK,
2661};
2662static const unsigned int scif4_ctrl_a_pins[] = {
2663 /* RTS, CTS */
2664 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2665};
2666static const unsigned int scif4_ctrl_a_mux[] = {
2667 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2668};
2669static const unsigned int scif4_data_b_pins[] = {
2670 /* RX, TX */
2671 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2672};
2673static const unsigned int scif4_data_b_mux[] = {
2674 RX4_B_MARK, TX4_B_MARK,
2675};
2676static const unsigned int scif4_clk_b_pins[] = {
2677 /* SCK */
2678 RCAR_GP_PIN(1, 5),
2679};
2680static const unsigned int scif4_clk_b_mux[] = {
2681 SCK4_B_MARK,
2682};
2683static const unsigned int scif4_ctrl_b_pins[] = {
2684 /* RTS, CTS */
2685 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2686};
2687static const unsigned int scif4_ctrl_b_mux[] = {
2688 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
2689};
2690static const unsigned int scif4_data_c_pins[] = {
2691 /* RX, TX */
2692 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2693};
2694static const unsigned int scif4_data_c_mux[] = {
2695 RX4_C_MARK, TX4_C_MARK,
2696};
2697static const unsigned int scif4_clk_c_pins[] = {
2698 /* SCK */
2699 RCAR_GP_PIN(0, 8),
2700};
2701static const unsigned int scif4_clk_c_mux[] = {
2702 SCK4_C_MARK,
2703};
2704static const unsigned int scif4_ctrl_c_pins[] = {
2705 /* RTS, CTS */
2706 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2707};
2708static const unsigned int scif4_ctrl_c_mux[] = {
2709 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2710};
2711/* - SCIF5 ------------------------------------------------------------------ */
2712static const unsigned int scif5_data_a_pins[] = {
2713 /* RX, TX */
2714 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2715};
2716static const unsigned int scif5_data_a_mux[] = {
2717 RX5_A_MARK, TX5_A_MARK,
2718};
2719static const unsigned int scif5_clk_a_pins[] = {
2720 /* SCK */
2721 RCAR_GP_PIN(6, 21),
2722};
2723static const unsigned int scif5_clk_a_mux[] = {
2724 SCK5_A_MARK,
2725};
2726static const unsigned int scif5_data_b_pins[] = {
2727 /* RX, TX */
2728 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
2729};
2730static const unsigned int scif5_data_b_mux[] = {
2731 RX5_B_MARK, TX5_B_MARK,
2732};
2733static const unsigned int scif5_clk_b_pins[] = {
2734 /* SCK */
2735 RCAR_GP_PIN(5, 0),
2736};
2737static const unsigned int scif5_clk_b_mux[] = {
2738 SCK5_B_MARK,
2739};
2740
d14a39ed
GU		 2741/* - SCIF Clock ------------------------------------------------------------- */
2742static const unsigned int scif_clk_a_pins[] = {
2743 /* SCIF_CLK */
2744 RCAR_GP_PIN(6, 23),
2745};
2746static const unsigned int scif_clk_a_mux[] = {
2747 SCIF_CLK_A_MARK,
2748};
2749static const unsigned int scif_clk_b_pins[] = {
2750 /* SCIF_CLK */
2751 RCAR_GP_PIN(5, 9),
2752};
2753static const unsigned int scif_clk_b_mux[] = {
2754 SCIF_CLK_B_MARK,
2755};
2756
933ddbe5
YS		 2757/* - USB0 ------------------------------------------------------------------- */
2758static const unsigned int usb0_pins[] = {
2759 /* PWEN, OVC */
2760 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2761};
2762static const unsigned int usb0_mux[] = {
2763 USB0_PWEN_MARK, USB0_OVC_MARK,
2764};
2765/* - USB1 ------------------------------------------------------------------- */
2766static const unsigned int usb1_pins[] = {
2767 /* PWEN, OVC */
2768 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2769};
2770static const unsigned int usb1_mux[] = {
2771 USB1_PWEN_MARK, USB1_OVC_MARK,
2772};
2773/* - USB2 ------------------------------------------------------------------- */
2774static const unsigned int usb2_pins[] = {
2775 /* PWEN, OVC */
2776 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2777};
2778static const unsigned int usb2_mux[] = {
2779 USB2_PWEN_MARK, USB2_OVC_MARK,
2780};
2781/* - USB2_CH3 --------------------------------------------------------------- */
2782static const unsigned int usb2_ch3_pins[] = {
2783 /* PWEN, OVC */
2784 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
2785};
2786static const unsigned int usb2_ch3_mux[] = {
2787 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
2788};
2789
b205914c 2790static const struct sh_pfc_pin_group pinmux_groups[] = {
30c078de
GU		 2791 SH_PFC_PIN_GROUP(avb_link),
2792 SH_PFC_PIN_GROUP(avb_magic),
2793 SH_PFC_PIN_GROUP(avb_phy_int),
2794 SH_PFC_PIN_GROUP(avb_mdc),
2795 SH_PFC_PIN_GROUP(avb_mii),
2796 SH_PFC_PIN_GROUP(avb_avtp_pps),
2797 SH_PFC_PIN_GROUP(avb_avtp_match_a),
2798 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2799 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2800 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a20a6585
LP		 2801 SH_PFC_PIN_GROUP(du_rgb666),
2802 SH_PFC_PIN_GROUP(du_rgb888),
2803 SH_PFC_PIN_GROUP(du_clk_out_0),
2804 SH_PFC_PIN_GROUP(du_clk_out_1),
2805 SH_PFC_PIN_GROUP(du_sync),
2806 SH_PFC_PIN_GROUP(du_oddf),
2807 SH_PFC_PIN_GROUP(du_cde),
2808 SH_PFC_PIN_GROUP(du_disp),
3e6c7727
GU		 2809 SH_PFC_PIN_GROUP(msiof0_clk),
2810 SH_PFC_PIN_GROUP(msiof0_sync),
2811 SH_PFC_PIN_GROUP(msiof0_ss1),
2812 SH_PFC_PIN_GROUP(msiof0_ss2),
2813 SH_PFC_PIN_GROUP(msiof0_txd),
2814 SH_PFC_PIN_GROUP(msiof0_rxd),
2815 SH_PFC_PIN_GROUP(msiof1_clk_a),
2816 SH_PFC_PIN_GROUP(msiof1_sync_a),
2817 SH_PFC_PIN_GROUP(msiof1_ss1_a),
2818 SH_PFC_PIN_GROUP(msiof1_ss2_a),
2819 SH_PFC_PIN_GROUP(msiof1_txd_a),
2820 SH_PFC_PIN_GROUP(msiof1_rxd_a),
2821 SH_PFC_PIN_GROUP(msiof1_clk_b),
2822 SH_PFC_PIN_GROUP(msiof1_sync_b),
2823 SH_PFC_PIN_GROUP(msiof1_ss1_b),
2824 SH_PFC_PIN_GROUP(msiof1_ss2_b),
2825 SH_PFC_PIN_GROUP(msiof1_txd_b),
2826 SH_PFC_PIN_GROUP(msiof1_rxd_b),
2827 SH_PFC_PIN_GROUP(msiof1_clk_c),
2828 SH_PFC_PIN_GROUP(msiof1_sync_c),
2829 SH_PFC_PIN_GROUP(msiof1_ss1_c),
2830 SH_PFC_PIN_GROUP(msiof1_ss2_c),
2831 SH_PFC_PIN_GROUP(msiof1_txd_c),
2832 SH_PFC_PIN_GROUP(msiof1_rxd_c),
2833 SH_PFC_PIN_GROUP(msiof1_clk_d),
2834 SH_PFC_PIN_GROUP(msiof1_sync_d),
2835 SH_PFC_PIN_GROUP(msiof1_ss1_d),
2836 SH_PFC_PIN_GROUP(msiof1_ss2_d),
2837 SH_PFC_PIN_GROUP(msiof1_txd_d),
2838 SH_PFC_PIN_GROUP(msiof1_rxd_d),
2839 SH_PFC_PIN_GROUP(msiof1_clk_e),
2840 SH_PFC_PIN_GROUP(msiof1_sync_e),
2841 SH_PFC_PIN_GROUP(msiof1_ss1_e),
2842 SH_PFC_PIN_GROUP(msiof1_ss2_e),
2843 SH_PFC_PIN_GROUP(msiof1_txd_e),
2844 SH_PFC_PIN_GROUP(msiof1_rxd_e),
2845 SH_PFC_PIN_GROUP(msiof1_clk_f),
2846 SH_PFC_PIN_GROUP(msiof1_sync_f),
2847 SH_PFC_PIN_GROUP(msiof1_ss1_f),
2848 SH_PFC_PIN_GROUP(msiof1_ss2_f),
2849 SH_PFC_PIN_GROUP(msiof1_txd_f),
2850 SH_PFC_PIN_GROUP(msiof1_rxd_f),
2851 SH_PFC_PIN_GROUP(msiof1_clk_g),
2852 SH_PFC_PIN_GROUP(msiof1_sync_g),
2853 SH_PFC_PIN_GROUP(msiof1_ss1_g),
2854 SH_PFC_PIN_GROUP(msiof1_ss2_g),
2855 SH_PFC_PIN_GROUP(msiof1_txd_g),
2856 SH_PFC_PIN_GROUP(msiof1_rxd_g),
2857 SH_PFC_PIN_GROUP(msiof2_clk_a),
2858 SH_PFC_PIN_GROUP(msiof2_sync_a),
2859 SH_PFC_PIN_GROUP(msiof2_ss1_a),
2860 SH_PFC_PIN_GROUP(msiof2_ss2_a),
2861 SH_PFC_PIN_GROUP(msiof2_txd_a),
2862 SH_PFC_PIN_GROUP(msiof2_rxd_a),
2863 SH_PFC_PIN_GROUP(msiof2_clk_b),
2864 SH_PFC_PIN_GROUP(msiof2_sync_b),
2865 SH_PFC_PIN_GROUP(msiof2_ss1_b),
2866 SH_PFC_PIN_GROUP(msiof2_ss2_b),
2867 SH_PFC_PIN_GROUP(msiof2_txd_b),
2868 SH_PFC_PIN_GROUP(msiof2_rxd_b),
2869 SH_PFC_PIN_GROUP(msiof2_clk_c),
2870 SH_PFC_PIN_GROUP(msiof2_sync_c),
2871 SH_PFC_PIN_GROUP(msiof2_ss1_c),
2872 SH_PFC_PIN_GROUP(msiof2_ss2_c),
2873 SH_PFC_PIN_GROUP(msiof2_txd_c),
2874 SH_PFC_PIN_GROUP(msiof2_rxd_c),
2875 SH_PFC_PIN_GROUP(msiof2_clk_d),
2876 SH_PFC_PIN_GROUP(msiof2_sync_d),
2877 SH_PFC_PIN_GROUP(msiof2_ss1_d),
2878 SH_PFC_PIN_GROUP(msiof2_ss2_d),
2879 SH_PFC_PIN_GROUP(msiof2_txd_d),
2880 SH_PFC_PIN_GROUP(msiof2_rxd_d),
2881 SH_PFC_PIN_GROUP(msiof3_clk_a),
2882 SH_PFC_PIN_GROUP(msiof3_sync_a),
2883 SH_PFC_PIN_GROUP(msiof3_ss1_a),
2884 SH_PFC_PIN_GROUP(msiof3_ss2_a),
2885 SH_PFC_PIN_GROUP(msiof3_txd_a),
2886 SH_PFC_PIN_GROUP(msiof3_rxd_a),
2887 SH_PFC_PIN_GROUP(msiof3_clk_b),
2888 SH_PFC_PIN_GROUP(msiof3_sync_b),
2889 SH_PFC_PIN_GROUP(msiof3_ss1_b),
2890 SH_PFC_PIN_GROUP(msiof3_ss2_b),
2891 SH_PFC_PIN_GROUP(msiof3_txd_b),
2892 SH_PFC_PIN_GROUP(msiof3_rxd_b),
2893 SH_PFC_PIN_GROUP(msiof3_clk_c),
2894 SH_PFC_PIN_GROUP(msiof3_sync_c),
2895 SH_PFC_PIN_GROUP(msiof3_txd_c),
2896 SH_PFC_PIN_GROUP(msiof3_rxd_c),
2897 SH_PFC_PIN_GROUP(msiof3_clk_d),
2898 SH_PFC_PIN_GROUP(msiof3_sync_d),
2899 SH_PFC_PIN_GROUP(msiof3_ss1_d),
2900 SH_PFC_PIN_GROUP(msiof3_txd_d),
2901 SH_PFC_PIN_GROUP(msiof3_rxd_d),
2902 SH_PFC_PIN_GROUP(msiof3_clk_e),
2903 SH_PFC_PIN_GROUP(msiof3_sync_e),
2904 SH_PFC_PIN_GROUP(msiof3_ss1_e),
2905 SH_PFC_PIN_GROUP(msiof3_ss2_e),
2906 SH_PFC_PIN_GROUP(msiof3_txd_e),
2907 SH_PFC_PIN_GROUP(msiof3_rxd_e),
c03a133b
LP		 2908 SH_PFC_PIN_GROUP(pwm0),
2909 SH_PFC_PIN_GROUP(pwm1_a),
2910 SH_PFC_PIN_GROUP(pwm1_b),
2911 SH_PFC_PIN_GROUP(pwm2_a),
2912 SH_PFC_PIN_GROUP(pwm2_b),
2913 SH_PFC_PIN_GROUP(pwm3_a),
2914 SH_PFC_PIN_GROUP(pwm3_b),
2915 SH_PFC_PIN_GROUP(pwm4_a),
2916 SH_PFC_PIN_GROUP(pwm4_b),
2917 SH_PFC_PIN_GROUP(pwm5_a),
2918 SH_PFC_PIN_GROUP(pwm5_b),
2919 SH_PFC_PIN_GROUP(pwm6_a),
2920 SH_PFC_PIN_GROUP(pwm6_b),
e7ad4d3c
GU		 2921 SH_PFC_PIN_GROUP(scif0_data),
2922 SH_PFC_PIN_GROUP(scif0_clk),
2923 SH_PFC_PIN_GROUP(scif0_ctrl),
2924 SH_PFC_PIN_GROUP(scif1_data_a),
2925 SH_PFC_PIN_GROUP(scif1_clk),
2926 SH_PFC_PIN_GROUP(scif1_ctrl),
2927 SH_PFC_PIN_GROUP(scif1_data_b),
2928 SH_PFC_PIN_GROUP(scif2_data_a),
2929 SH_PFC_PIN_GROUP(scif2_clk),
2930 SH_PFC_PIN_GROUP(scif2_data_b),
2931 SH_PFC_PIN_GROUP(scif3_data_a),
2932 SH_PFC_PIN_GROUP(scif3_clk),
2933 SH_PFC_PIN_GROUP(scif3_ctrl),
2934 SH_PFC_PIN_GROUP(scif3_data_b),
2935 SH_PFC_PIN_GROUP(scif4_data_a),
2936 SH_PFC_PIN_GROUP(scif4_clk_a),
2937 SH_PFC_PIN_GROUP(scif4_ctrl_a),
2938 SH_PFC_PIN_GROUP(scif4_data_b),
2939 SH_PFC_PIN_GROUP(scif4_clk_b),
2940 SH_PFC_PIN_GROUP(scif4_ctrl_b),
2941 SH_PFC_PIN_GROUP(scif4_data_c),
2942 SH_PFC_PIN_GROUP(scif4_clk_c),
2943 SH_PFC_PIN_GROUP(scif4_ctrl_c),
2944 SH_PFC_PIN_GROUP(scif5_data_a),
2945 SH_PFC_PIN_GROUP(scif5_clk_a),
2946 SH_PFC_PIN_GROUP(scif5_data_b),
2947 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 2948 SH_PFC_PIN_GROUP(scif_clk_a),
2949 SH_PFC_PIN_GROUP(scif_clk_b),
933ddbe5
YS		 2950 SH_PFC_PIN_GROUP(usb0),
2951 SH_PFC_PIN_GROUP(usb1),
2952 SH_PFC_PIN_GROUP(usb2),
2953 SH_PFC_PIN_GROUP(usb2_ch3),
e7ad4d3c
GU		 2954};
2955
30c078de
GU		 2956static const char * const avb_groups[] = {
2957 "avb_link",
2958 "avb_magic",
2959 "avb_phy_int",
2960 "avb_mdc",
2961 "avb_mii",
2962 "avb_avtp_pps",
2963 "avb_avtp_match_a",
2964 "avb_avtp_capture_a",
2965 "avb_avtp_match_b",
2966 "avb_avtp_capture_b",
2967};
2968
a20a6585
LP		 2969static const char * const du_groups[] = {
2970 "du_rgb666",
2971 "du_rgb888",
2972 "du_clk_out_0",
2973 "du_clk_out_1",
2974 "du_sync",
2975 "du_oddf",
2976 "du_cde",
2977 "du_disp",
2978};
2979
3e6c7727
GU		 2980static const char * const msiof0_groups[] = {
2981 "msiof0_clk",
2982 "msiof0_sync",
2983 "msiof0_ss1",
2984 "msiof0_ss2",
2985 "msiof0_txd",
2986 "msiof0_rxd",
2987};
2988
2989static const char * const msiof1_groups[] = {
2990 "msiof1_clk_a",
2991 "msiof1_sync_a",
2992 "msiof1_ss1_a",
2993 "msiof1_ss2_a",
2994 "msiof1_txd_a",
2995 "msiof1_rxd_a",
2996 "msiof1_clk_b",
2997 "msiof1_sync_b",
2998 "msiof1_ss1_b",
2999 "msiof1_ss2_b",
3000 "msiof1_txd_b",
3001 "msiof1_rxd_b",
3002 "msiof1_clk_c",
3003 "msiof1_sync_c",
3004 "msiof1_ss1_c",
3005 "msiof1_ss2_c",
3006 "msiof1_txd_c",
3007 "msiof1_rxd_c",
3008 "msiof1_clk_d",
3009 "msiof1_sync_d",
3010 "msiof1_ss1_d",
3011 "msiof1_ss2_d",
3012 "msiof1_txd_d",
3013 "msiof1_rxd_d",
3014 "msiof1_clk_e",
3015 "msiof1_sync_e",
3016 "msiof1_ss1_e",
3017 "msiof1_ss2_e",
3018 "msiof1_txd_e",
3019 "msiof1_rxd_e",
3020 "msiof1_clk_f",
3021 "msiof1_sync_f",
3022 "msiof1_ss1_f",
3023 "msiof1_ss2_f",
3024 "msiof1_txd_f",
3025 "msiof1_rxd_f",
3026 "msiof1_clk_g",
3027 "msiof1_sync_g",
3028 "msiof1_ss1_g",
3029 "msiof1_ss2_g",
3030 "msiof1_txd_g",
3031 "msiof1_rxd_g",
3032};
3033
3034static const char * const msiof2_groups[] = {
3035 "msiof2_clk_a",
3036 "msiof2_sync_a",
3037 "msiof2_ss1_a",
3038 "msiof2_ss2_a",
3039 "msiof2_txd_a",
3040 "msiof2_rxd_a",
3041 "msiof2_clk_b",
3042 "msiof2_sync_b",
3043 "msiof2_ss1_b",
3044 "msiof2_ss2_b",
3045 "msiof2_txd_b",
3046 "msiof2_rxd_b",
3047 "msiof2_clk_c",
3048 "msiof2_sync_c",
3049 "msiof2_ss1_c",
3050 "msiof2_ss2_c",
3051 "msiof2_txd_c",
3052 "msiof2_rxd_c",
3053 "msiof2_clk_d",
3054 "msiof2_sync_d",
3055 "msiof2_ss1_d",
3056 "msiof2_ss2_d",
3057 "msiof2_txd_d",
3058 "msiof2_rxd_d",
3059};
3060
3061static const char * const msiof3_groups[] = {
3062 "msiof3_clk_a",
3063 "msiof3_sync_a",
3064 "msiof3_ss1_a",
3065 "msiof3_ss2_a",
3066 "msiof3_txd_a",
3067 "msiof3_rxd_a",
3068 "msiof3_clk_b",
3069 "msiof3_sync_b",
3070 "msiof3_ss1_b",
3071 "msiof3_ss2_b",
3072 "msiof3_txd_b",
3073 "msiof3_rxd_b",
3074 "msiof3_clk_c",
3075 "msiof3_sync_c",
3076 "msiof3_txd_c",
3077 "msiof3_rxd_c",
3078 "msiof3_clk_d",
3079 "msiof3_sync_d",
3080 "msiof3_ss1_d",
3081 "msiof3_txd_d",
3082 "msiof3_rxd_d",
3083 "msiof3_clk_e",
3084 "msiof3_sync_e",
3085 "msiof3_ss1_e",
3086 "msiof3_ss2_e",
3087 "msiof3_txd_e",
3088 "msiof3_rxd_e",
3089};
3090
c03a133b
LP		 3091static const char * const pwm0_groups[] = {
3092 "pwm0",
3093};
3094
3095static const char * const pwm1_groups[] = {
3096 "pwm1_a",
3097 "pwm1_b",
3098};
3099
3100static const char * const pwm2_groups[] = {
3101 "pwm2_a",
3102 "pwm2_b",
3103};
3104
3105static const char * const pwm3_groups[] = {
3106 "pwm3_a",
3107 "pwm3_b",
3108};
3109
3110static const char * const pwm4_groups[] = {
3111 "pwm4_a",
3112 "pwm4_b",
3113};
3114
3115static const char * const pwm5_groups[] = {
3116 "pwm5_a",
3117 "pwm5_b",
3118};
3119
3120static const char * const pwm6_groups[] = {
3121 "pwm6_a",
3122 "pwm6_b",
3123};
3124
e7ad4d3c
GU		 3125static const char * const scif0_groups[] = {
3126 "scif0_data",
3127 "scif0_clk",
3128 "scif0_ctrl",
3129};
3130
3131static const char * const scif1_groups[] = {
3132 "scif1_data_a",
3133 "scif1_clk",
3134 "scif1_ctrl",
3135 "scif1_data_b",
3136};
3137
3138static const char * const scif2_groups[] = {
3139 "scif2_data_a",
3140 "scif2_clk",
3141 "scif2_data_b",
3142};
3143
3144static const char * const scif3_groups[] = {
3145 "scif3_data_a",
3146 "scif3_clk",
3147 "scif3_ctrl",
3148 "scif3_data_b",
3149};
3150
3151static const char * const scif4_groups[] = {
3152 "scif4_data_a",
3153 "scif4_clk_a",
3154 "scif4_ctrl_a",
3155 "scif4_data_b",
3156 "scif4_clk_b",
3157 "scif4_ctrl_b",
3158 "scif4_data_c",
3159 "scif4_clk_c",
3160 "scif4_ctrl_c",
3161};
3162
3163static const char * const scif5_groups[] = {
3164 "scif5_data_a",
3165 "scif5_clk_a",
3166 "scif5_data_b",
3167 "scif5_clk_b",
76250a6c
TK		 3168};
3169
d14a39ed
GU		 3170static const char * const scif_clk_groups[] = {
3171 "scif_clk_a",
3172 "scif_clk_b",
3173};
3174
933ddbe5
YS		 3175static const char * const usb0_groups[] = {
3176 "usb0",
3177};
3178
3179static const char * const usb1_groups[] = {
3180 "usb1",
3181};
3182
3183static const char * const usb2_groups[] = {
3184 "usb2",
3185};
3186
3187static const char * const usb2_ch3_groups[] = {
3188 "usb2_ch3",
3189};
3190
0b0ffc96 3191static const struct sh_pfc_function pinmux_functions[] = {
30c078de 3192 SH_PFC_FUNCTION(avb),
a20a6585 3193 SH_PFC_FUNCTION(du),
3e6c7727
GU		 3194 SH_PFC_FUNCTION(msiof0),
3195 SH_PFC_FUNCTION(msiof1),
3196 SH_PFC_FUNCTION(msiof2),
3197 SH_PFC_FUNCTION(msiof3),
c03a133b
LP		 3198 SH_PFC_FUNCTION(pwm0),
3199 SH_PFC_FUNCTION(pwm1),
3200 SH_PFC_FUNCTION(pwm2),
3201 SH_PFC_FUNCTION(pwm3),
3202 SH_PFC_FUNCTION(pwm4),
3203 SH_PFC_FUNCTION(pwm5),
3204 SH_PFC_FUNCTION(pwm6),
e7ad4d3c
GU		 3205 SH_PFC_FUNCTION(scif0),
3206 SH_PFC_FUNCTION(scif1),
3207 SH_PFC_FUNCTION(scif2),
3208 SH_PFC_FUNCTION(scif3),
3209 SH_PFC_FUNCTION(scif4),
3210 SH_PFC_FUNCTION(scif5),
d14a39ed 3211 SH_PFC_FUNCTION(scif_clk),
933ddbe5
YS		 3212 SH_PFC_FUNCTION(usb0),
3213 SH_PFC_FUNCTION(usb1),
3214 SH_PFC_FUNCTION(usb2),
3215 SH_PFC_FUNCTION(usb2_ch3),
0b0ffc96
TK		 3216};
3217
3218static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3219#define F_(x, y) FN_##y
3220#define FM(x) FN_##x
3221 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
3222 0, 0,
3223 0, 0,
3224 0, 0,
3225 0, 0,
3226 0, 0,
3227 0, 0,
3228 0, 0,
3229 0, 0,
3230 0, 0,
3231 0, 0,
3232 0, 0,
3233 0, 0,
3234 0, 0,
3235 0, 0,
3236 0, 0,
3237 0, 0,
3238 GP_0_15_FN, GPSR0_15,
3239 GP_0_14_FN, GPSR0_14,
3240 GP_0_13_FN, GPSR0_13,
3241 GP_0_12_FN, GPSR0_12,
3242 GP_0_11_FN, GPSR0_11,
3243 GP_0_10_FN, GPSR0_10,
3244 GP_0_9_FN, GPSR0_9,
3245 GP_0_8_FN, GPSR0_8,
3246 GP_0_7_FN, GPSR0_7,
3247 GP_0_6_FN, GPSR0_6,
3248 GP_0_5_FN, GPSR0_5,
3249 GP_0_4_FN, GPSR0_4,
3250 GP_0_3_FN, GPSR0_3,
3251 GP_0_2_FN, GPSR0_2,
3252 GP_0_1_FN, GPSR0_1,
3253 GP_0_0_FN, GPSR0_0, }
3254 },
3255 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
3256 0, 0,
3257 0, 0,
3258 0, 0,
3259 0, 0,
3260 GP_1_27_FN, GPSR1_27,
3261 GP_1_26_FN, GPSR1_26,
3262 GP_1_25_FN, GPSR1_25,
3263 GP_1_24_FN, GPSR1_24,
3264 GP_1_23_FN, GPSR1_23,
3265 GP_1_22_FN, GPSR1_22,
3266 GP_1_21_FN, GPSR1_21,
3267 GP_1_20_FN, GPSR1_20,
3268 GP_1_19_FN, GPSR1_19,
3269 GP_1_18_FN, GPSR1_18,
3270 GP_1_17_FN, GPSR1_17,
3271 GP_1_16_FN, GPSR1_16,
3272 GP_1_15_FN, GPSR1_15,
3273 GP_1_14_FN, GPSR1_14,
3274 GP_1_13_FN, GPSR1_13,
3275 GP_1_12_FN, GPSR1_12,
3276 GP_1_11_FN, GPSR1_11,
3277 GP_1_10_FN, GPSR1_10,
3278 GP_1_9_FN, GPSR1_9,
3279 GP_1_8_FN, GPSR1_8,
3280 GP_1_7_FN, GPSR1_7,
3281 GP_1_6_FN, GPSR1_6,
3282 GP_1_5_FN, GPSR1_5,
3283 GP_1_4_FN, GPSR1_4,
3284 GP_1_3_FN, GPSR1_3,
3285 GP_1_2_FN, GPSR1_2,
3286 GP_1_1_FN, GPSR1_1,
3287 GP_1_0_FN, GPSR1_0, }
3288 },
3289 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
3290 0, 0,
3291 0, 0,
3292 0, 0,
3293 0, 0,
3294 0, 0,
3295 0, 0,
3296 0, 0,
3297 0, 0,
3298 0, 0,
3299 0, 0,
3300 0, 0,
3301 0, 0,
3302 0, 0,
3303 0, 0,
3304 0, 0,
3305 0, 0,
3306 0, 0,
3307 GP_2_14_FN, GPSR2_14,
3308 GP_2_13_FN, GPSR2_13,
3309 GP_2_12_FN, GPSR2_12,
3310 GP_2_11_FN, GPSR2_11,
3311 GP_2_10_FN, GPSR2_10,
3312 GP_2_9_FN, GPSR2_9,
3313 GP_2_8_FN, GPSR2_8,
3314 GP_2_7_FN, GPSR2_7,
3315 GP_2_6_FN, GPSR2_6,
3316 GP_2_5_FN, GPSR2_5,
3317 GP_2_4_FN, GPSR2_4,
3318 GP_2_3_FN, GPSR2_3,
3319 GP_2_2_FN, GPSR2_2,
3320 GP_2_1_FN, GPSR2_1,
3321 GP_2_0_FN, GPSR2_0, }
3322 },
3323 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
3324 0, 0,
3325 0, 0,
3326 0, 0,
3327 0, 0,
3328 0, 0,
3329 0, 0,
3330 0, 0,
3331 0, 0,
3332 0, 0,
3333 0, 0,
3334 0, 0,
3335 0, 0,
3336 0, 0,
3337 0, 0,
3338 0, 0,
3339 0, 0,
3340 GP_3_15_FN, GPSR3_15,
3341 GP_3_14_FN, GPSR3_14,
3342 GP_3_13_FN, GPSR3_13,
3343 GP_3_12_FN, GPSR3_12,
3344 GP_3_11_FN, GPSR3_11,
3345 GP_3_10_FN, GPSR3_10,
3346 GP_3_9_FN, GPSR3_9,
3347 GP_3_8_FN, GPSR3_8,
3348 GP_3_7_FN, GPSR3_7,
3349 GP_3_6_FN, GPSR3_6,
3350 GP_3_5_FN, GPSR3_5,
3351 GP_3_4_FN, GPSR3_4,
3352 GP_3_3_FN, GPSR3_3,
3353 GP_3_2_FN, GPSR3_2,
3354 GP_3_1_FN, GPSR3_1,
3355 GP_3_0_FN, GPSR3_0, }
3356 },
3357 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
3358 0, 0,
3359 0, 0,
3360 0, 0,
3361 0, 0,
3362 0, 0,
3363 0, 0,
3364 0, 0,
3365 0, 0,
3366 0, 0,
3367 0, 0,
3368 0, 0,
3369 0, 0,
3370 0, 0,
3371 0, 0,
3372 GP_4_17_FN, GPSR4_17,
3373 GP_4_16_FN, GPSR4_16,
3374 GP_4_15_FN, GPSR4_15,
3375 GP_4_14_FN, GPSR4_14,
3376 GP_4_13_FN, GPSR4_13,
3377 GP_4_12_FN, GPSR4_12,
3378 GP_4_11_FN, GPSR4_11,
3379 GP_4_10_FN, GPSR4_10,
3380 GP_4_9_FN, GPSR4_9,
3381 GP_4_8_FN, GPSR4_8,
3382 GP_4_7_FN, GPSR4_7,
3383 GP_4_6_FN, GPSR4_6,
3384 GP_4_5_FN, GPSR4_5,
3385 GP_4_4_FN, GPSR4_4,
3386 GP_4_3_FN, GPSR4_3,
3387 GP_4_2_FN, GPSR4_2,
3388 GP_4_1_FN, GPSR4_1,
3389 GP_4_0_FN, GPSR4_0, }
3390 },
3391 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
3392 0, 0,
3393 0, 0,
3394 0, 0,
3395 0, 0,
3396 0, 0,
3397 0, 0,
3398 GP_5_25_FN, GPSR5_25,
3399 GP_5_24_FN, GPSR5_24,
3400 GP_5_23_FN, GPSR5_23,
3401 GP_5_22_FN, GPSR5_22,
3402 GP_5_21_FN, GPSR5_21,
3403 GP_5_20_FN, GPSR5_20,
3404 GP_5_19_FN, GPSR5_19,
3405 GP_5_18_FN, GPSR5_18,
3406 GP_5_17_FN, GPSR5_17,
3407 GP_5_16_FN, GPSR5_16,
3408 GP_5_15_FN, GPSR5_15,
3409 GP_5_14_FN, GPSR5_14,
3410 GP_5_13_FN, GPSR5_13,
3411 GP_5_12_FN, GPSR5_12,
3412 GP_5_11_FN, GPSR5_11,
3413 GP_5_10_FN, GPSR5_10,
3414 GP_5_9_FN, GPSR5_9,
3415 GP_5_8_FN, GPSR5_8,
3416 GP_5_7_FN, GPSR5_7,
3417 GP_5_6_FN, GPSR5_6,
3418 GP_5_5_FN, GPSR5_5,
3419 GP_5_4_FN, GPSR5_4,
3420 GP_5_3_FN, GPSR5_3,
3421 GP_5_2_FN, GPSR5_2,
3422 GP_5_1_FN, GPSR5_1,
3423 GP_5_0_FN, GPSR5_0, }
3424 },
3425 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
3426 GP_6_31_FN, GPSR6_31,
3427 GP_6_30_FN, GPSR6_30,
3428 GP_6_29_FN, GPSR6_29,
3429 GP_6_28_FN, GPSR6_28,
3430 GP_6_27_FN, GPSR6_27,
3431 GP_6_26_FN, GPSR6_26,
3432 GP_6_25_FN, GPSR6_25,
3433 GP_6_24_FN, GPSR6_24,
3434 GP_6_23_FN, GPSR6_23,
3435 GP_6_22_FN, GPSR6_22,
3436 GP_6_21_FN, GPSR6_21,
3437 GP_6_20_FN, GPSR6_20,
3438 GP_6_19_FN, GPSR6_19,
3439 GP_6_18_FN, GPSR6_18,
3440 GP_6_17_FN, GPSR6_17,
3441 GP_6_16_FN, GPSR6_16,
3442 GP_6_15_FN, GPSR6_15,
3443 GP_6_14_FN, GPSR6_14,
3444 GP_6_13_FN, GPSR6_13,
3445 GP_6_12_FN, GPSR6_12,
3446 GP_6_11_FN, GPSR6_11,
3447 GP_6_10_FN, GPSR6_10,
3448 GP_6_9_FN, GPSR6_9,
3449 GP_6_8_FN, GPSR6_8,
3450 GP_6_7_FN, GPSR6_7,
3451 GP_6_6_FN, GPSR6_6,
3452 GP_6_5_FN, GPSR6_5,
3453 GP_6_4_FN, GPSR6_4,
3454 GP_6_3_FN, GPSR6_3,
3455 GP_6_2_FN, GPSR6_2,
3456 GP_6_1_FN, GPSR6_1,
3457 GP_6_0_FN, GPSR6_0, }
3458 },
3459 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
3460 0, 0,
3461 0, 0,
3462 0, 0,
3463 0, 0,
3464 0, 0,
3465 0, 0,
3466 0, 0,
3467 0, 0,
3468 0, 0,
3469 0, 0,
3470 0, 0,
3471 0, 0,
3472 0, 0,
3473 0, 0,
3474 0, 0,
3475 0, 0,
3476 0, 0,
3477 0, 0,
3478 0, 0,
3479 0, 0,
3480 0, 0,
3481 0, 0,
3482 0, 0,
3483 0, 0,
3484 0, 0,
3485 0, 0,
3486 0, 0,
3487 0, 0,
3488 GP_7_3_FN, GPSR7_3,
3489 GP_7_2_FN, GPSR7_2,
3490 GP_7_1_FN, GPSR7_1,
3491 GP_7_0_FN, GPSR7_0, }
3492 },
3493#undef F_
3494#undef FM
3495
3496#define F_(x, y) x,
3497#define FM(x) FN_##x,
3498 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
3499 IP0_31_28
3500 IP0_27_24
3501 IP0_23_20
3502 IP0_19_16
3503 IP0_15_12
3504 IP0_11_8
3505 IP0_7_4
3506 IP0_3_0 }
3507 },
3508 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
3509 IP1_31_28
3510 IP1_27_24
3511 IP1_23_20
3512 IP1_19_16
3513 IP1_15_12
3514 IP1_11_8
3515 IP1_7_4
3516 IP1_3_0 }
3517 },
3518 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
3519 IP2_31_28
3520 IP2_27_24
3521 IP2_23_20
3522 IP2_19_16
3523 IP2_15_12
3524 IP2_11_8
3525 IP2_7_4
3526 IP2_3_0 }
3527 },
3528 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
3529 IP3_31_28
3530 IP3_27_24
3531 IP3_23_20
3532 IP3_19_16
3533 IP3_15_12
3534 IP3_11_8
3535 IP3_7_4
3536 IP3_3_0 }
3537 },
3538 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
3539 IP4_31_28
3540 IP4_27_24
3541 IP4_23_20
3542 IP4_19_16
3543 IP4_15_12
3544 IP4_11_8
3545 IP4_7_4
3546 IP4_3_0 }
3547 },
3548 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
3549 IP5_31_28
3550 IP5_27_24
3551 IP5_23_20
3552 IP5_19_16
3553 IP5_15_12
3554 IP5_11_8
3555 IP5_7_4
3556 IP5_3_0 }
3557 },
3558 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
3559 IP6_31_28
3560 IP6_27_24
3561 IP6_23_20
3562 IP6_19_16
3563 IP6_15_12
3564 IP6_11_8
3565 IP6_7_4
3566 IP6_3_0 }
3567 },
3568 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
3569 IP7_31_28
3570 IP7_27_24
3571 IP7_23_20
3572 IP7_19_16
3573 IP7_15_12
3574 IP7_11_8
3575 IP7_7_4
3576 IP7_3_0 }
3577 },
3578 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
3579 IP8_31_28
3580 IP8_27_24
3581 IP8_23_20
3582 IP8_19_16
3583 IP8_15_12
3584 IP8_11_8
3585 IP8_7_4
3586 IP8_3_0 }
3587 },
3588 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
3589 IP9_31_28
3590 IP9_27_24
3591 IP9_23_20
3592 IP9_19_16
3593 IP9_15_12
3594 IP9_11_8
3595 IP9_7_4
3596 IP9_3_0 }
3597 },
3598 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
3599 IP10_31_28
3600 IP10_27_24
3601 IP10_23_20
3602 IP10_19_16
3603 IP10_15_12
3604 IP10_11_8
3605 IP10_7_4
3606 IP10_3_0 }
3607 },
3608 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
3609 IP11_31_28
3610 IP11_27_24
3611 IP11_23_20
3612 IP11_19_16
3613 IP11_15_12
3614 IP11_11_8
3615 IP11_7_4
3616 IP11_3_0 }
3617 },
3618 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
3619 IP12_31_28
3620 IP12_27_24
3621 IP12_23_20
3622 IP12_19_16
3623 IP12_15_12
3624 IP12_11_8
3625 IP12_7_4
3626 IP12_3_0 }
3627 },
3628 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
3629 IP13_31_28
3630 IP13_27_24
3631 IP13_23_20
3632 IP13_19_16
3633 IP13_15_12
3634 IP13_11_8
3635 IP13_7_4
3636 IP13_3_0 }
3637 },
3638 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
3639 IP14_31_28
3640 IP14_27_24
3641 IP14_23_20
3642 IP14_19_16
3643 IP14_15_12
3644 IP14_11_8
3645 IP14_7_4
3646 IP14_3_0 }
3647 },
3648 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
3649 IP15_31_28
3650 IP15_27_24
3651 IP15_23_20
3652 IP15_19_16
3653 IP15_15_12
3654 IP15_11_8
3655 IP15_7_4
3656 IP15_3_0 }
3657 },
3658 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
3659 IP16_31_28
3660 IP16_27_24
3661 IP16_23_20
3662 IP16_19_16
3663 IP16_15_12
3664 IP16_11_8
3665 IP16_7_4
3666 IP16_3_0 }
3667 },
3668 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
b205914c
GU		 3669 IP17_31_28
3670 IP17_27_24
3671 IP17_23_20
3672 IP17_19_16
3673 IP17_15_12
3674 IP17_11_8
0b0ffc96
TK		 3675 IP17_7_4
3676 IP17_3_0 }
3677 },
b205914c
GU		 3678 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
3679 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3680 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3681 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3682 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3683 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3684 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3685 IP18_7_4
3686 IP18_3_0 }
3687 },
0b0ffc96
TK		 3688#undef F_
3689#undef FM
3690
3691#define F_(x, y) x,
3692#define FM(x) FN_##x,
3693 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
b205914c
GU		 3694 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
3695 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
3696 MOD_SEL0_31_30_29
0b0ffc96
TK		 3697 MOD_SEL0_28_27
3698 MOD_SEL0_26_25_24
3699 MOD_SEL0_23
3700 MOD_SEL0_22
b205914c
GU		 3701 MOD_SEL0_21
3702 MOD_SEL0_20
0b0ffc96 3703 MOD_SEL0_19
b205914c
GU		 3704 MOD_SEL0_18_17
3705 MOD_SEL0_16
3706 0, 0, /* RESERVED 15 */
3707 MOD_SEL0_14_13
0b0ffc96
TK		 3708 MOD_SEL0_12
3709 MOD_SEL0_11
3710 MOD_SEL0_10
b205914c 3711 MOD_SEL0_9_8
0b0ffc96 3712 MOD_SEL0_7_6
b205914c
GU		 3713 MOD_SEL0_5
3714 MOD_SEL0_4_3
3715 /* RESERVED 2, 1, 0 */
3716 0, 0, 0, 0, 0, 0, 0, 0 }
0b0ffc96
TK		 3717 },
3718 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
3719 2, 3, 1, 2, 3, 1, 1, 2, 1,
3720 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
3721 MOD_SEL1_31_30
3722 MOD_SEL1_29_28_27
3723 MOD_SEL1_26
3724 MOD_SEL1_25_24
3725 MOD_SEL1_23_22_21
3726 MOD_SEL1_20
3727 MOD_SEL1_19
3728 MOD_SEL1_18_17
3729 MOD_SEL1_16
3730 MOD_SEL1_15_14
3731 MOD_SEL1_13
3732 MOD_SEL1_12
3733 MOD_SEL1_11
3734 MOD_SEL1_10
3735 MOD_SEL1_9
3736 0, 0, 0, 0, /* RESERVED 8, 7 */
3737 MOD_SEL1_6
3738 MOD_SEL1_5
3739 MOD_SEL1_4
3740 MOD_SEL1_3
3741 MOD_SEL1_2
3742 MOD_SEL1_1
3743 MOD_SEL1_0 }
3744 },
3745 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
b205914c
GU		 3746 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
3747 4, 4, 4, 3, 1) {
0b0ffc96
TK		 3748 MOD_SEL2_31
3749 MOD_SEL2_30
3750 MOD_SEL2_29
b205914c
GU		 3751 MOD_SEL2_28_27
3752 MOD_SEL2_26
3753 MOD_SEL2_25_24_23
3754 MOD_SEL2_22
3755 MOD_SEL2_21
3756 MOD_SEL2_20
3757 MOD_SEL2_19
3758 MOD_SEL2_18
3759 MOD_SEL2_17
3760 /* RESERVED 16 */
0b0ffc96 3761 0, 0,
0b0ffc96
TK		 3762 /* RESERVED 15, 14, 13, 12 */
3763 0, 0, 0, 0, 0, 0, 0, 0,
3764 0, 0, 0, 0, 0, 0, 0, 0,
3765 /* RESERVED 11, 10, 9, 8 */
3766 0, 0, 0, 0, 0, 0, 0, 0,
3767 0, 0, 0, 0, 0, 0, 0, 0,
3768 /* RESERVED 7, 6, 5, 4 */
3769 0, 0, 0, 0, 0, 0, 0, 0,
3770 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 3771 /* RESERVED 3, 2, 1 */
3772 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 3773 MOD_SEL2_0 }
3774 },
3775 { },
3776};
3777
92e6d9a2 3778static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 3779 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
3780 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
3781 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
3782 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
3783 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
3784 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
3785 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
3786 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
3787 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
3788 } },
3789 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
3790 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
3791 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
3792 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
3793 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
3794 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
3795 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
3796 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
3797 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
3798 } },
3799 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
3800 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
3801 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
3802 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
3803 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
3804 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
3805 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
3806 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
3807 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
3808 } },
92e6d9a2 3809 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 3810 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
3811 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
3812 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
3813 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
3814 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
3815 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
3816 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
3817 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 3818 } },
3819 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
3820 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
3821 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
3822 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
3823 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
3824 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
3825 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
3826 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
3827 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
3828 } },
3829 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
3830 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
3831 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
3832 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
3833 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
3834 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
3835 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
3836 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
3837 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
3838 } },
3839 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
3840 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
3841 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
3842 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
3843 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
3844 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
3845 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
3846 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
3847 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
3848 } },
3849 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
3850 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
3851 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
3852 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
3853 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
3854 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
3855 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
3856 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
3857 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
3858 } },
3859 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
ea9c7405 3860 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 3861 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
3862 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
3863 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
3864 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
3865 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
3866 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
3867 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
3868 } },
3869 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
3870 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 3871 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 3872 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
3873 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
3874 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
3875 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
3876 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
3877 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
3878 } },
3879 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
3880 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
3881 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
3882 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
3883 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
3884 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
3885 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
3886 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
3887 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
3888 } },
3889 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 3890 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
3891 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
3892 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
3893 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
3894 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
3895 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
3896 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
3897 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
3898 } },
3899 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
3900 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
3901 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
3902 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
3903 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 3904 } },
3905 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 3906 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
3907 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
3908 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
3909 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
3910 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
3911 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
3912 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
3913 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 3914 } },
3915 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
3916 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
3917 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
3918 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
3919 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
3920 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
3921 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
3922 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
3923 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
3924 } },
3925 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
3926 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
3927 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
3928 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
3929 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
3930 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
3931 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
3932 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
3933 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
3934 } },
3935 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
3936 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
3937 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
3938 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
3939 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
3940 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
3941 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
3942 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
3943 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
3944 } },
3945 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
3946 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
3947 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
3948 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
3949 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
3950 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
3951 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
3952 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
3953 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
3954 } },
3955 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
3956 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
3957 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
3958 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
3959 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
3960 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
3961 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
3962 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
3963 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
3964 } },
3965 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
3966 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
3967 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
3968 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
3969 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
3970 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
3971 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
3972 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
3973 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
3974 } },
3975 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
3976 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
3977 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
3978 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
3979 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
3980 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
3981 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 3982 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 3983 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
3984 } },
3985 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
3986 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
3987 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
3988 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
3989 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 3990 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
3991 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 3992 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
3993 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
3994 } },
3995 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
3996 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
3997 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
3998 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
3999 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4000 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4001 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4002 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4003 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4004 } },
4005 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4006 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4007 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4008 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4009 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4010 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4011 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4012 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4013 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4014 } },
4015 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4016 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4017 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4018 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4019 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4020 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
f9d13080
YS		 4021 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
4022 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
92e6d9a2
LP		 4023 } },
4024 { },
4025};
4026
e9eace32
WS		 4027static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4028{
4029 int bit = -EINVAL;
4030
4031 *pocctrl = 0xe6060380;
4032
4033 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4034 bit = pin & 0x1f;
4035
4036 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4037 bit = (pin & 0x1f) + 12;
4038
4039 return bit;
4040}
4041
56065524
UH		 4042#define PUEN 0xe6060400
4043#define PUD 0xe6060440
4044
4045#define PU0 0x00
4046#define PU1 0x04
4047#define PU2 0x08
4048#define PU3 0x0c
4049#define PU4 0x10
4050#define PU5 0x14
4051#define PU6 0x18
4052
d3b861bc 4053static const struct sh_pfc_bias_info bias_info[] = {
4c2fb44d
NS		 4054 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
4055 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
4056 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
4057 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
4058 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
4059 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
4060 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
4061 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
4062 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
4063 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
4064 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
4065 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
4066 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
4067 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
4068 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
4069 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
4070 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
4071 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
4072 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
4073 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
4074 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
4075 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
4076 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
4077 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
4078 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
4079 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
4080 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
4081 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
4082 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
4083 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
4084 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
4085 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
4086
4087 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
4088 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
4089 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
4090 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
4091 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
4092 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
4093 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
4094 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
4095 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
4096 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
4097 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
4098 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
4099 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
4100 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
4101 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
4102 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
4103 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
4104 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
4105 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
4106 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
4107 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
4108 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
4109 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
4110 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
4111 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
4112 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
4113 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
4114 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
4115 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
4116 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
4117 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
4118 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
4119
4120 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
4121 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
4122 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
4123 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
4124 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
4125 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
4126 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
4127 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
4128 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
4129 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
4130 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
4131 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
4132 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
4133 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
4134 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
4135 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
4136 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
4137 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
4138 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
4139 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
4140 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
4141 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
4142 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
4143 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
4144 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
4145 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
4146 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
4147 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
4148 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
4149 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
4150 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
4151 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
4152
4153 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
4154 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
4155 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
4156 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
4157 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
4158 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
4159 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
4160 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
4161 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
4162 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
4163 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
4164 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
4165 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
4166 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
4167 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
4168 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
4169 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
4170 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
4171 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
4172 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
4173 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
4174 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
4175 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
4176 /* bit 8 n/a */
4177 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
4178 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
4179 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
4180 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
4181 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
4182 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
4183 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
4184 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
4185
4186 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
4187 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
4188 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
4189 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
4190 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
4191 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
4192 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
4193 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
4194 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
4195 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
4196 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
4197 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
4198 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
4199 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
4200 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
4201 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
4202 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
4203 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
4204 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
4205 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
4206 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
4207 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
4208 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
4209 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
4210 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
4211 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
4212 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
4213 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
4214 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
4215 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
4216 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
4217 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
4218
4219 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
4220 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
4221 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
4222 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
4223 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
4224 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
4225 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
4226 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
4227 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
4228 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
4229 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
4230 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
4231 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
4232 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
4233 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
4234 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
4235 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
4236 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
68e63892
KM		 4237 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
4238 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
4c2fb44d
NS		 4239 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
4240 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
4241 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
4242 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
4243 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
4244 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
4245 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
4246 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
4247 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
4248 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
4249 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
4250 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
4251
f9d13080
YS		 4252 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */
4253 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */
4c2fb44d
NS		 4254 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
4255 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
4256 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
4257 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
4258 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
56065524
UH		 4259};
4260
4261static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
4262 unsigned int pin)
4263{
d3b861bc 4264 const struct sh_pfc_bias_info *info;
56065524
UH		 4265 u32 reg;
4266 u32 bit;
4267
d3b861bc
NS		 4268 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
4269 if (!info)
56065524
UH		 4270 return PIN_CONFIG_BIAS_DISABLE;
4271
d3b861bc
NS		 4272 reg = info->reg;
4273 bit = BIT(info->bit);
56065524 4274
42831cf9 4275 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
56065524 4276 return PIN_CONFIG_BIAS_DISABLE;
42831cf9
NS		 4277 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
4278 return PIN_CONFIG_BIAS_PULL_UP;
4279 else
4280 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 4281}
4282
4283static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4284 unsigned int bias)
4285{
d3b861bc 4286 const struct sh_pfc_bias_info *info;
56065524
UH		 4287 u32 enable, updown;
4288 u32 reg;
4289 u32 bit;
4290
d3b861bc
NS		 4291 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
4292 if (!info)
56065524
UH		 4293 return;
4294
d3b861bc
NS		 4295 reg = info->reg;
4296 bit = BIT(info->bit);
56065524
UH		 4297
4298 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
4299 if (bias != PIN_CONFIG_BIAS_DISABLE)
4300 enable |= bit;
4301
4302 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
4303 if (bias == PIN_CONFIG_BIAS_PULL_UP)
4304 updown |= bit;
4305
4306 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
4307 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
4308}
4309
b205914c
GU		 4310static const struct soc_device_attribute r8a7795es1[] = {
4311 { .soc_id = "r8a7795", .revision = "ES1.*" },
4312 { /* sentinel */ }
4313};
4314
4315static int r8a7795_pinmux_init(struct sh_pfc *pfc)
4316{
4317 if (soc_device_match(r8a7795es1))
4318 pfc->info = &r8a7795es1_pinmux_info;
4319
4320 return 0;
4321}
4322
e9eace32 4323static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 4324 .init = r8a7795_pinmux_init,
e9eace32 4325 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 4326 .get_bias = r8a7795_pinmux_get_bias,
4327 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 4328};
4329
0b0ffc96 4330const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 4331 .name = "r8a77951_pfc",
e9eace32 4332 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 4333 .unlock_reg = 0xe6060000, /* PMMR */
4334
4335 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4336
4337 .pins = pinmux_pins,
4338 .nr_pins = ARRAY_SIZE(pinmux_pins),
4339 .groups = pinmux_groups,
4340 .nr_groups = ARRAY_SIZE(pinmux_groups),
4341 .functions = pinmux_functions,
4342 .nr_functions = ARRAY_SIZE(pinmux_functions),
4343
4344 .cfg_regs = pinmux_config_regs,
92e6d9a2 4345 .drive_regs = pinmux_drive_regs,
0b0ffc96 4346
b8b47d67
GU		 4347 .pinmux_data = pinmux_data,
4348 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 4349};
Linux 6.x block layer and io_uring tree(s)