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pinctrl: exynos: add exynos5260 SoC specific data
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / pfc-r8a7790.c
CommitLineData
58c229e1
KM		 1/*
2 * R8A7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2012 Renesas Solutions Corp.
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
1627769b 23
58c229e1 24#include <linux/kernel.h>
1627769b
LP		 25#include <linux/platform_data/gpio-rcar.h>
26
58c229e1
KM		 27#include "core.h"
28#include "sh_pfc.h"
29
ed3e2604
LP		 30#define CPU_ALL_PORT(fn, sfx) \
31 PORT_GP_32(0, fn, sfx), \
32 PORT_GP_32(1, fn, sfx), \
33 PORT_GP_32(2, fn, sfx), \
34 PORT_GP_32(3, fn, sfx), \
35 PORT_GP_32(4, fn, sfx), \
36 PORT_GP_32(5, fn, sfx)
37
58c229e1
KM		 38enum {
39 PINMUX_RESERVED = 0,
40
41 PINMUX_DATA_BEGIN,
42 GP_ALL(DATA),
43 PINMUX_DATA_END,
44
58c229e1
KM		 45 PINMUX_FUNCTION_BEGIN,
46 GP_ALL(FN),
47
48 /* GPSR0 */
49 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
50 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
51 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
52 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
53 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
54 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
55 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
56 FN_IP3_14_12, FN_IP3_17_15,
57
58 /* GPSR1 */
59 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
60 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
61 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
62 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
63 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
64 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
65 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
66
67 /* GPSR2 */
68 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
69 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
70 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
71 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
72 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
73 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
74 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
75
76 /* GPSR3 */
77 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
78 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
79 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
80 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
81 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
82 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
83 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
84
85 /* GPSR4 */
86 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
87 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
88 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
89 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
90 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
91 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
92 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
93 FN_IP14_15_12, FN_IP14_18_16,
94
95 /* GPSR5 */
96 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
97 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
98 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
99 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
100 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
101 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
102 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
103
104 /* IPSR0 */
105 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
106 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
107 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
108 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
109 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
110 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
111 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
112 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
113 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
c4721249
SK		 114 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
115 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
05bcb07b 116 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
9f2edd41 117 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
58c229e1
KM		 118 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
119
120 /* IPSR1 */
9f2edd41 121 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
58c229e1 122 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
9f2edd41 123 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
58c229e1 124 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
9f2edd41 125 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
58c229e1
KM		 126 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
127 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
128 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
129 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
130 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
131 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
132 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
133 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
134 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
135 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
136
137 /* IPSR2 */
138 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
139 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
140 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
141 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
142 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
143 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
1ddb66cd 144 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
58c229e1 145 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
1ddb66cd 146 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
58c229e1
KM		 147 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
148 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
149
150 /* IPSR3 */
151 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
152 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
153 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
154 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
155 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
156 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
157 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
158 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
159 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
160 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
161 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
162 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
163 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
164
165 /* IPSR4 */
166 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
167 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
168 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
169 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
170 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
171 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
172 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
173 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
174 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
175 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
176 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
177 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
178 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
179 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
180 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
181
182 /* IPSR5 */
183 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
184 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
c4721249
SK		 185 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
186 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
58c229e1 187 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
c4721249
SK		 188 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
189 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
58c229e1
KM		 190 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
191 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
192 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
193 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
194 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
195 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
196 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
197 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
198 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
199 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
200 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
201 FN_SSI_WS78_B,
202
203 /* IPSR6 */
204 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
205 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
206 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
207 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
208 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
209 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
210 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
211 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
9f2edd41 212 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
c4721249 213 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
9f2edd41 214 FN_I2C2_SCL_E, FN_ETH_RX_ER,
58c229e1 215 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
9f2edd41 216 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
58c229e1
KM		 217 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
218 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
9f2edd41 219 FN_HRX0_E, FN_STP_ISSYNC_0_B,
58c229e1 220 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
9f2edd41 221 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
58c229e1 222 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
9f2edd41 223 FN_ETH_REF_CLK, FN_HCTS0_N_E,
58c229e1
KM		 224 FN_STP_IVCXO27_1_B, FN_HRX0_F,
225
226 /* IPSR7 */
9f2edd41 227 FN_ETH_MDIO, FN_HRTS0_N_E,
58c229e1 228 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
14da999b 229 FN_HTX0_F, FN_BPFCLK_G,
9f2edd41
SK		 230 FN_ETH_TX_EN, FN_SIM0_CLK_C,
231 FN_HRTS0_N_F, FN_ETH_MAGIC,
232 FN_SIM0_RST_C, FN_ETH_TXD0,
58c229e1 233 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
9f2edd41 234 FN_ETH_MDC, FN_STP_ISD_1_B,
58c229e1
KM		 235 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
236 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
237 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
238 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
239 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
f0681209 240 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
58c229e1 241 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
9f2edd41 242 FN_ATACS00_N, FN_AVB_RXD1,
58c229e1 243 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
58c229e1
KM		 244
245 /* IPSR8 */
246 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
9f2edd41 247 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
58c229e1
KM		 248 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
249 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
250 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
251 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
9f2edd41
SK		 252 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
253 FN_VI1_CLK, FN_AVB_RX_DV,
254 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
255 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
256 FN_SCIFA1_RXD_D, FN_AVB_MDC,
58c229e1 257 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
9f2edd41 258 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
58c229e1 259 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
9f2edd41 260 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
58c229e1
KM		 261 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
262 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
263 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
264
265 /* IPSR9 */
266 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
267 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
268 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
269 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
270 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
c4721249
SK		 271 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
272 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
58c229e1 273 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
c4721249
SK		 274 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
275 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
9f2edd41
SK		 276 FN_AVB_TX_EN, FN_SD1_CMD,
277 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
278 FN_SD1_DAT0, FN_AVB_TX_CLK,
58c229e1 279 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
9f2edd41
SK		 280 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
281 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
282 FN_SD1_DAT3, FN_AVB_RXD0,
58c229e1
KM		 283 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
284 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
c4721249 285 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
58c229e1
KM		 286 FN_VI3_CLK_B,
287
288 /* IPSR10 */
289 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
c4721249 290 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
58c229e1
KM		 291 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
292 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
293 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
294 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
295 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
296 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
297 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
298 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
14da999b 299 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
58c229e1
KM		 300 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
301 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
14da999b 302 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
58c229e1
KM		 303 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
304 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
305 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
306 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
307 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
308 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
309 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
310 FN_GLO_I0_B, FN_VI3_DATA6_B,
311
312 /* IPSR11 */
313 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
314 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
315 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
316 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
317 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
318 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
319 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
320 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
321 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
322 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
14da999b
SK		 323 FN_FMIN_E, FN_FMIN_F,
324 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
c4721249 325 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
7d2b2854 326 FN_I2C2_SDA_B, FN_MLB_DAT,
58c229e1 327 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
14da999b 328 FN_SSI_SCK0129, FN_CAN_CLK_B,
58c229e1
KM		 329 FN_MOUT0,
330
331 /* IPSR12 */
332 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
333 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
334 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
335 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
336 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
337 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
338 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
339 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
340 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
341 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
342 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
343 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
344 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
345 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
346 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
347 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
348 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
349 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
350 FN_CAN_DEBUGOUT4,
351
352 /* IPSR13 */
353 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
354 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
14da999b 355 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
58c229e1 356 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
14da999b 357 FN_BPFCLK_F, FN_SSI_WS6,
58c229e1
KM		 358 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
359 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
14da999b 360 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
58c229e1
KM		 361 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
362 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
363 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
364 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
365 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
366 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
367 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
14da999b
SK		 368 FN_BPFCLK_E, FN_SSI_SDATA7_B,
369 FN_FMIN_G, FN_SSI_SDATA8,
58c229e1
KM		 370 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
371 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
372 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
373 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
374 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
375
376 /* IPSR14 */
377 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
378 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
379 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
c4721249
SK		 380 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
381 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
58c229e1
KM		 382 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
383 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
384 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
c4721249 385 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
bcec7475 386 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
58c229e1
KM		 387 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
388 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
389 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
390 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
391 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
392 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
bcec7475 393 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
58c229e1
KM		 394 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
395 FN_HRTS0_N_C,
396
397 /* IPSR15 */
1ddb66cd 398 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
58c229e1 399 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
1ddb66cd
SK		 400 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
401 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
c4721249 402 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
58c229e1
KM		 403 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
404 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
405 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
406 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
407 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
408 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
409 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
5de880dd 410 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
58c229e1
KM		 411 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
412 FN_DU2_DG6, FN_LCDOUT14,
413
414 /* IPSR16 */
415 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
416 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
417 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5de880dd 418 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
58c229e1
KM		 419 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
420 FN_TCLK1_B,
421
422 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
423 FN_SEL_SCIF1_4,
424 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
425 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
426 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
427 FN_SEL_SCIFB1_4,
428 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
429 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
430 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
431 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
432 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
433 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
434 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
435 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
436 FN_SEL_VI3_0, FN_SEL_VI3_1,
437 FN_SEL_VI2_0, FN_SEL_VI2_1,
438 FN_SEL_VI1_0, FN_SEL_VI1_1,
439 FN_SEL_VI0_0, FN_SEL_VI0_1,
440 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
441 FN_SEL_LBS_0, FN_SEL_LBS_1,
442 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
443 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
444 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
445
446 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
447 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
448 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
449 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
450 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
451 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
452 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
1ddb66cd 453 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
58c229e1
KM		 454 FN_SEL_ADI_0, FN_SEL_ADI_1,
455 FN_SEL_SSP_0, FN_SEL_SSP_1,
456 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
457 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
458 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
459 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
460 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
58c229e1
KM		 461 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
462 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
463
464 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
465 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
466 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
467 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
468 FN_SEL_IIC2_4,
469 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
470 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
471 FN_SEL_I2C2_4,
472 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
473 PINMUX_FUNCTION_END,
474
475 PINMUX_MARK_BEGIN,
476
477 VI1_DATA7_VI1_B7_MARK,
478
479 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
480 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
481 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
482
483 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
484 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
485 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
486 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
487 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
488 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
489 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
490 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
491 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
c4721249
SK		 492 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
493 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
05bcb07b 494 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
9f2edd41 495 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
58c229e1
KM		 496 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
497
9f2edd41 498 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
58c229e1 499 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
9f2edd41 500 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
58c229e1 501 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
9f2edd41 502 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
58c229e1
KM		 503 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
504 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
505 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
506 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
507 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
508 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
509 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
510 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
511 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
512 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
513
514 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
515 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
516 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
517 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
518 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
519 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
1ddb66cd 520 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
58c229e1 521 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
1ddb66cd 522 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
58c229e1
KM		 523 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
524 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
525
526 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
527 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
528 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
529 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
530 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
531 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
532 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
533 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
534 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
535 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
536 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
537 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
538 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
539
540 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
541 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
542 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
543 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
544 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
545 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
546 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
547 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
548 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
549 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
550 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
551 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
552 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
553 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
554 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
555
556 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
557 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
558 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
c4721249
SK		 559 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
560 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
58c229e1 561 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
c4721249
SK		 562 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
563 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
58c229e1
KM		 564 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
565 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
566 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
567 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
568 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
569 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
570 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
571 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
572 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
573 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
574 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
575 SSI_WS78_B_MARK,
576
577 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
578 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
579 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
580 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
581 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
582 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
583 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
584 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
9f2edd41 585 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
c4721249 586 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
9f2edd41 587 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
58c229e1 588 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
9f2edd41 589 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
58c229e1
KM		 590 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
591 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
9f2edd41 592 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
58c229e1 593 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
9f2edd41 594 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
58c229e1 595 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
9f2edd41 596 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
58c229e1
KM		 597 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
598
9f2edd41 599 ETH_MDIO_MARK, HRTS0_N_E_MARK,
58c229e1 600 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
14da999b 601 HTX0_F_MARK, BPFCLK_G_MARK,
9f2edd41
SK		 602 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
603 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
604 SIM0_RST_C_MARK, ETH_TXD0_MARK,
58c229e1 605 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
9f2edd41 606 ETH_MDC_MARK, STP_ISD_1_B_MARK,
58c229e1
KM		 607 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
608 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
609 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
610 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
611 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
f0681209 612 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
58c229e1 613 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
9f2edd41 614 ATACS00_N_MARK, AVB_RXD1_MARK,
58c229e1 615 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
58c229e1
KM		 616
617 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
9f2edd41 618 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
58c229e1
KM		 619 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
620 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
621 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
622 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
9f2edd41
SK		 623 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
624 VI1_CLK_MARK, AVB_RX_DV_MARK,
625 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
626 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
627 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
58c229e1 628 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
9f2edd41 629 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
58c229e1 630 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
9f2edd41 631 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
58c229e1
KM		 632 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
633 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
634 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
635
636 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
637 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
638 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
639 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
640 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
c4721249
SK		 641 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
642 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
58c229e1 643 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
c4721249
SK		 644 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
645 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
9f2edd41
SK		 646 AVB_TX_EN_MARK, SD1_CMD_MARK,
647 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
648 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
58c229e1 649 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
9f2edd41
SK		 650 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
651 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
652 SD1_DAT3_MARK, AVB_RXD0_MARK,
58c229e1
KM		 653 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
654 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
c4721249 655 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
58c229e1
KM		 656 VI3_CLK_B_MARK,
657
658 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
c4721249 659 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
58c229e1
KM		 660 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
661 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
662 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
663 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
664 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
665 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
666 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
667 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
14da999b 668 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
58c229e1
KM		 669 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
670 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
14da999b 671 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
58c229e1
KM		 672 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
673 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
674 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
675 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
676 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
677 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
678 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
679 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
680
681 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
682 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
683 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
684 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
685 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
686 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
687 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
688 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
689 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
690 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
14da999b
SK		 691 FMIN_E_MARK, FMIN_F_MARK,
692 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
c4721249 693 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
7d2b2854 694 I2C2_SDA_B_MARK, MLB_DAT_MARK,
58c229e1 695 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
14da999b 696 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
58c229e1
KM		 697 MOUT0_MARK,
698
699 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
700 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
701 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
702 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
703 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
704 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
705 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
706 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
707 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
708 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
709 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
710 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
711 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
712 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
713 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
714 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
715 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
716 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
717 CAN_DEBUGOUT4_MARK,
718
719 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
720 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
14da999b 721 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
58c229e1 722 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
14da999b 723 BPFCLK_F_MARK, SSI_WS6_MARK,
58c229e1
KM		 724 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
725 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
14da999b 726 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
58c229e1
KM		 727 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
728 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
729 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
730 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
731 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
732 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
733 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
14da999b
SK		 734 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
735 FMIN_G_MARK, SSI_SDATA8_MARK,
58c229e1
KM		 736 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
737 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
738 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
739 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
740 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
741
742 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
743 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
744 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
c4721249
SK		 745 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
746 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
58c229e1
KM		 747 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
748 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
749 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
c4721249 750 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
bcec7475 751 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
58c229e1
KM		 752 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
753 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
754 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
755 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
756 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
757 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
bcec7475 758 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
58c229e1
KM		 759 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
760 HRTS0_N_C_MARK,
761
1ddb66cd 762 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
58c229e1 763 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
1ddb66cd
SK		 764 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
765 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
c4721249 766 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
58c229e1
KM		 767 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
768 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
769 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
770 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
771 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
772 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
773 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
5de880dd 774 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
58c229e1
KM		 775 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
776 DU2_DG6_MARK, LCDOUT14_MARK,
777
778 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
779 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
780 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
5de880dd 781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
58c229e1
KM		 782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
783 TCLK1_B_MARK,
f6aaaac9
GL		 784
785 I2C3_SCL_MARK, I2C3_SDA_MARK,
58c229e1
KM		 786 PINMUX_MARK_END,
787};
788
533743dc 789static const u16 pinmux_data[] = {
58c229e1
KM		 790 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
791
792 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
793 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
794 PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
795 PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
796 PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
797 PINMUX_DATA(AVS1_MARK, FN_AVS1),
798 PINMUX_DATA(AVS2_MARK, FN_AVS2),
799 PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
800 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
801
802 PINMUX_IPSR_DATA(IP0_2_0, D0),
803 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
804 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
805 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
806 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
807 PINMUX_IPSR_DATA(IP0_5_3, D1),
808 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
809 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
810 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
811 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
812 PINMUX_IPSR_DATA(IP0_8_6, D2),
813 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
814 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
815 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
816 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
817 PINMUX_IPSR_DATA(IP0_11_9, D3),
818 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
819 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
820 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
821 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
822 PINMUX_IPSR_DATA(IP0_15_12, D4),
823 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
824 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
825 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
826 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
827 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
828 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
829 PINMUX_IPSR_DATA(IP0_19_16, D5),
830 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
831 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
832 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
833 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
834 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
835 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
836 PINMUX_IPSR_DATA(IP0_22_20, D6),
c4721249 837 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
58c229e1
KM		 838 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
839 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
840 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
c4721249 841 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
58c229e1
KM		 842 PINMUX_IPSR_DATA(IP0_26_23, D7),
843 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
c4721249 844 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
58c229e1
KM		 845 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
846 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
847 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
c4721249 848 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
05bcb07b 849 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
58c229e1
KM		 850 PINMUX_IPSR_DATA(IP0_30_27, D8),
851 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
852 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
58c229e1
KM		 853 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
854 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
855 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
856
857 PINMUX_IPSR_DATA(IP1_3_0, D9),
858 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
859 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
58c229e1
KM		 860 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
861 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
862 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
863 PINMUX_IPSR_DATA(IP1_7_4, D10),
864 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
865 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
58c229e1
KM		 866 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
867 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
868 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
869 PINMUX_IPSR_DATA(IP1_11_8, D11),
870 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
871 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
58c229e1
KM		 872 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
873 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
874 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
875 PINMUX_IPSR_DATA(IP1_14_12, D12),
876 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
877 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
878 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
879 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
880 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
881 PINMUX_IPSR_DATA(IP1_17_15, D13),
0a664e3d 882 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
58c229e1
KM		 883 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
884 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
885 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
886 PINMUX_IPSR_DATA(IP1_21_18, D14),
887 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
888 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
889 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
890 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
891 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
892 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
893 PINMUX_IPSR_DATA(IP1_25_22, D15),
894 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
895 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
896 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
897 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
898 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
899 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
900 PINMUX_IPSR_DATA(IP1_27_26, A0),
901 PINMUX_IPSR_DATA(IP1_27_26, PWM3),
902 PINMUX_IPSR_DATA(IP1_29_28, A1),
903 PINMUX_IPSR_DATA(IP1_29_28, PWM4),
904
905 PINMUX_IPSR_DATA(IP2_2_0, A2),
906 PINMUX_IPSR_DATA(IP2_2_0, PWM5),
907 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
908 PINMUX_IPSR_DATA(IP2_5_3, A3),
909 PINMUX_IPSR_DATA(IP2_5_3, PWM6),
910 PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
911 PINMUX_IPSR_DATA(IP2_8_6, A4),
912 PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
913 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
914 PINMUX_IPSR_DATA(IP2_11_9, A5),
915 PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
916 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
917 PINMUX_IPSR_DATA(IP2_14_12, A6),
918 PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
919 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
920 PINMUX_IPSR_DATA(IP2_17_15, A7),
921 PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
922 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
923 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
924 PINMUX_IPSR_DATA(IP2_21_18, A8),
925 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
926 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
927 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
928 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
929 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
1ddb66cd 930 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
58c229e1
KM		 931 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
932 PINMUX_IPSR_DATA(IP2_25_22, A9),
933 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
934 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
935 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
936 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
937 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
1ddb66cd 938 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
58c229e1
KM		 939 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
940 PINMUX_IPSR_DATA(IP2_28_26, A10),
941 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
942 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
943 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
944 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
945 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
946
947 PINMUX_IPSR_DATA(IP3_3_0, A11),
948 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
949 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
950 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
951 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
952 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
0a664e3d 953 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
58c229e1
KM		 954 PINMUX_IPSR_DATA(IP3_7_4, A12),
955 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
956 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
957 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
958 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
959 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
0a664e3d 960 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
58c229e1
KM		 961 PINMUX_IPSR_DATA(IP3_11_8, A13),
962 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
963 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
964 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
965 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
966 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
967 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
0a664e3d 968 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
58c229e1
KM		 969 PINMUX_IPSR_DATA(IP3_14_12, A14),
970 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
971 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
972 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
973 PINMUX_IPSR_DATA(IP3_17_15, A15),
974 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
975 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
976 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
977 PINMUX_IPSR_DATA(IP3_19_18, A16),
978 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
979 PINMUX_IPSR_DATA(IP3_22_20, A17),
980 PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
981 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
982 PINMUX_IPSR_DATA(IP3_25_23, A18),
983 PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
984 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
985 PINMUX_IPSR_DATA(IP3_28_26, A19),
986 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
987 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
988 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
989 PINMUX_IPSR_DATA(IP3_31_29, A20),
990 PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
991 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
992 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
993 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
994
995 PINMUX_IPSR_DATA(IP4_2_0, A21),
996 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
997 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
998 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
999 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1000 PINMUX_IPSR_DATA(IP4_5_3, A22),
1001 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1002 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1003 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1004 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1005 PINMUX_IPSR_DATA(IP4_8_6, A23),
1006 PINMUX_IPSR_DATA(IP4_8_6, IO2),
1007 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1008 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1009 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1010 PINMUX_IPSR_DATA(IP4_11_9, A24),
1011 PINMUX_IPSR_DATA(IP4_11_9, IO3),
1012 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1013 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1014 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1015 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1016 PINMUX_IPSR_DATA(IP4_14_12, A25),
1017 PINMUX_IPSR_DATA(IP4_14_12, SSL),
1018 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1019 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1022 PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1023 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1024 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1025 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1026 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1027 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1028 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1029 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1030 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1031 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1032 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1033 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1034 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1035 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1036 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1037 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1038 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1039 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1040 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1041 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1042 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1043 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1044 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1045 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1046 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1047 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1048 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1049 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1050 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1051 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1052 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1053
1054 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1055 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1056 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1057 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1058 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1059 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
0a664e3d 1060 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
58c229e1
KM		 1061 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1062 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1063 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
c4721249 1064 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
58c229e1
KM		 1065 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1066 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
c4721249 1067 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
58c229e1
KM		 1068 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1070 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1071 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1073 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1074 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
c4721249 1075 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
58c229e1 1076 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
c4721249 1077 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
58c229e1
KM		 1078 PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1079 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1080 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1081 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1082 PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1083 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1084 PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1085 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1086 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1087 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1088 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1089 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1090 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1091 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1092 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1093 PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1094 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1095 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1096 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1097 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1098 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1099 PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1100 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1101 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1102 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1103 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1104 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1105 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1106 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
0a664e3d 1107 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
58c229e1
KM		 1108 PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1109 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1110 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1111 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1112 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1113 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1114 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1115 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1116 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1117 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1118 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1119 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1120
1121 PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1122 PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1123 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1124 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1125 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1126 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1127 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1128 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1129 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1130 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1131 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1132 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1133 PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1134 PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1135 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1136 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1137 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1138 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1139 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1141 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1142 PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1143 PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1144 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1145 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1146 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1147 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1148 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
58c229e1
KM		 1149 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1150 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1151 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
c4721249
SK		 1152 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1153 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
58c229e1 1154 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
58c229e1
KM		 1155 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1156 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1157 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
c4721249
SK		 1158 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1159 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
58c229e1 1160 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
58c229e1
KM		 1161 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1162 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1163 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1164 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1165 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1166 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
58c229e1
KM		 1167 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1168 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1169 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1170 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1171 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1172 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1173 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
58c229e1
KM		 1174 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1175 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1176 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1177 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1178 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
58c229e1
KM		 1179 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1180 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1181 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1182
1183 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
58c229e1
KM		 1184 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1185 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1186 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1187 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
0a664e3d
SK		 1188 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1189 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
58c229e1 1190 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
58c229e1
KM		 1191 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1192 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1193 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
58c229e1
KM		 1194 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1195 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
58c229e1
KM		 1196 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1197 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1199 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
58c229e1
KM		 1200 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1201 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1203 PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1204 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1205 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1208 PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1209 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1210 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1213 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1214 PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1215 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1216 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1217 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1218 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
f0681209 1219 PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
58c229e1
KM		 1220 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1221 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1222 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1223 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1224 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
58c229e1
KM		 1225 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1226 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1227 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
58c229e1
KM		 1228
1229 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1230 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1231 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
58c229e1
KM		 1232 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1233 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1234 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1235 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1236 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1237 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1238 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1239 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1240 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1241 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1242 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1243 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1244 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1245 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
58c229e1
KM		 1246 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1247 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
58c229e1
KM		 1248 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1249 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
58c229e1
KM		 1250 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1251 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1252 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
58c229e1
KM		 1253 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1254 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1255 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
58c229e1
KM		 1256 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1257 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1258 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
58c229e1
KM		 1259 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1260 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1261 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1262 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1263 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1264 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
58c229e1 1265 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
0a664e3d 1266 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
58c229e1
KM		 1267 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1268 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1269 PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1270 PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1271 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1272 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1273 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1274
1275 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1276 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1277 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1278 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1279 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1280 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1281 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1282 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1283 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1284 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1285 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1286 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1287 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1288 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1290 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1291 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1292 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
c4721249
SK		 1293 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1294 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
58c229e1
KM		 1295 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1296 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1297 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1299 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
c4721249
SK		 1302 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1303 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
58c229e1
KM		 1304 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1305 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1306 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
58c229e1
KM		 1307 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1308 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
58c229e1
KM		 1309 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1310 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1311 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
58c229e1
KM		 1312 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1313 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1314 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
58c229e1
KM		 1315 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1316 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1317 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
58c229e1
KM		 1318 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1319 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1320 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
58c229e1
KM		 1321 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1322 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1323 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1324 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1325 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1326 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1327 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
c4721249
SK		 1328 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1329 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
58c229e1
KM		 1330 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1331 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1332
1333 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1334 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1335 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1336 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1337 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1338 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
c4721249
SK		 1339 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1340 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
58c229e1
KM		 1341 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1342 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1343 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1344 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1345 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1346 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1347 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1349 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1350 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1351 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1352 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1355 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1357 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1358 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1359 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1360 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1361 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1363 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1364 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1365 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1367 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1368 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1369 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
58c229e1
KM		 1370 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1371 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1372 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1373 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1376 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1377 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1378 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
58c229e1
KM		 1379 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1381 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1382 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1383 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1384 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1385 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1386 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1387 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1388 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1389 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1390 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1391 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1392 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1393 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1394 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1395 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1396 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1397 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1398 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1399 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1400 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1401 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1402
1403 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1404 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1405 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1406 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1407 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1408 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1409 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1410 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1411 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1412 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1413 PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1414 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1415 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1416 PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1417 PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1418 PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1419 PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1420 PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1421 PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1422 PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1423 PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1424 PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1425 PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1426 PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1427 PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1428 PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1429 PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1430 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1431 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1432 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1433 PINMUX_IPSR_DATA(IP11_17_15, VSP),
1434 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1435 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1436 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1437 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1438 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1439 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1440 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
58c229e1 1441 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
58c229e1 1442 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
58c229e1 1443 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
c4721249
SK		 1444 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1445 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
58c229e1
KM		 1446 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1447 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1448 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
c4721249
SK		 1449 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1450 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
58c229e1 1451 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
58c229e1
KM		 1452 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1453 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1454 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
58c229e1
KM		 1455 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1456 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1457 PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1458
1459 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1460 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1461 PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1462 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1463 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1464 PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1465 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1466 PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1467 PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1468 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1469 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
0a664e3d 1470 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
58c229e1
KM		 1471 PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1472 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1473 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1474 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1475 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1476 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1477 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1479 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1480 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1481 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1482 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1483 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1484 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1485 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1486 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1487 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1488 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1489 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1490 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1491 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1492 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1493 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1494 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1495 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1496 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1497 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1498 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1499 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1500 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1501 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1502 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1503 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1504 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1505 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1506 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1507 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1508 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1509 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1510 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1511 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1512 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1513 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1514 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1515
1516 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1517 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1518 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1519 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1520 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1521 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1522 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1523 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1524 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
58c229e1
KM		 1525 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1526 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1527 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1528 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
58c229e1
KM		 1529 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1530 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1531 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1532 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1533 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1534 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1535 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1536 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
58c229e1
KM		 1537 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1538 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1539 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1540 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1541 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1542 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1543 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1544 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1545 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1546 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1547 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1548 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1549 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1550 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1551 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1552 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1553 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1554 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1555 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1556 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1557 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1558 PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1559 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1560 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1561 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
58c229e1
KM		 1562 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1563 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
58c229e1
KM		 1564 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1565 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1566 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1567 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1568 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1569 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1570 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1571 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1572 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1573 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1574 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1575 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1576 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1577 PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1578 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1579
1580 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1581 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1582 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1583 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1584 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1585 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1586 PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1587 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1588 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1589 PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1590 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1591 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1592 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
c4721249
SK		 1593 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1594 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
58c229e1
KM		 1595 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1596 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1597 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1598 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1599 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1600 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1601 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1602 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1603 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1604 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1605 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1606 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
0a664e3d 1607 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
58c229e1
KM		 1608 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1609 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
0a664e3d
SK		 1610 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1611 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
c4721249
SK		 1612 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1613 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
58c229e1
KM		 1614 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1615 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
bcec7475 1616 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
58c229e1
KM		 1617 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1618 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1619 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1620 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1621 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1622 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1623 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1624 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1625 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1626 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1627 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1628 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1629 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1630 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1631 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1632 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1633 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1634 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1635 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1636 PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1637 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1638 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
bcec7475 1639 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
58c229e1
KM		 1640 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1641 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1642 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1643 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1644
1645 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1646 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1ddb66cd 1647 PINMUX_IPSR_DATA(IP15_2_0, SCK2),
58c229e1
KM		 1648 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1649 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1650 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
0a664e3d 1651 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
58c229e1
KM		 1652 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1653 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1ddb66cd 1654 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
58c229e1
KM		 1655 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1656 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
c4721249
SK		 1657 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1658 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
58c229e1
KM		 1659 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1660 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1ddb66cd 1661 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
58c229e1
KM		 1662 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1663 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
c4721249
SK		 1664 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1665 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
58c229e1
KM		 1666 PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1667 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1668 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1669 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
0a664e3d 1670 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
58c229e1
KM		 1671 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1672 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1673 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1674 PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1675 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1676 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1677 PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1678 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1679 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1680 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1681 PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1682 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1683 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1684 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1685 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1686 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1687 PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1688 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1689 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1690 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1691 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1692 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1693 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1694 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1695 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
5de880dd 1696 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
58c229e1
KM		 1697 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1698 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1699 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1700 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1701 PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1702 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1703 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1704 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1705
1706 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1707 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1708 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1709 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1710 PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1711 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1712 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1713 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1714 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1715 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1716 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1717 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1718 PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
5de880dd 1719 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
58c229e1
KM		 1720 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1721 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1722 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1723 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
f6aaaac9
GL		 1724
1725 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1726 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
58c229e1
KM		 1727};
1728
f6aaaac9
GL		 1729/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1730#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1731#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1732#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1733
44a45b55 1734static const struct sh_pfc_pin pinmux_pins[] = {
58c229e1 1735 PINMUX_GPIO_GP_ALL(),
f6aaaac9
GL		 1736
1737 /* Pins not associated with a GPIO port */
1738 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
58c229e1
KM		 1740};
1741
fcec5b22
KM		 1742/* - AUDIO CLOCK ------------------------------------------------------------ */
1743static const unsigned int audio_clk_a_pins[] = {
1744 /* CLK A */
1745 RCAR_GP_PIN(4, 25),
1746};
1747static const unsigned int audio_clk_a_mux[] = {
1748 AUDIO_CLKA_MARK,
1749};
1750static const unsigned int audio_clk_b_pins[] = {
1751 /* CLK B */
1752 RCAR_GP_PIN(4, 26),
1753};
1754static const unsigned int audio_clk_b_mux[] = {
1755 AUDIO_CLKB_MARK,
1756};
1757static const unsigned int audio_clk_c_pins[] = {
1758 /* CLK C */
1759 RCAR_GP_PIN(5, 27),
1760};
1761static const unsigned int audio_clk_c_mux[] = {
1762 AUDIO_CLKC_MARK,
1763};
1764static const unsigned int audio_clkout_pins[] = {
1765 /* CLK OUT */
1766 RCAR_GP_PIN(5, 16),
1767};
1768static const unsigned int audio_clkout_mux[] = {
1769 AUDIO_CLKOUT_MARK,
1770};
1771static const unsigned int audio_clkout_b_pins[] = {
1772 /* CLK OUT B */
1773 RCAR_GP_PIN(0, 23),
1774};
1775static const unsigned int audio_clkout_b_mux[] = {
1776 AUDIO_CLKOUT_B_MARK,
1777};
1778static const unsigned int audio_clkout_c_pins[] = {
1779 /* CLK OUT C */
1780 RCAR_GP_PIN(5, 27),
1781};
1782static const unsigned int audio_clkout_c_mux[] = {
1783 AUDIO_CLKOUT_C_MARK,
1784};
1785static const unsigned int audio_clkout_d_pins[] = {
1786 /* CLK OUT D */
1787 RCAR_GP_PIN(5, 20),
1788};
1789static const unsigned int audio_clkout_d_mux[] = {
1790 AUDIO_CLKOUT_D_MARK,
1791};
62783b71
LP		 1792/* - DU RGB ----------------------------------------------------------------- */
1793static const unsigned int du_rgb666_pins[] = {
1794 /* R[7:2], G[7:2], B[7:2] */
1795 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1796 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1797 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1798 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1799 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1800 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1801};
1802static const unsigned int du_rgb666_mux[] = {
1803 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1804 DU2_DR3_MARK, DU2_DR2_MARK,
1805 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1806 DU2_DG3_MARK, DU2_DG2_MARK,
1807 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1808 DU2_DB3_MARK, DU2_DB2_MARK,
1809};
1810static const unsigned int du_rgb888_pins[] = {
1811 /* R[7:0], G[7:0], B[7:0] */
1812 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1813 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1814 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1815 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1816 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1817 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1818 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1819 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1820};
1821static const unsigned int du_rgb888_mux[] = {
1822 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1823 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1824 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1825 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1826 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1827 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1828};
1829static const unsigned int du_clk_out_0_pins[] = {
1830 /* CLKOUT */
1831 RCAR_GP_PIN(5, 2),
1832};
1833static const unsigned int du_clk_out_0_mux[] = {
1834 DU0_DOTCLKOUT_MARK
1835};
1836static const unsigned int du_clk_out_1_pins[] = {
1837 /* CLKOUT */
1838 RCAR_GP_PIN(5, 3),
1839};
1840static const unsigned int du_clk_out_1_mux[] = {
1841 DU1_DOTCLKOUT_MARK
1842};
1843static const unsigned int du_sync_0_pins[] = {
1844 /* VSYNC, HSYNC, DISP */
1845 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1846};
1847static const unsigned int du_sync_0_mux[] = {
1848 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1849 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1850};
1851static const unsigned int du_sync_1_pins[] = {
1852 /* VSYNC, HSYNC, DISP */
1853 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1854};
1855static const unsigned int du_sync_1_mux[] = {
1856 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1857 DU2_DISP_MARK
1858};
1859static const unsigned int du_cde_pins[] = {
1860 /* CDE */
1861 RCAR_GP_PIN(5, 17),
1862};
1863static const unsigned int du_cde_mux[] = {
1864 DU2_CDE_MARK,
1865};
1866/* - DU0 -------------------------------------------------------------------- */
1867static const unsigned int du0_clk_in_pins[] = {
1868 /* CLKIN */
1869 RCAR_GP_PIN(5, 26),
1870};
1871static const unsigned int du0_clk_in_mux[] = {
1872 DU_DOTCLKIN0_MARK
1873};
1874/* - DU1 -------------------------------------------------------------------- */
1875static const unsigned int du1_clk_in_pins[] = {
1876 /* CLKIN */
1877 RCAR_GP_PIN(5, 27),
1878};
1879static const unsigned int du1_clk_in_mux[] = {
1880 DU_DOTCLKIN1_MARK,
1881};
1882/* - DU2 -------------------------------------------------------------------- */
1883static const unsigned int du2_clk_in_pins[] = {
1884 /* CLKIN */
1885 RCAR_GP_PIN(5, 28),
1886};
1887static const unsigned int du2_clk_in_mux[] = {
1888 DU_DOTCLKIN2_MARK,
1889};
1627769b
LP		 1890/* - ETH -------------------------------------------------------------------- */
1891static const unsigned int eth_link_pins[] = {
1892 /* LINK */
1893 RCAR_GP_PIN(2, 22),
1894};
1895static const unsigned int eth_link_mux[] = {
1896 ETH_LINK_MARK,
1897};
1898static const unsigned int eth_magic_pins[] = {
1899 /* MAGIC */
1900 RCAR_GP_PIN(2, 27),
1901};
1902static const unsigned int eth_magic_mux[] = {
1903 ETH_MAGIC_MARK,
1904};
1905static const unsigned int eth_mdio_pins[] = {
1906 /* MDC, MDIO */
1907 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1908};
1909static const unsigned int eth_mdio_mux[] = {
1910 ETH_MDC_MARK, ETH_MDIO_MARK,
1911};
1912static const unsigned int eth_rmii_pins[] = {
1913 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1914 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1915 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1916 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1917};
1918static const unsigned int eth_rmii_mux[] = {
1919 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1920 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1921};
fbd0ca3d
UH		 1922/* - HSCIF0 ----------------------------------------------------------------- */
1923static const unsigned int hscif0_data_pins[] = {
1924 /* RX, TX */
1925 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1926};
1927static const unsigned int hscif0_data_mux[] = {
1928 HRX0_MARK, HTX0_MARK,
1929};
1930static const unsigned int hscif0_clk_pins[] = {
1931 /* SCK */
1932 RCAR_GP_PIN(5, 7),
1933};
1934static const unsigned int hscif0_clk_mux[] = {
1935 HSCK0_MARK,
1936};
1937static const unsigned int hscif0_ctrl_pins[] = {
1938 /* RTS, CTS */
1939 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1940};
1941static const unsigned int hscif0_ctrl_mux[] = {
1942 HRTS0_N_MARK, HCTS0_N_MARK,
1943};
1944static const unsigned int hscif0_data_b_pins[] = {
1945 /* RX, TX */
1946 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
1947};
1948static const unsigned int hscif0_data_b_mux[] = {
1949 HRX0_B_MARK, HTX0_B_MARK,
1950};
1951static const unsigned int hscif0_ctrl_b_pins[] = {
1952 /* RTS, CTS */
1953 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
1954};
1955static const unsigned int hscif0_ctrl_b_mux[] = {
1956 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1957};
1958static const unsigned int hscif0_data_c_pins[] = {
1959 /* RX, TX */
1960 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
1961};
1962static const unsigned int hscif0_data_c_mux[] = {
1963 HRX0_C_MARK, HTX0_C_MARK,
1964};
1965static const unsigned int hscif0_ctrl_c_pins[] = {
1966 /* RTS, CTS */
1967 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
1968};
1969static const unsigned int hscif0_ctrl_c_mux[] = {
1970 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
1971};
1972static const unsigned int hscif0_data_d_pins[] = {
1973 /* RX, TX */
1974 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1975};
1976static const unsigned int hscif0_data_d_mux[] = {
1977 HRX0_D_MARK, HTX0_D_MARK,
1978};
1979static const unsigned int hscif0_ctrl_d_pins[] = {
1980 /* RTS, CTS */
1981 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
1982};
1983static const unsigned int hscif0_ctrl_d_mux[] = {
1984 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
1985};
1986static const unsigned int hscif0_data_e_pins[] = {
1987 /* RX, TX */
1988 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1989};
1990static const unsigned int hscif0_data_e_mux[] = {
1991 HRX0_E_MARK, HTX0_E_MARK,
1992};
1993static const unsigned int hscif0_ctrl_e_pins[] = {
1994 /* RTS, CTS */
1995 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1996};
1997static const unsigned int hscif0_ctrl_e_mux[] = {
1998 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
1999};
2000static const unsigned int hscif0_data_f_pins[] = {
2001 /* RX, TX */
2002 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2003};
2004static const unsigned int hscif0_data_f_mux[] = {
2005 HRX0_F_MARK, HTX0_F_MARK,
2006};
2007static const unsigned int hscif0_ctrl_f_pins[] = {
2008 /* RTS, CTS */
2009 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2010};
2011static const unsigned int hscif0_ctrl_f_mux[] = {
2012 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2013};
2014/* - HSCIF1 ----------------------------------------------------------------- */
2015static const unsigned int hscif1_data_pins[] = {
2016 /* RX, TX */
2017 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2018};
2019static const unsigned int hscif1_data_mux[] = {
2020 HRX1_MARK, HTX1_MARK,
2021};
2022static const unsigned int hscif1_clk_pins[] = {
2023 /* SCK */
2024 RCAR_GP_PIN(4, 27),
2025};
2026static const unsigned int hscif1_clk_mux[] = {
2027 HSCK1_MARK,
2028};
2029static const unsigned int hscif1_ctrl_pins[] = {
2030 /* RTS, CTS */
2031 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2032};
2033static const unsigned int hscif1_ctrl_mux[] = {
2034 HRTS1_N_MARK, HCTS1_N_MARK,
2035};
2036static const unsigned int hscif1_data_b_pins[] = {
2037 /* RX, TX */
2038 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2039};
2040static const unsigned int hscif1_data_b_mux[] = {
2041 HRX1_B_MARK, HTX1_B_MARK,
2042};
2043static const unsigned int hscif1_clk_b_pins[] = {
2044 /* SCK */
2045 RCAR_GP_PIN(1, 28),
2046};
2047static const unsigned int hscif1_clk_b_mux[] = {
2048 HSCK1_B_MARK,
2049};
2050static const unsigned int hscif1_ctrl_b_pins[] = {
2051 /* RTS, CTS */
2052 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2053};
2054static const unsigned int hscif1_ctrl_b_mux[] = {
2055 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2056};
70702bfc
UH		 2057/* - I2C1 ------------------------------------------------------------------- */
2058static const unsigned int i2c1_pins[] = {
2059 /* SCL, SDA */
2060 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2061};
2062static const unsigned int i2c1_mux[] = {
2063 I2C1_SCL_MARK, I2C1_SDA_MARK,
2064};
2065static const unsigned int i2c1_b_pins[] = {
2066 /* SCL, SDA */
2067 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2068};
2069static const unsigned int i2c1_b_mux[] = {
2070 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2071};
2072static const unsigned int i2c1_c_pins[] = {
2073 /* SCL, SDA */
2074 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2075};
2076static const unsigned int i2c1_c_mux[] = {
2077 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2078};
2079/* - I2C2 ------------------------------------------------------------------- */
2080static const unsigned int i2c2_pins[] = {
2081 /* SCL, SDA */
2082 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2083};
2084static const unsigned int i2c2_mux[] = {
2085 I2C2_SCL_MARK, I2C2_SDA_MARK,
2086};
2087static const unsigned int i2c2_b_pins[] = {
2088 /* SCL, SDA */
2089 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2090};
2091static const unsigned int i2c2_b_mux[] = {
2092 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2093};
2094static const unsigned int i2c2_c_pins[] = {
2095 /* SCL, SDA */
2096 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2097};
2098static const unsigned int i2c2_c_mux[] = {
2099 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2100};
2101static const unsigned int i2c2_d_pins[] = {
2102 /* SCL, SDA */
2103 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2104};
2105static const unsigned int i2c2_d_mux[] = {
2106 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2107};
2108static const unsigned int i2c2_e_pins[] = {
2109 /* SCL, SDA */
2110 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2111};
2112static const unsigned int i2c2_e_mux[] = {
2113 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2114};
f6aaaac9
GL		 2115/* - I2C3 ------------------------------------------------------------------- */
2116static const unsigned int i2c3_pins[] = {
2117 /* SCL, SDA */
2118 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2119};
2120static const unsigned int i2c3_mux[] = {
2121 I2C3_SCL_MARK, I2C3_SDA_MARK,
2122};
457c11d3
LP		 2123/* - INTC ------------------------------------------------------------------- */
2124static const unsigned int intc_irq0_pins[] = {
2125 /* IRQ */
2126 RCAR_GP_PIN(1, 25),
2127};
2128static const unsigned int intc_irq0_mux[] = {
2129 IRQ0_MARK,
2130};
2131static const unsigned int intc_irq1_pins[] = {
2132 /* IRQ */
2133 RCAR_GP_PIN(1, 27),
2134};
2135static const unsigned int intc_irq1_mux[] = {
2136 IRQ1_MARK,
2137};
2138static const unsigned int intc_irq2_pins[] = {
2139 /* IRQ */
2140 RCAR_GP_PIN(1, 29),
2141};
2142static const unsigned int intc_irq2_mux[] = {
2143 IRQ2_MARK,
2144};
2145static const unsigned int intc_irq3_pins[] = {
2146 /* IRQ */
2147 RCAR_GP_PIN(1, 23),
2148};
2149static const unsigned int intc_irq3_mux[] = {
2150 IRQ3_MARK,
2151};
2152/* - MMCIF0 ----------------------------------------------------------------- */
2153static const unsigned int mmc0_data1_pins[] = {
2154 /* D[0] */
2155 RCAR_GP_PIN(3, 18),
2156};
2157static const unsigned int mmc0_data1_mux[] = {
2158 MMC0_D0_MARK,
2159};
2160static const unsigned int mmc0_data4_pins[] = {
2161 /* D[0:3] */
2162 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2163 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2164};
2165static const unsigned int mmc0_data4_mux[] = {
2166 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2167};
2168static const unsigned int mmc0_data8_pins[] = {
2169 /* D[0:7] */
2170 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2171 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2172 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2173 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2174};
2175static const unsigned int mmc0_data8_mux[] = {
2176 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2177 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2178};
2179static const unsigned int mmc0_ctrl_pins[] = {
2180 /* CLK, CMD */
2181 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2182};
2183static const unsigned int mmc0_ctrl_mux[] = {
2184 MMC0_CLK_MARK, MMC0_CMD_MARK,
2185};
2186/* - MMCIF1 ----------------------------------------------------------------- */
2187static const unsigned int mmc1_data1_pins[] = {
2188 /* D[0] */
2189 RCAR_GP_PIN(3, 26),
2190};
2191static const unsigned int mmc1_data1_mux[] = {
2192 MMC1_D0_MARK,
2193};
2194static const unsigned int mmc1_data4_pins[] = {
2195 /* D[0:3] */
2196 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2197 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2198};
2199static const unsigned int mmc1_data4_mux[] = {
2200 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2201};
2202static const unsigned int mmc1_data8_pins[] = {
2203 /* D[0:7] */
2204 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2205 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2206 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2207 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2208};
2209static const unsigned int mmc1_data8_mux[] = {
2210 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2211 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2212};
2213static const unsigned int mmc1_ctrl_pins[] = {
2214 /* CLK, CMD */
2215 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2216};
2217static const unsigned int mmc1_ctrl_mux[] = {
2218 MMC1_CLK_MARK, MMC1_CMD_MARK,
2219};
4f47cc5e
KH		 2220/* - MSIOF0 ----------------------------------------------------------------- */
2221static const unsigned int msiof0_clk_pins[] = {
2222 /* SCK */
2223 RCAR_GP_PIN(5, 12),
2224};
2225static const unsigned int msiof0_clk_mux[] = {
2226 MSIOF0_SCK_MARK,
2227};
2228static const unsigned int msiof0_sync_pins[] = {
2229 /* SYNC */
2230 RCAR_GP_PIN(5, 13),
2231};
2232static const unsigned int msiof0_sync_mux[] = {
2233 MSIOF0_SYNC_MARK,
2234};
2235static const unsigned int msiof0_ss1_pins[] = {
2236 /* SS1 */
2237 RCAR_GP_PIN(5, 14),
2238};
2239static const unsigned int msiof0_ss1_mux[] = {
2240 MSIOF0_SS1_MARK,
2241};
2242static const unsigned int msiof0_ss2_pins[] = {
2243 /* SS2 */
2244 RCAR_GP_PIN(5, 16),
2245};
2246static const unsigned int msiof0_ss2_mux[] = {
2247 MSIOF0_SS2_MARK,
2248};
2249static const unsigned int msiof0_rx_pins[] = {
2250 /* RXD */
2251 RCAR_GP_PIN(5, 17),
2252};
2253static const unsigned int msiof0_rx_mux[] = {
2254 MSIOF0_RXD_MARK,
2255};
2256static const unsigned int msiof0_tx_pins[] = {
2257 /* TXD */
2258 RCAR_GP_PIN(5, 15),
2259};
2260static const unsigned int msiof0_tx_mux[] = {
2261 MSIOF0_TXD_MARK,
2262};
2263/* - MSIOF1 ----------------------------------------------------------------- */
2264static const unsigned int msiof1_clk_pins[] = {
2265 /* SCK */
2266 RCAR_GP_PIN(4, 8),
2267};
2268static const unsigned int msiof1_clk_mux[] = {
2269 MSIOF1_SCK_MARK,
2270};
2271static const unsigned int msiof1_sync_pins[] = {
2272 /* SYNC */
2273 RCAR_GP_PIN(4, 9),
2274};
2275static const unsigned int msiof1_sync_mux[] = {
2276 MSIOF1_SYNC_MARK,
2277};
2278static const unsigned int msiof1_ss1_pins[] = {
2279 /* SS1 */
2280 RCAR_GP_PIN(4, 10),
2281};
2282static const unsigned int msiof1_ss1_mux[] = {
2283 MSIOF1_SS1_MARK,
2284};
2285static const unsigned int msiof1_ss2_pins[] = {
2286 /* SS2 */
2287 RCAR_GP_PIN(4, 11),
2288};
2289static const unsigned int msiof1_ss2_mux[] = {
2290 MSIOF1_SS2_MARK,
2291};
2292static const unsigned int msiof1_rx_pins[] = {
2293 /* RXD */
2294 RCAR_GP_PIN(4, 13),
2295};
2296static const unsigned int msiof1_rx_mux[] = {
2297 MSIOF1_RXD_MARK,
2298};
2299static const unsigned int msiof1_tx_pins[] = {
2300 /* TXD */
2301 RCAR_GP_PIN(4, 12),
2302};
2303static const unsigned int msiof1_tx_mux[] = {
2304 MSIOF1_TXD_MARK,
2305};
2306/* - MSIOF2 ----------------------------------------------------------------- */
2307static const unsigned int msiof2_clk_pins[] = {
2308 /* SCK */
2309 RCAR_GP_PIN(0, 27),
2310};
2311static const unsigned int msiof2_clk_mux[] = {
2312 MSIOF2_SCK_MARK,
2313};
2314static const unsigned int msiof2_sync_pins[] = {
2315 /* SYNC */
2316 RCAR_GP_PIN(0, 26),
2317};
2318static const unsigned int msiof2_sync_mux[] = {
2319 MSIOF2_SYNC_MARK,
2320};
2321static const unsigned int msiof2_ss1_pins[] = {
2322 /* SS1 */
2323 RCAR_GP_PIN(0, 30),
2324};
2325static const unsigned int msiof2_ss1_mux[] = {
2326 MSIOF2_SS1_MARK,
2327};
2328static const unsigned int msiof2_ss2_pins[] = {
2329 /* SS2 */
2330 RCAR_GP_PIN(0, 31),
2331};
2332static const unsigned int msiof2_ss2_mux[] = {
2333 MSIOF2_SS2_MARK,
2334};
2335static const unsigned int msiof2_rx_pins[] = {
2336 /* RXD */
2337 RCAR_GP_PIN(0, 29),
2338};
2339static const unsigned int msiof2_rx_mux[] = {
2340 MSIOF2_RXD_MARK,
2341};
2342static const unsigned int msiof2_tx_pins[] = {
2343 /* TXD */
2344 RCAR_GP_PIN(0, 28),
2345};
2346static const unsigned int msiof2_tx_mux[] = {
2347 MSIOF2_TXD_MARK,
2348};
2349/* - MSIOF3 ----------------------------------------------------------------- */
2350static const unsigned int msiof3_clk_pins[] = {
2351 /* SCK */
2352 RCAR_GP_PIN(5, 4),
2353};
2354static const unsigned int msiof3_clk_mux[] = {
2355 MSIOF3_SCK_MARK,
2356};
2357static const unsigned int msiof3_sync_pins[] = {
2358 /* SYNC */
2359 RCAR_GP_PIN(4, 30),
2360};
2361static const unsigned int msiof3_sync_mux[] = {
2362 MSIOF3_SYNC_MARK,
2363};
2364static const unsigned int msiof3_ss1_pins[] = {
2365 /* SS1 */
2366 RCAR_GP_PIN(4, 31),
2367};
2368static const unsigned int msiof3_ss1_mux[] = {
2369 MSIOF3_SS1_MARK,
2370};
2371static const unsigned int msiof3_ss2_pins[] = {
2372 /* SS2 */
2373 RCAR_GP_PIN(4, 27),
2374};
2375static const unsigned int msiof3_ss2_mux[] = {
2376 MSIOF3_SS2_MARK,
2377};
2378static const unsigned int msiof3_rx_pins[] = {
2379 /* RXD */
2380 RCAR_GP_PIN(5, 2),
2381};
2382static const unsigned int msiof3_rx_mux[] = {
2383 MSIOF3_RXD_MARK,
2384};
2385static const unsigned int msiof3_tx_pins[] = {
2386 /* TXD */
2387 RCAR_GP_PIN(5, 3),
2388};
2389static const unsigned int msiof3_tx_mux[] = {
2390 MSIOF3_TXD_MARK,
2391};
457c11d3
LP		 2392/* - SCIF0 ------------------------------------------------------------------ */
2393static const unsigned int scif0_data_pins[] = {
2394 /* RX, TX */
2395 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2396};
2397static const unsigned int scif0_data_mux[] = {
2398 RX0_MARK, TX0_MARK,
2399};
2400static const unsigned int scif0_clk_pins[] = {
2401 /* SCK */
2402 RCAR_GP_PIN(4, 27),
2403};
2404static const unsigned int scif0_clk_mux[] = {
2405 SCK0_MARK,
2406};
2407static const unsigned int scif0_ctrl_pins[] = {
2408 /* RTS, CTS */
2409 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2410};
2411static const unsigned int scif0_ctrl_mux[] = {
2412 RTS0_N_MARK, CTS0_N_MARK,
2413};
2414static const unsigned int scif0_data_b_pins[] = {
2415 /* RX, TX */
2416 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2417};
2418static const unsigned int scif0_data_b_mux[] = {
2419 RX0_B_MARK, TX0_B_MARK,
2420};
2421/* - SCIF1 ------------------------------------------------------------------ */
2422static const unsigned int scif1_data_pins[] = {
2423 /* RX, TX */
2424 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2425};
2426static const unsigned int scif1_data_mux[] = {
2427 RX1_MARK, TX1_MARK,
2428};
2429static const unsigned int scif1_clk_pins[] = {
2430 /* SCK */
2431 RCAR_GP_PIN(4, 20),
2432};
2433static const unsigned int scif1_clk_mux[] = {
2434 SCK1_MARK,
2435};
2436static const unsigned int scif1_ctrl_pins[] = {
2437 /* RTS, CTS */
2438 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2439};
2440static const unsigned int scif1_ctrl_mux[] = {
2441 RTS1_N_MARK, CTS1_N_MARK,
2442};
2443static const unsigned int scif1_data_b_pins[] = {
2444 /* RX, TX */
2445 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2446};
2447static const unsigned int scif1_data_b_mux[] = {
2448 RX1_B_MARK, TX1_B_MARK,
2449};
2450static const unsigned int scif1_data_c_pins[] = {
2451 /* RX, TX */
2452 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2453};
2454static const unsigned int scif1_data_c_mux[] = {
2455 RX1_C_MARK, TX1_C_MARK,
fbd0ca3d 2456};
457c11d3 2457static const unsigned int scif1_data_d_pins[] = {
fbd0ca3d 2458 /* RX, TX */
457c11d3 2459 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
fbd0ca3d 2460};
457c11d3
LP		 2461static const unsigned int scif1_data_d_mux[] = {
2462 RX1_D_MARK, TX1_D_MARK,
fbd0ca3d 2463};
457c11d3 2464static const unsigned int scif1_clk_d_pins[] = {
fbd0ca3d 2465 /* SCK */
457c11d3 2466 RCAR_GP_PIN(3, 17),
fbd0ca3d 2467};
457c11d3
LP		 2468static const unsigned int scif1_clk_d_mux[] = {
2469 SCK1_D_MARK,
fbd0ca3d 2470};
457c11d3
LP		 2471static const unsigned int scif1_data_e_pins[] = {
2472 /* RX, TX */
2473 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
fbd0ca3d 2474};
457c11d3
LP		 2475static const unsigned int scif1_data_e_mux[] = {
2476 RX1_E_MARK, TX1_E_MARK,
2477};
2478static const unsigned int scif1_clk_e_pins[] = {
2479 /* SCK */
2480 RCAR_GP_PIN(2, 20),
2481};
2482static const unsigned int scif1_clk_e_mux[] = {
2483 SCK1_E_MARK,
fbd0ca3d 2484};
2dbe7f2c
LP		 2485/* - SCIF2 ------------------------------------------------------------------ */
2486static const unsigned int scif2_data_pins[] = {
2487 /* RX, TX */
2488 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2489};
2490static const unsigned int scif2_data_mux[] = {
2491 RX2_MARK, TX2_MARK,
2492};
2493static const unsigned int scif2_clk_pins[] = {
2494 /* SCK */
2495 RCAR_GP_PIN(5, 4),
2496};
2497static const unsigned int scif2_clk_mux[] = {
2498 SCK2_MARK,
2499};
2500static const unsigned int scif2_data_b_pins[] = {
2501 /* RX, TX */
2502 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2503};
2504static const unsigned int scif2_data_b_mux[] = {
2505 RX2_B_MARK, TX2_B_MARK,
2506};
45c6c85d
LP		 2507/* - SCIFA0 ----------------------------------------------------------------- */
2508static const unsigned int scifa0_data_pins[] = {
2509 /* RXD, TXD */
2510 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2511};
2512static const unsigned int scifa0_data_mux[] = {
2513 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2514};
2515static const unsigned int scifa0_clk_pins[] = {
2516 /* SCK */
2517 RCAR_GP_PIN(4, 27),
2518};
2519static const unsigned int scifa0_clk_mux[] = {
2520 SCIFA0_SCK_MARK,
2521};
2522static const unsigned int scifa0_ctrl_pins[] = {
2523 /* RTS, CTS */
2524 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2525};
2526static const unsigned int scifa0_ctrl_mux[] = {
2527 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2528};
2529static const unsigned int scifa0_data_b_pins[] = {
2530 /* RXD, TXD */
2531 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2532};
2533static const unsigned int scifa0_data_b_mux[] = {
2534 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2535};
2536static const unsigned int scifa0_clk_b_pins[] = {
2537 /* SCK */
2538 RCAR_GP_PIN(1, 19),
2539};
2540static const unsigned int scifa0_clk_b_mux[] = {
2541 SCIFA0_SCK_B_MARK,
2542};
2543static const unsigned int scifa0_ctrl_b_pins[] = {
2544 /* RTS, CTS */
2545 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2546};
2547static const unsigned int scifa0_ctrl_b_mux[] = {
2548 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2549};
2550/* - SCIFA1 ----------------------------------------------------------------- */
2551static const unsigned int scifa1_data_pins[] = {
2552 /* RXD, TXD */
2553 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2554};
2555static const unsigned int scifa1_data_mux[] = {
2556 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2557};
2558static const unsigned int scifa1_clk_pins[] = {
2559 /* SCK */
2560 RCAR_GP_PIN(4, 20),
2561};
2562static const unsigned int scifa1_clk_mux[] = {
2563 SCIFA1_SCK_MARK,
2564};
2565static const unsigned int scifa1_ctrl_pins[] = {
2566 /* RTS, CTS */
2567 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2568};
2569static const unsigned int scifa1_ctrl_mux[] = {
2570 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2571};
2572static const unsigned int scifa1_data_b_pins[] = {
2573 /* RXD, TXD */
2574 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2575};
2576static const unsigned int scifa1_data_b_mux[] = {
2577 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2578};
2579static const unsigned int scifa1_clk_b_pins[] = {
2580 /* SCK */
2581 RCAR_GP_PIN(0, 23),
2582};
2583static const unsigned int scifa1_clk_b_mux[] = {
2584 SCIFA1_SCK_B_MARK,
2585};
2586static const unsigned int scifa1_ctrl_b_pins[] = {
2587 /* RTS, CTS */
2588 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2589};
2590static const unsigned int scifa1_ctrl_b_mux[] = {
2591 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2592};
2593static const unsigned int scifa1_data_c_pins[] = {
2594 /* RXD, TXD */
2595 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2596};
2597static const unsigned int scifa1_data_c_mux[] = {
2598 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2599};
2600static const unsigned int scifa1_clk_c_pins[] = {
2601 /* SCK */
2602 RCAR_GP_PIN(0, 8),
2603};
2604static const unsigned int scifa1_clk_c_mux[] = {
2605 SCIFA1_SCK_C_MARK,
2606};
2607static const unsigned int scifa1_ctrl_c_pins[] = {
2608 /* RTS, CTS */
2609 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2610};
2611static const unsigned int scifa1_ctrl_c_mux[] = {
2612 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2613};
2614static const unsigned int scifa1_data_d_pins[] = {
2615 /* RXD, TXD */
2616 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2617};
2618static const unsigned int scifa1_data_d_mux[] = {
2619 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2620};
2621static const unsigned int scifa1_clk_d_pins[] = {
2622 /* SCK */
2623 RCAR_GP_PIN(2, 10),
2624};
2625static const unsigned int scifa1_clk_d_mux[] = {
2626 SCIFA1_SCK_D_MARK,
2627};
2628static const unsigned int scifa1_ctrl_d_pins[] = {
2629 /* RTS, CTS */
2630 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2631};
2632static const unsigned int scifa1_ctrl_d_mux[] = {
2633 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2634};
2635/* - SCIFA2 ----------------------------------------------------------------- */
2636static const unsigned int scifa2_data_pins[] = {
2637 /* RXD, TXD */
2638 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2639};
2640static const unsigned int scifa2_data_mux[] = {
2641 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2642};
2643static const unsigned int scifa2_clk_pins[] = {
2644 /* SCK */
2645 RCAR_GP_PIN(5, 4),
2646};
2647static const unsigned int scifa2_clk_mux[] = {
2648 SCIFA2_SCK_MARK,
2649};
2650static const unsigned int scifa2_ctrl_pins[] = {
2651 /* RTS, CTS */
2652 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2653};
2654static const unsigned int scifa2_ctrl_mux[] = {
2655 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
2656};
2657static const unsigned int scifa2_data_b_pins[] = {
2658 /* RXD, TXD */
2659 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2660};
2661static const unsigned int scifa2_data_b_mux[] = {
2662 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2663};
2664static const unsigned int scifa2_data_c_pins[] = {
2665 /* RXD, TXD */
2666 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
2667};
2668static const unsigned int scifa2_data_c_mux[] = {
2669 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
2670};
2671static const unsigned int scifa2_clk_c_pins[] = {
2672 /* SCK */
2673 RCAR_GP_PIN(5, 29),
2674};
2675static const unsigned int scifa2_clk_c_mux[] = {
2676 SCIFA2_SCK_C_MARK,
2677};
2678/* - SCIFB0 ----------------------------------------------------------------- */
2679static const unsigned int scifb0_data_pins[] = {
2680 /* RXD, TXD */
2681 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2682};
2683static const unsigned int scifb0_data_mux[] = {
2684 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2685};
2686static const unsigned int scifb0_clk_pins[] = {
2687 /* SCK */
2688 RCAR_GP_PIN(4, 8),
2689};
2690static const unsigned int scifb0_clk_mux[] = {
2691 SCIFB0_SCK_MARK,
2692};
2693static const unsigned int scifb0_ctrl_pins[] = {
2694 /* RTS, CTS */
2695 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2696};
2697static const unsigned int scifb0_ctrl_mux[] = {
2698 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2699};
2700static const unsigned int scifb0_data_b_pins[] = {
2701 /* RXD, TXD */
2702 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2703};
2704static const unsigned int scifb0_data_b_mux[] = {
2705 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2706};
2707static const unsigned int scifb0_clk_b_pins[] = {
2708 /* SCK */
2709 RCAR_GP_PIN(3, 9),
2710};
2711static const unsigned int scifb0_clk_b_mux[] = {
2712 SCIFB0_SCK_B_MARK,
2713};
2714static const unsigned int scifb0_ctrl_b_pins[] = {
2715 /* RTS, CTS */
2716 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2717};
2718static const unsigned int scifb0_ctrl_b_mux[] = {
2719 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2720};
2721static const unsigned int scifb0_data_c_pins[] = {
2722 /* RXD, TXD */
2723 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2724};
2725static const unsigned int scifb0_data_c_mux[] = {
2726 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2727};
2728/* - SCIFB1 ----------------------------------------------------------------- */
2729static const unsigned int scifb1_data_pins[] = {
2730 /* RXD, TXD */
2731 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2732};
2733static const unsigned int scifb1_data_mux[] = {
2734 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2735};
2736static const unsigned int scifb1_clk_pins[] = {
2737 /* SCK */
2738 RCAR_GP_PIN(4, 14),
2739};
2740static const unsigned int scifb1_clk_mux[] = {
2741 SCIFB1_SCK_MARK,
2742};
2743static const unsigned int scifb1_ctrl_pins[] = {
2744 /* RTS, CTS */
2745 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
2746};
2747static const unsigned int scifb1_ctrl_mux[] = {
2748 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2749};
2750static const unsigned int scifb1_data_b_pins[] = {
2751 /* RXD, TXD */
2752 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2753};
2754static const unsigned int scifb1_data_b_mux[] = {
2755 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2756};
2757static const unsigned int scifb1_clk_b_pins[] = {
2758 /* SCK */
2759 RCAR_GP_PIN(3, 1),
2760};
2761static const unsigned int scifb1_clk_b_mux[] = {
2762 SCIFB1_SCK_B_MARK,
2763};
2764static const unsigned int scifb1_ctrl_b_pins[] = {
2765 /* RTS, CTS */
2766 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
2767};
2768static const unsigned int scifb1_ctrl_b_mux[] = {
2769 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
2770};
2771static const unsigned int scifb1_data_c_pins[] = {
2772 /* RXD, TXD */
2773 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2774};
2775static const unsigned int scifb1_data_c_mux[] = {
2776 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2777};
2778static const unsigned int scifb1_data_d_pins[] = {
2779 /* RXD, TXD */
2780 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2781};
2782static const unsigned int scifb1_data_d_mux[] = {
2783 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2784};
2785static const unsigned int scifb1_data_e_pins[] = {
2786 /* RXD, TXD */
2787 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2788};
2789static const unsigned int scifb1_data_e_mux[] = {
2790 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
2791};
2792static const unsigned int scifb1_clk_e_pins[] = {
2793 /* SCK */
2794 RCAR_GP_PIN(3, 17),
2795};
2796static const unsigned int scifb1_clk_e_mux[] = {
2797 SCIFB1_SCK_E_MARK,
2798};
2799static const unsigned int scifb1_data_f_pins[] = {
2800 /* RXD, TXD */
2801 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2802};
2803static const unsigned int scifb1_data_f_mux[] = {
2804 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
2805};
2806static const unsigned int scifb1_data_g_pins[] = {
2807 /* RXD, TXD */
2808 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2809};
2810static const unsigned int scifb1_data_g_mux[] = {
2811 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
2812};
2813static const unsigned int scifb1_clk_g_pins[] = {
2814 /* SCK */
2815 RCAR_GP_PIN(2, 20),
2816};
2817static const unsigned int scifb1_clk_g_mux[] = {
2818 SCIFB1_SCK_G_MARK,
066f0d6e 2819};
45c6c85d
LP		 2820/* - SCIFB2 ----------------------------------------------------------------- */
2821static const unsigned int scifb2_data_pins[] = {
2822 /* RXD, TXD */
2823 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
066f0d6e 2824};
45c6c85d
LP		 2825static const unsigned int scifb2_data_mux[] = {
2826 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
066f0d6e 2827};
45c6c85d
LP		 2828static const unsigned int scifb2_clk_pins[] = {
2829 /* SCK */
2830 RCAR_GP_PIN(4, 21),
066f0d6e 2831};
45c6c85d
LP		 2832static const unsigned int scifb2_clk_mux[] = {
2833 SCIFB2_SCK_MARK,
066f0d6e 2834};
45c6c85d
LP		 2835static const unsigned int scifb2_ctrl_pins[] = {
2836 /* RTS, CTS */
2837 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
066f0d6e 2838};
45c6c85d
LP		 2839static const unsigned int scifb2_ctrl_mux[] = {
2840 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
066f0d6e 2841};
45c6c85d
LP		 2842static const unsigned int scifb2_data_b_pins[] = {
2843 /* RXD, TXD */
2844 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
066f0d6e 2845};
45c6c85d
LP		 2846static const unsigned int scifb2_data_b_mux[] = {
2847 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
066f0d6e 2848};
45c6c85d
LP		 2849static const unsigned int scifb2_clk_b_pins[] = {
2850 /* SCK */
2851 RCAR_GP_PIN(0, 31),
066f0d6e 2852};
45c6c85d
LP		 2853static const unsigned int scifb2_clk_b_mux[] = {
2854 SCIFB2_SCK_B_MARK,
066f0d6e 2855};
45c6c85d
LP		 2856static const unsigned int scifb2_ctrl_b_pins[] = {
2857 /* RTS, CTS */
2858 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
066f0d6e 2859};
45c6c85d
LP		 2860static const unsigned int scifb2_ctrl_b_mux[] = {
2861 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
066f0d6e 2862};
45c6c85d
LP		 2863static const unsigned int scifb2_data_c_pins[] = {
2864 /* RXD, TXD */
2865 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2866};
2867static const unsigned int scifb2_data_c_mux[] = {
2868 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
066f0d6e 2869};
0a6ea54f 2870/* - SDHI0 ------------------------------------------------------------------ */
066f0d6e
GL		 2871static const unsigned int sdhi0_data1_pins[] = {
2872 /* D0 */
2873 RCAR_GP_PIN(3, 2),
2874};
2875static const unsigned int sdhi0_data1_mux[] = {
2876 SD0_DAT0_MARK,
2877};
2878static const unsigned int sdhi0_data4_pins[] = {
2879 /* D[0:3] */
2880 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2881};
2882static const unsigned int sdhi0_data4_mux[] = {
2883 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2884};
2885static const unsigned int sdhi0_ctrl_pins[] = {
2886 /* CLK, CMD */
2887 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2888};
2889static const unsigned int sdhi0_ctrl_mux[] = {
2890 SD0_CLK_MARK, SD0_CMD_MARK,
2891};
2892static const unsigned int sdhi0_cd_pins[] = {
2893 /* CD */
2894 RCAR_GP_PIN(3, 6),
2895};
2896static const unsigned int sdhi0_cd_mux[] = {
2897 SD0_CD_MARK,
2898};
2899static const unsigned int sdhi0_wp_pins[] = {
2900 /* WP */
2901 RCAR_GP_PIN(3, 7),
2902};
2903static const unsigned int sdhi0_wp_mux[] = {
2904 SD0_WP_MARK,
2905};
0a6ea54f 2906/* - SDHI1 ------------------------------------------------------------------ */
066f0d6e
GL		 2907static const unsigned int sdhi1_data1_pins[] = {
2908 /* D0 */
2909 RCAR_GP_PIN(3, 10),
2910};
2911static const unsigned int sdhi1_data1_mux[] = {
2912 SD1_DAT0_MARK,
2913};
2914static const unsigned int sdhi1_data4_pins[] = {
2915 /* D[0:3] */
2916 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2917};
2918static const unsigned int sdhi1_data4_mux[] = {
2919 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2920};
2921static const unsigned int sdhi1_ctrl_pins[] = {
2922 /* CLK, CMD */
2923 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2924};
2925static const unsigned int sdhi1_ctrl_mux[] = {
2926 SD1_CLK_MARK, SD1_CMD_MARK,
2927};
2928static const unsigned int sdhi1_cd_pins[] = {
2929 /* CD */
2930 RCAR_GP_PIN(3, 14),
2931};
2932static const unsigned int sdhi1_cd_mux[] = {
2933 SD1_CD_MARK,
2934};
2935static const unsigned int sdhi1_wp_pins[] = {
2936 /* WP */
2937 RCAR_GP_PIN(3, 15),
2938};
2939static const unsigned int sdhi1_wp_mux[] = {
2940 SD1_WP_MARK,
2941};
0a6ea54f 2942/* - SDHI2 ------------------------------------------------------------------ */
066f0d6e
GL		 2943static const unsigned int sdhi2_data1_pins[] = {
2944 /* D0 */
2945 RCAR_GP_PIN(3, 18),
2946};
2947static const unsigned int sdhi2_data1_mux[] = {
2948 SD2_DAT0_MARK,
2949};
2950static const unsigned int sdhi2_data4_pins[] = {
2951 /* D[0:3] */
2952 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2953};
2954static const unsigned int sdhi2_data4_mux[] = {
2955 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2956};
2957static const unsigned int sdhi2_ctrl_pins[] = {
2958 /* CLK, CMD */
2959 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2960};
2961static const unsigned int sdhi2_ctrl_mux[] = {
2962 SD2_CLK_MARK, SD2_CMD_MARK,
2963};
2964static const unsigned int sdhi2_cd_pins[] = {
2965 /* CD */
2966 RCAR_GP_PIN(3, 22),
2967};
2968static const unsigned int sdhi2_cd_mux[] = {
2969 SD2_CD_MARK,
2970};
2971static const unsigned int sdhi2_wp_pins[] = {
2972 /* WP */
2973 RCAR_GP_PIN(3, 23),
2974};
2975static const unsigned int sdhi2_wp_mux[] = {
2976 SD2_WP_MARK,
2977};
0a6ea54f 2978/* - SDHI3 ------------------------------------------------------------------ */
066f0d6e
GL		 2979static const unsigned int sdhi3_data1_pins[] = {
2980 /* D0 */
2981 RCAR_GP_PIN(3, 26),
2982};
2983static const unsigned int sdhi3_data1_mux[] = {
2984 SD3_DAT0_MARK,
2985};
2986static const unsigned int sdhi3_data4_pins[] = {
2987 /* D[0:3] */
2988 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2989};
2990static const unsigned int sdhi3_data4_mux[] = {
2991 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2992};
2993static const unsigned int sdhi3_ctrl_pins[] = {
2994 /* CLK, CMD */
2995 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2996};
2997static const unsigned int sdhi3_ctrl_mux[] = {
2998 SD3_CLK_MARK, SD3_CMD_MARK,
2999};
3000static const unsigned int sdhi3_cd_pins[] = {
3001 /* CD */
3002 RCAR_GP_PIN(3, 30),
3003};
3004static const unsigned int sdhi3_cd_mux[] = {
3005 SD3_CD_MARK,
3006};
3007static const unsigned int sdhi3_wp_pins[] = {
3008 /* WP */
3009 RCAR_GP_PIN(3, 31),
3010};
3011static const unsigned int sdhi3_wp_mux[] = {
3012 SD3_WP_MARK,
3013};
1d7b59a0
KM		 3014/* - SSI -------------------------------------------------------------------- */
3015static const unsigned int ssi0_data_pins[] = {
3016 /* SDATA0 */
3017 RCAR_GP_PIN(4, 5),
3018};
3019static const unsigned int ssi0_data_mux[] = {
3020 SSI_SDATA0_MARK,
3021};
3022static const unsigned int ssi0129_ctrl_pins[] = {
3023 /* SCK, WS */
3024 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3025};
3026static const unsigned int ssi0129_ctrl_mux[] = {
3027 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3028};
3029static const unsigned int ssi1_data_pins[] = {
3030 /* SDATA1 */
3031 RCAR_GP_PIN(4, 6),
3032};
3033static const unsigned int ssi1_data_mux[] = {
3034 SSI_SDATA1_MARK,
3035};
3036static const unsigned int ssi1_ctrl_pins[] = {
3037 /* SCK, WS */
3038 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3039};
3040static const unsigned int ssi1_ctrl_mux[] = {
3041 SSI_SCK1_MARK, SSI_WS1_MARK,
3042};
3043static const unsigned int ssi2_data_pins[] = {
3044 /* SDATA2 */
3045 RCAR_GP_PIN(4, 7),
3046};
3047static const unsigned int ssi2_data_mux[] = {
3048 SSI_SDATA2_MARK,
3049};
3050static const unsigned int ssi2_ctrl_pins[] = {
3051 /* SCK, WS */
3052 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3053};
3054static const unsigned int ssi2_ctrl_mux[] = {
3055 SSI_SCK2_MARK, SSI_WS2_MARK,
3056};
3057static const unsigned int ssi3_data_pins[] = {
3058 /* SDATA3 */
3059 RCAR_GP_PIN(4, 10),
3060};
3061static const unsigned int ssi3_data_mux[] = {
3062 SSI_SDATA3_MARK
3063};
3064static const unsigned int ssi34_ctrl_pins[] = {
3065 /* SCK, WS */
3066 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3067};
3068static const unsigned int ssi34_ctrl_mux[] = {
3069 SSI_SCK34_MARK, SSI_WS34_MARK,
3070};
3071static const unsigned int ssi4_data_pins[] = {
3072 /* SDATA4 */
3073 RCAR_GP_PIN(4, 13),
3074};
3075static const unsigned int ssi4_data_mux[] = {
3076 SSI_SDATA4_MARK,
3077};
3078static const unsigned int ssi4_ctrl_pins[] = {
3079 /* SCK, WS */
3080 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3081};
3082static const unsigned int ssi4_ctrl_mux[] = {
3083 SSI_SCK4_MARK, SSI_WS4_MARK,
3084};
3085static const unsigned int ssi5_pins[] = {
3086 /* SDATA5, SCK, WS */
3087 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3088};
3089static const unsigned int ssi5_mux[] = {
3090 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3091};
3092static const unsigned int ssi5_b_pins[] = {
3093 /* SDATA5, SCK, WS */
3094 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3095};
3096static const unsigned int ssi5_b_mux[] = {
3097 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3098};
3099static const unsigned int ssi5_c_pins[] = {
3100 /* SDATA5, SCK, WS */
3101 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3102};
3103static const unsigned int ssi5_c_mux[] = {
3104 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3105};
3106static const unsigned int ssi6_pins[] = {
3107 /* SDATA6, SCK, WS */
3108 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3109};
3110static const unsigned int ssi6_mux[] = {
3111 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3112};
3113static const unsigned int ssi6_b_pins[] = {
3114 /* SDATA6, SCK, WS */
3115 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3116};
3117static const unsigned int ssi6_b_mux[] = {
3118 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3119};
3120static const unsigned int ssi7_data_pins[] = {
3121 /* SDATA7 */
3122 RCAR_GP_PIN(4, 22),
3123};
3124static const unsigned int ssi7_data_mux[] = {
3125 SSI_SDATA7_MARK,
3126};
3127static const unsigned int ssi7_b_data_pins[] = {
3128 /* SDATA7 */
3129 RCAR_GP_PIN(4, 22),
3130};
3131static const unsigned int ssi7_b_data_mux[] = {
3132 SSI_SDATA7_B_MARK,
3133};
3134static const unsigned int ssi7_c_data_pins[] = {
3135 /* SDATA7 */
3136 RCAR_GP_PIN(1, 26),
3137};
3138static const unsigned int ssi7_c_data_mux[] = {
3139 SSI_SDATA7_C_MARK,
3140};
3141static const unsigned int ssi78_ctrl_pins[] = {
3142 /* SCK, WS */
3143 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3144};
3145static const unsigned int ssi78_ctrl_mux[] = {
3146 SSI_SCK78_MARK, SSI_WS78_MARK,
3147};
3148static const unsigned int ssi78_b_ctrl_pins[] = {
3149 /* SCK, WS */
3150 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3151};
3152static const unsigned int ssi78_b_ctrl_mux[] = {
3153 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3154};
3155static const unsigned int ssi78_c_ctrl_pins[] = {
3156 /* SCK, WS */
3157 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3158};
3159static const unsigned int ssi78_c_ctrl_mux[] = {
3160 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3161};
3162static const unsigned int ssi8_data_pins[] = {
3163 /* SDATA8 */
3164 RCAR_GP_PIN(4, 23),
3165};
3166static const unsigned int ssi8_data_mux[] = {
3167 SSI_SDATA8_MARK,
3168};
3169static const unsigned int ssi8_b_data_pins[] = {
3170 /* SDATA8 */
3171 RCAR_GP_PIN(4, 23),
3172};
3173static const unsigned int ssi8_b_data_mux[] = {
3174 SSI_SDATA8_B_MARK,
3175};
3176static const unsigned int ssi8_c_data_pins[] = {
3177 /* SDATA8 */
3178 RCAR_GP_PIN(1, 27),
3179};
3180static const unsigned int ssi8_c_data_mux[] = {
3181 SSI_SDATA8_C_MARK,
3182};
3183static const unsigned int ssi9_data_pins[] = {
3184 /* SDATA9 */
3185 RCAR_GP_PIN(4, 24),
3186};
3187static const unsigned int ssi9_data_mux[] = {
3188 SSI_SDATA9_MARK,
3189};
3190static const unsigned int ssi9_ctrl_pins[] = {
3191 /* SCK, WS */
3192 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3193};
3194static const unsigned int ssi9_ctrl_mux[] = {
3195 SSI_SCK9_MARK, SSI_WS9_MARK,
3196};
457c11d3
LP		 3197/* - TPU0 ------------------------------------------------------------------- */
3198static const unsigned int tpu0_to0_pins[] = {
3199 /* TO */
3200 RCAR_GP_PIN(0, 20),
3201};
3202static const unsigned int tpu0_to0_mux[] = {
3203 TPU0TO0_MARK,
3204};
3205static const unsigned int tpu0_to1_pins[] = {
3206 /* TO */
3207 RCAR_GP_PIN(0, 21),
3208};
3209static const unsigned int tpu0_to1_mux[] = {
3210 TPU0TO1_MARK,
3211};
3212static const unsigned int tpu0_to2_pins[] = {
3213 /* TO */
3214 RCAR_GP_PIN(0, 22),
3215};
3216static const unsigned int tpu0_to2_mux[] = {
3217 TPU0TO2_MARK,
3218};
3219static const unsigned int tpu0_to3_pins[] = {
3220 /* TO */
3221 RCAR_GP_PIN(0, 23),
3222};
3223static const unsigned int tpu0_to3_mux[] = {
3224 TPU0TO3_MARK,
3225};
dac896e2
SU		 3226/* - USB0 ------------------------------------------------------------------- */
3227static const unsigned int usb0_pins[] = {
3228 /* PWEN, OVC/VBUS */
3229 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3230};
3231static const unsigned int usb0_mux[] = {
3232 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3233};
3234/* - USB1 ------------------------------------------------------------------- */
3235static const unsigned int usb1_pins[] = {
3236 /* PWEN, OVC */
3237 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3238};
3239static const unsigned int usb1_mux[] = {
3240 USB1_PWEN_MARK, USB1_OVC_MARK,
3241};
3242/* - USB2 ------------------------------------------------------------------- */
3243static const unsigned int usb2_pins[] = {
3244 /* PWEN, OVC */
3245 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3246};
3247static const unsigned int usb2_mux[] = {
3248 USB2_PWEN_MARK, USB2_OVC_MARK,
3249};
64fe8abc
VB		 3250
3251union vin_data {
3252 unsigned int data24[24];
3253 unsigned int data20[20];
3254 unsigned int data16[16];
3255 unsigned int data12[12];
3256 unsigned int data10[10];
3257 unsigned int data8[8];
3258 unsigned int data4[4];
3259};
3260
3261#define VIN_DATA_PIN_GROUP(n, s) \
3262 { \
3263 .name = #n#s, \
3264 .pins = n##_pins.data##s, \
3265 .mux = n##_mux.data##s, \
3266 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
3267 }
3268
e120cacf 3269/* - VIN0 ------------------------------------------------------------------- */
64fe8abc
VB		 3270static const union vin_data vin0_data_pins = {
3271 .data24 = {
3272 /* B */
3273 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3274 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3275 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3276 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3277 /* G */
3278 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3279 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3280 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3281 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3282 /* R */
3283 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3284 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3285 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3286 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3287 },
3288};
3289static const union vin_data vin0_data_mux = {
3290 .data24 = {
3291 /* B */
3292 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3293 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3294 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3295 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3296 /* G */
3297 VI0_G0_MARK, VI0_G1_MARK,
3298 VI0_G2_MARK, VI0_G3_MARK,
3299 VI0_G4_MARK, VI0_G5_MARK,
3300 VI0_G6_MARK, VI0_G7_MARK,
3301 /* R */
3302 VI0_R0_MARK, VI0_R1_MARK,
3303 VI0_R2_MARK, VI0_R3_MARK,
3304 VI0_R4_MARK, VI0_R5_MARK,
3305 VI0_R6_MARK, VI0_R7_MARK,
3306 },
3307};
3308static const unsigned int vin0_data18_pins[] = {
3309 /* B */
3310 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3311 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3312 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3313 /* G */
3314 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3315 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
e120cacf 3316 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
64fe8abc
VB		 3317 /* R */
3318 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3319 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
e120cacf
SU		 3320 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3321};
64fe8abc
VB		 3322static const unsigned int vin0_data18_mux[] = {
3323 /* B */
3324 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3325 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
e120cacf 3326 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
64fe8abc
VB		 3327 /* G */
3328 VI0_G2_MARK, VI0_G3_MARK,
3329 VI0_G4_MARK, VI0_G5_MARK,
3330 VI0_G6_MARK, VI0_G7_MARK,
3331 /* R */
3332 VI0_R2_MARK, VI0_R3_MARK,
3333 VI0_R4_MARK, VI0_R5_MARK,
3334 VI0_R6_MARK, VI0_R7_MARK,
e120cacf 3335};
a9e4c7bb
VB		 3336static const unsigned int vin0_sync_pins[] = {
3337 RCAR_GP_PIN(0, 12), /* HSYNC */
3338 RCAR_GP_PIN(0, 13), /* VSYNC */
e120cacf 3339};
a9e4c7bb 3340static const unsigned int vin0_sync_mux[] = {
e120cacf 3341 VI0_HSYNC_N_MARK,
e120cacf
SU		 3342 VI0_VSYNC_N_MARK,
3343};
7a57be87 3344static const unsigned int vin0_field_pins[] = {
e120cacf
SU		 3345 RCAR_GP_PIN(0, 15),
3346};
7a57be87 3347static const unsigned int vin0_field_mux[] = {
e120cacf
SU		 3348 VI0_FIELD_MARK,
3349};
7a57be87 3350static const unsigned int vin0_clkenb_pins[] = {
e120cacf
SU		 3351 RCAR_GP_PIN(0, 14),
3352};
7a57be87 3353static const unsigned int vin0_clkenb_mux[] = {
e120cacf
SU		 3354 VI0_CLKENB_MARK,
3355};
3356static const unsigned int vin0_clk_pins[] = {
3357 RCAR_GP_PIN(2, 0),
3358};
3359static const unsigned int vin0_clk_mux[] = {
3360 VI0_CLK_MARK,
3361};
3362/* - VIN1 ------------------------------------------------------------------- */
317a03a9
VB		 3363static const union vin_data vin1_data_pins = {
3364 .data24 = {
3365 /* B */
3366 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3367 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3368 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3369 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3370 /* G */
3371 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3372 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3373 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3374 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3375 /* R */
3376 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3377 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3378 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3379 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3380 },
3381};
3382static const union vin_data vin1_data_mux = {
3383 .data24 = {
3384 /* B */
3385 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3386 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3387 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3388 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3389 /* G */
3390 VI1_G0_MARK, VI1_G1_MARK,
3391 VI1_G2_MARK, VI1_G3_MARK,
3392 VI1_G4_MARK, VI1_G5_MARK,
3393 VI1_G6_MARK, VI1_G7_MARK,
3394 /* R */
3395 VI1_R0_MARK, VI1_R1_MARK,
3396 VI1_R2_MARK, VI1_R3_MARK,
3397 VI1_R4_MARK, VI1_R5_MARK,
3398 VI1_R6_MARK, VI1_R7_MARK,
3399 },
3400};
3401static const unsigned int vin1_data18_pins[] = {
3402 /* B */
3403 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3404 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
e120cacf 3405 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
317a03a9
VB		 3406 /* G */
3407 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3408 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3409 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3410 /* R */
3411 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3412 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3413 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
e120cacf 3414};
317a03a9
VB		 3415static const unsigned int vin1_data18_mux[] = {
3416 /* B */
3417 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3418 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
e120cacf 3419 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
317a03a9
VB		 3420 /* G */
3421 VI1_G2_MARK, VI1_G3_MARK,
3422 VI1_G4_MARK, VI1_G5_MARK,
3423 VI1_G6_MARK, VI1_G7_MARK,
3424 /* R */
3425 VI1_R2_MARK, VI1_R3_MARK,
3426 VI1_R4_MARK, VI1_R5_MARK,
3427 VI1_R6_MARK, VI1_R7_MARK,
3428};
3429static const unsigned int vin1_sync_pins[] = {
3430 RCAR_GP_PIN(1, 24), /* HSYNC */
3431 RCAR_GP_PIN(1, 25), /* VSYNC */
3432};
3433static const unsigned int vin1_sync_mux[] = {
3434 VI1_HSYNC_N_MARK,
3435 VI1_VSYNC_N_MARK,
3436};
3437static const unsigned int vin1_field_pins[] = {
3438 RCAR_GP_PIN(1, 13),
3439};
3440static const unsigned int vin1_field_mux[] = {
3441 VI1_FIELD_MARK,
3442};
3443static const unsigned int vin1_clkenb_pins[] = {
3444 RCAR_GP_PIN(1, 26),
3445};
3446static const unsigned int vin1_clkenb_mux[] = {
3447 VI1_CLKENB_MARK,
e120cacf
SU		 3448};
3449static const unsigned int vin1_clk_pins[] = {
3450 RCAR_GP_PIN(2, 9),
3451};
3452static const unsigned int vin1_clk_mux[] = {
3453 VI1_CLK_MARK,
3454};
054d4259
VB		 3455/* - VIN2 ----------------------------------------------------------------- */
3456static const union vin_data vin2_data_pins = {
3457 .data24 = {
3458 /* B */
3459 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3460 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3461 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3462 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3463 /* G */
3464 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3465 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3466 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3467 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3468 /* R */
3469 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3470 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3471 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3472 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3473 },
3474};
3475static const union vin_data vin2_data_mux = {
3476 .data24 = {
3477 /* B */
3478 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3479 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3480 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3481 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3482 /* G */
3483 VI2_G0_MARK, VI2_G1_MARK,
3484 VI2_G2_MARK, VI2_G3_MARK,
3485 VI2_G4_MARK, VI2_G5_MARK,
3486 VI2_G6_MARK, VI2_G7_MARK,
3487 /* R */
3488 VI2_R0_MARK, VI2_R1_MARK,
3489 VI2_R2_MARK, VI2_R3_MARK,
3490 VI2_R4_MARK, VI2_R5_MARK,
3491 VI2_R6_MARK, VI2_R7_MARK,
3492 },
3493};
3494static const unsigned int vin2_data18_pins[] = {
3495 /* B */
3496 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3497 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3498 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3499 /* G */
3500 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3501 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3502 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3503 /* R */
3504 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3505 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3506 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3507};
3508static const unsigned int vin2_data18_mux[] = {
3509 /* B */
3510 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3511 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3512 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3513 /* G */
3514 VI2_G2_MARK, VI2_G3_MARK,
3515 VI2_G4_MARK, VI2_G5_MARK,
3516 VI2_G6_MARK, VI2_G7_MARK,
3517 /* R */
3518 VI2_R2_MARK, VI2_R3_MARK,
3519 VI2_R4_MARK, VI2_R5_MARK,
3520 VI2_R6_MARK, VI2_R7_MARK,
3521};
3522static const unsigned int vin2_sync_pins[] = {
3523 RCAR_GP_PIN(1, 16), /* HSYNC */
3524 RCAR_GP_PIN(1, 21), /* VSYNC */
3525};
3526static const unsigned int vin2_sync_mux[] = {
3527 VI2_HSYNC_N_MARK,
3528 VI2_VSYNC_N_MARK,
3529};
3530static const unsigned int vin2_field_pins[] = {
3531 RCAR_GP_PIN(1, 9),
3532};
3533static const unsigned int vin2_field_mux[] = {
3534 VI2_FIELD_MARK,
3535};
3536static const unsigned int vin2_clkenb_pins[] = {
3537 RCAR_GP_PIN(1, 8),
3538};
3539static const unsigned int vin2_clkenb_mux[] = {
3540 VI2_CLKENB_MARK,
3541};
3542static const unsigned int vin2_clk_pins[] = {
3543 RCAR_GP_PIN(1, 11),
3544};
3545static const unsigned int vin2_clk_mux[] = {
3546 VI2_CLK_MARK,
3547};
3548/* - VIN3 ----------------------------------------------------------------- */
3549static const unsigned int vin3_data8_pins[] = {
3550 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3551 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3552 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3553 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3554};
3555static const unsigned int vin3_data8_mux[] = {
3556 VI3_DATA0_MARK, VI3_DATA1_MARK,
3557 VI3_DATA2_MARK, VI3_DATA3_MARK,
3558 VI3_DATA4_MARK, VI3_DATA5_MARK,
3559 VI3_DATA6_MARK, VI3_DATA7_MARK,
3560};
3561static const unsigned int vin3_sync_pins[] = {
3562 RCAR_GP_PIN(1, 16), /* HSYNC */
3563 RCAR_GP_PIN(1, 17), /* VSYNC */
3564};
3565static const unsigned int vin3_sync_mux[] = {
3566 VI3_HSYNC_N_MARK,
646ae3ef 3567 VI3_VSYNC_N_MARK,
054d4259
VB		 3568};
3569static const unsigned int vin3_field_pins[] = {
3570 RCAR_GP_PIN(1, 15),
3571};
3572static const unsigned int vin3_field_mux[] = {
3573 VI3_FIELD_MARK,
3574};
3575static const unsigned int vin3_clkenb_pins[] = {
3576 RCAR_GP_PIN(1, 14),
3577};
3578static const unsigned int vin3_clkenb_mux[] = {
3579 VI3_CLKENB_MARK,
3580};
3581static const unsigned int vin3_clk_pins[] = {
3582 RCAR_GP_PIN(1, 23),
3583};
3584static const unsigned int vin3_clk_mux[] = {
3585 VI3_CLK_MARK,
3586};
066f0d6e 3587
1627769b 3588static const struct sh_pfc_pin_group pinmux_groups[] = {
fcec5b22
KM		 3589 SH_PFC_PIN_GROUP(audio_clk_a),
3590 SH_PFC_PIN_GROUP(audio_clk_b),
3591 SH_PFC_PIN_GROUP(audio_clk_c),
3592 SH_PFC_PIN_GROUP(audio_clkout),
3593 SH_PFC_PIN_GROUP(audio_clkout_b),
3594 SH_PFC_PIN_GROUP(audio_clkout_c),
3595 SH_PFC_PIN_GROUP(audio_clkout_d),
62783b71
LP		 3596 SH_PFC_PIN_GROUP(du_rgb666),
3597 SH_PFC_PIN_GROUP(du_rgb888),
3598 SH_PFC_PIN_GROUP(du_clk_out_0),
3599 SH_PFC_PIN_GROUP(du_clk_out_1),
3600 SH_PFC_PIN_GROUP(du_sync_0),
3601 SH_PFC_PIN_GROUP(du_sync_1),
3602 SH_PFC_PIN_GROUP(du_cde),
3603 SH_PFC_PIN_GROUP(du0_clk_in),
3604 SH_PFC_PIN_GROUP(du1_clk_in),
3605 SH_PFC_PIN_GROUP(du2_clk_in),
1627769b
LP		 3606 SH_PFC_PIN_GROUP(eth_link),
3607 SH_PFC_PIN_GROUP(eth_magic),
3608 SH_PFC_PIN_GROUP(eth_mdio),
3609 SH_PFC_PIN_GROUP(eth_rmii),
fbd0ca3d
UH		 3610 SH_PFC_PIN_GROUP(hscif0_data),
3611 SH_PFC_PIN_GROUP(hscif0_clk),
3612 SH_PFC_PIN_GROUP(hscif0_ctrl),
3613 SH_PFC_PIN_GROUP(hscif0_data_b),
3614 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3615 SH_PFC_PIN_GROUP(hscif0_data_c),
3616 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3617 SH_PFC_PIN_GROUP(hscif0_data_d),
3618 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3619 SH_PFC_PIN_GROUP(hscif0_data_e),
3620 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3621 SH_PFC_PIN_GROUP(hscif0_data_f),
3622 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3623 SH_PFC_PIN_GROUP(hscif1_data),
3624 SH_PFC_PIN_GROUP(hscif1_clk),
3625 SH_PFC_PIN_GROUP(hscif1_ctrl),
3626 SH_PFC_PIN_GROUP(hscif1_data_b),
3627 SH_PFC_PIN_GROUP(hscif1_clk_b),
3628 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
70702bfc
UH		 3629 SH_PFC_PIN_GROUP(i2c1),
3630 SH_PFC_PIN_GROUP(i2c1_b),
3631 SH_PFC_PIN_GROUP(i2c1_c),
3632 SH_PFC_PIN_GROUP(i2c2),
3633 SH_PFC_PIN_GROUP(i2c2_b),
3634 SH_PFC_PIN_GROUP(i2c2_c),
3635 SH_PFC_PIN_GROUP(i2c2_d),
3636 SH_PFC_PIN_GROUP(i2c2_e),
f6aaaac9 3637 SH_PFC_PIN_GROUP(i2c3),
04e7ce78
LP		 3638 SH_PFC_PIN_GROUP(intc_irq0),
3639 SH_PFC_PIN_GROUP(intc_irq1),
3640 SH_PFC_PIN_GROUP(intc_irq2),
3641 SH_PFC_PIN_GROUP(intc_irq3),
fbd0ca3d
UH		 3642 SH_PFC_PIN_GROUP(mmc0_data1),
3643 SH_PFC_PIN_GROUP(mmc0_data4),
3644 SH_PFC_PIN_GROUP(mmc0_data8),
3645 SH_PFC_PIN_GROUP(mmc0_ctrl),
3646 SH_PFC_PIN_GROUP(mmc1_data1),
3647 SH_PFC_PIN_GROUP(mmc1_data4),
3648 SH_PFC_PIN_GROUP(mmc1_data8),
3649 SH_PFC_PIN_GROUP(mmc1_ctrl),
4f47cc5e
KH		 3650 SH_PFC_PIN_GROUP(msiof0_clk),
3651 SH_PFC_PIN_GROUP(msiof0_sync),
3652 SH_PFC_PIN_GROUP(msiof0_ss1),
3653 SH_PFC_PIN_GROUP(msiof0_ss2),
3654 SH_PFC_PIN_GROUP(msiof0_rx),
3655 SH_PFC_PIN_GROUP(msiof0_tx),
3656 SH_PFC_PIN_GROUP(msiof1_clk),
3657 SH_PFC_PIN_GROUP(msiof1_sync),
3658 SH_PFC_PIN_GROUP(msiof1_ss1),
3659 SH_PFC_PIN_GROUP(msiof1_ss2),
3660 SH_PFC_PIN_GROUP(msiof1_rx),
3661 SH_PFC_PIN_GROUP(msiof1_tx),
3662 SH_PFC_PIN_GROUP(msiof2_clk),
3663 SH_PFC_PIN_GROUP(msiof2_sync),
3664 SH_PFC_PIN_GROUP(msiof2_ss1),
3665 SH_PFC_PIN_GROUP(msiof2_ss2),
3666 SH_PFC_PIN_GROUP(msiof2_rx),
3667 SH_PFC_PIN_GROUP(msiof2_tx),
3668 SH_PFC_PIN_GROUP(msiof3_clk),
3669 SH_PFC_PIN_GROUP(msiof3_sync),
3670 SH_PFC_PIN_GROUP(msiof3_ss1),
3671 SH_PFC_PIN_GROUP(msiof3_ss2),
3672 SH_PFC_PIN_GROUP(msiof3_rx),
3673 SH_PFC_PIN_GROUP(msiof3_tx),
45c6c85d
LP		 3674 SH_PFC_PIN_GROUP(scif0_data),
3675 SH_PFC_PIN_GROUP(scif0_clk),
3676 SH_PFC_PIN_GROUP(scif0_ctrl),
3677 SH_PFC_PIN_GROUP(scif0_data_b),
3678 SH_PFC_PIN_GROUP(scif1_data),
3679 SH_PFC_PIN_GROUP(scif1_clk),
3680 SH_PFC_PIN_GROUP(scif1_ctrl),
3681 SH_PFC_PIN_GROUP(scif1_data_b),
3682 SH_PFC_PIN_GROUP(scif1_data_c),
3683 SH_PFC_PIN_GROUP(scif1_data_d),
3684 SH_PFC_PIN_GROUP(scif1_clk_d),
3685 SH_PFC_PIN_GROUP(scif1_data_e),
3686 SH_PFC_PIN_GROUP(scif1_clk_e),
2dbe7f2c
LP		 3687 SH_PFC_PIN_GROUP(scif2_data),
3688 SH_PFC_PIN_GROUP(scif2_clk),
3689 SH_PFC_PIN_GROUP(scif2_data_b),
45c6c85d
LP		 3690 SH_PFC_PIN_GROUP(scifa0_data),
3691 SH_PFC_PIN_GROUP(scifa0_clk),
3692 SH_PFC_PIN_GROUP(scifa0_ctrl),
3693 SH_PFC_PIN_GROUP(scifa0_data_b),
3694 SH_PFC_PIN_GROUP(scifa0_clk_b),
3695 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
3696 SH_PFC_PIN_GROUP(scifa1_data),
3697 SH_PFC_PIN_GROUP(scifa1_clk),
3698 SH_PFC_PIN_GROUP(scifa1_ctrl),
3699 SH_PFC_PIN_GROUP(scifa1_data_b),
3700 SH_PFC_PIN_GROUP(scifa1_clk_b),
3701 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
3702 SH_PFC_PIN_GROUP(scifa1_data_c),
3703 SH_PFC_PIN_GROUP(scifa1_clk_c),
3704 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
3705 SH_PFC_PIN_GROUP(scifa1_data_d),
3706 SH_PFC_PIN_GROUP(scifa1_clk_d),
3707 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
3708 SH_PFC_PIN_GROUP(scifa2_data),
3709 SH_PFC_PIN_GROUP(scifa2_clk),
3710 SH_PFC_PIN_GROUP(scifa2_ctrl),
3711 SH_PFC_PIN_GROUP(scifa2_data_b),
3712 SH_PFC_PIN_GROUP(scifa2_data_c),
3713 SH_PFC_PIN_GROUP(scifa2_clk_c),
3714 SH_PFC_PIN_GROUP(scifb0_data),
3715 SH_PFC_PIN_GROUP(scifb0_clk),
3716 SH_PFC_PIN_GROUP(scifb0_ctrl),
3717 SH_PFC_PIN_GROUP(scifb0_data_b),
3718 SH_PFC_PIN_GROUP(scifb0_clk_b),
3719 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3720 SH_PFC_PIN_GROUP(scifb0_data_c),
3721 SH_PFC_PIN_GROUP(scifb1_data),
3722 SH_PFC_PIN_GROUP(scifb1_clk),
3723 SH_PFC_PIN_GROUP(scifb1_ctrl),
3724 SH_PFC_PIN_GROUP(scifb1_data_b),
3725 SH_PFC_PIN_GROUP(scifb1_clk_b),
3726 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
3727 SH_PFC_PIN_GROUP(scifb1_data_c),
3728 SH_PFC_PIN_GROUP(scifb1_data_d),
3729 SH_PFC_PIN_GROUP(scifb1_data_e),
3730 SH_PFC_PIN_GROUP(scifb1_clk_e),
3731 SH_PFC_PIN_GROUP(scifb1_data_f),
3732 SH_PFC_PIN_GROUP(scifb1_data_g),
3733 SH_PFC_PIN_GROUP(scifb1_clk_g),
3734 SH_PFC_PIN_GROUP(scifb2_data),
3735 SH_PFC_PIN_GROUP(scifb2_clk),
3736 SH_PFC_PIN_GROUP(scifb2_ctrl),
3737 SH_PFC_PIN_GROUP(scifb2_data_b),
3738 SH_PFC_PIN_GROUP(scifb2_clk_b),
3739 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3740 SH_PFC_PIN_GROUP(scifb2_data_c),
066f0d6e
GL		 3741 SH_PFC_PIN_GROUP(sdhi0_data1),
3742 SH_PFC_PIN_GROUP(sdhi0_data4),
3743 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3744 SH_PFC_PIN_GROUP(sdhi0_cd),
3745 SH_PFC_PIN_GROUP(sdhi0_wp),
3746 SH_PFC_PIN_GROUP(sdhi1_data1),
3747 SH_PFC_PIN_GROUP(sdhi1_data4),
3748 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3749 SH_PFC_PIN_GROUP(sdhi1_cd),
3750 SH_PFC_PIN_GROUP(sdhi1_wp),
3751 SH_PFC_PIN_GROUP(sdhi2_data1),
3752 SH_PFC_PIN_GROUP(sdhi2_data4),
3753 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3754 SH_PFC_PIN_GROUP(sdhi2_cd),
3755 SH_PFC_PIN_GROUP(sdhi2_wp),
3756 SH_PFC_PIN_GROUP(sdhi3_data1),
3757 SH_PFC_PIN_GROUP(sdhi3_data4),
3758 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3759 SH_PFC_PIN_GROUP(sdhi3_cd),
3760 SH_PFC_PIN_GROUP(sdhi3_wp),
1d7b59a0
KM		 3761 SH_PFC_PIN_GROUP(ssi0_data),
3762 SH_PFC_PIN_GROUP(ssi0129_ctrl),
3763 SH_PFC_PIN_GROUP(ssi1_data),
3764 SH_PFC_PIN_GROUP(ssi1_ctrl),
3765 SH_PFC_PIN_GROUP(ssi2_data),
3766 SH_PFC_PIN_GROUP(ssi2_ctrl),
3767 SH_PFC_PIN_GROUP(ssi3_data),
3768 SH_PFC_PIN_GROUP(ssi34_ctrl),
3769 SH_PFC_PIN_GROUP(ssi4_data),
3770 SH_PFC_PIN_GROUP(ssi4_ctrl),
3771 SH_PFC_PIN_GROUP(ssi5),
3772 SH_PFC_PIN_GROUP(ssi5_b),
3773 SH_PFC_PIN_GROUP(ssi5_c),
3774 SH_PFC_PIN_GROUP(ssi6),
3775 SH_PFC_PIN_GROUP(ssi6_b),
3776 SH_PFC_PIN_GROUP(ssi7_data),
3777 SH_PFC_PIN_GROUP(ssi7_b_data),
3778 SH_PFC_PIN_GROUP(ssi7_c_data),
3779 SH_PFC_PIN_GROUP(ssi78_ctrl),
3780 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
3781 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
3782 SH_PFC_PIN_GROUP(ssi8_data),
3783 SH_PFC_PIN_GROUP(ssi8_b_data),
3784 SH_PFC_PIN_GROUP(ssi8_c_data),
3785 SH_PFC_PIN_GROUP(ssi9_data),
3786 SH_PFC_PIN_GROUP(ssi9_ctrl),
fbd0ca3d
UH		 3787 SH_PFC_PIN_GROUP(tpu0_to0),
3788 SH_PFC_PIN_GROUP(tpu0_to1),
3789 SH_PFC_PIN_GROUP(tpu0_to2),
3790 SH_PFC_PIN_GROUP(tpu0_to3),
dac896e2
SU		 3791 SH_PFC_PIN_GROUP(usb0),
3792 SH_PFC_PIN_GROUP(usb1),
3793 SH_PFC_PIN_GROUP(usb2),
64fe8abc
VB		 3794 VIN_DATA_PIN_GROUP(vin0_data, 24),
3795 VIN_DATA_PIN_GROUP(vin0_data, 20),
3796 SH_PFC_PIN_GROUP(vin0_data18),
3797 VIN_DATA_PIN_GROUP(vin0_data, 16),
3798 VIN_DATA_PIN_GROUP(vin0_data, 12),
3799 VIN_DATA_PIN_GROUP(vin0_data, 10),
3800 VIN_DATA_PIN_GROUP(vin0_data, 8),
3801 VIN_DATA_PIN_GROUP(vin0_data, 4),
a9e4c7bb 3802 SH_PFC_PIN_GROUP(vin0_sync),
7a57be87
VB		 3803 SH_PFC_PIN_GROUP(vin0_field),
3804 SH_PFC_PIN_GROUP(vin0_clkenb),
e120cacf 3805 SH_PFC_PIN_GROUP(vin0_clk),
317a03a9
VB		 3806 VIN_DATA_PIN_GROUP(vin1_data, 24),
3807 VIN_DATA_PIN_GROUP(vin1_data, 20),
3808 SH_PFC_PIN_GROUP(vin1_data18),
3809 VIN_DATA_PIN_GROUP(vin1_data, 16),
3810 VIN_DATA_PIN_GROUP(vin1_data, 12),
3811 VIN_DATA_PIN_GROUP(vin1_data, 10),
3812 VIN_DATA_PIN_GROUP(vin1_data, 8),
3813 VIN_DATA_PIN_GROUP(vin1_data, 4),
3814 SH_PFC_PIN_GROUP(vin1_sync),
3815 SH_PFC_PIN_GROUP(vin1_field),
3816 SH_PFC_PIN_GROUP(vin1_clkenb),
e120cacf 3817 SH_PFC_PIN_GROUP(vin1_clk),
054d4259
VB		 3818 VIN_DATA_PIN_GROUP(vin2_data, 24),
3819 SH_PFC_PIN_GROUP(vin2_data18),
3820 VIN_DATA_PIN_GROUP(vin2_data, 16),
3821 VIN_DATA_PIN_GROUP(vin2_data, 8),
3822 VIN_DATA_PIN_GROUP(vin2_data, 4),
3823 SH_PFC_PIN_GROUP(vin2_sync),
3824 SH_PFC_PIN_GROUP(vin2_field),
3825 SH_PFC_PIN_GROUP(vin2_clkenb),
3826 SH_PFC_PIN_GROUP(vin2_clk),
3827 SH_PFC_PIN_GROUP(vin3_data8),
3828 SH_PFC_PIN_GROUP(vin3_sync),
3829 SH_PFC_PIN_GROUP(vin3_field),
3830 SH_PFC_PIN_GROUP(vin3_clkenb),
3831 SH_PFC_PIN_GROUP(vin3_clk),
1627769b
LP		 3832};
3833
fcec5b22
KM		 3834static const char * const audio_clk_groups[] = {
3835 "audio_clk_a",
3836 "audio_clk_b",
3837 "audio_clk_c",
3838 "audio_clkout",
3839 "audio_clkout_b",
3840 "audio_clkout_c",
3841 "audio_clkout_d",
3842};
3843
62783b71
LP		 3844static const char * const du_groups[] = {
3845 "du_rgb666",
3846 "du_rgb888",
3847 "du_clk_out_0",
3848 "du_clk_out_1",
3849 "du_sync_0",
3850 "du_sync_1",
3851 "du_cde",
3852};
3853
3854static const char * const du0_groups[] = {
3855 "du0_clk_in",
3856};
3857
3858static const char * const du1_groups[] = {
3859 "du1_clk_in",
3860};
3861
3862static const char * const du2_groups[] = {
3863 "du2_clk_in",
3864};
3865
1627769b
LP		 3866static const char * const eth_groups[] = {
3867 "eth_link",
3868 "eth_magic",
3869 "eth_mdio",
3870 "eth_rmii",
3871};
3872
457c11d3
LP		 3873static const char * const hscif0_groups[] = {
3874 "hscif0_data",
3875 "hscif0_clk",
3876 "hscif0_ctrl",
3877 "hscif0_data_b",
3878 "hscif0_ctrl_b",
3879 "hscif0_data_c",
3880 "hscif0_ctrl_c",
3881 "hscif0_data_d",
3882 "hscif0_ctrl_d",
3883 "hscif0_data_e",
3884 "hscif0_ctrl_e",
3885 "hscif0_data_f",
3886 "hscif0_ctrl_f",
3887};
3888
3889static const char * const hscif1_groups[] = {
3890 "hscif1_data",
3891 "hscif1_clk",
3892 "hscif1_ctrl",
3893 "hscif1_data_b",
3894 "hscif1_clk_b",
3895 "hscif1_ctrl_b",
3896};
3897
70702bfc
UH		 3898static const char * const i2c1_groups[] = {
3899 "i2c1",
3900 "i2c1_b",
3901 "i2c1_c",
3902};
3903
3904static const char * const i2c2_groups[] = {
3905 "i2c2",
3906 "i2c2_b",
3907 "i2c2_c",
3908 "i2c2_d",
3909 "i2c2_e",
3910};
3911
f6aaaac9
GL		 3912static const char * const i2c3_groups[] = {
3913 "i2c3",
3914};
3915
04e7ce78
LP		 3916static const char * const intc_groups[] = {
3917 "intc_irq0",
3918 "intc_irq1",
3919 "intc_irq2",
3920 "intc_irq3",
3921};
45c6c85d 3922
457c11d3
LP		 3923static const char * const mmc0_groups[] = {
3924 "mmc0_data1",
3925 "mmc0_data4",
3926 "mmc0_data8",
3927 "mmc0_ctrl",
3928};
3929
3930static const char * const mmc1_groups[] = {
3931 "mmc1_data1",
3932 "mmc1_data4",
3933 "mmc1_data8",
3934 "mmc1_ctrl",
3935};
3936
4f47cc5e
KH		 3937static const char * const msiof0_groups[] = {
3938 "msiof0_clk",
3939 "msiof0_sync",
3940 "msiof0_ss1",
3941 "msiof0_ss2",
3942 "msiof0_rx",
3943 "msiof0_tx",
3944};
3945
3946static const char * const msiof1_groups[] = {
3947 "msiof1_clk",
3948 "msiof1_sync",
3949 "msiof1_ss1",
3950 "msiof1_ss2",
3951 "msiof1_rx",
3952 "msiof1_tx",
3953};
3954
3955static const char * const msiof2_groups[] = {
3956 "msiof2_clk",
3957 "msiof2_sync",
3958 "msiof2_ss1",
3959 "msiof2_ss2",
3960 "msiof2_rx",
3961 "msiof2_tx",
3962};
3963
3964static const char * const msiof3_groups[] = {
3965 "msiof3_clk",
3966 "msiof3_sync",
3967 "msiof3_ss1",
3968 "msiof3_ss2",
3969 "msiof3_rx",
3970 "msiof3_tx",
3971};
3972
45c6c85d
LP		 3973static const char * const scif0_groups[] = {
3974 "scif0_data",
3975 "scif0_clk",
3976 "scif0_ctrl",
3977 "scif0_data_b",
3978};
3979
3980static const char * const scif1_groups[] = {
3981 "scif1_data",
3982 "scif1_clk",
3983 "scif1_ctrl",
3984 "scif1_data_b",
3985 "scif1_data_c",
3986 "scif1_data_d",
3987 "scif1_clk_d",
3988 "scif1_data_e",
3989 "scif1_clk_e",
3990};
3991
2dbe7f2c
LP		 3992static const char * const scif2_groups[] = {
3993 "scif2_data",
3994 "scif2_clk",
3995 "scif2_data_b",
fbd0ca3d
UH		 3996};
3997
45c6c85d
LP		 3998static const char * const scifa0_groups[] = {
3999 "scifa0_data",
4000 "scifa0_clk",
4001 "scifa0_ctrl",
4002 "scifa0_data_b",
4003 "scifa0_clk_b",
4004 "scifa0_ctrl_b",
4005};
4006
4007static const char * const scifa1_groups[] = {
4008 "scifa1_data",
4009 "scifa1_clk",
4010 "scifa1_ctrl",
4011 "scifa1_data_b",
4012 "scifa1_clk_b",
4013 "scifa1_ctrl_b",
4014 "scifa1_data_c",
4015 "scifa1_clk_c",
4016 "scifa1_ctrl_c",
4017 "scifa1_data_d",
4018 "scifa1_clk_d",
4019 "scifa1_ctrl_d",
4020};
4021
4022static const char * const scifa2_groups[] = {
4023 "scifa2_data",
4024 "scifa2_clk",
4025 "scifa2_ctrl",
4026 "scifa2_data_b",
4027 "scifa2_data_c",
4028 "scifa2_clk_c",
4029};
4030
4031static const char * const scifb0_groups[] = {
4032 "scifb0_data",
4033 "scifb0_clk",
4034 "scifb0_ctrl",
4035 "scifb0_data_b",
4036 "scifb0_clk_b",
4037 "scifb0_ctrl_b",
4038 "scifb0_data_c",
4039};
4040
4041static const char * const scifb1_groups[] = {
4042 "scifb1_data",
4043 "scifb1_clk",
4044 "scifb1_ctrl",
4045 "scifb1_data_b",
4046 "scifb1_clk_b",
4047 "scifb1_ctrl_b",
4048 "scifb1_data_c",
4049 "scifb1_data_d",
4050 "scifb1_data_e",
4051 "scifb1_clk_e",
4052 "scifb1_data_f",
4053 "scifb1_data_g",
4054 "scifb1_clk_g",
4055};
4056
4057static const char * const scifb2_groups[] = {
4058 "scifb2_data",
4059 "scifb2_clk",
4060 "scifb2_ctrl",
4061 "scifb2_data_b",
4062 "scifb2_clk_b",
4063 "scifb2_ctrl_b",
4064 "scifb2_data_c",
4065};
4066
066f0d6e
GL		 4067static const char * const sdhi0_groups[] = {
4068 "sdhi0_data1",
4069 "sdhi0_data4",
4070 "sdhi0_ctrl",
4071 "sdhi0_cd",
4072 "sdhi0_wp",
4073};
4074
4075static const char * const sdhi1_groups[] = {
4076 "sdhi1_data1",
4077 "sdhi1_data4",
4078 "sdhi1_ctrl",
4079 "sdhi1_cd",
4080 "sdhi1_wp",
4081};
4082
4083static const char * const sdhi2_groups[] = {
4084 "sdhi2_data1",
4085 "sdhi2_data4",
4086 "sdhi2_ctrl",
4087 "sdhi2_cd",
4088 "sdhi2_wp",
4089};
4090
4091static const char * const sdhi3_groups[] = {
4092 "sdhi3_data1",
4093 "sdhi3_data4",
4094 "sdhi3_ctrl",
4095 "sdhi3_cd",
4096 "sdhi3_wp",
4097};
4098
1d7b59a0
KM		 4099static const char * const ssi_groups[] = {
4100 "ssi0_data",
4101 "ssi0129_ctrl",
4102 "ssi1_data",
4103 "ssi1_ctrl",
4104 "ssi2_data",
4105 "ssi2_ctrl",
4106 "ssi3_data",
4107 "ssi34_ctrl",
4108 "ssi4_data",
4109 "ssi4_ctrl",
4110 "ssi5",
4111 "ssi5_b",
4112 "ssi5_c",
4113 "ssi6",
4114 "ssi6_b",
4115 "ssi7_data",
4116 "ssi7_b_data",
4117 "ssi7_c_data",
4118 "ssi78_ctrl",
4119 "ssi78_b_ctrl",
4120 "ssi78_c_ctrl",
4121 "ssi8_data",
4122 "ssi8_b_data",
4123 "ssi8_c_data",
4124 "ssi9_data",
4125 "ssi9_ctrl",
4126};
4127
457c11d3
LP		 4128static const char * const tpu0_groups[] = {
4129 "tpu0_to0",
4130 "tpu0_to1",
4131 "tpu0_to2",
4132 "tpu0_to3",
4133};
4134
dac896e2
SU		 4135static const char * const usb0_groups[] = {
4136 "usb0",
4137};
4138
4139static const char * const usb1_groups[] = {
4140 "usb1",
4141};
4142
4143static const char * const usb2_groups[] = {
4144 "usb2",
4145};
4146
e120cacf 4147static const char * const vin0_groups[] = {
64fe8abc
VB		 4148 "vin0_data24",
4149 "vin0_data20",
4150 "vin0_data18",
4151 "vin0_data16",
4152 "vin0_data12",
4153 "vin0_data10",
4154 "vin0_data8",
4155 "vin0_data4",
a9e4c7bb 4156 "vin0_sync",
7a57be87
VB		 4157 "vin0_field",
4158 "vin0_clkenb",
e120cacf
SU		 4159 "vin0_clk",
4160};
4161
4162static const char * const vin1_groups[] = {
317a03a9
VB		 4163 "vin1_data24",
4164 "vin1_data20",
4165 "vin1_data18",
4166 "vin1_data16",
4167 "vin1_data12",
4168 "vin1_data10",
4169 "vin1_data8",
4170 "vin1_data4",
4171 "vin1_sync",
4172 "vin1_field",
4173 "vin1_clkenb",
e120cacf
SU		 4174 "vin1_clk",
4175};
4176
054d4259
VB		 4177static const char * const vin2_groups[] = {
4178 "vin2_data24",
4179 "vin2_data18",
4180 "vin2_data16",
4181 "vin2_data8",
4182 "vin2_data4",
4183 "vin2_sync",
4184 "vin2_field",
4185 "vin2_clkenb",
4186 "vin2_clk",
4187};
4188
4189static const char * const vin3_groups[] = {
4190 "vin3_data8",
4191 "vin3_sync",
4192 "vin3_field",
4193 "vin3_clkenb",
4194 "vin3_clk",
4195};
4196
1627769b 4197static const struct sh_pfc_function pinmux_functions[] = {
fcec5b22 4198 SH_PFC_FUNCTION(audio_clk),
62783b71
LP		 4199 SH_PFC_FUNCTION(du),
4200 SH_PFC_FUNCTION(du0),
4201 SH_PFC_FUNCTION(du1),
4202 SH_PFC_FUNCTION(du2),
1627769b 4203 SH_PFC_FUNCTION(eth),
fbd0ca3d
UH		 4204 SH_PFC_FUNCTION(hscif0),
4205 SH_PFC_FUNCTION(hscif1),
70702bfc
UH		 4206 SH_PFC_FUNCTION(i2c1),
4207 SH_PFC_FUNCTION(i2c2),
f6aaaac9 4208 SH_PFC_FUNCTION(i2c3),
04e7ce78 4209 SH_PFC_FUNCTION(intc),
fbd0ca3d
UH		 4210 SH_PFC_FUNCTION(mmc0),
4211 SH_PFC_FUNCTION(mmc1),
4f47cc5e
KH		 4212 SH_PFC_FUNCTION(msiof0),
4213 SH_PFC_FUNCTION(msiof1),
4214 SH_PFC_FUNCTION(msiof2),
4215 SH_PFC_FUNCTION(msiof3),
45c6c85d
LP		 4216 SH_PFC_FUNCTION(scif0),
4217 SH_PFC_FUNCTION(scif1),
2dbe7f2c 4218 SH_PFC_FUNCTION(scif2),
45c6c85d
LP		 4219 SH_PFC_FUNCTION(scifa0),
4220 SH_PFC_FUNCTION(scifa1),
4221 SH_PFC_FUNCTION(scifa2),
4222 SH_PFC_FUNCTION(scifb0),
4223 SH_PFC_FUNCTION(scifb1),
4224 SH_PFC_FUNCTION(scifb2),
066f0d6e
GL		 4225 SH_PFC_FUNCTION(sdhi0),
4226 SH_PFC_FUNCTION(sdhi1),
4227 SH_PFC_FUNCTION(sdhi2),
4228 SH_PFC_FUNCTION(sdhi3),
1d7b59a0 4229 SH_PFC_FUNCTION(ssi),
fbd0ca3d 4230 SH_PFC_FUNCTION(tpu0),
dac896e2
SU		 4231 SH_PFC_FUNCTION(usb0),
4232 SH_PFC_FUNCTION(usb1),
4233 SH_PFC_FUNCTION(usb2),
e120cacf
SU		 4234 SH_PFC_FUNCTION(vin0),
4235 SH_PFC_FUNCTION(vin1),
054d4259
VB		 4236 SH_PFC_FUNCTION(vin2),
4237 SH_PFC_FUNCTION(vin3),
1627769b
LP		 4238};
4239
44a45b55 4240static const struct pinmux_cfg_reg pinmux_config_regs[] = {
58c229e1
KM		 4241 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4242 GP_0_31_FN, FN_IP3_17_15,
4243 GP_0_30_FN, FN_IP3_14_12,
4244 GP_0_29_FN, FN_IP3_11_8,
4245 GP_0_28_FN, FN_IP3_7_4,
4246 GP_0_27_FN, FN_IP3_3_0,
4247 GP_0_26_FN, FN_IP2_28_26,
4248 GP_0_25_FN, FN_IP2_25_22,
4249 GP_0_24_FN, FN_IP2_21_18,
4250 GP_0_23_FN, FN_IP2_17_15,
4251 GP_0_22_FN, FN_IP2_14_12,
4252 GP_0_21_FN, FN_IP2_11_9,
4253 GP_0_20_FN, FN_IP2_8_6,
4254 GP_0_19_FN, FN_IP2_5_3,
4255 GP_0_18_FN, FN_IP2_2_0,
4256 GP_0_17_FN, FN_IP1_29_28,
4257 GP_0_16_FN, FN_IP1_27_26,
4258 GP_0_15_FN, FN_IP1_25_22,
4259 GP_0_14_FN, FN_IP1_21_18,
4260 GP_0_13_FN, FN_IP1_17_15,
4261 GP_0_12_FN, FN_IP1_14_12,
4262 GP_0_11_FN, FN_IP1_11_8,
4263 GP_0_10_FN, FN_IP1_7_4,
4264 GP_0_9_FN, FN_IP1_3_0,
4265 GP_0_8_FN, FN_IP0_30_27,
4266 GP_0_7_FN, FN_IP0_26_23,
4267 GP_0_6_FN, FN_IP0_22_20,
4268 GP_0_5_FN, FN_IP0_19_16,
4269 GP_0_4_FN, FN_IP0_15_12,
4270 GP_0_3_FN, FN_IP0_11_9,
4271 GP_0_2_FN, FN_IP0_8_6,
4272 GP_0_1_FN, FN_IP0_5_3,
4273 GP_0_0_FN, FN_IP0_2_0 }
4274 },
4275 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4276 0, 0,
4277 0, 0,
4278 GP_1_29_FN, FN_IP6_13_11,
4279 GP_1_28_FN, FN_IP6_10_9,
4280 GP_1_27_FN, FN_IP6_8_6,
4281 GP_1_26_FN, FN_IP6_5_3,
4282 GP_1_25_FN, FN_IP6_2_0,
4283 GP_1_24_FN, FN_IP5_29_27,
4284 GP_1_23_FN, FN_IP5_26_24,
4285 GP_1_22_FN, FN_IP5_23_21,
4286 GP_1_21_FN, FN_IP5_20_18,
4287 GP_1_20_FN, FN_IP5_17_15,
4288 GP_1_19_FN, FN_IP5_14_13,
4289 GP_1_18_FN, FN_IP5_12_10,
4290 GP_1_17_FN, FN_IP5_9_6,
4291 GP_1_16_FN, FN_IP5_5_3,
4292 GP_1_15_FN, FN_IP5_2_0,
4293 GP_1_14_FN, FN_IP4_29_27,
4294 GP_1_13_FN, FN_IP4_26_24,
4295 GP_1_12_FN, FN_IP4_23_21,
4296 GP_1_11_FN, FN_IP4_20_18,
4297 GP_1_10_FN, FN_IP4_17_15,
4298 GP_1_9_FN, FN_IP4_14_12,
4299 GP_1_8_FN, FN_IP4_11_9,
4300 GP_1_7_FN, FN_IP4_8_6,
4301 GP_1_6_FN, FN_IP4_5_3,
4302 GP_1_5_FN, FN_IP4_2_0,
4303 GP_1_4_FN, FN_IP3_31_29,
4304 GP_1_3_FN, FN_IP3_28_26,
4305 GP_1_2_FN, FN_IP3_25_23,
4306 GP_1_1_FN, FN_IP3_22_20,
4307 GP_1_0_FN, FN_IP3_19_18, }
4308 },
4309 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4310 0, 0,
4311 0, 0,
4312 GP_2_29_FN, FN_IP7_15_13,
4313 GP_2_28_FN, FN_IP7_12_10,
4314 GP_2_27_FN, FN_IP7_9_8,
4315 GP_2_26_FN, FN_IP7_7_6,
4316 GP_2_25_FN, FN_IP7_5_3,
4317 GP_2_24_FN, FN_IP7_2_0,
4318 GP_2_23_FN, FN_IP6_31_29,
4319 GP_2_22_FN, FN_IP6_28_26,
4320 GP_2_21_FN, FN_IP6_25_23,
4321 GP_2_20_FN, FN_IP6_22_20,
4322 GP_2_19_FN, FN_IP6_19_17,
4323 GP_2_18_FN, FN_IP6_16_14,
4324 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4325 GP_2_16_FN, FN_IP8_27,
4326 GP_2_15_FN, FN_IP8_26,
4327 GP_2_14_FN, FN_IP8_25_24,
4328 GP_2_13_FN, FN_IP8_23_22,
4329 GP_2_12_FN, FN_IP8_21_20,
4330 GP_2_11_FN, FN_IP8_19_18,
4331 GP_2_10_FN, FN_IP8_17_16,
4332 GP_2_9_FN, FN_IP8_15_14,
4333 GP_2_8_FN, FN_IP8_13_12,
4334 GP_2_7_FN, FN_IP8_11_10,
4335 GP_2_6_FN, FN_IP8_9_8,
4336 GP_2_5_FN, FN_IP8_7_6,
4337 GP_2_4_FN, FN_IP8_5_4,
4338 GP_2_3_FN, FN_IP8_3_2,
4339 GP_2_2_FN, FN_IP8_1_0,
4340 GP_2_1_FN, FN_IP7_30_29,
4341 GP_2_0_FN, FN_IP7_28_27 }
4342 },
4343 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4344 GP_3_31_FN, FN_IP11_21_18,
4345 GP_3_30_FN, FN_IP11_17_15,
4346 GP_3_29_FN, FN_IP11_14_13,
4347 GP_3_28_FN, FN_IP11_12_11,
4348 GP_3_27_FN, FN_IP11_10_9,
4349 GP_3_26_FN, FN_IP11_8_7,
4350 GP_3_25_FN, FN_IP11_6_5,
4351 GP_3_24_FN, FN_IP11_4,
4352 GP_3_23_FN, FN_IP11_3_0,
4353 GP_3_22_FN, FN_IP10_29_26,
4354 GP_3_21_FN, FN_IP10_25_23,
4355 GP_3_20_FN, FN_IP10_22_19,
4356 GP_3_19_FN, FN_IP10_18_15,
4357 GP_3_18_FN, FN_IP10_14_11,
4358 GP_3_17_FN, FN_IP10_10_7,
4359 GP_3_16_FN, FN_IP10_6_4,
4360 GP_3_15_FN, FN_IP10_3_0,
4361 GP_3_14_FN, FN_IP9_31_28,
4362 GP_3_13_FN, FN_IP9_27_26,
4363 GP_3_12_FN, FN_IP9_25_24,
4364 GP_3_11_FN, FN_IP9_23_22,
4365 GP_3_10_FN, FN_IP9_21_20,
4366 GP_3_9_FN, FN_IP9_19_18,
4367 GP_3_8_FN, FN_IP9_17_16,
4368 GP_3_7_FN, FN_IP9_15_12,
4369 GP_3_6_FN, FN_IP9_11_8,
4370 GP_3_5_FN, FN_IP9_7_6,
4371 GP_3_4_FN, FN_IP9_5_4,
4372 GP_3_3_FN, FN_IP9_3_2,
4373 GP_3_2_FN, FN_IP9_1_0,
4374 GP_3_1_FN, FN_IP8_30_29,
4375 GP_3_0_FN, FN_IP8_28 }
4376 },
4377 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4378 GP_4_31_FN, FN_IP14_18_16,
4379 GP_4_30_FN, FN_IP14_15_12,
4380 GP_4_29_FN, FN_IP14_11_9,
4381 GP_4_28_FN, FN_IP14_8_6,
4382 GP_4_27_FN, FN_IP14_5_3,
4383 GP_4_26_FN, FN_IP14_2_0,
4384 GP_4_25_FN, FN_IP13_30_29,
4385 GP_4_24_FN, FN_IP13_28_26,
4386 GP_4_23_FN, FN_IP13_25_23,
4387 GP_4_22_FN, FN_IP13_22_19,
4388 GP_4_21_FN, FN_IP13_18_16,
4389 GP_4_20_FN, FN_IP13_15_13,
4390 GP_4_19_FN, FN_IP13_12_10,
4391 GP_4_18_FN, FN_IP13_9_7,
4392 GP_4_17_FN, FN_IP13_6_3,
4393 GP_4_16_FN, FN_IP13_2_0,
4394 GP_4_15_FN, FN_IP12_30_28,
4395 GP_4_14_FN, FN_IP12_27_25,
4396 GP_4_13_FN, FN_IP12_24_23,
4397 GP_4_12_FN, FN_IP12_22_20,
4398 GP_4_11_FN, FN_IP12_19_17,
4399 GP_4_10_FN, FN_IP12_16_14,
4400 GP_4_9_FN, FN_IP12_13_11,
4401 GP_4_8_FN, FN_IP12_10_8,
4402 GP_4_7_FN, FN_IP12_7_6,
4403 GP_4_6_FN, FN_IP12_5_4,
4404 GP_4_5_FN, FN_IP12_3_2,
4405 GP_4_4_FN, FN_IP12_1_0,
4406 GP_4_3_FN, FN_IP11_31_30,
4407 GP_4_2_FN, FN_IP11_29_27,
4408 GP_4_1_FN, FN_IP11_26_24,
4409 GP_4_0_FN, FN_IP11_23_22 }
4410 },
4411 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4412 GP_5_31_FN, FN_IP7_24_22,
4413 GP_5_30_FN, FN_IP7_21_19,
4414 GP_5_29_FN, FN_IP7_18_16,
4415 GP_5_28_FN, FN_DU_DOTCLKIN2,
4416 GP_5_27_FN, FN_IP7_26_25,
4417 GP_5_26_FN, FN_DU_DOTCLKIN0,
4418 GP_5_25_FN, FN_AVS2,
4419 GP_5_24_FN, FN_AVS1,
4420 GP_5_23_FN, FN_USB2_OVC,
4421 GP_5_22_FN, FN_USB2_PWEN,
4422 GP_5_21_FN, FN_IP16_7,
4423 GP_5_20_FN, FN_IP16_6,
4424 GP_5_19_FN, FN_USB0_OVC_VBUS,
4425 GP_5_18_FN, FN_USB0_PWEN,
4426 GP_5_17_FN, FN_IP16_5_3,
4427 GP_5_16_FN, FN_IP16_2_0,
4428 GP_5_15_FN, FN_IP15_29_28,
4429 GP_5_14_FN, FN_IP15_27_26,
4430 GP_5_13_FN, FN_IP15_25_23,
4431 GP_5_12_FN, FN_IP15_22_20,
4432 GP_5_11_FN, FN_IP15_19_18,
4433 GP_5_10_FN, FN_IP15_17_16,
4434 GP_5_9_FN, FN_IP15_15_14,
4435 GP_5_8_FN, FN_IP15_13_12,
4436 GP_5_7_FN, FN_IP15_11_9,
4437 GP_5_6_FN, FN_IP15_8_6,
4438 GP_5_5_FN, FN_IP15_5_3,
4439 GP_5_4_FN, FN_IP15_2_0,
4440 GP_5_3_FN, FN_IP14_30_28,
4441 GP_5_2_FN, FN_IP14_27_25,
4442 GP_5_1_FN, FN_IP14_24_22,
4443 GP_5_0_FN, FN_IP14_21_19 }
4444 },
4445 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4446 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4447 /* IP0_31 [1] */
4448 0, 0,
4449 /* IP0_30_27 [4] */
9f2edd41 4450 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
58c229e1
KM		 4451 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4452 0, 0, 0, 0, 0, 0, 0, 0, 0,
4453 /* IP0_26_23 [4] */
c4721249
SK		 4454 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4455 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
05bcb07b 4456 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1 4457 /* IP0_22_20 [3] */
c4721249
SK		 4458 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4459 FN_I2C2_SCL_C, 0, 0,
58c229e1
KM		 4460 /* IP0_19_16 [4] */
4461 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4462 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4463 0, 0, 0, 0, 0, 0, 0, 0, 0,
4464 /* IP0_15_12 [4] */
4465 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4466 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4467 0, 0, 0, 0, 0, 0, 0, 0, 0,
4468 /* IP0_11_9 [3] */
4469 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4470 0, 0, 0,
4471 /* IP0_8_6 [3] */
4472 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
4473 0, 0, 0,
4474 /* IP0_5_3 [3] */
4475 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
4476 0, 0, 0,
4477 /* IP0_2_0 [3] */
4478 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
4479 0, 0, 0, }
4480 },
4481 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4482 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
4483 /* IP1_31_30 [2] */
4484 0, 0, 0, 0,
4485 /* IP1_29_28 [2] */
4486 FN_A1, FN_PWM4, 0, 0,
4487 /* IP1_27_26 [2] */
4488 FN_A0, FN_PWM3, 0, 0,
4489 /* IP1_25_22 [4] */
4490 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
4491 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
4492 0, 0, 0, 0, 0, 0, 0, 0, 0,
4493 /* IP1_21_18 [4] */
4494 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
4495 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
4496 0, 0, 0, 0, 0, 0, 0, 0, 0,
4497 /* IP1_17_15 [3] */
4498 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
4499 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
4500 0, 0, 0,
4501 /* IP1_14_12 [3] */
4502 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
4503 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
4504 0, 0,
4505 /* IP1_11_8 [4] */
9f2edd41 4506 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
58c229e1
KM		 4507 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
4508 0, 0, 0, 0, 0, 0, 0, 0, 0,
4509 /* IP1_7_4 [4] */
9f2edd41 4510 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
58c229e1
KM		 4511 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
4512 0, 0, 0, 0, 0, 0, 0, 0, 0,
4513 /* IP1_3_0 [4] */
9f2edd41 4514 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
58c229e1
KM		 4515 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
4516 0, 0, 0, 0, 0, 0, 0, 0, 0, }
4517 },
4518 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4519 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
4520 /* IP2_31_29 [3] */
4521 0, 0, 0, 0, 0, 0, 0, 0,
4522 /* IP2_28_26 [3] */
4523 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
4524 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
4525 /* IP2_25_22 [4] */
4526 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
1ddb66cd 4527 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
58c229e1
KM		 4528 0, 0, 0, 0, 0, 0, 0, 0,
4529 /* IP2_21_18 [4] */
4530 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
1ddb66cd 4531 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
58c229e1
KM		 4532 0, 0, 0, 0, 0, 0, 0, 0,
4533 /* IP2_17_15 [3] */
4534 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
4535 0, 0, 0, 0,
4536 /* IP2_14_12 [3] */
4537 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
4538 /* IP2_11_9 [3] */
4539 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
4540 /* IP2_8_6 [3] */
4541 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
4542 /* IP2_5_3 [3] */
4543 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
4544 /* IP2_2_0 [3] */
4545 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
4546 },
4547 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4548 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
4549 /* IP3_31_29 [3] */
4550 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
4551 0, 0, 0,
4552 /* IP3_28_26 [3] */
4553 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
4554 0, 0, 0, 0,
4555 /* IP3_25_23 [3] */
4556 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
4557 /* IP3_22_20 [3] */
4558 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
4559 /* IP3_19_18 [2] */
4560 FN_A16, FN_ATAWR1_N, 0, 0,
4561 /* IP3_17_15 [3] */
4562 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
4563 0, 0, 0, 0,
4564 /* IP3_14_12 [3] */
4565 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
4566 0, 0, 0, 0,
4567 /* IP3_11_8 [4] */
4568 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
4569 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
4570 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
4571 /* IP3_7_4 [4] */
4572 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
4573 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
4574 0, 0, 0, 0, 0, 0, 0, 0, 0,
4575 /* IP3_3_0 [4] */
4576 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
4577 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
4578 0, 0, 0, 0, 0, 0, 0, 0, }
4579 },
4580 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4581 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4582 /* IP4_31_30 [2] */
4583 0, 0, 0, 0,
4584 /* IP4_29_27 [3] */
4585 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
4586 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
4587 /* IP4_26_24 [3] */
4588 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
4589 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
4590 /* IP4_23_21 [3] */
4591 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
4592 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
4593 /* IP4_20_18 [3] */
4594 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
4595 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
4596 /* IP4_17_15 [3] */
4597 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
4598 0, 0, 0,
4599 /* IP4_14_12 [3] */
4600 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
4601 FN_VI2_FIELD_B, 0, 0,
4602 /* IP4_11_9 [3] */
4603 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
4604 FN_VI2_CLKENB_B, 0, 0,
4605 /* IP4_8_6 [3] */
4606 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
4607 /* IP4_5_3 [3] */
4608 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
4609 /* IP4_2_0 [3] */
4610 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
4611 }
4612 },
4613 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4614 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
4615 /* IP5_31_30 [2] */
4616 0, 0, 0, 0,
4617 /* IP5_29_27 [3] */
4618 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
4619 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
4620 /* IP5_26_24 [3] */
4621 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
4622 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
4623 FN_MSIOF0_SCK_B, 0,
4624 /* IP5_23_21 [3] */
4625 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
4626 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
4627 FN_IERX_C, 0,
4628 /* IP5_20_18 [3] */
4629 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
4630 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
4631 /* IP5_17_15 [3] */
4632 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
4633 FN_INTC_IRQ4_N, 0, 0,
4634 /* IP5_14_13 [2] */
4635 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
4636 /* IP5_12_10 [3] */
4637 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
4638 0, 0,
4639 /* IP5_9_6 [4] */
4640 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
c4721249
SK		 4641 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
4642 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 4643 /* IP5_5_3 [3] */
4644 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
c4721249
SK		 4645 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
4646 FN_INTC_EN0_N, FN_I2C1_SCL,
58c229e1
KM		 4647 /* IP5_2_0 [3] */
4648 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
4649 FN_VI2_R3, 0, 0, }
4650 },
4651 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4652 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
4653 /* IP6_31_29 [3] */
9f2edd41 4654 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
58c229e1
KM		 4655 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
4656 /* IP6_28_26 [3] */
9f2edd41 4657 FN_ETH_LINK, 0, FN_HTX0_E,
58c229e1
KM		 4658 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
4659 /* IP6_25_23 [3] */
9f2edd41 4660 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
58c229e1
KM		 4661 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
4662 /* IP6_22_20 [3] */
9f2edd41 4663 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
58c229e1
KM		 4664 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
4665 /* IP6_19_17 [3] */
9f2edd41 4666 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
c4721249 4667 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
58c229e1 4668 /* IP6_16_14 [3] */
9f2edd41 4669 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
c4721249
SK		 4670 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
4671 FN_I2C2_SCL_E, 0,
58c229e1
KM		 4672 /* IP6_13_11 [3] */
4673 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
4674 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
4675 /* IP6_10_9 [2] */
4676 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
4677 /* IP6_8_6 [3] */
4678 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
4679 FN_SSI_SDATA8_C, 0, 0, 0,
4680 /* IP6_5_3 [3] */
4681 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
4682 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
4683 /* IP6_2_0 [3] */
4684 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
4685 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
4686 },
4687 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4688 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
4689 /* IP7_31 [1] */
4690 0, 0,
4691 /* IP7_30_29 [2] */
9f2edd41 4692 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
58c229e1 4693 /* IP7_28_27 [2] */
9f2edd41 4694 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
58c229e1 4695 /* IP7_26_25 [2] */
f0681209 4696 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
58c229e1
KM		 4697 /* IP7_24_22 [3] */
4698 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
4699 0, 0, 0,
4700 /* IP7_21_19 [3] */
4701 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
4702 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
4703 /* IP7_18_16 [3] */
4704 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
4705 FN_GLO_SS_C, 0, 0, 0,
4706 /* IP7_15_13 [3] */
9f2edd41 4707 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
58c229e1
KM		 4708 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
4709 /* IP7_12_10 [3] */
9f2edd41 4710 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
58c229e1
KM		 4711 FN_GLO_SCLK_C, 0, 0, 0,
4712 /* IP7_9_8 [2] */
9f2edd41 4713 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
58c229e1 4714 /* IP7_7_6 [2] */
9f2edd41 4715 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
58c229e1 4716 /* IP7_5_3 [3] */
14da999b 4717 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
58c229e1 4718 /* IP7_2_0 [3] */
9f2edd41 4719 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
58c229e1
KM		 4720 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
4721 },
4722 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4723 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
4724 2, 2, 2, 2, 2, 2, 2) {
4725 /* IP8_31 [1] */
4726 0, 0,
4727 /* IP8_30_29 [2] */
4728 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
4729 /* IP8_28 [1] */
4730 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
4731 /* IP8_27 [1] */
4732 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
4733 /* IP8_26 [1] */
4734 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
4735 /* IP8_25_24 [2] */
4736 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
9f2edd41 4737 FN_AVB_MAGIC, 0,
58c229e1
KM		 4738 /* IP8_23_22 [2] */
4739 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
4740 /* IP8_21_20 [2] */
9f2edd41 4741 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
58c229e1 4742 /* IP8_19_18 [2] */
9f2edd41 4743 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
58c229e1 4744 /* IP8_17_16 [2] */
9f2edd41 4745 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
58c229e1 4746 /* IP8_15_14 [2] */
9f2edd41 4747 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
58c229e1 4748 /* IP8_13_12 [2] */
9f2edd41 4749 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
58c229e1 4750 /* IP8_11_10 [2] */
9f2edd41 4751 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
58c229e1
KM		 4752 /* IP8_9_8 [2] */
4753 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
4754 /* IP8_7_6 [2] */
4755 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
4756 /* IP8_5_4 [2] */
4757 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
4758 /* IP8_3_2 [2] */
4759 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
4760 /* IP8_1_0 [2] */
9f2edd41 4761 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
58c229e1
KM		 4762 },
4763 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4764 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
4765 /* IP9_31_28 [4] */
4766 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
c4721249 4767 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
58c229e1
KM		 4768 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
4769 /* IP9_27_26 [2] */
9f2edd41 4770 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
58c229e1 4771 /* IP9_25_24 [2] */
9f2edd41 4772 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
58c229e1 4773 /* IP9_23_22 [2] */
9f2edd41 4774 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
58c229e1 4775 /* IP9_21_20 [2] */
9f2edd41 4776 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
58c229e1 4777 /* IP9_19_18 [2] */
9f2edd41 4778 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
58c229e1 4779 /* IP9_17_16 [2] */
9f2edd41 4780 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
58c229e1
KM		 4781 /* IP9_15_12 [4] */
4782 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
c4721249
SK		 4783 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
4784 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 4785 /* IP9_11_8 [4] */
4786 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
c4721249
SK		 4787 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
4788 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 4789 /* IP9_7_6 [2] */
4790 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
4791 /* IP9_5_4 [2] */
4792 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
4793 /* IP9_3_2 [2] */
4794 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
4795 /* IP9_1_0 [2] */
4796 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
4797 },
4798 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4799 2, 4, 3, 4, 4, 4, 4, 3, 4) {
4800 /* IP10_31_30 [2] */
4801 0, 0, 0, 0,
4802 /* IP10_29_26 [4] */
4803 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
4804 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
4805 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
4806 /* IP10_25_23 [3] */
4807 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
4808 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
4809 /* IP10_22_19 [4] */
14da999b 4810 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
58c229e1
KM		 4811 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
4812 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
4813 /* IP10_18_15 [4] */
14da999b 4814 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
58c229e1
KM		 4815 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
4816 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
4817 0, 0, 0, 0, 0, 0,
4818 /* IP10_14_11 [4] */
4819 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
4820 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
4821 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
4822 0, 0, 0, 0, 0, 0, 0,
4823 /* IP10_10_7 [4] */
4824 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
4825 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
4826 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
4827 0, 0, 0, 0, 0, 0, 0,
4828 /* IP10_6_4 [3] */
4829 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
4830 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
4831 FN_VI3_DATA0_B, 0,
4832 /* IP10_3_0 [4] */
4833 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
c4721249 4834 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
58c229e1
KM		 4835 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
4836 },
4837 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
17babad6 4838 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
58c229e1
KM		 4839 /* IP11_31_30 [2] */
4840 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
4841 /* IP11_29_27 [3] */
7d2b2854 4842 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
14da999b 4843 0, 0, 0,
58c229e1 4844 /* IP11_26_24 [3] */
c4721249 4845 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
58c229e1
KM		 4846 0, 0, 0,
4847 /* IP11_23_22 [2] */
c4721249 4848 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
58c229e1
KM		 4849 /* IP11_21_18 [4] */
4850 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
14da999b 4851 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 4852 /* IP11_17_15 [3] */
4853 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
4854 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
4855 /* IP11_14_13 [2] */
4856 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
4857 /* IP11_12_11 [2] */
4858 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
4859 /* IP11_10_9 [2] */
4860 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
4861 /* IP11_8_7 [2] */
4862 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
4863 /* IP11_6_5 [2] */
4864 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
4865 /* IP11_4 [1] */
4866 FN_SD3_CLK, FN_MMC1_CLK,
4867 /* IP11_3_0 [4] */
4868 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
4869 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
4870 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
4871 },
4872 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4873 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
4874 /* IP12_31 [1] */
4875 0, 0,
4876 /* IP12_30_28 [3] */
4877 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
4878 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
4879 FN_CAN_DEBUGOUT4, 0, 0,
4880 /* IP12_27_25 [3] */
4881 FN_SSI_SCK5, FN_SCIFB1_SCK,
4882 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
4883 FN_CAN_DEBUGOUT3, 0, 0,
4884 /* IP12_24_23 [2] */
4885 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
4886 FN_CAN_DEBUGOUT2,
4887 /* IP12_22_20 [3] */
4888 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
4889 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
4890 /* IP12_19_17 [3] */
4891 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
4892 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
4893 /* IP12_16_14 [3] */
4894 FN_SSI_SDATA3, FN_STP_ISCLK_0,
4895 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
4896 /* IP12_13_11 [3] */
4897 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
4898 FN_CAN_STEP0, 0, 0, 0,
4899 /* IP12_10_8 [3] */
4900 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
4901 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
4902 /* IP12_7_6 [2] */
4903 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
4904 /* IP12_5_4 [2] */
4905 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
4906 /* IP12_3_2 [2] */
4907 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
4908 /* IP12_1_0 [2] */
4909 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
4910 },
4911 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4912 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
4913 /* IP13_31 [1] */
4914 0, 0,
4915 /* IP13_30_29 [2] */
4916 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
4917 /* IP13_28_26 [3] */
4918 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
4919 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
4920 /* IP13_25_23 [3] */
4921 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
4922 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
4923 /* IP13_22_19 [4] */
4924 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
4925 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
14da999b 4926 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
58c229e1
KM		 4927 /* IP13_18_16 [3] */
4928 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
4929 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
4930 /* IP13_15_13 [3] */
4931 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
4932 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
4933 /* IP13_12_10 [3] */
14da999b 4934 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
58c229e1
KM		 4935 FN_CAN_DEBUGOUT8, 0, 0,
4936 /* IP13_9_7 [3] */
4937 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
4938 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
4939 /* IP13_6_3 [4] */
14da999b 4940 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
58c229e1 4941 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
14da999b 4942 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 4943 /* IP13_2_0 [3] */
4944 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
4945 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
4946 },
4947 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
4948 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
4949 /* IP14_30 [1] */
4950 0, 0,
4951 /* IP14_30_28 [3] */
bcec7475 4952 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
58c229e1
KM		 4953 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
4954 FN_HRTS0_N_C, 0,
4955 /* IP14_27_25 [3] */
4956 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
4957 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
4958 /* IP14_24_22 [3] */
4959 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
4960 FN_LCDOUT9, 0, 0, 0,
4961 /* IP14_21_19 [3] */
4962 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
4963 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
4964 /* IP14_18_16 [3] */
bcec7475 4965 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
58c229e1
KM		 4966 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
4967 /* IP14_15_12 [4] */
4968 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
c4721249 4969 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
58c229e1
KM		 4970 0, 0, 0, 0, 0, 0, 0,
4971 /* IP14_11_9 [3] */
4972 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
4973 0, 0, 0,
4974 /* IP14_8_6 [3] */
4975 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
4976 0, 0, 0,
4977 /* IP14_5_3 [3] */
4978 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
c4721249 4979 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
58c229e1
KM		 4980 /* IP14_2_0 [3] */
4981 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
4982 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
4983 FN_REMOCON, 0, }
4984 },
4985 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
4986 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
4987 /* IP15_31_30 [2] */
4988 0, 0, 0, 0,
4989 /* IP15_29_28 [2] */
4990 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
4991 /* IP15_27_26 [2] */
4992 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
4993 /* IP15_25_23 [3] */
4994 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5de880dd 4995 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
58c229e1
KM		 4996 /* IP15_22_20 [3] */
4997 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
4998 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
4999 /* IP15_19_18 [2] */
5000 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5001 /* IP15_17_16 [2] */
5002 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5003 /* IP15_15_14 [2] */
5004 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5005 /* IP15_13_12 [2] */
5006 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5007 /* IP15_11_9 [3] */
5008 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5009 0, 0, 0,
5010 /* IP15_8_6 [3] */
1ddb66cd 5011 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
c4721249 5012 FN_IIC2_SDA, FN_I2C2_SDA, 0,
58c229e1 5013 /* IP15_5_3 [3] */
1ddb66cd 5014 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
c4721249 5015 FN_IIC2_SCL, FN_I2C2_SCL, 0,
58c229e1 5016 /* IP15_2_0 [3] */
1ddb66cd 5017 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
58c229e1
KM		 5018 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
5019 },
5020 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5021 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5022 /* IP16_31_28 [4] */
5023 0, 0, 0, 0, 0, 0, 0, 0,
5024 0, 0, 0, 0, 0, 0, 0, 0,
5025 /* IP16_27_24 [4] */
5026 0, 0, 0, 0, 0, 0, 0, 0,
5027 0, 0, 0, 0, 0, 0, 0, 0,
5028 /* IP16_23_20 [4] */
5029 0, 0, 0, 0, 0, 0, 0, 0,
5030 0, 0, 0, 0, 0, 0, 0, 0,
5031 /* IP16_19_16 [4] */
5032 0, 0, 0, 0, 0, 0, 0, 0,
5033 0, 0, 0, 0, 0, 0, 0, 0,
5034 /* IP16_15_12 [4] */
5035 0, 0, 0, 0, 0, 0, 0, 0,
5036 0, 0, 0, 0, 0, 0, 0, 0,
5037 /* IP16_11_8 [4] */
5038 0, 0, 0, 0, 0, 0, 0, 0,
5039 0, 0, 0, 0, 0, 0, 0, 0,
5040 /* IP16_7 [1] */
5041 FN_USB1_OVC, FN_TCLK1_B,
5042 /* IP16_6 [1] */
5043 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5044 /* IP16_5_3 [3] */
5045 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5de880dd 5046 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
58c229e1
KM		 5047 /* IP16_2_0 [3] */
5048 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5049 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
5050 },
5051 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5052 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5053 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5054 /* SEL_SCIF1 [3] */
5055 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5056 FN_SEL_SCIF1_4, 0, 0, 0,
5057 /* SEL_SCIFB [2] */
5058 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5059 /* SEL_SCIFB2 [2] */
5060 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5061 /* SEL_SCIFB1 [3] */
5062 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5063 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5064 FN_SEL_SCIFB1_6, 0,
5065 /* SEL_SCIFA1 [2] */
5066 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5067 FN_SEL_SCIFA1_3,
5068 /* SEL_SCIF0 [1] */
5069 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5070 /* SEL_SCIFA [1] */
5071 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5072 /* SEL_SOF1 [1] */
5073 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5074 /* SEL_SSI7 [2] */
5075 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5076 /* SEL_SSI6 [1] */
5077 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5078 /* SEL_SSI5 [2] */
5079 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5080 /* SEL_VI3 [1] */
5081 FN_SEL_VI3_0, FN_SEL_VI3_1,
5082 /* SEL_VI2 [1] */
5083 FN_SEL_VI2_0, FN_SEL_VI2_1,
5084 /* SEL_VI1 [1] */
5085 FN_SEL_VI1_0, FN_SEL_VI1_1,
5086 /* SEL_VI0 [1] */
5087 FN_SEL_VI0_0, FN_SEL_VI0_1,
5088 /* SEL_TSIF1 [2] */
5089 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5090 /* RESERVED [1] */
5091 0, 0,
5092 /* SEL_LBS [1] */
5093 FN_SEL_LBS_0, FN_SEL_LBS_1,
5094 /* SEL_TSIF0 [2] */
5095 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5096 /* SEL_SOF3 [1] */
5097 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5098 /* SEL_SOF0 [1] */
5099 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
5100 },
5101 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
17babad6
GL		 5102 3, 1, 1, 1, 2, 1, 2, 1, 2,
5103 1, 1, 1, 3, 3, 2, 3, 2, 2) {
7f35184b 5104 /* RESERVED [3] */
58c229e1 5105 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5106 /* SEL_TMU1 [1] */
5107 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5108 /* SEL_HSCIF1 [1] */
5109 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5110 /* SEL_SCIFCLK [1] */
5111 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5112 /* SEL_CAN0 [2] */
5113 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5114 /* SEL_CANCLK [1] */
5115 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5116 /* SEL_SCIFA2 [2] */
5117 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5118 /* SEL_CAN1 [1] */
5119 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
7f35184b 5120 /* RESERVED [2] */
17babad6 5121 0, 0, 0, 0,
1ddb66cd
SK		 5122 /* SEL_SCIF2 [1] */
5123 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
58c229e1
KM		 5124 /* SEL_ADI [1] */
5125 FN_SEL_ADI_0, FN_SEL_ADI_1,
5126 /* SEL_SSP [1] */
5127 FN_SEL_SSP_0, FN_SEL_SSP_1,
5128 /* SEL_FM [3] */
5129 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5130 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5131 /* SEL_HSCIF0 [3] */
5132 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5133 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5134 /* SEL_GPS [2] */
5135 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
14da999b
SK		 5136 /* RESERVED [3] */
5137 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5138 /* SEL_SIM [2] */
5139 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5140 /* SEL_SSI8 [2] */
5141 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
5142 },
5143 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5144 1, 1, 2, 4, 4, 2, 2,
5145 4, 2, 3, 2, 3, 2) {
5146 /* SEL_IICDVFS [1] */
5147 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5148 /* SEL_IIC0 [1] */
5149 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
7f35184b 5150 /* RESERVED [2] */
58c229e1 5151 0, 0, 0, 0,
7f35184b 5152 /* RESERVED [4] */
58c229e1
KM		 5153 0, 0, 0, 0, 0, 0, 0, 0,
5154 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5155 /* RESERVED [4] */
58c229e1
KM		 5156 0, 0, 0, 0, 0, 0, 0, 0,
5157 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5158 /* RESERVED [2] */
58c229e1
KM		 5159 0, 0, 0, 0,
5160 /* SEL_IEB [2] */
5161 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
7f35184b 5162 /* RESERVED [4] */
58c229e1
KM		 5163 0, 0, 0, 0, 0, 0, 0, 0,
5164 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5165 /* RESERVED [2] */
58c229e1
KM		 5166 0, 0, 0, 0,
5167 /* SEL_IIC2 [3] */
5168 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5169 FN_SEL_IIC2_4, 0, 0, 0,
5170 /* SEL_IIC1 [2] */
5171 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5172 /* SEL_I2C2 [3] */
5173 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5174 FN_SEL_I2C2_4, 0, 0, 0,
5175 /* SEL_I2C1 [2] */
5176 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
5177 },
58c229e1
KM		 5178 { },
5179};
5180
5181const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5182 .name = "r8a77900_pfc",
5183 .unlock_reg = 0xe6060000, /* PMMR */
5184
58c229e1
KM		 5185 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5186
5187 .pins = pinmux_pins,
5188 .nr_pins = ARRAY_SIZE(pinmux_pins),
1627769b
LP		 5189 .groups = pinmux_groups,
5190 .nr_groups = ARRAY_SIZE(pinmux_groups),
5191 .functions = pinmux_functions,
5192 .nr_functions = ARRAY_SIZE(pinmux_functions),
58c229e1 5193
58c229e1 5194 .cfg_regs = pinmux_config_regs,
58c229e1
KM		 5195
5196 .gpio_data = pinmux_data,
5197 .gpio_data_size = ARRAY_SIZE(pinmux_data),
5198};
Linux 6.x block layer and io_uring tree(s)