Commit | Line | Data |
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58c229e1 KM |
1 | /* |
2 | * R8A7790 processor support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
5 | * Copyright (C) 2013 Magnus Damm | |
6 | * Copyright (C) 2012 Renesas Solutions Corp. | |
7 | * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; version 2 of the | |
12 | * License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | */ | |
1627769b | 23 | |
58c229e1 | 24 | #include <linux/kernel.h> |
1627769b LP |
25 | #include <linux/platform_data/gpio-rcar.h> |
26 | ||
58c229e1 KM |
27 | #include "core.h" |
28 | #include "sh_pfc.h" | |
29 | ||
ed3e2604 LP |
30 | #define CPU_ALL_PORT(fn, sfx) \ |
31 | PORT_GP_32(0, fn, sfx), \ | |
32 | PORT_GP_32(1, fn, sfx), \ | |
33 | PORT_GP_32(2, fn, sfx), \ | |
34 | PORT_GP_32(3, fn, sfx), \ | |
35 | PORT_GP_32(4, fn, sfx), \ | |
36 | PORT_GP_32(5, fn, sfx) | |
37 | ||
58c229e1 KM |
38 | enum { |
39 | PINMUX_RESERVED = 0, | |
40 | ||
41 | PINMUX_DATA_BEGIN, | |
42 | GP_ALL(DATA), | |
43 | PINMUX_DATA_END, | |
44 | ||
58c229e1 KM |
45 | PINMUX_FUNCTION_BEGIN, |
46 | GP_ALL(FN), | |
47 | ||
48 | /* GPSR0 */ | |
49 | FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, | |
50 | FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, | |
51 | FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, | |
52 | FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, | |
53 | FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, | |
54 | FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, | |
55 | FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, | |
56 | FN_IP3_14_12, FN_IP3_17_15, | |
57 | ||
58 | /* GPSR1 */ | |
59 | FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, | |
60 | FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, | |
61 | FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, | |
62 | FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, | |
63 | FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, | |
64 | FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, | |
65 | FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, | |
66 | ||
67 | /* GPSR2 */ | |
68 | FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, | |
69 | FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, | |
70 | FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, | |
71 | FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, | |
72 | FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, | |
73 | FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, | |
74 | FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, | |
75 | ||
76 | /* GPSR3 */ | |
77 | FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, | |
78 | FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, | |
79 | FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, | |
80 | FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, | |
81 | FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, | |
82 | FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, | |
83 | FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, | |
84 | ||
85 | /* GPSR4 */ | |
86 | FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, | |
87 | FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, | |
88 | FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, | |
89 | FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, | |
90 | FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, | |
91 | FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, | |
92 | FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, | |
93 | FN_IP14_15_12, FN_IP14_18_16, | |
94 | ||
95 | /* GPSR5 */ | |
96 | FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, | |
97 | FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, | |
98 | FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, | |
99 | FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, | |
100 | FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, | |
101 | FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, | |
102 | FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, | |
103 | ||
104 | /* IPSR0 */ | |
105 | FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, | |
106 | FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, | |
107 | FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, | |
108 | FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, | |
109 | FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, | |
110 | FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, | |
111 | FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, | |
112 | FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, | |
113 | FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, | |
c4721249 SK |
114 | FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
115 | FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, | |
05bcb07b | 116 | FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, |
9f2edd41 | 117 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, |
58c229e1 KM |
118 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, |
119 | ||
120 | /* IPSR1 */ | |
9f2edd41 | 121 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, |
58c229e1 | 122 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, |
9f2edd41 | 123 | FN_SCIFA1_TXD_C, FN_AVB_TXD2, |
58c229e1 | 124 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, |
9f2edd41 | 125 | FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, |
58c229e1 KM |
126 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, |
127 | FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, | |
128 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, | |
129 | FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, | |
130 | FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, | |
131 | FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, | |
132 | FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, | |
133 | FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, | |
134 | FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, | |
135 | FN_A0, FN_PWM3, FN_A1, FN_PWM4, | |
136 | ||
137 | /* IPSR2 */ | |
138 | FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, | |
139 | FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, | |
140 | FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, | |
141 | FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, | |
142 | FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, | |
143 | FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, | |
1ddb66cd | 144 | FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, |
58c229e1 | 145 | FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, |
1ddb66cd | 146 | FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, |
58c229e1 KM |
147 | FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, |
148 | FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, | |
149 | ||
150 | /* IPSR3 */ | |
151 | FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, | |
152 | FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, | |
153 | FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, | |
154 | FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, | |
155 | FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, | |
156 | FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, | |
157 | FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, | |
158 | FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, | |
159 | FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, | |
160 | FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, | |
161 | FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, | |
162 | FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, | |
163 | FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, | |
164 | ||
165 | /* IPSR4 */ | |
166 | FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, | |
167 | FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, | |
168 | FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, | |
169 | FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, | |
170 | FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, | |
171 | FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, | |
172 | FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, | |
173 | FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, | |
174 | FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, | |
175 | FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, | |
176 | FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, | |
177 | FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, | |
178 | FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, | |
179 | FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, | |
180 | FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, | |
181 | ||
182 | /* IPSR5 */ | |
183 | FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, | |
184 | FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, | |
c4721249 SK |
185 | FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, |
186 | FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, | |
58c229e1 | 187 | FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, |
c4721249 SK |
188 | FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, |
189 | FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, | |
58c229e1 KM |
190 | FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, |
191 | FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, | |
192 | FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, | |
193 | FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, | |
194 | FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, | |
195 | FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, | |
196 | FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, | |
197 | FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, | |
198 | FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, | |
199 | FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, | |
200 | FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, | |
201 | FN_SSI_WS78_B, | |
202 | ||
203 | /* IPSR6 */ | |
204 | FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, | |
205 | FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, | |
206 | FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, | |
207 | FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, | |
208 | FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, | |
209 | FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, | |
210 | FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, | |
211 | FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, | |
9f2edd41 | 212 | FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, |
c4721249 | 213 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, |
9f2edd41 | 214 | FN_I2C2_SCL_E, FN_ETH_RX_ER, |
58c229e1 | 215 | FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, |
9f2edd41 | 216 | FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, |
58c229e1 KM |
217 | FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, |
218 | FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, | |
9f2edd41 | 219 | FN_HRX0_E, FN_STP_ISSYNC_0_B, |
58c229e1 | 220 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, |
9f2edd41 | 221 | FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, |
58c229e1 | 222 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, |
9f2edd41 | 223 | FN_ETH_REF_CLK, FN_HCTS0_N_E, |
58c229e1 KM |
224 | FN_STP_IVCXO27_1_B, FN_HRX0_F, |
225 | ||
226 | /* IPSR7 */ | |
9f2edd41 | 227 | FN_ETH_MDIO, FN_HRTS0_N_E, |
58c229e1 | 228 | FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, |
14da999b | 229 | FN_HTX0_F, FN_BPFCLK_G, |
9f2edd41 SK |
230 | FN_ETH_TX_EN, FN_SIM0_CLK_C, |
231 | FN_HRTS0_N_F, FN_ETH_MAGIC, | |
232 | FN_SIM0_RST_C, FN_ETH_TXD0, | |
58c229e1 | 233 | FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, |
9f2edd41 | 234 | FN_ETH_MDC, FN_STP_ISD_1_B, |
58c229e1 KM |
235 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, |
236 | FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, | |
237 | FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, | |
238 | FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, | |
239 | FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, | |
f0681209 | 240 | FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, |
58c229e1 | 241 | FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, |
9f2edd41 | 242 | FN_ATACS00_N, FN_AVB_RXD1, |
58c229e1 | 243 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, |
58c229e1 KM |
244 | |
245 | /* IPSR8 */ | |
246 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, | |
9f2edd41 | 247 | FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, |
58c229e1 KM |
248 | FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, |
249 | FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, | |
250 | FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, | |
251 | FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, | |
9f2edd41 SK |
252 | FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, |
253 | FN_VI1_CLK, FN_AVB_RX_DV, | |
254 | FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, | |
255 | FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, | |
256 | FN_SCIFA1_RXD_D, FN_AVB_MDC, | |
58c229e1 | 257 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, |
9f2edd41 | 258 | FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, |
58c229e1 | 259 | FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, |
9f2edd41 | 260 | FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, |
58c229e1 KM |
261 | FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, |
262 | FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, | |
263 | FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, | |
264 | ||
265 | /* IPSR9 */ | |
266 | FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, | |
267 | FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, | |
268 | FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, | |
269 | FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, | |
270 | FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, | |
c4721249 SK |
271 | FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, |
272 | FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, | |
58c229e1 | 273 | FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, |
c4721249 SK |
274 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, |
275 | FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, | |
9f2edd41 SK |
276 | FN_AVB_TX_EN, FN_SD1_CMD, |
277 | FN_AVB_TX_ER, FN_SCIFB0_SCK_B, | |
278 | FN_SD1_DAT0, FN_AVB_TX_CLK, | |
58c229e1 | 279 | FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, |
9f2edd41 SK |
280 | FN_SCIFB0_TXD_B, FN_SD1_DAT2, |
281 | FN_AVB_COL, FN_SCIFB0_CTS_N_B, | |
282 | FN_SD1_DAT3, FN_AVB_RXD0, | |
58c229e1 KM |
283 | FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, |
284 | FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, | |
c4721249 | 285 | FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, |
58c229e1 KM |
286 | FN_VI3_CLK_B, |
287 | ||
288 | /* IPSR10 */ | |
289 | FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, | |
c4721249 | 290 | FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, |
58c229e1 KM |
291 | FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, |
292 | FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, | |
293 | FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, | |
294 | FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, | |
295 | FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, | |
296 | FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, | |
297 | FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, | |
298 | FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, | |
14da999b | 299 | FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, |
58c229e1 KM |
300 | FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, |
301 | FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, | |
14da999b | 302 | FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, |
58c229e1 KM |
303 | FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, |
304 | FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, | |
305 | FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, | |
306 | FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, | |
307 | FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, | |
308 | FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, | |
309 | FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, | |
310 | FN_GLO_I0_B, FN_VI3_DATA6_B, | |
311 | ||
312 | /* IPSR11 */ | |
313 | FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, | |
314 | FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, | |
315 | FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, | |
316 | FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, | |
317 | FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, | |
318 | FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, | |
319 | FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, | |
320 | FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, | |
321 | FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, | |
322 | FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, | |
14da999b SK |
323 | FN_FMIN_E, FN_FMIN_F, |
324 | FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, | |
c4721249 | 325 | FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, |
7d2b2854 | 326 | FN_I2C2_SDA_B, FN_MLB_DAT, |
58c229e1 | 327 | FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, |
14da999b | 328 | FN_SSI_SCK0129, FN_CAN_CLK_B, |
58c229e1 KM |
329 | FN_MOUT0, |
330 | ||
331 | /* IPSR12 */ | |
332 | FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, | |
333 | FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, | |
334 | FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, | |
335 | FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, | |
336 | FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, | |
337 | FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, | |
338 | FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, | |
339 | FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, | |
340 | FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, | |
341 | FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, | |
342 | FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, | |
343 | FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, | |
344 | FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, | |
345 | FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, | |
346 | FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, | |
347 | FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, | |
348 | FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, | |
349 | FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, | |
350 | FN_CAN_DEBUGOUT4, | |
351 | ||
352 | /* IPSR13 */ | |
353 | FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, | |
354 | FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, | |
14da999b | 355 | FN_SCIFB1_CTS_N, FN_BPFCLK_D, |
58c229e1 | 356 | FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, |
14da999b | 357 | FN_BPFCLK_F, FN_SSI_WS6, |
58c229e1 KM |
358 | FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, |
359 | FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, | |
14da999b | 360 | FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, |
58c229e1 KM |
361 | FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, |
362 | FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, | |
363 | FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, | |
364 | FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, | |
365 | FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, | |
366 | FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, | |
367 | FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, | |
14da999b SK |
368 | FN_BPFCLK_E, FN_SSI_SDATA7_B, |
369 | FN_FMIN_G, FN_SSI_SDATA8, | |
58c229e1 KM |
370 | FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, |
371 | FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, | |
372 | FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, | |
373 | FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, | |
374 | FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, | |
375 | ||
376 | /* IPSR14 */ | |
377 | FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, | |
378 | FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, | |
379 | FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, | |
c4721249 SK |
380 | FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, |
381 | FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, | |
58c229e1 KM |
382 | FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, |
383 | FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, | |
384 | FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, | |
c4721249 | 385 | FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, |
bcec7475 | 386 | FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, |
58c229e1 KM |
387 | FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, |
388 | FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, | |
389 | FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, | |
390 | FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, | |
391 | FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, | |
392 | FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, | |
bcec7475 | 393 | FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, |
58c229e1 KM |
394 | FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, |
395 | FN_HRTS0_N_C, | |
396 | ||
397 | /* IPSR15 */ | |
1ddb66cd | 398 | FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, |
58c229e1 | 399 | FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, |
1ddb66cd SK |
400 | FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, |
401 | FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, | |
c4721249 | 402 | FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, |
58c229e1 KM |
403 | FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, |
404 | FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, | |
405 | FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, | |
406 | FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, | |
407 | FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, | |
408 | FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, | |
409 | FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, | |
5de880dd | 410 | FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, |
58c229e1 KM |
411 | FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, |
412 | FN_DU2_DG6, FN_LCDOUT14, | |
413 | ||
414 | /* IPSR16 */ | |
415 | FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, | |
416 | FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, | |
417 | FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, | |
5de880dd | 418 | FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, |
58c229e1 KM |
419 | FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, |
420 | FN_TCLK1_B, | |
421 | ||
422 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, | |
423 | FN_SEL_SCIF1_4, | |
424 | FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, | |
425 | FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, | |
426 | FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, | |
427 | FN_SEL_SCIFB1_4, | |
428 | FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, | |
429 | FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, | |
430 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, | |
431 | FN_SEL_SCFA_0, FN_SEL_SCFA_1, | |
432 | FN_SEL_SOF1_0, FN_SEL_SOF1_1, | |
433 | FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, | |
434 | FN_SEL_SSI6_0, FN_SEL_SSI6_1, | |
435 | FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, | |
436 | FN_SEL_VI3_0, FN_SEL_VI3_1, | |
437 | FN_SEL_VI2_0, FN_SEL_VI2_1, | |
438 | FN_SEL_VI1_0, FN_SEL_VI1_1, | |
439 | FN_SEL_VI0_0, FN_SEL_VI0_1, | |
440 | FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, | |
441 | FN_SEL_LBS_0, FN_SEL_LBS_1, | |
442 | FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, | |
443 | FN_SEL_SOF3_0, FN_SEL_SOF3_1, | |
444 | FN_SEL_SOF0_0, FN_SEL_SOF0_1, | |
445 | ||
446 | FN_SEL_TMU1_0, FN_SEL_TMU1_1, | |
447 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, | |
448 | FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, | |
449 | FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, | |
450 | FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, | |
451 | FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, | |
452 | FN_SEL_CAN1_0, FN_SEL_CAN1_1, | |
1ddb66cd | 453 | FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, |
58c229e1 KM |
454 | FN_SEL_ADI_0, FN_SEL_ADI_1, |
455 | FN_SEL_SSP_0, FN_SEL_SSP_1, | |
456 | FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, | |
457 | FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, | |
458 | FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, | |
459 | FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, | |
460 | FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, | |
58c229e1 KM |
461 | FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, |
462 | FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, | |
463 | ||
464 | FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, | |
465 | FN_SEL_IIC0_0, FN_SEL_IIC0_1, | |
466 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, | |
467 | FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, | |
468 | FN_SEL_IIC2_4, | |
469 | FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, | |
470 | FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, | |
471 | FN_SEL_I2C2_4, | |
472 | FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, | |
473 | PINMUX_FUNCTION_END, | |
474 | ||
475 | PINMUX_MARK_BEGIN, | |
476 | ||
477 | VI1_DATA7_VI1_B7_MARK, | |
478 | ||
479 | USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, | |
480 | USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, | |
481 | DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, | |
482 | ||
483 | D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, | |
484 | D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, | |
485 | VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, | |
486 | VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, | |
487 | VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, | |
488 | SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, | |
489 | VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, | |
490 | SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, | |
491 | VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, | |
c4721249 SK |
492 | IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, |
493 | I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, | |
05bcb07b | 494 | VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, |
9f2edd41 | 495 | D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, |
58c229e1 KM |
496 | VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, |
497 | ||
9f2edd41 | 498 | D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, |
58c229e1 | 499 | VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, |
9f2edd41 | 500 | SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, |
58c229e1 | 501 | VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, |
9f2edd41 | 502 | SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, |
58c229e1 KM |
503 | VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, |
504 | D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, | |
505 | VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, | |
506 | D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, | |
507 | VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, | |
508 | SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, | |
509 | VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, | |
510 | D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, | |
511 | VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, | |
512 | A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, | |
513 | ||
514 | A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, | |
515 | PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, | |
516 | TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, | |
517 | A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, | |
518 | SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, | |
519 | A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, | |
1ddb66cd | 520 | VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, |
58c229e1 | 521 | A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, |
1ddb66cd | 522 | VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, |
58c229e1 KM |
523 | A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, |
524 | VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, | |
525 | ||
526 | A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, | |
527 | VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, | |
528 | A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, | |
529 | VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, | |
530 | A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, | |
531 | MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, | |
532 | VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, | |
533 | ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, | |
534 | ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, | |
535 | A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, | |
536 | AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, | |
537 | ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, | |
538 | VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, | |
539 | ||
540 | A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, | |
541 | A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, | |
542 | VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, | |
543 | VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, | |
544 | VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, | |
545 | VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, | |
546 | VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, | |
547 | VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, | |
548 | CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, | |
549 | VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, | |
550 | VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, | |
551 | MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, | |
552 | HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, | |
553 | VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, | |
554 | VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, | |
555 | ||
556 | EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, | |
557 | VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, | |
558 | EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, | |
c4721249 SK |
559 | VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, |
560 | INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, | |
58c229e1 | 561 | MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, |
c4721249 SK |
562 | VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, |
563 | I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, | |
58c229e1 KM |
564 | CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, |
565 | CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, | |
566 | VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, | |
567 | INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, | |
568 | VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, | |
569 | WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, | |
570 | VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, | |
571 | IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, | |
572 | VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, | |
573 | MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, | |
574 | VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, | |
575 | SSI_WS78_B_MARK, | |
576 | ||
577 | DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, | |
578 | VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, | |
579 | DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, | |
580 | SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, | |
581 | INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, | |
582 | DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, | |
583 | MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, | |
584 | SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, | |
9f2edd41 | 585 | ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, |
c4721249 | 586 | TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, |
9f2edd41 | 587 | I2C2_SCL_E_MARK, ETH_RX_ER_MARK, |
58c229e1 | 588 | STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, |
9f2edd41 | 589 | IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, |
58c229e1 KM |
590 | STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, |
591 | SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, | |
9f2edd41 | 592 | HRX0_E_MARK, STP_ISSYNC_0_B_MARK, |
58c229e1 | 593 | TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, |
9f2edd41 | 594 | RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, |
58c229e1 | 595 | STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, |
9f2edd41 | 596 | ETH_REF_CLK_MARK, HCTS0_N_E_MARK, |
58c229e1 KM |
597 | STP_IVCXO27_1_B_MARK, HRX0_F_MARK, |
598 | ||
9f2edd41 | 599 | ETH_MDIO_MARK, HRTS0_N_E_MARK, |
58c229e1 | 600 | SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, |
14da999b | 601 | HTX0_F_MARK, BPFCLK_G_MARK, |
9f2edd41 SK |
602 | ETH_TX_EN_MARK, SIM0_CLK_C_MARK, |
603 | HRTS0_N_F_MARK, ETH_MAGIC_MARK, | |
604 | SIM0_RST_C_MARK, ETH_TXD0_MARK, | |
58c229e1 | 605 | STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, |
9f2edd41 | 606 | ETH_MDC_MARK, STP_ISD_1_B_MARK, |
58c229e1 KM |
607 | TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, |
608 | SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, | |
609 | GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, | |
610 | STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, | |
611 | PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, | |
f0681209 | 612 | PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, |
58c229e1 | 613 | AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, |
9f2edd41 | 614 | ATACS00_N_MARK, AVB_RXD1_MARK, |
58c229e1 | 615 | VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, |
58c229e1 KM |
616 | |
617 | VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, | |
9f2edd41 | 618 | VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, |
58c229e1 KM |
619 | AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, |
620 | AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, | |
621 | AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, | |
622 | AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, | |
9f2edd41 SK |
623 | VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, |
624 | VI1_CLK_MARK, AVB_RX_DV_MARK, | |
625 | VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, | |
626 | AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, | |
627 | SCIFA1_RXD_D_MARK, AVB_MDC_MARK, | |
58c229e1 | 628 | VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, |
9f2edd41 | 629 | VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, |
58c229e1 | 630 | AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, |
9f2edd41 | 631 | AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, |
58c229e1 KM |
632 | AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, |
633 | SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, | |
634 | SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, | |
635 | ||
636 | SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, | |
637 | SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, | |
638 | SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, | |
639 | SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, | |
640 | SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, | |
c4721249 SK |
641 | GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, |
642 | I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, | |
58c229e1 | 643 | MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, |
c4721249 SK |
644 | GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, |
645 | I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, | |
9f2edd41 SK |
646 | AVB_TX_EN_MARK, SD1_CMD_MARK, |
647 | AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, | |
648 | SD1_DAT0_MARK, AVB_TX_CLK_MARK, | |
58c229e1 | 649 | SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, |
9f2edd41 SK |
650 | SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, |
651 | AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, | |
652 | SD1_DAT3_MARK, AVB_RXD0_MARK, | |
58c229e1 KM |
653 | SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, |
654 | TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, | |
c4721249 | 655 | IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, |
58c229e1 KM |
656 | VI3_CLK_B_MARK, |
657 | ||
658 | SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, | |
c4721249 | 659 | GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, |
58c229e1 KM |
660 | SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, |
661 | VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, | |
662 | VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, | |
663 | VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, | |
664 | TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, | |
665 | SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, | |
666 | VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, | |
667 | TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, | |
14da999b | 668 | SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, |
58c229e1 KM |
669 | VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, |
670 | TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, | |
14da999b | 671 | SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, |
58c229e1 KM |
672 | VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, |
673 | GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, | |
674 | MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, | |
675 | HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, | |
676 | VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, | |
677 | TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, | |
678 | VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, | |
679 | GLO_I0_B_MARK, VI3_DATA6_B_MARK, | |
680 | ||
681 | SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, | |
682 | GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, | |
683 | TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, | |
684 | SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, | |
685 | MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, | |
686 | SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, | |
687 | MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, | |
688 | SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, | |
689 | VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, | |
690 | MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, | |
14da999b SK |
691 | FMIN_E_MARK, FMIN_F_MARK, |
692 | MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, | |
c4721249 | 693 | MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, |
7d2b2854 | 694 | I2C2_SDA_B_MARK, MLB_DAT_MARK, |
58c229e1 | 695 | SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, |
14da999b | 696 | SSI_SCK0129_MARK, CAN_CLK_B_MARK, |
58c229e1 KM |
697 | MOUT0_MARK, |
698 | ||
699 | SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, | |
700 | SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, | |
701 | SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, | |
702 | SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, | |
703 | SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, | |
704 | MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, | |
705 | STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, | |
706 | CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, | |
707 | SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, | |
708 | SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, | |
709 | MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, | |
710 | SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, | |
711 | MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, | |
712 | SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, | |
713 | CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, | |
714 | IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, | |
715 | CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, | |
716 | IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, | |
717 | CAN_DEBUGOUT4_MARK, | |
718 | ||
719 | SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, | |
720 | LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, | |
14da999b | 721 | SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, |
58c229e1 | 722 | DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, |
14da999b | 723 | BPFCLK_F_MARK, SSI_WS6_MARK, |
58c229e1 KM |
724 | SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, |
725 | LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, | |
14da999b | 726 | FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, |
58c229e1 KM |
727 | CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, |
728 | SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, | |
729 | CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, | |
730 | SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, | |
731 | LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, | |
732 | STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, | |
733 | TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, | |
14da999b SK |
734 | BPFCLK_E_MARK, SSI_SDATA7_B_MARK, |
735 | FMIN_G_MARK, SSI_SDATA8_MARK, | |
58c229e1 KM |
736 | STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, |
737 | CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, | |
738 | STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, | |
739 | SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, | |
740 | SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, | |
741 | ||
742 | AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, | |
743 | DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, | |
744 | REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, | |
c4721249 SK |
745 | MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, |
746 | I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, | |
58c229e1 KM |
747 | DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, |
748 | TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, | |
749 | HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, | |
c4721249 | 750 | LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, |
bcec7475 | 751 | SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, |
58c229e1 KM |
752 | MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, |
753 | SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, | |
754 | DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, | |
755 | SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, | |
756 | LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, | |
757 | CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, | |
bcec7475 | 758 | SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, |
58c229e1 KM |
759 | MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, |
760 | HRTS0_N_C_MARK, | |
761 | ||
1ddb66cd | 762 | SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, |
58c229e1 | 763 | LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, |
1ddb66cd SK |
764 | TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, |
765 | SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, | |
c4721249 | 766 | IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, |
58c229e1 KM |
767 | DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, |
768 | DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, | |
769 | LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, | |
770 | LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, | |
771 | LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, | |
772 | DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, | |
773 | SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, | |
5de880dd | 774 | HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, |
58c229e1 KM |
775 | DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, |
776 | DU2_DG6_MARK, LCDOUT14_MARK, | |
777 | ||
778 | MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, | |
779 | DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, | |
780 | MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, | |
5de880dd | 781 | ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, |
58c229e1 KM |
782 | USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, |
783 | TCLK1_B_MARK, | |
784 | PINMUX_MARK_END, | |
785 | }; | |
786 | ||
533743dc | 787 | static const u16 pinmux_data[] = { |
58c229e1 KM |
788 | PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ |
789 | ||
790 | PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), | |
791 | PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), | |
792 | PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), | |
793 | PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), | |
794 | PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), | |
795 | PINMUX_DATA(AVS1_MARK, FN_AVS1), | |
796 | PINMUX_DATA(AVS2_MARK, FN_AVS2), | |
797 | PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), | |
798 | PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), | |
799 | ||
800 | PINMUX_IPSR_DATA(IP0_2_0, D0), | |
801 | PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), | |
802 | PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), | |
803 | PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), | |
804 | PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), | |
805 | PINMUX_IPSR_DATA(IP0_5_3, D1), | |
806 | PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), | |
807 | PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), | |
808 | PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), | |
809 | PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), | |
810 | PINMUX_IPSR_DATA(IP0_8_6, D2), | |
811 | PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), | |
812 | PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), | |
813 | PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), | |
814 | PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), | |
815 | PINMUX_IPSR_DATA(IP0_11_9, D3), | |
816 | PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), | |
817 | PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), | |
818 | PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), | |
819 | PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), | |
820 | PINMUX_IPSR_DATA(IP0_15_12, D4), | |
821 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), | |
822 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), | |
823 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), | |
824 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), | |
825 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), | |
826 | PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), | |
827 | PINMUX_IPSR_DATA(IP0_19_16, D5), | |
828 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), | |
829 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), | |
830 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), | |
831 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), | |
832 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), | |
833 | PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), | |
834 | PINMUX_IPSR_DATA(IP0_22_20, D6), | |
c4721249 | 835 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), |
58c229e1 KM |
836 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), |
837 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), | |
838 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), | |
c4721249 | 839 | PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), |
58c229e1 KM |
840 | PINMUX_IPSR_DATA(IP0_26_23, D7), |
841 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), | |
c4721249 | 842 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), |
58c229e1 KM |
843 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), |
844 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), | |
845 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), | |
c4721249 | 846 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), |
05bcb07b | 847 | PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0), |
58c229e1 KM |
848 | PINMUX_IPSR_DATA(IP0_30_27, D8), |
849 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), | |
850 | PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), | |
58c229e1 KM |
851 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), |
852 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), | |
853 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), | |
854 | ||
855 | PINMUX_IPSR_DATA(IP1_3_0, D9), | |
856 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), | |
857 | PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), | |
58c229e1 KM |
858 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), |
859 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), | |
860 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), | |
861 | PINMUX_IPSR_DATA(IP1_7_4, D10), | |
862 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), | |
863 | PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), | |
58c229e1 KM |
864 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), |
865 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), | |
866 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), | |
867 | PINMUX_IPSR_DATA(IP1_11_8, D11), | |
868 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), | |
869 | PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), | |
58c229e1 KM |
870 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), |
871 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), | |
872 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), | |
873 | PINMUX_IPSR_DATA(IP1_14_12, D12), | |
874 | PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), | |
875 | PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), | |
876 | PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), | |
877 | PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), | |
878 | PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), | |
879 | PINMUX_IPSR_DATA(IP1_17_15, D13), | |
0a664e3d | 880 | PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5), |
58c229e1 KM |
881 | PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), |
882 | PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), | |
883 | PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), | |
884 | PINMUX_IPSR_DATA(IP1_21_18, D14), | |
885 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), | |
886 | PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), | |
887 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), | |
888 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), | |
889 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), | |
890 | PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), | |
891 | PINMUX_IPSR_DATA(IP1_25_22, D15), | |
892 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), | |
893 | PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), | |
894 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), | |
895 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), | |
896 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), | |
897 | PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), | |
898 | PINMUX_IPSR_DATA(IP1_27_26, A0), | |
899 | PINMUX_IPSR_DATA(IP1_27_26, PWM3), | |
900 | PINMUX_IPSR_DATA(IP1_29_28, A1), | |
901 | PINMUX_IPSR_DATA(IP1_29_28, PWM4), | |
902 | ||
903 | PINMUX_IPSR_DATA(IP2_2_0, A2), | |
904 | PINMUX_IPSR_DATA(IP2_2_0, PWM5), | |
905 | PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), | |
906 | PINMUX_IPSR_DATA(IP2_5_3, A3), | |
907 | PINMUX_IPSR_DATA(IP2_5_3, PWM6), | |
908 | PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), | |
909 | PINMUX_IPSR_DATA(IP2_8_6, A4), | |
910 | PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), | |
911 | PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), | |
912 | PINMUX_IPSR_DATA(IP2_11_9, A5), | |
913 | PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), | |
914 | PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), | |
915 | PINMUX_IPSR_DATA(IP2_14_12, A6), | |
916 | PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), | |
917 | PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), | |
918 | PINMUX_IPSR_DATA(IP2_17_15, A7), | |
919 | PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), | |
920 | PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), | |
921 | PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), | |
922 | PINMUX_IPSR_DATA(IP2_21_18, A8), | |
923 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), | |
924 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), | |
925 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), | |
926 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), | |
927 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), | |
1ddb66cd | 928 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1), |
58c229e1 KM |
929 | PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), |
930 | PINMUX_IPSR_DATA(IP2_25_22, A9), | |
931 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), | |
932 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), | |
933 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), | |
934 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), | |
935 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), | |
1ddb66cd | 936 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1), |
58c229e1 KM |
937 | PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), |
938 | PINMUX_IPSR_DATA(IP2_28_26, A10), | |
939 | PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), | |
940 | PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), | |
941 | PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), | |
942 | PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), | |
943 | PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), | |
944 | ||
945 | PINMUX_IPSR_DATA(IP3_3_0, A11), | |
946 | PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), | |
947 | PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), | |
948 | PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), | |
949 | PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), | |
950 | PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), | |
0a664e3d | 951 | PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), |
58c229e1 KM |
952 | PINMUX_IPSR_DATA(IP3_7_4, A12), |
953 | PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), | |
954 | PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), | |
955 | PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), | |
956 | PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), | |
957 | PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), | |
0a664e3d | 958 | PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), |
58c229e1 KM |
959 | PINMUX_IPSR_DATA(IP3_11_8, A13), |
960 | PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), | |
961 | PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), | |
962 | PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), | |
963 | PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), | |
964 | PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), | |
965 | PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), | |
0a664e3d | 966 | PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), |
58c229e1 KM |
967 | PINMUX_IPSR_DATA(IP3_14_12, A14), |
968 | PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), | |
969 | PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), | |
970 | PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), | |
971 | PINMUX_IPSR_DATA(IP3_17_15, A15), | |
972 | PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), | |
973 | PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), | |
974 | PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), | |
975 | PINMUX_IPSR_DATA(IP3_19_18, A16), | |
976 | PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), | |
977 | PINMUX_IPSR_DATA(IP3_22_20, A17), | |
978 | PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), | |
979 | PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), | |
980 | PINMUX_IPSR_DATA(IP3_25_23, A18), | |
981 | PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), | |
982 | PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), | |
983 | PINMUX_IPSR_DATA(IP3_28_26, A19), | |
984 | PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), | |
985 | PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), | |
986 | PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), | |
987 | PINMUX_IPSR_DATA(IP3_31_29, A20), | |
988 | PINMUX_IPSR_DATA(IP3_31_29, SPCLK), | |
989 | PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), | |
990 | PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), | |
991 | PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), | |
992 | ||
993 | PINMUX_IPSR_DATA(IP4_2_0, A21), | |
994 | PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), | |
995 | PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), | |
996 | PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), | |
997 | PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), | |
998 | PINMUX_IPSR_DATA(IP4_5_3, A22), | |
999 | PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), | |
1000 | PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), | |
1001 | PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), | |
1002 | PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), | |
1003 | PINMUX_IPSR_DATA(IP4_8_6, A23), | |
1004 | PINMUX_IPSR_DATA(IP4_8_6, IO2), | |
1005 | PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), | |
1006 | PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), | |
1007 | PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), | |
1008 | PINMUX_IPSR_DATA(IP4_11_9, A24), | |
1009 | PINMUX_IPSR_DATA(IP4_11_9, IO3), | |
1010 | PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), | |
1011 | PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), | |
1012 | PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), | |
1013 | PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), | |
1014 | PINMUX_IPSR_DATA(IP4_14_12, A25), | |
1015 | PINMUX_IPSR_DATA(IP4_14_12, SSL), | |
1016 | PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), | |
1017 | PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), | |
1018 | PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), | |
1019 | PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), | |
1020 | PINMUX_IPSR_DATA(IP4_17_15, CS0_N), | |
1021 | PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), | |
1022 | PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), | |
1023 | PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), | |
1024 | PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), | |
1025 | PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), | |
1026 | PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), | |
1027 | PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), | |
1028 | PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), | |
1029 | PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), | |
1030 | PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), | |
1031 | PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), | |
1032 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), | |
1033 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), | |
1034 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), | |
1035 | PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), | |
1036 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), | |
1037 | PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), | |
1038 | PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), | |
1039 | PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), | |
1040 | PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), | |
1041 | PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), | |
1042 | PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), | |
1043 | PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), | |
1044 | PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), | |
1045 | PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), | |
1046 | PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), | |
1047 | PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), | |
1048 | PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), | |
1049 | PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), | |
1050 | PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), | |
1051 | ||
1052 | PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), | |
1053 | PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), | |
1054 | PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), | |
1055 | PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), | |
1056 | PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), | |
1057 | PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), | |
0a664e3d | 1058 | PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N), |
58c229e1 KM |
1059 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), |
1060 | PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), | |
1061 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), | |
c4721249 | 1062 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0), |
58c229e1 KM |
1063 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), |
1064 | PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), | |
c4721249 | 1065 | PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0), |
58c229e1 KM |
1066 | PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), |
1067 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), | |
1068 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), | |
1069 | PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), | |
1070 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), | |
1071 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), | |
1072 | PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), | |
c4721249 | 1073 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0), |
58c229e1 | 1074 | PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), |
c4721249 | 1075 | PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0), |
58c229e1 KM |
1076 | PINMUX_IPSR_DATA(IP5_12_10, BS_N), |
1077 | PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), | |
1078 | PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), | |
1079 | PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), | |
1080 | PINMUX_IPSR_DATA(IP5_12_10, DRACK0), | |
1081 | PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), | |
1082 | PINMUX_IPSR_DATA(IP5_14_13, RD_N), | |
1083 | PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), | |
1084 | PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), | |
1085 | PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), | |
1086 | PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), | |
1087 | PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), | |
1088 | PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), | |
1089 | PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), | |
1090 | PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), | |
1091 | PINMUX_IPSR_DATA(IP5_20_18, WE0_N), | |
1092 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), | |
1093 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), | |
1094 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), | |
1095 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), | |
1096 | PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), | |
1097 | PINMUX_IPSR_DATA(IP5_23_21, WE1_N), | |
1098 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), | |
1099 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), | |
1100 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), | |
1101 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), | |
1102 | PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), | |
1103 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), | |
1104 | PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), | |
0a664e3d | 1105 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0), |
58c229e1 KM |
1106 | PINMUX_IPSR_DATA(IP5_26_24, IRQ3), |
1107 | PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), | |
1108 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), | |
1109 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), | |
1110 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), | |
1111 | PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), | |
1112 | PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), | |
1113 | PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), | |
1114 | PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), | |
1115 | PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), | |
1116 | PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), | |
1117 | PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), | |
1118 | ||
1119 | PINMUX_IPSR_DATA(IP6_2_0, DACK0), | |
1120 | PINMUX_IPSR_DATA(IP6_2_0, IRQ0), | |
1121 | PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), | |
1122 | PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), | |
1123 | PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), | |
1124 | PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), | |
1125 | PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), | |
1126 | PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), | |
1127 | PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), | |
1128 | PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), | |
1129 | PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), | |
1130 | PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), | |
1131 | PINMUX_IPSR_DATA(IP6_8_6, DACK1), | |
1132 | PINMUX_IPSR_DATA(IP6_8_6, IRQ1), | |
1133 | PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), | |
1134 | PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), | |
1135 | PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), | |
1136 | PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), | |
1137 | PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), | |
1138 | PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), | |
1139 | PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), | |
1140 | PINMUX_IPSR_DATA(IP6_13_11, DACK2), | |
1141 | PINMUX_IPSR_DATA(IP6_13_11, IRQ2), | |
1142 | PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), | |
1143 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), | |
1144 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), | |
1145 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), | |
1146 | PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), | |
58c229e1 KM |
1147 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), |
1148 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), | |
1149 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), | |
c4721249 SK |
1150 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), |
1151 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), | |
58c229e1 | 1152 | PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), |
58c229e1 KM |
1153 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), |
1154 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), | |
1155 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), | |
c4721249 SK |
1156 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), |
1157 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), | |
58c229e1 | 1158 | PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), |
58c229e1 KM |
1159 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), |
1160 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), | |
1161 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), | |
1162 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), | |
1163 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), | |
1164 | PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), | |
58c229e1 KM |
1165 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), |
1166 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), | |
1167 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), | |
1168 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), | |
1169 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), | |
1170 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), | |
1171 | PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), | |
58c229e1 KM |
1172 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), |
1173 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), | |
1174 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), | |
1175 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), | |
1176 | PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), | |
58c229e1 KM |
1177 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), |
1178 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), | |
1179 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), | |
1180 | ||
1181 | PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), | |
58c229e1 KM |
1182 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), |
1183 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), | |
1184 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), | |
1185 | PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), | |
0a664e3d SK |
1186 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5), |
1187 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6), | |
58c229e1 | 1188 | PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), |
58c229e1 KM |
1189 | PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), |
1190 | PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), | |
1191 | PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), | |
58c229e1 KM |
1192 | PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), |
1193 | PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), | |
58c229e1 KM |
1194 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), |
1195 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), | |
1196 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), | |
1197 | PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), | |
58c229e1 KM |
1198 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), |
1199 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), | |
1200 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), | |
1201 | PINMUX_IPSR_DATA(IP7_18_16, PWM0), | |
1202 | PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), | |
1203 | PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), | |
1204 | PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), | |
1205 | PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), | |
1206 | PINMUX_IPSR_DATA(IP7_21_19, PWM1), | |
1207 | PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), | |
1208 | PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), | |
1209 | PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), | |
1210 | PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), | |
1211 | PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), | |
1212 | PINMUX_IPSR_DATA(IP7_24_22, PWM2), | |
1213 | PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), | |
1214 | PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), | |
1215 | PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), | |
1216 | PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), | |
f0681209 | 1217 | PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1), |
58c229e1 KM |
1218 | PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), |
1219 | PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), | |
1220 | PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), | |
1221 | PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), | |
1222 | PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), | |
58c229e1 KM |
1223 | PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), |
1224 | PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), | |
1225 | PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), | |
58c229e1 KM |
1226 | |
1227 | PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), | |
1228 | PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), | |
1229 | PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), | |
58c229e1 KM |
1230 | PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), |
1231 | PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), | |
1232 | PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), | |
1233 | PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), | |
1234 | PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), | |
1235 | PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), | |
1236 | PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), | |
1237 | PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), | |
1238 | PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), | |
1239 | PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), | |
1240 | PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), | |
1241 | PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), | |
1242 | PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), | |
1243 | PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), | |
58c229e1 KM |
1244 | PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), |
1245 | PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), | |
58c229e1 KM |
1246 | PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), |
1247 | PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), | |
58c229e1 KM |
1248 | PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), |
1249 | PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), | |
1250 | PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), | |
58c229e1 KM |
1251 | PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), |
1252 | PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), | |
1253 | PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), | |
58c229e1 KM |
1254 | PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), |
1255 | PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), | |
1256 | PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), | |
58c229e1 KM |
1257 | PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), |
1258 | PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), | |
1259 | PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), | |
1260 | PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), | |
1261 | PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), | |
1262 | PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), | |
58c229e1 | 1263 | PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), |
0a664e3d | 1264 | PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT), |
58c229e1 KM |
1265 | PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), |
1266 | PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), | |
1267 | PINMUX_IPSR_DATA(IP8_28, SD0_CLK), | |
1268 | PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), | |
1269 | PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), | |
1270 | PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), | |
1271 | PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), | |
1272 | ||
1273 | PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), | |
1274 | PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), | |
1275 | PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), | |
1276 | PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), | |
1277 | PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), | |
1278 | PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), | |
1279 | PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), | |
1280 | PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), | |
1281 | PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), | |
1282 | PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), | |
1283 | PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), | |
1284 | PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), | |
1285 | PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), | |
1286 | PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), | |
1287 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), | |
1288 | PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), | |
1289 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), | |
1290 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), | |
c4721249 SK |
1291 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), |
1292 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), | |
58c229e1 KM |
1293 | PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), |
1294 | PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), | |
1295 | PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), | |
1296 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), | |
1297 | PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), | |
1298 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), | |
1299 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), | |
c4721249 SK |
1300 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), |
1301 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), | |
58c229e1 KM |
1302 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), |
1303 | PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), | |
1304 | PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), | |
58c229e1 KM |
1305 | PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), |
1306 | PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), | |
58c229e1 KM |
1307 | PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), |
1308 | PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), | |
1309 | PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), | |
58c229e1 KM |
1310 | PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), |
1311 | PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), | |
1312 | PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), | |
58c229e1 KM |
1313 | PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), |
1314 | PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), | |
1315 | PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), | |
58c229e1 KM |
1316 | PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), |
1317 | PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), | |
1318 | PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), | |
58c229e1 KM |
1319 | PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), |
1320 | PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), | |
1321 | PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), | |
1322 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), | |
1323 | PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), | |
1324 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), | |
1325 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), | |
c4721249 SK |
1326 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), |
1327 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), | |
58c229e1 KM |
1328 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), |
1329 | PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), | |
1330 | ||
1331 | PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), | |
1332 | PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), | |
1333 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), | |
1334 | PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), | |
1335 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), | |
1336 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), | |
c4721249 SK |
1337 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), |
1338 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), | |
58c229e1 KM |
1339 | PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), |
1340 | PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), | |
1341 | PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), | |
1342 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), | |
1343 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), | |
1344 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), | |
1345 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), | |
1346 | PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), | |
1347 | PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), | |
1348 | PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), | |
1349 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), | |
1350 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), | |
1351 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), | |
1352 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), | |
1353 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), | |
1354 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), | |
1355 | PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), | |
1356 | PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), | |
1357 | PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), | |
1358 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), | |
1359 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), | |
1360 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), | |
1361 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), | |
1362 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), | |
1363 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), | |
1364 | PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), | |
1365 | PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), | |
1366 | PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), | |
1367 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), | |
58c229e1 KM |
1368 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), |
1369 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), | |
1370 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), | |
1371 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), | |
1372 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), | |
1373 | PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), | |
1374 | PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), | |
1375 | PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), | |
1376 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), | |
58c229e1 KM |
1377 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), |
1378 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), | |
1379 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), | |
1380 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), | |
1381 | PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), | |
1382 | PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), | |
1383 | PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), | |
1384 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), | |
1385 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), | |
1386 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), | |
1387 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), | |
1388 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), | |
1389 | PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), | |
1390 | PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), | |
1391 | PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), | |
1392 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), | |
1393 | PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), | |
1394 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), | |
1395 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), | |
1396 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), | |
1397 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), | |
1398 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), | |
1399 | PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), | |
1400 | ||
1401 | PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), | |
1402 | PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), | |
1403 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), | |
1404 | PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), | |
1405 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), | |
1406 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), | |
1407 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), | |
1408 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), | |
1409 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), | |
1410 | PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), | |
1411 | PINMUX_IPSR_DATA(IP11_4, SD3_CLK), | |
1412 | PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), | |
1413 | PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), | |
1414 | PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), | |
1415 | PINMUX_IPSR_DATA(IP11_6_5, MTS_N), | |
1416 | PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), | |
1417 | PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), | |
1418 | PINMUX_IPSR_DATA(IP11_8_7, STM_N), | |
1419 | PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), | |
1420 | PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), | |
1421 | PINMUX_IPSR_DATA(IP11_10_9, MDATA), | |
1422 | PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), | |
1423 | PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), | |
1424 | PINMUX_IPSR_DATA(IP11_12_11, SDATA), | |
1425 | PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), | |
1426 | PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), | |
1427 | PINMUX_IPSR_DATA(IP11_14_13, SCKZ), | |
1428 | PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), | |
1429 | PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), | |
1430 | PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), | |
1431 | PINMUX_IPSR_DATA(IP11_17_15, VSP), | |
1432 | PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), | |
1433 | PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), | |
1434 | PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), | |
1435 | PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), | |
1436 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), | |
1437 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), | |
1438 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), | |
58c229e1 | 1439 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), |
58c229e1 | 1440 | PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), |
58c229e1 | 1441 | PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), |
c4721249 SK |
1442 | PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), |
1443 | PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), | |
58c229e1 KM |
1444 | PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), |
1445 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), | |
1446 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), | |
c4721249 SK |
1447 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), |
1448 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), | |
58c229e1 | 1449 | PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), |
58c229e1 KM |
1450 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), |
1451 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), | |
1452 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), | |
58c229e1 KM |
1453 | PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), |
1454 | PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), | |
1455 | PINMUX_IPSR_DATA(IP11_31_30, MOUT0), | |
1456 | ||
1457 | PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), | |
1458 | PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), | |
1459 | PINMUX_IPSR_DATA(IP12_1_0, MOUT1), | |
1460 | PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), | |
1461 | PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), | |
1462 | PINMUX_IPSR_DATA(IP12_3_2, MOUT2), | |
1463 | PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), | |
1464 | PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), | |
1465 | PINMUX_IPSR_DATA(IP12_5_4, MOUT5), | |
1466 | PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), | |
1467 | PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), | |
0a664e3d | 1468 | PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1), |
58c229e1 KM |
1469 | PINMUX_IPSR_DATA(IP12_7_6, MOUT6), |
1470 | PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), | |
1471 | PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), | |
1472 | PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), | |
1473 | PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), | |
1474 | PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), | |
1475 | PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), | |
1476 | PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), | |
1477 | PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), | |
1478 | PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), | |
1479 | PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), | |
1480 | PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), | |
1481 | PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), | |
1482 | PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), | |
1483 | PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), | |
1484 | PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), | |
1485 | PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), | |
1486 | PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), | |
1487 | PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), | |
1488 | PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), | |
1489 | PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), | |
1490 | PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), | |
1491 | PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), | |
1492 | PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), | |
1493 | PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), | |
1494 | PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), | |
1495 | PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), | |
1496 | PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), | |
1497 | PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), | |
1498 | PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), | |
1499 | PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), | |
1500 | PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), | |
1501 | PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), | |
1502 | PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), | |
1503 | PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), | |
1504 | PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), | |
1505 | PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), | |
1506 | PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), | |
1507 | PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), | |
1508 | PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), | |
1509 | PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), | |
1510 | PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), | |
1511 | PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), | |
1512 | PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), | |
1513 | ||
1514 | PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), | |
1515 | PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), | |
1516 | PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), | |
1517 | PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), | |
1518 | PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), | |
1519 | PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), | |
1520 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), | |
1521 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), | |
1522 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), | |
58c229e1 KM |
1523 | PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), |
1524 | PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), | |
1525 | PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), | |
1526 | PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), | |
58c229e1 KM |
1527 | PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), |
1528 | PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), | |
1529 | PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), | |
1530 | PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), | |
1531 | PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), | |
1532 | PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), | |
1533 | PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), | |
1534 | PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), | |
58c229e1 KM |
1535 | PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), |
1536 | PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), | |
1537 | PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), | |
1538 | PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), | |
1539 | PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), | |
1540 | PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), | |
1541 | PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), | |
1542 | PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), | |
1543 | PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), | |
1544 | PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), | |
1545 | PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), | |
1546 | PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), | |
1547 | PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), | |
1548 | PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), | |
1549 | PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), | |
1550 | PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), | |
1551 | PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), | |
1552 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), | |
1553 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), | |
1554 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), | |
1555 | PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), | |
1556 | PINMUX_IPSR_DATA(IP13_22_19, TCLK2), | |
1557 | PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), | |
1558 | PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), | |
1559 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), | |
58c229e1 KM |
1560 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), |
1561 | PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), | |
58c229e1 KM |
1562 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), |
1563 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), | |
1564 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), | |
1565 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), | |
1566 | PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), | |
1567 | PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), | |
1568 | PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), | |
1569 | PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), | |
1570 | PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), | |
1571 | PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), | |
1572 | PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), | |
1573 | PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), | |
1574 | PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), | |
1575 | PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), | |
1576 | PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), | |
1577 | ||
1578 | PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), | |
1579 | PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), | |
1580 | PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), | |
1581 | PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), | |
1582 | PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), | |
1583 | PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), | |
1584 | PINMUX_IPSR_DATA(IP14_2_0, REMOCON), | |
1585 | PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), | |
1586 | PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), | |
1587 | PINMUX_IPSR_DATA(IP14_5_3, SCK0), | |
1588 | PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), | |
1589 | PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), | |
1590 | PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), | |
c4721249 SK |
1591 | PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), |
1592 | PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), | |
58c229e1 KM |
1593 | PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), |
1594 | PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), | |
1595 | PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), | |
1596 | PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), | |
1597 | PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), | |
1598 | PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), | |
1599 | PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), | |
1600 | PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), | |
1601 | PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), | |
1602 | PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), | |
1603 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), | |
1604 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), | |
0a664e3d | 1605 | PINMUX_IPSR_DATA(IP14_15_12, CTS0_N), |
58c229e1 KM |
1606 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), |
1607 | PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), | |
0a664e3d SK |
1608 | PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11), |
1609 | PINMUX_IPSR_DATA(IP14_15_12, PWM0_B), | |
c4721249 SK |
1610 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), |
1611 | PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), | |
58c229e1 KM |
1612 | PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), |
1613 | PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), | |
bcec7475 | 1614 | PINMUX_IPSR_DATA(IP14_18_16, RTS0_N), |
58c229e1 KM |
1615 | PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), |
1616 | PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), | |
1617 | PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), | |
1618 | PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), | |
1619 | PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), | |
1620 | PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), | |
1621 | PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), | |
1622 | PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), | |
1623 | PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), | |
1624 | PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), | |
1625 | PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), | |
1626 | PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), | |
1627 | PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), | |
1628 | PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), | |
1629 | PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), | |
1630 | PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), | |
1631 | PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), | |
1632 | PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), | |
1633 | PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), | |
1634 | PINMUX_IPSR_DATA(IP14_27_25, QCLK), | |
1635 | PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), | |
1636 | PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), | |
bcec7475 | 1637 | PINMUX_IPSR_DATA(IP14_30_28, RTS1_N), |
58c229e1 KM |
1638 | PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), |
1639 | PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), | |
1640 | PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), | |
1641 | PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), | |
1642 | ||
1643 | PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), | |
1644 | PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), | |
1ddb66cd | 1645 | PINMUX_IPSR_DATA(IP15_2_0, SCK2), |
58c229e1 KM |
1646 | PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), |
1647 | PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), | |
1648 | PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), | |
0a664e3d | 1649 | PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), |
58c229e1 KM |
1650 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), |
1651 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), | |
1ddb66cd | 1652 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0), |
58c229e1 KM |
1653 | PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), |
1654 | PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), | |
c4721249 SK |
1655 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), |
1656 | PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), | |
58c229e1 KM |
1657 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), |
1658 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), | |
1ddb66cd | 1659 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0), |
58c229e1 KM |
1660 | PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), |
1661 | PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), | |
c4721249 SK |
1662 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), |
1663 | PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0), | |
58c229e1 KM |
1664 | PINMUX_IPSR_DATA(IP15_11_9, HSCK0), |
1665 | PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), | |
1666 | PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), | |
1667 | PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), | |
0a664e3d | 1668 | PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), |
58c229e1 KM |
1669 | PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), |
1670 | PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), | |
1671 | PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), | |
1672 | PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), | |
1673 | PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), | |
1674 | PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), | |
1675 | PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), | |
1676 | PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), | |
1677 | PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), | |
1678 | PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), | |
1679 | PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), | |
1680 | PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), | |
1681 | PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), | |
1682 | PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), | |
1683 | PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), | |
1684 | PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), | |
1685 | PINMUX_IPSR_DATA(IP15_22_20, ADICLK), | |
1686 | PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), | |
1687 | PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), | |
1688 | PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), | |
1689 | PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), | |
1690 | PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), | |
1691 | PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), | |
1692 | PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), | |
1693 | PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), | |
5de880dd | 1694 | PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1), |
58c229e1 KM |
1695 | PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), |
1696 | PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), | |
1697 | PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), | |
1698 | PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), | |
1699 | PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), | |
1700 | PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), | |
1701 | PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), | |
1702 | PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), | |
1703 | ||
1704 | PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), | |
1705 | PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), | |
1706 | PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), | |
1707 | PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), | |
1708 | PINMUX_IPSR_DATA(IP16_2_0, QPOLA), | |
1709 | PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), | |
1710 | PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), | |
1711 | PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), | |
1712 | PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), | |
1713 | PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), | |
1714 | PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), | |
1715 | PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), | |
1716 | PINMUX_IPSR_DATA(IP16_5_3, QPOLB), | |
5de880dd | 1717 | PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), |
58c229e1 KM |
1718 | PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), |
1719 | PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), | |
1720 | PINMUX_IPSR_DATA(IP16_7, USB1_OVC), | |
1721 | PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), | |
1722 | }; | |
1723 | ||
1724 | static struct sh_pfc_pin pinmux_pins[] = { | |
1725 | PINMUX_GPIO_GP_ALL(), | |
1726 | }; | |
1727 | ||
62783b71 LP |
1728 | /* - DU RGB ----------------------------------------------------------------- */ |
1729 | static const unsigned int du_rgb666_pins[] = { | |
1730 | /* R[7:2], G[7:2], B[7:2] */ | |
1731 | RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), | |
1732 | RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), | |
1733 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), | |
1734 | RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), | |
1735 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), | |
1736 | RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), | |
1737 | }; | |
1738 | static const unsigned int du_rgb666_mux[] = { | |
1739 | DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, | |
1740 | DU2_DR3_MARK, DU2_DR2_MARK, | |
1741 | DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, | |
1742 | DU2_DG3_MARK, DU2_DG2_MARK, | |
1743 | DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, | |
1744 | DU2_DB3_MARK, DU2_DB2_MARK, | |
1745 | }; | |
1746 | static const unsigned int du_rgb888_pins[] = { | |
1747 | /* R[7:0], G[7:0], B[7:0] */ | |
1748 | RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), | |
1749 | RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), | |
1750 | RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), | |
1751 | RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), | |
1752 | RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), | |
1753 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), | |
1754 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), | |
1755 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), | |
1756 | }; | |
1757 | static const unsigned int du_rgb888_mux[] = { | |
1758 | DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, | |
1759 | DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, | |
1760 | DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, | |
1761 | DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, | |
1762 | DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, | |
1763 | DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, | |
1764 | }; | |
1765 | static const unsigned int du_clk_out_0_pins[] = { | |
1766 | /* CLKOUT */ | |
1767 | RCAR_GP_PIN(5, 2), | |
1768 | }; | |
1769 | static const unsigned int du_clk_out_0_mux[] = { | |
1770 | DU0_DOTCLKOUT_MARK | |
1771 | }; | |
1772 | static const unsigned int du_clk_out_1_pins[] = { | |
1773 | /* CLKOUT */ | |
1774 | RCAR_GP_PIN(5, 3), | |
1775 | }; | |
1776 | static const unsigned int du_clk_out_1_mux[] = { | |
1777 | DU1_DOTCLKOUT_MARK | |
1778 | }; | |
1779 | static const unsigned int du_sync_0_pins[] = { | |
1780 | /* VSYNC, HSYNC, DISP */ | |
1781 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), | |
1782 | }; | |
1783 | static const unsigned int du_sync_0_mux[] = { | |
1784 | DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, | |
1785 | DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK | |
1786 | }; | |
1787 | static const unsigned int du_sync_1_pins[] = { | |
1788 | /* VSYNC, HSYNC, DISP */ | |
1789 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), | |
1790 | }; | |
1791 | static const unsigned int du_sync_1_mux[] = { | |
1792 | DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, | |
1793 | DU2_DISP_MARK | |
1794 | }; | |
1795 | static const unsigned int du_cde_pins[] = { | |
1796 | /* CDE */ | |
1797 | RCAR_GP_PIN(5, 17), | |
1798 | }; | |
1799 | static const unsigned int du_cde_mux[] = { | |
1800 | DU2_CDE_MARK, | |
1801 | }; | |
1802 | /* - DU0 -------------------------------------------------------------------- */ | |
1803 | static const unsigned int du0_clk_in_pins[] = { | |
1804 | /* CLKIN */ | |
1805 | RCAR_GP_PIN(5, 26), | |
1806 | }; | |
1807 | static const unsigned int du0_clk_in_mux[] = { | |
1808 | DU_DOTCLKIN0_MARK | |
1809 | }; | |
1810 | /* - DU1 -------------------------------------------------------------------- */ | |
1811 | static const unsigned int du1_clk_in_pins[] = { | |
1812 | /* CLKIN */ | |
1813 | RCAR_GP_PIN(5, 27), | |
1814 | }; | |
1815 | static const unsigned int du1_clk_in_mux[] = { | |
1816 | DU_DOTCLKIN1_MARK, | |
1817 | }; | |
1818 | /* - DU2 -------------------------------------------------------------------- */ | |
1819 | static const unsigned int du2_clk_in_pins[] = { | |
1820 | /* CLKIN */ | |
1821 | RCAR_GP_PIN(5, 28), | |
1822 | }; | |
1823 | static const unsigned int du2_clk_in_mux[] = { | |
1824 | DU_DOTCLKIN2_MARK, | |
1825 | }; | |
1627769b LP |
1826 | /* - ETH -------------------------------------------------------------------- */ |
1827 | static const unsigned int eth_link_pins[] = { | |
1828 | /* LINK */ | |
1829 | RCAR_GP_PIN(2, 22), | |
1830 | }; | |
1831 | static const unsigned int eth_link_mux[] = { | |
1832 | ETH_LINK_MARK, | |
1833 | }; | |
1834 | static const unsigned int eth_magic_pins[] = { | |
1835 | /* MAGIC */ | |
1836 | RCAR_GP_PIN(2, 27), | |
1837 | }; | |
1838 | static const unsigned int eth_magic_mux[] = { | |
1839 | ETH_MAGIC_MARK, | |
1840 | }; | |
1841 | static const unsigned int eth_mdio_pins[] = { | |
1842 | /* MDC, MDIO */ | |
1843 | RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), | |
1844 | }; | |
1845 | static const unsigned int eth_mdio_mux[] = { | |
1846 | ETH_MDC_MARK, ETH_MDIO_MARK, | |
1847 | }; | |
1848 | static const unsigned int eth_rmii_pins[] = { | |
1849 | /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ | |
1850 | RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), | |
1851 | RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), | |
1852 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), | |
1853 | }; | |
1854 | static const unsigned int eth_rmii_mux[] = { | |
1855 | ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, | |
1856 | ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, | |
1857 | }; | |
fbd0ca3d UH |
1858 | /* - HSCIF0 ----------------------------------------------------------------- */ |
1859 | static const unsigned int hscif0_data_pins[] = { | |
1860 | /* RX, TX */ | |
1861 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), | |
1862 | }; | |
1863 | static const unsigned int hscif0_data_mux[] = { | |
1864 | HRX0_MARK, HTX0_MARK, | |
1865 | }; | |
1866 | static const unsigned int hscif0_clk_pins[] = { | |
1867 | /* SCK */ | |
1868 | RCAR_GP_PIN(5, 7), | |
1869 | }; | |
1870 | static const unsigned int hscif0_clk_mux[] = { | |
1871 | HSCK0_MARK, | |
1872 | }; | |
1873 | static const unsigned int hscif0_ctrl_pins[] = { | |
1874 | /* RTS, CTS */ | |
1875 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), | |
1876 | }; | |
1877 | static const unsigned int hscif0_ctrl_mux[] = { | |
1878 | HRTS0_N_MARK, HCTS0_N_MARK, | |
1879 | }; | |
1880 | static const unsigned int hscif0_data_b_pins[] = { | |
1881 | /* RX, TX */ | |
1882 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), | |
1883 | }; | |
1884 | static const unsigned int hscif0_data_b_mux[] = { | |
1885 | HRX0_B_MARK, HTX0_B_MARK, | |
1886 | }; | |
1887 | static const unsigned int hscif0_ctrl_b_pins[] = { | |
1888 | /* RTS, CTS */ | |
1889 | RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), | |
1890 | }; | |
1891 | static const unsigned int hscif0_ctrl_b_mux[] = { | |
1892 | HRTS0_N_B_MARK, HCTS0_N_B_MARK, | |
1893 | }; | |
1894 | static const unsigned int hscif0_data_c_pins[] = { | |
1895 | /* RX, TX */ | |
1896 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), | |
1897 | }; | |
1898 | static const unsigned int hscif0_data_c_mux[] = { | |
1899 | HRX0_C_MARK, HTX0_C_MARK, | |
1900 | }; | |
1901 | static const unsigned int hscif0_ctrl_c_pins[] = { | |
1902 | /* RTS, CTS */ | |
1903 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), | |
1904 | }; | |
1905 | static const unsigned int hscif0_ctrl_c_mux[] = { | |
1906 | HRTS0_N_C_MARK, HCTS0_N_C_MARK, | |
1907 | }; | |
1908 | static const unsigned int hscif0_data_d_pins[] = { | |
1909 | /* RX, TX */ | |
1910 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
1911 | }; | |
1912 | static const unsigned int hscif0_data_d_mux[] = { | |
1913 | HRX0_D_MARK, HTX0_D_MARK, | |
1914 | }; | |
1915 | static const unsigned int hscif0_ctrl_d_pins[] = { | |
1916 | /* RTS, CTS */ | |
1917 | RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), | |
1918 | }; | |
1919 | static const unsigned int hscif0_ctrl_d_mux[] = { | |
1920 | HRTS0_N_D_MARK, HCTS0_N_D_MARK, | |
1921 | }; | |
1922 | static const unsigned int hscif0_data_e_pins[] = { | |
1923 | /* RX, TX */ | |
1924 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | |
1925 | }; | |
1926 | static const unsigned int hscif0_data_e_mux[] = { | |
1927 | HRX0_E_MARK, HTX0_E_MARK, | |
1928 | }; | |
1929 | static const unsigned int hscif0_ctrl_e_pins[] = { | |
1930 | /* RTS, CTS */ | |
1931 | RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), | |
1932 | }; | |
1933 | static const unsigned int hscif0_ctrl_e_mux[] = { | |
1934 | HRTS0_N_E_MARK, HCTS0_N_E_MARK, | |
1935 | }; | |
1936 | static const unsigned int hscif0_data_f_pins[] = { | |
1937 | /* RX, TX */ | |
1938 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), | |
1939 | }; | |
1940 | static const unsigned int hscif0_data_f_mux[] = { | |
1941 | HRX0_F_MARK, HTX0_F_MARK, | |
1942 | }; | |
1943 | static const unsigned int hscif0_ctrl_f_pins[] = { | |
1944 | /* RTS, CTS */ | |
1945 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), | |
1946 | }; | |
1947 | static const unsigned int hscif0_ctrl_f_mux[] = { | |
1948 | HRTS0_N_F_MARK, HCTS0_N_F_MARK, | |
1949 | }; | |
1950 | /* - HSCIF1 ----------------------------------------------------------------- */ | |
1951 | static const unsigned int hscif1_data_pins[] = { | |
1952 | /* RX, TX */ | |
1953 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | |
1954 | }; | |
1955 | static const unsigned int hscif1_data_mux[] = { | |
1956 | HRX1_MARK, HTX1_MARK, | |
1957 | }; | |
1958 | static const unsigned int hscif1_clk_pins[] = { | |
1959 | /* SCK */ | |
1960 | RCAR_GP_PIN(4, 27), | |
1961 | }; | |
1962 | static const unsigned int hscif1_clk_mux[] = { | |
1963 | HSCK1_MARK, | |
1964 | }; | |
1965 | static const unsigned int hscif1_ctrl_pins[] = { | |
1966 | /* RTS, CTS */ | |
1967 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), | |
1968 | }; | |
1969 | static const unsigned int hscif1_ctrl_mux[] = { | |
1970 | HRTS1_N_MARK, HCTS1_N_MARK, | |
1971 | }; | |
1972 | static const unsigned int hscif1_data_b_pins[] = { | |
1973 | /* RX, TX */ | |
1974 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), | |
1975 | }; | |
1976 | static const unsigned int hscif1_data_b_mux[] = { | |
1977 | HRX1_B_MARK, HTX1_B_MARK, | |
1978 | }; | |
1979 | static const unsigned int hscif1_clk_b_pins[] = { | |
1980 | /* SCK */ | |
1981 | RCAR_GP_PIN(1, 28), | |
1982 | }; | |
1983 | static const unsigned int hscif1_clk_b_mux[] = { | |
1984 | HSCK1_B_MARK, | |
1985 | }; | |
1986 | static const unsigned int hscif1_ctrl_b_pins[] = { | |
1987 | /* RTS, CTS */ | |
1988 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), | |
1989 | }; | |
1990 | static const unsigned int hscif1_ctrl_b_mux[] = { | |
1991 | HRTS1_N_B_MARK, HCTS1_N_B_MARK, | |
1992 | }; | |
457c11d3 LP |
1993 | /* - INTC ------------------------------------------------------------------- */ |
1994 | static const unsigned int intc_irq0_pins[] = { | |
1995 | /* IRQ */ | |
1996 | RCAR_GP_PIN(1, 25), | |
1997 | }; | |
1998 | static const unsigned int intc_irq0_mux[] = { | |
1999 | IRQ0_MARK, | |
2000 | }; | |
2001 | static const unsigned int intc_irq1_pins[] = { | |
2002 | /* IRQ */ | |
2003 | RCAR_GP_PIN(1, 27), | |
2004 | }; | |
2005 | static const unsigned int intc_irq1_mux[] = { | |
2006 | IRQ1_MARK, | |
2007 | }; | |
2008 | static const unsigned int intc_irq2_pins[] = { | |
2009 | /* IRQ */ | |
2010 | RCAR_GP_PIN(1, 29), | |
2011 | }; | |
2012 | static const unsigned int intc_irq2_mux[] = { | |
2013 | IRQ2_MARK, | |
2014 | }; | |
2015 | static const unsigned int intc_irq3_pins[] = { | |
2016 | /* IRQ */ | |
2017 | RCAR_GP_PIN(1, 23), | |
2018 | }; | |
2019 | static const unsigned int intc_irq3_mux[] = { | |
2020 | IRQ3_MARK, | |
2021 | }; | |
2022 | /* - MMCIF0 ----------------------------------------------------------------- */ | |
2023 | static const unsigned int mmc0_data1_pins[] = { | |
2024 | /* D[0] */ | |
2025 | RCAR_GP_PIN(3, 18), | |
2026 | }; | |
2027 | static const unsigned int mmc0_data1_mux[] = { | |
2028 | MMC0_D0_MARK, | |
2029 | }; | |
2030 | static const unsigned int mmc0_data4_pins[] = { | |
2031 | /* D[0:3] */ | |
2032 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | |
2033 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
2034 | }; | |
2035 | static const unsigned int mmc0_data4_mux[] = { | |
2036 | MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, | |
2037 | }; | |
2038 | static const unsigned int mmc0_data8_pins[] = { | |
2039 | /* D[0:7] */ | |
2040 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | |
2041 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
2042 | RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), | |
2043 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | |
2044 | }; | |
2045 | static const unsigned int mmc0_data8_mux[] = { | |
2046 | MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, | |
2047 | MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, | |
2048 | }; | |
2049 | static const unsigned int mmc0_ctrl_pins[] = { | |
2050 | /* CLK, CMD */ | |
2051 | RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), | |
2052 | }; | |
2053 | static const unsigned int mmc0_ctrl_mux[] = { | |
2054 | MMC0_CLK_MARK, MMC0_CMD_MARK, | |
2055 | }; | |
2056 | /* - MMCIF1 ----------------------------------------------------------------- */ | |
2057 | static const unsigned int mmc1_data1_pins[] = { | |
2058 | /* D[0] */ | |
2059 | RCAR_GP_PIN(3, 26), | |
2060 | }; | |
2061 | static const unsigned int mmc1_data1_mux[] = { | |
2062 | MMC1_D0_MARK, | |
2063 | }; | |
2064 | static const unsigned int mmc1_data4_pins[] = { | |
2065 | /* D[0:3] */ | |
2066 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | |
2067 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | |
2068 | }; | |
2069 | static const unsigned int mmc1_data4_mux[] = { | |
2070 | MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, | |
2071 | }; | |
2072 | static const unsigned int mmc1_data8_pins[] = { | |
2073 | /* D[0:7] */ | |
2074 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | |
2075 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | |
2076 | RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), | |
2077 | RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), | |
2078 | }; | |
2079 | static const unsigned int mmc1_data8_mux[] = { | |
2080 | MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, | |
2081 | MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, | |
2082 | }; | |
2083 | static const unsigned int mmc1_ctrl_pins[] = { | |
2084 | /* CLK, CMD */ | |
2085 | RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), | |
2086 | }; | |
2087 | static const unsigned int mmc1_ctrl_mux[] = { | |
2088 | MMC1_CLK_MARK, MMC1_CMD_MARK, | |
2089 | }; | |
4f47cc5e KH |
2090 | /* - MSIOF0 ----------------------------------------------------------------- */ |
2091 | static const unsigned int msiof0_clk_pins[] = { | |
2092 | /* SCK */ | |
2093 | RCAR_GP_PIN(5, 12), | |
2094 | }; | |
2095 | static const unsigned int msiof0_clk_mux[] = { | |
2096 | MSIOF0_SCK_MARK, | |
2097 | }; | |
2098 | static const unsigned int msiof0_sync_pins[] = { | |
2099 | /* SYNC */ | |
2100 | RCAR_GP_PIN(5, 13), | |
2101 | }; | |
2102 | static const unsigned int msiof0_sync_mux[] = { | |
2103 | MSIOF0_SYNC_MARK, | |
2104 | }; | |
2105 | static const unsigned int msiof0_ss1_pins[] = { | |
2106 | /* SS1 */ | |
2107 | RCAR_GP_PIN(5, 14), | |
2108 | }; | |
2109 | static const unsigned int msiof0_ss1_mux[] = { | |
2110 | MSIOF0_SS1_MARK, | |
2111 | }; | |
2112 | static const unsigned int msiof0_ss2_pins[] = { | |
2113 | /* SS2 */ | |
2114 | RCAR_GP_PIN(5, 16), | |
2115 | }; | |
2116 | static const unsigned int msiof0_ss2_mux[] = { | |
2117 | MSIOF0_SS2_MARK, | |
2118 | }; | |
2119 | static const unsigned int msiof0_rx_pins[] = { | |
2120 | /* RXD */ | |
2121 | RCAR_GP_PIN(5, 17), | |
2122 | }; | |
2123 | static const unsigned int msiof0_rx_mux[] = { | |
2124 | MSIOF0_RXD_MARK, | |
2125 | }; | |
2126 | static const unsigned int msiof0_tx_pins[] = { | |
2127 | /* TXD */ | |
2128 | RCAR_GP_PIN(5, 15), | |
2129 | }; | |
2130 | static const unsigned int msiof0_tx_mux[] = { | |
2131 | MSIOF0_TXD_MARK, | |
2132 | }; | |
2133 | /* - MSIOF1 ----------------------------------------------------------------- */ | |
2134 | static const unsigned int msiof1_clk_pins[] = { | |
2135 | /* SCK */ | |
2136 | RCAR_GP_PIN(4, 8), | |
2137 | }; | |
2138 | static const unsigned int msiof1_clk_mux[] = { | |
2139 | MSIOF1_SCK_MARK, | |
2140 | }; | |
2141 | static const unsigned int msiof1_sync_pins[] = { | |
2142 | /* SYNC */ | |
2143 | RCAR_GP_PIN(4, 9), | |
2144 | }; | |
2145 | static const unsigned int msiof1_sync_mux[] = { | |
2146 | MSIOF1_SYNC_MARK, | |
2147 | }; | |
2148 | static const unsigned int msiof1_ss1_pins[] = { | |
2149 | /* SS1 */ | |
2150 | RCAR_GP_PIN(4, 10), | |
2151 | }; | |
2152 | static const unsigned int msiof1_ss1_mux[] = { | |
2153 | MSIOF1_SS1_MARK, | |
2154 | }; | |
2155 | static const unsigned int msiof1_ss2_pins[] = { | |
2156 | /* SS2 */ | |
2157 | RCAR_GP_PIN(4, 11), | |
2158 | }; | |
2159 | static const unsigned int msiof1_ss2_mux[] = { | |
2160 | MSIOF1_SS2_MARK, | |
2161 | }; | |
2162 | static const unsigned int msiof1_rx_pins[] = { | |
2163 | /* RXD */ | |
2164 | RCAR_GP_PIN(4, 13), | |
2165 | }; | |
2166 | static const unsigned int msiof1_rx_mux[] = { | |
2167 | MSIOF1_RXD_MARK, | |
2168 | }; | |
2169 | static const unsigned int msiof1_tx_pins[] = { | |
2170 | /* TXD */ | |
2171 | RCAR_GP_PIN(4, 12), | |
2172 | }; | |
2173 | static const unsigned int msiof1_tx_mux[] = { | |
2174 | MSIOF1_TXD_MARK, | |
2175 | }; | |
2176 | /* - MSIOF2 ----------------------------------------------------------------- */ | |
2177 | static const unsigned int msiof2_clk_pins[] = { | |
2178 | /* SCK */ | |
2179 | RCAR_GP_PIN(0, 27), | |
2180 | }; | |
2181 | static const unsigned int msiof2_clk_mux[] = { | |
2182 | MSIOF2_SCK_MARK, | |
2183 | }; | |
2184 | static const unsigned int msiof2_sync_pins[] = { | |
2185 | /* SYNC */ | |
2186 | RCAR_GP_PIN(0, 26), | |
2187 | }; | |
2188 | static const unsigned int msiof2_sync_mux[] = { | |
2189 | MSIOF2_SYNC_MARK, | |
2190 | }; | |
2191 | static const unsigned int msiof2_ss1_pins[] = { | |
2192 | /* SS1 */ | |
2193 | RCAR_GP_PIN(0, 30), | |
2194 | }; | |
2195 | static const unsigned int msiof2_ss1_mux[] = { | |
2196 | MSIOF2_SS1_MARK, | |
2197 | }; | |
2198 | static const unsigned int msiof2_ss2_pins[] = { | |
2199 | /* SS2 */ | |
2200 | RCAR_GP_PIN(0, 31), | |
2201 | }; | |
2202 | static const unsigned int msiof2_ss2_mux[] = { | |
2203 | MSIOF2_SS2_MARK, | |
2204 | }; | |
2205 | static const unsigned int msiof2_rx_pins[] = { | |
2206 | /* RXD */ | |
2207 | RCAR_GP_PIN(0, 29), | |
2208 | }; | |
2209 | static const unsigned int msiof2_rx_mux[] = { | |
2210 | MSIOF2_RXD_MARK, | |
2211 | }; | |
2212 | static const unsigned int msiof2_tx_pins[] = { | |
2213 | /* TXD */ | |
2214 | RCAR_GP_PIN(0, 28), | |
2215 | }; | |
2216 | static const unsigned int msiof2_tx_mux[] = { | |
2217 | MSIOF2_TXD_MARK, | |
2218 | }; | |
2219 | /* - MSIOF3 ----------------------------------------------------------------- */ | |
2220 | static const unsigned int msiof3_clk_pins[] = { | |
2221 | /* SCK */ | |
2222 | RCAR_GP_PIN(5, 4), | |
2223 | }; | |
2224 | static const unsigned int msiof3_clk_mux[] = { | |
2225 | MSIOF3_SCK_MARK, | |
2226 | }; | |
2227 | static const unsigned int msiof3_sync_pins[] = { | |
2228 | /* SYNC */ | |
2229 | RCAR_GP_PIN(4, 30), | |
2230 | }; | |
2231 | static const unsigned int msiof3_sync_mux[] = { | |
2232 | MSIOF3_SYNC_MARK, | |
2233 | }; | |
2234 | static const unsigned int msiof3_ss1_pins[] = { | |
2235 | /* SS1 */ | |
2236 | RCAR_GP_PIN(4, 31), | |
2237 | }; | |
2238 | static const unsigned int msiof3_ss1_mux[] = { | |
2239 | MSIOF3_SS1_MARK, | |
2240 | }; | |
2241 | static const unsigned int msiof3_ss2_pins[] = { | |
2242 | /* SS2 */ | |
2243 | RCAR_GP_PIN(4, 27), | |
2244 | }; | |
2245 | static const unsigned int msiof3_ss2_mux[] = { | |
2246 | MSIOF3_SS2_MARK, | |
2247 | }; | |
2248 | static const unsigned int msiof3_rx_pins[] = { | |
2249 | /* RXD */ | |
2250 | RCAR_GP_PIN(5, 2), | |
2251 | }; | |
2252 | static const unsigned int msiof3_rx_mux[] = { | |
2253 | MSIOF3_RXD_MARK, | |
2254 | }; | |
2255 | static const unsigned int msiof3_tx_pins[] = { | |
2256 | /* TXD */ | |
2257 | RCAR_GP_PIN(5, 3), | |
2258 | }; | |
2259 | static const unsigned int msiof3_tx_mux[] = { | |
2260 | MSIOF3_TXD_MARK, | |
2261 | }; | |
457c11d3 LP |
2262 | /* - SCIF0 ------------------------------------------------------------------ */ |
2263 | static const unsigned int scif0_data_pins[] = { | |
2264 | /* RX, TX */ | |
2265 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | |
2266 | }; | |
2267 | static const unsigned int scif0_data_mux[] = { | |
2268 | RX0_MARK, TX0_MARK, | |
2269 | }; | |
2270 | static const unsigned int scif0_clk_pins[] = { | |
2271 | /* SCK */ | |
2272 | RCAR_GP_PIN(4, 27), | |
2273 | }; | |
2274 | static const unsigned int scif0_clk_mux[] = { | |
2275 | SCK0_MARK, | |
2276 | }; | |
2277 | static const unsigned int scif0_ctrl_pins[] = { | |
2278 | /* RTS, CTS */ | |
2279 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), | |
2280 | }; | |
2281 | static const unsigned int scif0_ctrl_mux[] = { | |
2282 | RTS0_N_MARK, CTS0_N_MARK, | |
2283 | }; | |
2284 | static const unsigned int scif0_data_b_pins[] = { | |
2285 | /* RX, TX */ | |
2286 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
2287 | }; | |
2288 | static const unsigned int scif0_data_b_mux[] = { | |
2289 | RX0_B_MARK, TX0_B_MARK, | |
2290 | }; | |
2291 | /* - SCIF1 ------------------------------------------------------------------ */ | |
2292 | static const unsigned int scif1_data_pins[] = { | |
2293 | /* RX, TX */ | |
2294 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), | |
2295 | }; | |
2296 | static const unsigned int scif1_data_mux[] = { | |
2297 | RX1_MARK, TX1_MARK, | |
2298 | }; | |
2299 | static const unsigned int scif1_clk_pins[] = { | |
2300 | /* SCK */ | |
2301 | RCAR_GP_PIN(4, 20), | |
2302 | }; | |
2303 | static const unsigned int scif1_clk_mux[] = { | |
2304 | SCK1_MARK, | |
2305 | }; | |
2306 | static const unsigned int scif1_ctrl_pins[] = { | |
2307 | /* RTS, CTS */ | |
2308 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), | |
2309 | }; | |
2310 | static const unsigned int scif1_ctrl_mux[] = { | |
2311 | RTS1_N_MARK, CTS1_N_MARK, | |
2312 | }; | |
2313 | static const unsigned int scif1_data_b_pins[] = { | |
2314 | /* RX, TX */ | |
2315 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
2316 | }; | |
2317 | static const unsigned int scif1_data_b_mux[] = { | |
2318 | RX1_B_MARK, TX1_B_MARK, | |
2319 | }; | |
2320 | static const unsigned int scif1_data_c_pins[] = { | |
2321 | /* RX, TX */ | |
2322 | RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), | |
2323 | }; | |
2324 | static const unsigned int scif1_data_c_mux[] = { | |
2325 | RX1_C_MARK, TX1_C_MARK, | |
fbd0ca3d | 2326 | }; |
457c11d3 | 2327 | static const unsigned int scif1_data_d_pins[] = { |
fbd0ca3d | 2328 | /* RX, TX */ |
457c11d3 | 2329 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), |
fbd0ca3d | 2330 | }; |
457c11d3 LP |
2331 | static const unsigned int scif1_data_d_mux[] = { |
2332 | RX1_D_MARK, TX1_D_MARK, | |
fbd0ca3d | 2333 | }; |
457c11d3 | 2334 | static const unsigned int scif1_clk_d_pins[] = { |
fbd0ca3d | 2335 | /* SCK */ |
457c11d3 | 2336 | RCAR_GP_PIN(3, 17), |
fbd0ca3d | 2337 | }; |
457c11d3 LP |
2338 | static const unsigned int scif1_clk_d_mux[] = { |
2339 | SCK1_D_MARK, | |
fbd0ca3d | 2340 | }; |
457c11d3 LP |
2341 | static const unsigned int scif1_data_e_pins[] = { |
2342 | /* RX, TX */ | |
2343 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | |
fbd0ca3d | 2344 | }; |
457c11d3 LP |
2345 | static const unsigned int scif1_data_e_mux[] = { |
2346 | RX1_E_MARK, TX1_E_MARK, | |
2347 | }; | |
2348 | static const unsigned int scif1_clk_e_pins[] = { | |
2349 | /* SCK */ | |
2350 | RCAR_GP_PIN(2, 20), | |
2351 | }; | |
2352 | static const unsigned int scif1_clk_e_mux[] = { | |
2353 | SCK1_E_MARK, | |
fbd0ca3d | 2354 | }; |
2dbe7f2c LP |
2355 | /* - SCIF2 ------------------------------------------------------------------ */ |
2356 | static const unsigned int scif2_data_pins[] = { | |
2357 | /* RX, TX */ | |
2358 | RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), | |
2359 | }; | |
2360 | static const unsigned int scif2_data_mux[] = { | |
2361 | RX2_MARK, TX2_MARK, | |
2362 | }; | |
2363 | static const unsigned int scif2_clk_pins[] = { | |
2364 | /* SCK */ | |
2365 | RCAR_GP_PIN(5, 4), | |
2366 | }; | |
2367 | static const unsigned int scif2_clk_mux[] = { | |
2368 | SCK2_MARK, | |
2369 | }; | |
2370 | static const unsigned int scif2_data_b_pins[] = { | |
2371 | /* RX, TX */ | |
2372 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
2373 | }; | |
2374 | static const unsigned int scif2_data_b_mux[] = { | |
2375 | RX2_B_MARK, TX2_B_MARK, | |
2376 | }; | |
45c6c85d LP |
2377 | /* - SCIFA0 ----------------------------------------------------------------- */ |
2378 | static const unsigned int scifa0_data_pins[] = { | |
2379 | /* RXD, TXD */ | |
2380 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | |
2381 | }; | |
2382 | static const unsigned int scifa0_data_mux[] = { | |
2383 | SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, | |
2384 | }; | |
2385 | static const unsigned int scifa0_clk_pins[] = { | |
2386 | /* SCK */ | |
2387 | RCAR_GP_PIN(4, 27), | |
2388 | }; | |
2389 | static const unsigned int scifa0_clk_mux[] = { | |
2390 | SCIFA0_SCK_MARK, | |
2391 | }; | |
2392 | static const unsigned int scifa0_ctrl_pins[] = { | |
2393 | /* RTS, CTS */ | |
2394 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), | |
2395 | }; | |
2396 | static const unsigned int scifa0_ctrl_mux[] = { | |
2397 | SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, | |
2398 | }; | |
2399 | static const unsigned int scifa0_data_b_pins[] = { | |
2400 | /* RXD, TXD */ | |
2401 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), | |
2402 | }; | |
2403 | static const unsigned int scifa0_data_b_mux[] = { | |
2404 | SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK | |
2405 | }; | |
2406 | static const unsigned int scifa0_clk_b_pins[] = { | |
2407 | /* SCK */ | |
2408 | RCAR_GP_PIN(1, 19), | |
2409 | }; | |
2410 | static const unsigned int scifa0_clk_b_mux[] = { | |
2411 | SCIFA0_SCK_B_MARK, | |
2412 | }; | |
2413 | static const unsigned int scifa0_ctrl_b_pins[] = { | |
2414 | /* RTS, CTS */ | |
2415 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), | |
2416 | }; | |
2417 | static const unsigned int scifa0_ctrl_b_mux[] = { | |
2418 | SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, | |
2419 | }; | |
2420 | /* - SCIFA1 ----------------------------------------------------------------- */ | |
2421 | static const unsigned int scifa1_data_pins[] = { | |
2422 | /* RXD, TXD */ | |
2423 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), | |
2424 | }; | |
2425 | static const unsigned int scifa1_data_mux[] = { | |
2426 | SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, | |
2427 | }; | |
2428 | static const unsigned int scifa1_clk_pins[] = { | |
2429 | /* SCK */ | |
2430 | RCAR_GP_PIN(4, 20), | |
2431 | }; | |
2432 | static const unsigned int scifa1_clk_mux[] = { | |
2433 | SCIFA1_SCK_MARK, | |
2434 | }; | |
2435 | static const unsigned int scifa1_ctrl_pins[] = { | |
2436 | /* RTS, CTS */ | |
2437 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), | |
2438 | }; | |
2439 | static const unsigned int scifa1_ctrl_mux[] = { | |
2440 | SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, | |
2441 | }; | |
2442 | static const unsigned int scifa1_data_b_pins[] = { | |
2443 | /* RXD, TXD */ | |
2444 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), | |
2445 | }; | |
2446 | static const unsigned int scifa1_data_b_mux[] = { | |
2447 | SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, | |
2448 | }; | |
2449 | static const unsigned int scifa1_clk_b_pins[] = { | |
2450 | /* SCK */ | |
2451 | RCAR_GP_PIN(0, 23), | |
2452 | }; | |
2453 | static const unsigned int scifa1_clk_b_mux[] = { | |
2454 | SCIFA1_SCK_B_MARK, | |
2455 | }; | |
2456 | static const unsigned int scifa1_ctrl_b_pins[] = { | |
2457 | /* RTS, CTS */ | |
2458 | RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), | |
2459 | }; | |
2460 | static const unsigned int scifa1_ctrl_b_mux[] = { | |
2461 | SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, | |
2462 | }; | |
2463 | static const unsigned int scifa1_data_c_pins[] = { | |
2464 | /* RXD, TXD */ | |
2465 | RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), | |
2466 | }; | |
2467 | static const unsigned int scifa1_data_c_mux[] = { | |
2468 | SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, | |
2469 | }; | |
2470 | static const unsigned int scifa1_clk_c_pins[] = { | |
2471 | /* SCK */ | |
2472 | RCAR_GP_PIN(0, 8), | |
2473 | }; | |
2474 | static const unsigned int scifa1_clk_c_mux[] = { | |
2475 | SCIFA1_SCK_C_MARK, | |
2476 | }; | |
2477 | static const unsigned int scifa1_ctrl_c_pins[] = { | |
2478 | /* RTS, CTS */ | |
2479 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), | |
2480 | }; | |
2481 | static const unsigned int scifa1_ctrl_c_mux[] = { | |
2482 | SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, | |
2483 | }; | |
2484 | static const unsigned int scifa1_data_d_pins[] = { | |
2485 | /* RXD, TXD */ | |
2486 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
2487 | }; | |
2488 | static const unsigned int scifa1_data_d_mux[] = { | |
2489 | SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, | |
2490 | }; | |
2491 | static const unsigned int scifa1_clk_d_pins[] = { | |
2492 | /* SCK */ | |
2493 | RCAR_GP_PIN(2, 10), | |
2494 | }; | |
2495 | static const unsigned int scifa1_clk_d_mux[] = { | |
2496 | SCIFA1_SCK_D_MARK, | |
2497 | }; | |
2498 | static const unsigned int scifa1_ctrl_d_pins[] = { | |
2499 | /* RTS, CTS */ | |
2500 | RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), | |
2501 | }; | |
2502 | static const unsigned int scifa1_ctrl_d_mux[] = { | |
2503 | SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, | |
2504 | }; | |
2505 | /* - SCIFA2 ----------------------------------------------------------------- */ | |
2506 | static const unsigned int scifa2_data_pins[] = { | |
2507 | /* RXD, TXD */ | |
2508 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
2509 | }; | |
2510 | static const unsigned int scifa2_data_mux[] = { | |
2511 | SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, | |
2512 | }; | |
2513 | static const unsigned int scifa2_clk_pins[] = { | |
2514 | /* SCK */ | |
2515 | RCAR_GP_PIN(5, 4), | |
2516 | }; | |
2517 | static const unsigned int scifa2_clk_mux[] = { | |
2518 | SCIFA2_SCK_MARK, | |
2519 | }; | |
2520 | static const unsigned int scifa2_ctrl_pins[] = { | |
2521 | /* RTS, CTS */ | |
2522 | RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), | |
2523 | }; | |
2524 | static const unsigned int scifa2_ctrl_mux[] = { | |
2525 | SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, | |
2526 | }; | |
2527 | static const unsigned int scifa2_data_b_pins[] = { | |
2528 | /* RXD, TXD */ | |
2529 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), | |
2530 | }; | |
2531 | static const unsigned int scifa2_data_b_mux[] = { | |
2532 | SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, | |
2533 | }; | |
2534 | static const unsigned int scifa2_data_c_pins[] = { | |
2535 | /* RXD, TXD */ | |
2536 | RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), | |
2537 | }; | |
2538 | static const unsigned int scifa2_data_c_mux[] = { | |
2539 | SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, | |
2540 | }; | |
2541 | static const unsigned int scifa2_clk_c_pins[] = { | |
2542 | /* SCK */ | |
2543 | RCAR_GP_PIN(5, 29), | |
2544 | }; | |
2545 | static const unsigned int scifa2_clk_c_mux[] = { | |
2546 | SCIFA2_SCK_C_MARK, | |
2547 | }; | |
2548 | /* - SCIFB0 ----------------------------------------------------------------- */ | |
2549 | static const unsigned int scifb0_data_pins[] = { | |
2550 | /* RXD, TXD */ | |
2551 | RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), | |
2552 | }; | |
2553 | static const unsigned int scifb0_data_mux[] = { | |
2554 | SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, | |
2555 | }; | |
2556 | static const unsigned int scifb0_clk_pins[] = { | |
2557 | /* SCK */ | |
2558 | RCAR_GP_PIN(4, 8), | |
2559 | }; | |
2560 | static const unsigned int scifb0_clk_mux[] = { | |
2561 | SCIFB0_SCK_MARK, | |
2562 | }; | |
2563 | static const unsigned int scifb0_ctrl_pins[] = { | |
2564 | /* RTS, CTS */ | |
2565 | RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), | |
2566 | }; | |
2567 | static const unsigned int scifb0_ctrl_mux[] = { | |
2568 | SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, | |
2569 | }; | |
2570 | static const unsigned int scifb0_data_b_pins[] = { | |
2571 | /* RXD, TXD */ | |
2572 | RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), | |
2573 | }; | |
2574 | static const unsigned int scifb0_data_b_mux[] = { | |
2575 | SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, | |
2576 | }; | |
2577 | static const unsigned int scifb0_clk_b_pins[] = { | |
2578 | /* SCK */ | |
2579 | RCAR_GP_PIN(3, 9), | |
2580 | }; | |
2581 | static const unsigned int scifb0_clk_b_mux[] = { | |
2582 | SCIFB0_SCK_B_MARK, | |
2583 | }; | |
2584 | static const unsigned int scifb0_ctrl_b_pins[] = { | |
2585 | /* RTS, CTS */ | |
2586 | RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), | |
2587 | }; | |
2588 | static const unsigned int scifb0_ctrl_b_mux[] = { | |
2589 | SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, | |
2590 | }; | |
2591 | static const unsigned int scifb0_data_c_pins[] = { | |
2592 | /* RXD, TXD */ | |
2593 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
2594 | }; | |
2595 | static const unsigned int scifb0_data_c_mux[] = { | |
2596 | SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, | |
2597 | }; | |
2598 | /* - SCIFB1 ----------------------------------------------------------------- */ | |
2599 | static const unsigned int scifb1_data_pins[] = { | |
2600 | /* RXD, TXD */ | |
2601 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), | |
2602 | }; | |
2603 | static const unsigned int scifb1_data_mux[] = { | |
2604 | SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, | |
2605 | }; | |
2606 | static const unsigned int scifb1_clk_pins[] = { | |
2607 | /* SCK */ | |
2608 | RCAR_GP_PIN(4, 14), | |
2609 | }; | |
2610 | static const unsigned int scifb1_clk_mux[] = { | |
2611 | SCIFB1_SCK_MARK, | |
2612 | }; | |
2613 | static const unsigned int scifb1_ctrl_pins[] = { | |
2614 | /* RTS, CTS */ | |
2615 | RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), | |
2616 | }; | |
2617 | static const unsigned int scifb1_ctrl_mux[] = { | |
2618 | SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, | |
2619 | }; | |
2620 | static const unsigned int scifb1_data_b_pins[] = { | |
2621 | /* RXD, TXD */ | |
2622 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), | |
2623 | }; | |
2624 | static const unsigned int scifb1_data_b_mux[] = { | |
2625 | SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, | |
2626 | }; | |
2627 | static const unsigned int scifb1_clk_b_pins[] = { | |
2628 | /* SCK */ | |
2629 | RCAR_GP_PIN(3, 1), | |
2630 | }; | |
2631 | static const unsigned int scifb1_clk_b_mux[] = { | |
2632 | SCIFB1_SCK_B_MARK, | |
2633 | }; | |
2634 | static const unsigned int scifb1_ctrl_b_pins[] = { | |
2635 | /* RTS, CTS */ | |
2636 | RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), | |
2637 | }; | |
2638 | static const unsigned int scifb1_ctrl_b_mux[] = { | |
2639 | SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, | |
2640 | }; | |
2641 | static const unsigned int scifb1_data_c_pins[] = { | |
2642 | /* RXD, TXD */ | |
2643 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
2644 | }; | |
2645 | static const unsigned int scifb1_data_c_mux[] = { | |
2646 | SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, | |
2647 | }; | |
2648 | static const unsigned int scifb1_data_d_pins[] = { | |
2649 | /* RXD, TXD */ | |
2650 | RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), | |
2651 | }; | |
2652 | static const unsigned int scifb1_data_d_mux[] = { | |
2653 | SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, | |
2654 | }; | |
2655 | static const unsigned int scifb1_data_e_pins[] = { | |
2656 | /* RXD, TXD */ | |
2657 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | |
2658 | }; | |
2659 | static const unsigned int scifb1_data_e_mux[] = { | |
2660 | SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, | |
2661 | }; | |
2662 | static const unsigned int scifb1_clk_e_pins[] = { | |
2663 | /* SCK */ | |
2664 | RCAR_GP_PIN(3, 17), | |
2665 | }; | |
2666 | static const unsigned int scifb1_clk_e_mux[] = { | |
2667 | SCIFB1_SCK_E_MARK, | |
2668 | }; | |
2669 | static const unsigned int scifb1_data_f_pins[] = { | |
2670 | /* RXD, TXD */ | |
2671 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
2672 | }; | |
2673 | static const unsigned int scifb1_data_f_mux[] = { | |
2674 | SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, | |
2675 | }; | |
2676 | static const unsigned int scifb1_data_g_pins[] = { | |
2677 | /* RXD, TXD */ | |
2678 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | |
2679 | }; | |
2680 | static const unsigned int scifb1_data_g_mux[] = { | |
2681 | SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, | |
2682 | }; | |
2683 | static const unsigned int scifb1_clk_g_pins[] = { | |
2684 | /* SCK */ | |
2685 | RCAR_GP_PIN(2, 20), | |
2686 | }; | |
2687 | static const unsigned int scifb1_clk_g_mux[] = { | |
2688 | SCIFB1_SCK_G_MARK, | |
066f0d6e | 2689 | }; |
45c6c85d LP |
2690 | /* - SCIFB2 ----------------------------------------------------------------- */ |
2691 | static const unsigned int scifb2_data_pins[] = { | |
2692 | /* RXD, TXD */ | |
2693 | RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), | |
066f0d6e | 2694 | }; |
45c6c85d LP |
2695 | static const unsigned int scifb2_data_mux[] = { |
2696 | SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, | |
066f0d6e | 2697 | }; |
45c6c85d LP |
2698 | static const unsigned int scifb2_clk_pins[] = { |
2699 | /* SCK */ | |
2700 | RCAR_GP_PIN(4, 21), | |
066f0d6e | 2701 | }; |
45c6c85d LP |
2702 | static const unsigned int scifb2_clk_mux[] = { |
2703 | SCIFB2_SCK_MARK, | |
066f0d6e | 2704 | }; |
45c6c85d LP |
2705 | static const unsigned int scifb2_ctrl_pins[] = { |
2706 | /* RTS, CTS */ | |
2707 | RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), | |
066f0d6e | 2708 | }; |
45c6c85d LP |
2709 | static const unsigned int scifb2_ctrl_mux[] = { |
2710 | SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, | |
066f0d6e | 2711 | }; |
45c6c85d LP |
2712 | static const unsigned int scifb2_data_b_pins[] = { |
2713 | /* RXD, TXD */ | |
2714 | RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), | |
066f0d6e | 2715 | }; |
45c6c85d LP |
2716 | static const unsigned int scifb2_data_b_mux[] = { |
2717 | SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, | |
066f0d6e | 2718 | }; |
45c6c85d LP |
2719 | static const unsigned int scifb2_clk_b_pins[] = { |
2720 | /* SCK */ | |
2721 | RCAR_GP_PIN(0, 31), | |
066f0d6e | 2722 | }; |
45c6c85d LP |
2723 | static const unsigned int scifb2_clk_b_mux[] = { |
2724 | SCIFB2_SCK_B_MARK, | |
066f0d6e | 2725 | }; |
45c6c85d LP |
2726 | static const unsigned int scifb2_ctrl_b_pins[] = { |
2727 | /* RTS, CTS */ | |
2728 | RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), | |
066f0d6e | 2729 | }; |
45c6c85d LP |
2730 | static const unsigned int scifb2_ctrl_b_mux[] = { |
2731 | SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, | |
066f0d6e | 2732 | }; |
45c6c85d LP |
2733 | static const unsigned int scifb2_data_c_pins[] = { |
2734 | /* RXD, TXD */ | |
2735 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
2736 | }; | |
2737 | static const unsigned int scifb2_data_c_mux[] = { | |
2738 | SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, | |
066f0d6e | 2739 | }; |
0a6ea54f | 2740 | /* - SDHI0 ------------------------------------------------------------------ */ |
066f0d6e GL |
2741 | static const unsigned int sdhi0_data1_pins[] = { |
2742 | /* D0 */ | |
2743 | RCAR_GP_PIN(3, 2), | |
2744 | }; | |
2745 | static const unsigned int sdhi0_data1_mux[] = { | |
2746 | SD0_DAT0_MARK, | |
2747 | }; | |
2748 | static const unsigned int sdhi0_data4_pins[] = { | |
2749 | /* D[0:3] */ | |
2750 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), | |
2751 | }; | |
2752 | static const unsigned int sdhi0_data4_mux[] = { | |
2753 | SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, | |
2754 | }; | |
2755 | static const unsigned int sdhi0_ctrl_pins[] = { | |
2756 | /* CLK, CMD */ | |
2757 | RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), | |
2758 | }; | |
2759 | static const unsigned int sdhi0_ctrl_mux[] = { | |
2760 | SD0_CLK_MARK, SD0_CMD_MARK, | |
2761 | }; | |
2762 | static const unsigned int sdhi0_cd_pins[] = { | |
2763 | /* CD */ | |
2764 | RCAR_GP_PIN(3, 6), | |
2765 | }; | |
2766 | static const unsigned int sdhi0_cd_mux[] = { | |
2767 | SD0_CD_MARK, | |
2768 | }; | |
2769 | static const unsigned int sdhi0_wp_pins[] = { | |
2770 | /* WP */ | |
2771 | RCAR_GP_PIN(3, 7), | |
2772 | }; | |
2773 | static const unsigned int sdhi0_wp_mux[] = { | |
2774 | SD0_WP_MARK, | |
2775 | }; | |
0a6ea54f | 2776 | /* - SDHI1 ------------------------------------------------------------------ */ |
066f0d6e GL |
2777 | static const unsigned int sdhi1_data1_pins[] = { |
2778 | /* D0 */ | |
2779 | RCAR_GP_PIN(3, 10), | |
2780 | }; | |
2781 | static const unsigned int sdhi1_data1_mux[] = { | |
2782 | SD1_DAT0_MARK, | |
2783 | }; | |
2784 | static const unsigned int sdhi1_data4_pins[] = { | |
2785 | /* D[0:3] */ | |
2786 | RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), | |
2787 | }; | |
2788 | static const unsigned int sdhi1_data4_mux[] = { | |
2789 | SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, | |
2790 | }; | |
2791 | static const unsigned int sdhi1_ctrl_pins[] = { | |
2792 | /* CLK, CMD */ | |
2793 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), | |
2794 | }; | |
2795 | static const unsigned int sdhi1_ctrl_mux[] = { | |
2796 | SD1_CLK_MARK, SD1_CMD_MARK, | |
2797 | }; | |
2798 | static const unsigned int sdhi1_cd_pins[] = { | |
2799 | /* CD */ | |
2800 | RCAR_GP_PIN(3, 14), | |
2801 | }; | |
2802 | static const unsigned int sdhi1_cd_mux[] = { | |
2803 | SD1_CD_MARK, | |
2804 | }; | |
2805 | static const unsigned int sdhi1_wp_pins[] = { | |
2806 | /* WP */ | |
2807 | RCAR_GP_PIN(3, 15), | |
2808 | }; | |
2809 | static const unsigned int sdhi1_wp_mux[] = { | |
2810 | SD1_WP_MARK, | |
2811 | }; | |
0a6ea54f | 2812 | /* - SDHI2 ------------------------------------------------------------------ */ |
066f0d6e GL |
2813 | static const unsigned int sdhi2_data1_pins[] = { |
2814 | /* D0 */ | |
2815 | RCAR_GP_PIN(3, 18), | |
2816 | }; | |
2817 | static const unsigned int sdhi2_data1_mux[] = { | |
2818 | SD2_DAT0_MARK, | |
2819 | }; | |
2820 | static const unsigned int sdhi2_data4_pins[] = { | |
2821 | /* D[0:3] */ | |
2822 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
2823 | }; | |
2824 | static const unsigned int sdhi2_data4_mux[] = { | |
2825 | SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, | |
2826 | }; | |
2827 | static const unsigned int sdhi2_ctrl_pins[] = { | |
2828 | /* CLK, CMD */ | |
2829 | RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), | |
2830 | }; | |
2831 | static const unsigned int sdhi2_ctrl_mux[] = { | |
2832 | SD2_CLK_MARK, SD2_CMD_MARK, | |
2833 | }; | |
2834 | static const unsigned int sdhi2_cd_pins[] = { | |
2835 | /* CD */ | |
2836 | RCAR_GP_PIN(3, 22), | |
2837 | }; | |
2838 | static const unsigned int sdhi2_cd_mux[] = { | |
2839 | SD2_CD_MARK, | |
2840 | }; | |
2841 | static const unsigned int sdhi2_wp_pins[] = { | |
2842 | /* WP */ | |
2843 | RCAR_GP_PIN(3, 23), | |
2844 | }; | |
2845 | static const unsigned int sdhi2_wp_mux[] = { | |
2846 | SD2_WP_MARK, | |
2847 | }; | |
0a6ea54f | 2848 | /* - SDHI3 ------------------------------------------------------------------ */ |
066f0d6e GL |
2849 | static const unsigned int sdhi3_data1_pins[] = { |
2850 | /* D0 */ | |
2851 | RCAR_GP_PIN(3, 26), | |
2852 | }; | |
2853 | static const unsigned int sdhi3_data1_mux[] = { | |
2854 | SD3_DAT0_MARK, | |
2855 | }; | |
2856 | static const unsigned int sdhi3_data4_pins[] = { | |
2857 | /* D[0:3] */ | |
2858 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | |
2859 | }; | |
2860 | static const unsigned int sdhi3_data4_mux[] = { | |
2861 | SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, | |
2862 | }; | |
2863 | static const unsigned int sdhi3_ctrl_pins[] = { | |
2864 | /* CLK, CMD */ | |
2865 | RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), | |
2866 | }; | |
2867 | static const unsigned int sdhi3_ctrl_mux[] = { | |
2868 | SD3_CLK_MARK, SD3_CMD_MARK, | |
2869 | }; | |
2870 | static const unsigned int sdhi3_cd_pins[] = { | |
2871 | /* CD */ | |
2872 | RCAR_GP_PIN(3, 30), | |
2873 | }; | |
2874 | static const unsigned int sdhi3_cd_mux[] = { | |
2875 | SD3_CD_MARK, | |
2876 | }; | |
2877 | static const unsigned int sdhi3_wp_pins[] = { | |
2878 | /* WP */ | |
2879 | RCAR_GP_PIN(3, 31), | |
2880 | }; | |
2881 | static const unsigned int sdhi3_wp_mux[] = { | |
2882 | SD3_WP_MARK, | |
2883 | }; | |
457c11d3 LP |
2884 | /* - TPU0 ------------------------------------------------------------------- */ |
2885 | static const unsigned int tpu0_to0_pins[] = { | |
2886 | /* TO */ | |
2887 | RCAR_GP_PIN(0, 20), | |
2888 | }; | |
2889 | static const unsigned int tpu0_to0_mux[] = { | |
2890 | TPU0TO0_MARK, | |
2891 | }; | |
2892 | static const unsigned int tpu0_to1_pins[] = { | |
2893 | /* TO */ | |
2894 | RCAR_GP_PIN(0, 21), | |
2895 | }; | |
2896 | static const unsigned int tpu0_to1_mux[] = { | |
2897 | TPU0TO1_MARK, | |
2898 | }; | |
2899 | static const unsigned int tpu0_to2_pins[] = { | |
2900 | /* TO */ | |
2901 | RCAR_GP_PIN(0, 22), | |
2902 | }; | |
2903 | static const unsigned int tpu0_to2_mux[] = { | |
2904 | TPU0TO2_MARK, | |
2905 | }; | |
2906 | static const unsigned int tpu0_to3_pins[] = { | |
2907 | /* TO */ | |
2908 | RCAR_GP_PIN(0, 23), | |
2909 | }; | |
2910 | static const unsigned int tpu0_to3_mux[] = { | |
2911 | TPU0TO3_MARK, | |
2912 | }; | |
dac896e2 SU |
2913 | /* - USB0 ------------------------------------------------------------------- */ |
2914 | static const unsigned int usb0_pins[] = { | |
2915 | /* PWEN, OVC/VBUS */ | |
2916 | RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), | |
2917 | }; | |
2918 | static const unsigned int usb0_mux[] = { | |
2919 | USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, | |
2920 | }; | |
2921 | /* - USB1 ------------------------------------------------------------------- */ | |
2922 | static const unsigned int usb1_pins[] = { | |
2923 | /* PWEN, OVC */ | |
2924 | RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), | |
2925 | }; | |
2926 | static const unsigned int usb1_mux[] = { | |
2927 | USB1_PWEN_MARK, USB1_OVC_MARK, | |
2928 | }; | |
2929 | /* - USB2 ------------------------------------------------------------------- */ | |
2930 | static const unsigned int usb2_pins[] = { | |
2931 | /* PWEN, OVC */ | |
2932 | RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), | |
2933 | }; | |
2934 | static const unsigned int usb2_mux[] = { | |
2935 | USB2_PWEN_MARK, USB2_OVC_MARK, | |
2936 | }; | |
e120cacf SU |
2937 | /* - VIN0 ------------------------------------------------------------------- */ |
2938 | static const unsigned int vin0_data_g_pins[] = { | |
2939 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), | |
2940 | RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | |
2941 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | |
2942 | }; | |
2943 | static const unsigned int vin0_data_g_mux[] = { | |
2944 | VI0_G0_MARK, VI0_G1_MARK, VI0_G2_MARK, | |
2945 | VI0_G3_MARK, VI0_G4_MARK, VI0_G5_MARK, | |
2946 | VI0_G6_MARK, VI0_G7_MARK, | |
2947 | }; | |
2948 | static const unsigned int vin0_data_r_pins[] = { | |
2949 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), | |
2950 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
2951 | RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), | |
2952 | }; | |
2953 | static const unsigned int vin0_data_r_mux[] = { | |
2954 | VI0_R0_MARK, VI0_R1_MARK, VI0_R2_MARK, | |
2955 | VI0_R3_MARK, VI0_R4_MARK, VI0_R5_MARK, | |
2956 | VI0_R6_MARK, VI0_R7_MARK, | |
2957 | }; | |
2958 | static const unsigned int vin0_data_b_pins[] = { | |
2959 | RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | |
2960 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), | |
2961 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), | |
2962 | }; | |
2963 | static const unsigned int vin0_data_b_mux[] = { | |
2964 | VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, | |
2965 | VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, | |
2966 | VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, | |
2967 | }; | |
2968 | static const unsigned int vin0_hsync_signal_pins[] = { | |
2969 | RCAR_GP_PIN(0, 12), | |
2970 | }; | |
2971 | static const unsigned int vin0_hsync_signal_mux[] = { | |
2972 | VI0_HSYNC_N_MARK, | |
2973 | }; | |
2974 | static const unsigned int vin0_vsync_signal_pins[] = { | |
2975 | RCAR_GP_PIN(0, 13), | |
2976 | }; | |
2977 | static const unsigned int vin0_vsync_signal_mux[] = { | |
2978 | VI0_VSYNC_N_MARK, | |
2979 | }; | |
2980 | static const unsigned int vin0_field_signal_pins[] = { | |
2981 | RCAR_GP_PIN(0, 15), | |
2982 | }; | |
2983 | static const unsigned int vin0_field_signal_mux[] = { | |
2984 | VI0_FIELD_MARK, | |
2985 | }; | |
2986 | static const unsigned int vin0_data_enable_pins[] = { | |
2987 | RCAR_GP_PIN(0, 14), | |
2988 | }; | |
2989 | static const unsigned int vin0_data_enable_mux[] = { | |
2990 | VI0_CLKENB_MARK, | |
2991 | }; | |
2992 | static const unsigned int vin0_clk_pins[] = { | |
2993 | RCAR_GP_PIN(2, 0), | |
2994 | }; | |
2995 | static const unsigned int vin0_clk_mux[] = { | |
2996 | VI0_CLK_MARK, | |
2997 | }; | |
2998 | /* - VIN1 ------------------------------------------------------------------- */ | |
2999 | static const unsigned int vin1_data_pins[] = { | |
3000 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
3001 | RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), | |
3002 | RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), | |
3003 | }; | |
3004 | static const unsigned int vin1_data_mux[] = { | |
3005 | VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, | |
3006 | VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, | |
3007 | VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, | |
3008 | }; | |
3009 | static const unsigned int vin1_clk_pins[] = { | |
3010 | RCAR_GP_PIN(2, 9), | |
3011 | }; | |
3012 | static const unsigned int vin1_clk_mux[] = { | |
3013 | VI1_CLK_MARK, | |
3014 | }; | |
066f0d6e | 3015 | |
1627769b | 3016 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
62783b71 LP |
3017 | SH_PFC_PIN_GROUP(du_rgb666), |
3018 | SH_PFC_PIN_GROUP(du_rgb888), | |
3019 | SH_PFC_PIN_GROUP(du_clk_out_0), | |
3020 | SH_PFC_PIN_GROUP(du_clk_out_1), | |
3021 | SH_PFC_PIN_GROUP(du_sync_0), | |
3022 | SH_PFC_PIN_GROUP(du_sync_1), | |
3023 | SH_PFC_PIN_GROUP(du_cde), | |
3024 | SH_PFC_PIN_GROUP(du0_clk_in), | |
3025 | SH_PFC_PIN_GROUP(du1_clk_in), | |
3026 | SH_PFC_PIN_GROUP(du2_clk_in), | |
1627769b LP |
3027 | SH_PFC_PIN_GROUP(eth_link), |
3028 | SH_PFC_PIN_GROUP(eth_magic), | |
3029 | SH_PFC_PIN_GROUP(eth_mdio), | |
3030 | SH_PFC_PIN_GROUP(eth_rmii), | |
fbd0ca3d UH |
3031 | SH_PFC_PIN_GROUP(hscif0_data), |
3032 | SH_PFC_PIN_GROUP(hscif0_clk), | |
3033 | SH_PFC_PIN_GROUP(hscif0_ctrl), | |
3034 | SH_PFC_PIN_GROUP(hscif0_data_b), | |
3035 | SH_PFC_PIN_GROUP(hscif0_ctrl_b), | |
3036 | SH_PFC_PIN_GROUP(hscif0_data_c), | |
3037 | SH_PFC_PIN_GROUP(hscif0_ctrl_c), | |
3038 | SH_PFC_PIN_GROUP(hscif0_data_d), | |
3039 | SH_PFC_PIN_GROUP(hscif0_ctrl_d), | |
3040 | SH_PFC_PIN_GROUP(hscif0_data_e), | |
3041 | SH_PFC_PIN_GROUP(hscif0_ctrl_e), | |
3042 | SH_PFC_PIN_GROUP(hscif0_data_f), | |
3043 | SH_PFC_PIN_GROUP(hscif0_ctrl_f), | |
3044 | SH_PFC_PIN_GROUP(hscif1_data), | |
3045 | SH_PFC_PIN_GROUP(hscif1_clk), | |
3046 | SH_PFC_PIN_GROUP(hscif1_ctrl), | |
3047 | SH_PFC_PIN_GROUP(hscif1_data_b), | |
3048 | SH_PFC_PIN_GROUP(hscif1_clk_b), | |
3049 | SH_PFC_PIN_GROUP(hscif1_ctrl_b), | |
04e7ce78 LP |
3050 | SH_PFC_PIN_GROUP(intc_irq0), |
3051 | SH_PFC_PIN_GROUP(intc_irq1), | |
3052 | SH_PFC_PIN_GROUP(intc_irq2), | |
3053 | SH_PFC_PIN_GROUP(intc_irq3), | |
fbd0ca3d UH |
3054 | SH_PFC_PIN_GROUP(mmc0_data1), |
3055 | SH_PFC_PIN_GROUP(mmc0_data4), | |
3056 | SH_PFC_PIN_GROUP(mmc0_data8), | |
3057 | SH_PFC_PIN_GROUP(mmc0_ctrl), | |
3058 | SH_PFC_PIN_GROUP(mmc1_data1), | |
3059 | SH_PFC_PIN_GROUP(mmc1_data4), | |
3060 | SH_PFC_PIN_GROUP(mmc1_data8), | |
3061 | SH_PFC_PIN_GROUP(mmc1_ctrl), | |
4f47cc5e KH |
3062 | SH_PFC_PIN_GROUP(msiof0_clk), |
3063 | SH_PFC_PIN_GROUP(msiof0_sync), | |
3064 | SH_PFC_PIN_GROUP(msiof0_ss1), | |
3065 | SH_PFC_PIN_GROUP(msiof0_ss2), | |
3066 | SH_PFC_PIN_GROUP(msiof0_rx), | |
3067 | SH_PFC_PIN_GROUP(msiof0_tx), | |
3068 | SH_PFC_PIN_GROUP(msiof1_clk), | |
3069 | SH_PFC_PIN_GROUP(msiof1_sync), | |
3070 | SH_PFC_PIN_GROUP(msiof1_ss1), | |
3071 | SH_PFC_PIN_GROUP(msiof1_ss2), | |
3072 | SH_PFC_PIN_GROUP(msiof1_rx), | |
3073 | SH_PFC_PIN_GROUP(msiof1_tx), | |
3074 | SH_PFC_PIN_GROUP(msiof2_clk), | |
3075 | SH_PFC_PIN_GROUP(msiof2_sync), | |
3076 | SH_PFC_PIN_GROUP(msiof2_ss1), | |
3077 | SH_PFC_PIN_GROUP(msiof2_ss2), | |
3078 | SH_PFC_PIN_GROUP(msiof2_rx), | |
3079 | SH_PFC_PIN_GROUP(msiof2_tx), | |
3080 | SH_PFC_PIN_GROUP(msiof3_clk), | |
3081 | SH_PFC_PIN_GROUP(msiof3_sync), | |
3082 | SH_PFC_PIN_GROUP(msiof3_ss1), | |
3083 | SH_PFC_PIN_GROUP(msiof3_ss2), | |
3084 | SH_PFC_PIN_GROUP(msiof3_rx), | |
3085 | SH_PFC_PIN_GROUP(msiof3_tx), | |
45c6c85d LP |
3086 | SH_PFC_PIN_GROUP(scif0_data), |
3087 | SH_PFC_PIN_GROUP(scif0_clk), | |
3088 | SH_PFC_PIN_GROUP(scif0_ctrl), | |
3089 | SH_PFC_PIN_GROUP(scif0_data_b), | |
3090 | SH_PFC_PIN_GROUP(scif1_data), | |
3091 | SH_PFC_PIN_GROUP(scif1_clk), | |
3092 | SH_PFC_PIN_GROUP(scif1_ctrl), | |
3093 | SH_PFC_PIN_GROUP(scif1_data_b), | |
3094 | SH_PFC_PIN_GROUP(scif1_data_c), | |
3095 | SH_PFC_PIN_GROUP(scif1_data_d), | |
3096 | SH_PFC_PIN_GROUP(scif1_clk_d), | |
3097 | SH_PFC_PIN_GROUP(scif1_data_e), | |
3098 | SH_PFC_PIN_GROUP(scif1_clk_e), | |
2dbe7f2c LP |
3099 | SH_PFC_PIN_GROUP(scif2_data), |
3100 | SH_PFC_PIN_GROUP(scif2_clk), | |
3101 | SH_PFC_PIN_GROUP(scif2_data_b), | |
45c6c85d LP |
3102 | SH_PFC_PIN_GROUP(scifa0_data), |
3103 | SH_PFC_PIN_GROUP(scifa0_clk), | |
3104 | SH_PFC_PIN_GROUP(scifa0_ctrl), | |
3105 | SH_PFC_PIN_GROUP(scifa0_data_b), | |
3106 | SH_PFC_PIN_GROUP(scifa0_clk_b), | |
3107 | SH_PFC_PIN_GROUP(scifa0_ctrl_b), | |
3108 | SH_PFC_PIN_GROUP(scifa1_data), | |
3109 | SH_PFC_PIN_GROUP(scifa1_clk), | |
3110 | SH_PFC_PIN_GROUP(scifa1_ctrl), | |
3111 | SH_PFC_PIN_GROUP(scifa1_data_b), | |
3112 | SH_PFC_PIN_GROUP(scifa1_clk_b), | |
3113 | SH_PFC_PIN_GROUP(scifa1_ctrl_b), | |
3114 | SH_PFC_PIN_GROUP(scifa1_data_c), | |
3115 | SH_PFC_PIN_GROUP(scifa1_clk_c), | |
3116 | SH_PFC_PIN_GROUP(scifa1_ctrl_c), | |
3117 | SH_PFC_PIN_GROUP(scifa1_data_d), | |
3118 | SH_PFC_PIN_GROUP(scifa1_clk_d), | |
3119 | SH_PFC_PIN_GROUP(scifa1_ctrl_d), | |
3120 | SH_PFC_PIN_GROUP(scifa2_data), | |
3121 | SH_PFC_PIN_GROUP(scifa2_clk), | |
3122 | SH_PFC_PIN_GROUP(scifa2_ctrl), | |
3123 | SH_PFC_PIN_GROUP(scifa2_data_b), | |
3124 | SH_PFC_PIN_GROUP(scifa2_data_c), | |
3125 | SH_PFC_PIN_GROUP(scifa2_clk_c), | |
3126 | SH_PFC_PIN_GROUP(scifb0_data), | |
3127 | SH_PFC_PIN_GROUP(scifb0_clk), | |
3128 | SH_PFC_PIN_GROUP(scifb0_ctrl), | |
3129 | SH_PFC_PIN_GROUP(scifb0_data_b), | |
3130 | SH_PFC_PIN_GROUP(scifb0_clk_b), | |
3131 | SH_PFC_PIN_GROUP(scifb0_ctrl_b), | |
3132 | SH_PFC_PIN_GROUP(scifb0_data_c), | |
3133 | SH_PFC_PIN_GROUP(scifb1_data), | |
3134 | SH_PFC_PIN_GROUP(scifb1_clk), | |
3135 | SH_PFC_PIN_GROUP(scifb1_ctrl), | |
3136 | SH_PFC_PIN_GROUP(scifb1_data_b), | |
3137 | SH_PFC_PIN_GROUP(scifb1_clk_b), | |
3138 | SH_PFC_PIN_GROUP(scifb1_ctrl_b), | |
3139 | SH_PFC_PIN_GROUP(scifb1_data_c), | |
3140 | SH_PFC_PIN_GROUP(scifb1_data_d), | |
3141 | SH_PFC_PIN_GROUP(scifb1_data_e), | |
3142 | SH_PFC_PIN_GROUP(scifb1_clk_e), | |
3143 | SH_PFC_PIN_GROUP(scifb1_data_f), | |
3144 | SH_PFC_PIN_GROUP(scifb1_data_g), | |
3145 | SH_PFC_PIN_GROUP(scifb1_clk_g), | |
3146 | SH_PFC_PIN_GROUP(scifb2_data), | |
3147 | SH_PFC_PIN_GROUP(scifb2_clk), | |
3148 | SH_PFC_PIN_GROUP(scifb2_ctrl), | |
3149 | SH_PFC_PIN_GROUP(scifb2_data_b), | |
3150 | SH_PFC_PIN_GROUP(scifb2_clk_b), | |
3151 | SH_PFC_PIN_GROUP(scifb2_ctrl_b), | |
3152 | SH_PFC_PIN_GROUP(scifb2_data_c), | |
066f0d6e GL |
3153 | SH_PFC_PIN_GROUP(sdhi0_data1), |
3154 | SH_PFC_PIN_GROUP(sdhi0_data4), | |
3155 | SH_PFC_PIN_GROUP(sdhi0_ctrl), | |
3156 | SH_PFC_PIN_GROUP(sdhi0_cd), | |
3157 | SH_PFC_PIN_GROUP(sdhi0_wp), | |
3158 | SH_PFC_PIN_GROUP(sdhi1_data1), | |
3159 | SH_PFC_PIN_GROUP(sdhi1_data4), | |
3160 | SH_PFC_PIN_GROUP(sdhi1_ctrl), | |
3161 | SH_PFC_PIN_GROUP(sdhi1_cd), | |
3162 | SH_PFC_PIN_GROUP(sdhi1_wp), | |
3163 | SH_PFC_PIN_GROUP(sdhi2_data1), | |
3164 | SH_PFC_PIN_GROUP(sdhi2_data4), | |
3165 | SH_PFC_PIN_GROUP(sdhi2_ctrl), | |
3166 | SH_PFC_PIN_GROUP(sdhi2_cd), | |
3167 | SH_PFC_PIN_GROUP(sdhi2_wp), | |
3168 | SH_PFC_PIN_GROUP(sdhi3_data1), | |
3169 | SH_PFC_PIN_GROUP(sdhi3_data4), | |
3170 | SH_PFC_PIN_GROUP(sdhi3_ctrl), | |
3171 | SH_PFC_PIN_GROUP(sdhi3_cd), | |
3172 | SH_PFC_PIN_GROUP(sdhi3_wp), | |
fbd0ca3d UH |
3173 | SH_PFC_PIN_GROUP(tpu0_to0), |
3174 | SH_PFC_PIN_GROUP(tpu0_to1), | |
3175 | SH_PFC_PIN_GROUP(tpu0_to2), | |
3176 | SH_PFC_PIN_GROUP(tpu0_to3), | |
dac896e2 SU |
3177 | SH_PFC_PIN_GROUP(usb0), |
3178 | SH_PFC_PIN_GROUP(usb1), | |
3179 | SH_PFC_PIN_GROUP(usb2), | |
e120cacf SU |
3180 | SH_PFC_PIN_GROUP(vin0_data_g), |
3181 | SH_PFC_PIN_GROUP(vin0_data_r), | |
3182 | SH_PFC_PIN_GROUP(vin0_data_b), | |
3183 | SH_PFC_PIN_GROUP(vin0_hsync_signal), | |
3184 | SH_PFC_PIN_GROUP(vin0_vsync_signal), | |
3185 | SH_PFC_PIN_GROUP(vin0_field_signal), | |
3186 | SH_PFC_PIN_GROUP(vin0_data_enable), | |
3187 | SH_PFC_PIN_GROUP(vin0_clk), | |
3188 | SH_PFC_PIN_GROUP(vin1_data), | |
3189 | SH_PFC_PIN_GROUP(vin1_clk), | |
1627769b LP |
3190 | }; |
3191 | ||
62783b71 LP |
3192 | static const char * const du_groups[] = { |
3193 | "du_rgb666", | |
3194 | "du_rgb888", | |
3195 | "du_clk_out_0", | |
3196 | "du_clk_out_1", | |
3197 | "du_sync_0", | |
3198 | "du_sync_1", | |
3199 | "du_cde", | |
3200 | }; | |
3201 | ||
3202 | static const char * const du0_groups[] = { | |
3203 | "du0_clk_in", | |
3204 | }; | |
3205 | ||
3206 | static const char * const du1_groups[] = { | |
3207 | "du1_clk_in", | |
3208 | }; | |
3209 | ||
3210 | static const char * const du2_groups[] = { | |
3211 | "du2_clk_in", | |
3212 | }; | |
3213 | ||
1627769b LP |
3214 | static const char * const eth_groups[] = { |
3215 | "eth_link", | |
3216 | "eth_magic", | |
3217 | "eth_mdio", | |
3218 | "eth_rmii", | |
3219 | }; | |
3220 | ||
457c11d3 LP |
3221 | static const char * const hscif0_groups[] = { |
3222 | "hscif0_data", | |
3223 | "hscif0_clk", | |
3224 | "hscif0_ctrl", | |
3225 | "hscif0_data_b", | |
3226 | "hscif0_ctrl_b", | |
3227 | "hscif0_data_c", | |
3228 | "hscif0_ctrl_c", | |
3229 | "hscif0_data_d", | |
3230 | "hscif0_ctrl_d", | |
3231 | "hscif0_data_e", | |
3232 | "hscif0_ctrl_e", | |
3233 | "hscif0_data_f", | |
3234 | "hscif0_ctrl_f", | |
3235 | }; | |
3236 | ||
3237 | static const char * const hscif1_groups[] = { | |
3238 | "hscif1_data", | |
3239 | "hscif1_clk", | |
3240 | "hscif1_ctrl", | |
3241 | "hscif1_data_b", | |
3242 | "hscif1_clk_b", | |
3243 | "hscif1_ctrl_b", | |
3244 | }; | |
3245 | ||
04e7ce78 LP |
3246 | static const char * const intc_groups[] = { |
3247 | "intc_irq0", | |
3248 | "intc_irq1", | |
3249 | "intc_irq2", | |
3250 | "intc_irq3", | |
3251 | }; | |
45c6c85d | 3252 | |
457c11d3 LP |
3253 | static const char * const mmc0_groups[] = { |
3254 | "mmc0_data1", | |
3255 | "mmc0_data4", | |
3256 | "mmc0_data8", | |
3257 | "mmc0_ctrl", | |
3258 | }; | |
3259 | ||
3260 | static const char * const mmc1_groups[] = { | |
3261 | "mmc1_data1", | |
3262 | "mmc1_data4", | |
3263 | "mmc1_data8", | |
3264 | "mmc1_ctrl", | |
3265 | }; | |
3266 | ||
4f47cc5e KH |
3267 | static const char * const msiof0_groups[] = { |
3268 | "msiof0_clk", | |
3269 | "msiof0_sync", | |
3270 | "msiof0_ss1", | |
3271 | "msiof0_ss2", | |
3272 | "msiof0_rx", | |
3273 | "msiof0_tx", | |
3274 | }; | |
3275 | ||
3276 | static const char * const msiof1_groups[] = { | |
3277 | "msiof1_clk", | |
3278 | "msiof1_sync", | |
3279 | "msiof1_ss1", | |
3280 | "msiof1_ss2", | |
3281 | "msiof1_rx", | |
3282 | "msiof1_tx", | |
3283 | }; | |
3284 | ||
3285 | static const char * const msiof2_groups[] = { | |
3286 | "msiof2_clk", | |
3287 | "msiof2_sync", | |
3288 | "msiof2_ss1", | |
3289 | "msiof2_ss2", | |
3290 | "msiof2_rx", | |
3291 | "msiof2_tx", | |
3292 | }; | |
3293 | ||
3294 | static const char * const msiof3_groups[] = { | |
3295 | "msiof3_clk", | |
3296 | "msiof3_sync", | |
3297 | "msiof3_ss1", | |
3298 | "msiof3_ss2", | |
3299 | "msiof3_rx", | |
3300 | "msiof3_tx", | |
3301 | }; | |
3302 | ||
45c6c85d LP |
3303 | static const char * const scif0_groups[] = { |
3304 | "scif0_data", | |
3305 | "scif0_clk", | |
3306 | "scif0_ctrl", | |
3307 | "scif0_data_b", | |
3308 | }; | |
3309 | ||
3310 | static const char * const scif1_groups[] = { | |
3311 | "scif1_data", | |
3312 | "scif1_clk", | |
3313 | "scif1_ctrl", | |
3314 | "scif1_data_b", | |
3315 | "scif1_data_c", | |
3316 | "scif1_data_d", | |
3317 | "scif1_clk_d", | |
3318 | "scif1_data_e", | |
3319 | "scif1_clk_e", | |
3320 | }; | |
3321 | ||
2dbe7f2c LP |
3322 | static const char * const scif2_groups[] = { |
3323 | "scif2_data", | |
3324 | "scif2_clk", | |
3325 | "scif2_data_b", | |
fbd0ca3d UH |
3326 | }; |
3327 | ||
45c6c85d LP |
3328 | static const char * const scifa0_groups[] = { |
3329 | "scifa0_data", | |
3330 | "scifa0_clk", | |
3331 | "scifa0_ctrl", | |
3332 | "scifa0_data_b", | |
3333 | "scifa0_clk_b", | |
3334 | "scifa0_ctrl_b", | |
3335 | }; | |
3336 | ||
3337 | static const char * const scifa1_groups[] = { | |
3338 | "scifa1_data", | |
3339 | "scifa1_clk", | |
3340 | "scifa1_ctrl", | |
3341 | "scifa1_data_b", | |
3342 | "scifa1_clk_b", | |
3343 | "scifa1_ctrl_b", | |
3344 | "scifa1_data_c", | |
3345 | "scifa1_clk_c", | |
3346 | "scifa1_ctrl_c", | |
3347 | "scifa1_data_d", | |
3348 | "scifa1_clk_d", | |
3349 | "scifa1_ctrl_d", | |
3350 | }; | |
3351 | ||
3352 | static const char * const scifa2_groups[] = { | |
3353 | "scifa2_data", | |
3354 | "scifa2_clk", | |
3355 | "scifa2_ctrl", | |
3356 | "scifa2_data_b", | |
3357 | "scifa2_data_c", | |
3358 | "scifa2_clk_c", | |
3359 | }; | |
3360 | ||
3361 | static const char * const scifb0_groups[] = { | |
3362 | "scifb0_data", | |
3363 | "scifb0_clk", | |
3364 | "scifb0_ctrl", | |
3365 | "scifb0_data_b", | |
3366 | "scifb0_clk_b", | |
3367 | "scifb0_ctrl_b", | |
3368 | "scifb0_data_c", | |
3369 | }; | |
3370 | ||
3371 | static const char * const scifb1_groups[] = { | |
3372 | "scifb1_data", | |
3373 | "scifb1_clk", | |
3374 | "scifb1_ctrl", | |
3375 | "scifb1_data_b", | |
3376 | "scifb1_clk_b", | |
3377 | "scifb1_ctrl_b", | |
3378 | "scifb1_data_c", | |
3379 | "scifb1_data_d", | |
3380 | "scifb1_data_e", | |
3381 | "scifb1_clk_e", | |
3382 | "scifb1_data_f", | |
3383 | "scifb1_data_g", | |
3384 | "scifb1_clk_g", | |
3385 | }; | |
3386 | ||
3387 | static const char * const scifb2_groups[] = { | |
3388 | "scifb2_data", | |
3389 | "scifb2_clk", | |
3390 | "scifb2_ctrl", | |
3391 | "scifb2_data_b", | |
3392 | "scifb2_clk_b", | |
3393 | "scifb2_ctrl_b", | |
3394 | "scifb2_data_c", | |
3395 | }; | |
3396 | ||
066f0d6e GL |
3397 | static const char * const sdhi0_groups[] = { |
3398 | "sdhi0_data1", | |
3399 | "sdhi0_data4", | |
3400 | "sdhi0_ctrl", | |
3401 | "sdhi0_cd", | |
3402 | "sdhi0_wp", | |
3403 | }; | |
3404 | ||
3405 | static const char * const sdhi1_groups[] = { | |
3406 | "sdhi1_data1", | |
3407 | "sdhi1_data4", | |
3408 | "sdhi1_ctrl", | |
3409 | "sdhi1_cd", | |
3410 | "sdhi1_wp", | |
3411 | }; | |
3412 | ||
3413 | static const char * const sdhi2_groups[] = { | |
3414 | "sdhi2_data1", | |
3415 | "sdhi2_data4", | |
3416 | "sdhi2_ctrl", | |
3417 | "sdhi2_cd", | |
3418 | "sdhi2_wp", | |
3419 | }; | |
3420 | ||
3421 | static const char * const sdhi3_groups[] = { | |
3422 | "sdhi3_data1", | |
3423 | "sdhi3_data4", | |
3424 | "sdhi3_ctrl", | |
3425 | "sdhi3_cd", | |
3426 | "sdhi3_wp", | |
3427 | }; | |
3428 | ||
457c11d3 LP |
3429 | static const char * const tpu0_groups[] = { |
3430 | "tpu0_to0", | |
3431 | "tpu0_to1", | |
3432 | "tpu0_to2", | |
3433 | "tpu0_to3", | |
3434 | }; | |
3435 | ||
dac896e2 SU |
3436 | static const char * const usb0_groups[] = { |
3437 | "usb0", | |
3438 | }; | |
3439 | ||
3440 | static const char * const usb1_groups[] = { | |
3441 | "usb1", | |
3442 | }; | |
3443 | ||
3444 | static const char * const usb2_groups[] = { | |
3445 | "usb2", | |
3446 | }; | |
3447 | ||
e120cacf SU |
3448 | static const char * const vin0_groups[] = { |
3449 | "vin0_data_g", | |
3450 | "vin0_data_r", | |
3451 | "vin0_data_b", | |
3452 | "vin0_hsync_signal", | |
3453 | "vin0_vsync_signal", | |
3454 | "vin0_field_signal", | |
3455 | "vin0_data_enable", | |
3456 | "vin0_clk", | |
3457 | }; | |
3458 | ||
3459 | static const char * const vin1_groups[] = { | |
3460 | "vin1_data", | |
3461 | "vin1_clk", | |
3462 | }; | |
3463 | ||
1627769b | 3464 | static const struct sh_pfc_function pinmux_functions[] = { |
62783b71 LP |
3465 | SH_PFC_FUNCTION(du), |
3466 | SH_PFC_FUNCTION(du0), | |
3467 | SH_PFC_FUNCTION(du1), | |
3468 | SH_PFC_FUNCTION(du2), | |
1627769b | 3469 | SH_PFC_FUNCTION(eth), |
fbd0ca3d UH |
3470 | SH_PFC_FUNCTION(hscif0), |
3471 | SH_PFC_FUNCTION(hscif1), | |
04e7ce78 | 3472 | SH_PFC_FUNCTION(intc), |
fbd0ca3d UH |
3473 | SH_PFC_FUNCTION(mmc0), |
3474 | SH_PFC_FUNCTION(mmc1), | |
4f47cc5e KH |
3475 | SH_PFC_FUNCTION(msiof0), |
3476 | SH_PFC_FUNCTION(msiof1), | |
3477 | SH_PFC_FUNCTION(msiof2), | |
3478 | SH_PFC_FUNCTION(msiof3), | |
45c6c85d LP |
3479 | SH_PFC_FUNCTION(scif0), |
3480 | SH_PFC_FUNCTION(scif1), | |
2dbe7f2c | 3481 | SH_PFC_FUNCTION(scif2), |
45c6c85d LP |
3482 | SH_PFC_FUNCTION(scifa0), |
3483 | SH_PFC_FUNCTION(scifa1), | |
3484 | SH_PFC_FUNCTION(scifa2), | |
3485 | SH_PFC_FUNCTION(scifb0), | |
3486 | SH_PFC_FUNCTION(scifb1), | |
3487 | SH_PFC_FUNCTION(scifb2), | |
066f0d6e GL |
3488 | SH_PFC_FUNCTION(sdhi0), |
3489 | SH_PFC_FUNCTION(sdhi1), | |
3490 | SH_PFC_FUNCTION(sdhi2), | |
3491 | SH_PFC_FUNCTION(sdhi3), | |
fbd0ca3d | 3492 | SH_PFC_FUNCTION(tpu0), |
dac896e2 SU |
3493 | SH_PFC_FUNCTION(usb0), |
3494 | SH_PFC_FUNCTION(usb1), | |
3495 | SH_PFC_FUNCTION(usb2), | |
e120cacf SU |
3496 | SH_PFC_FUNCTION(vin0), |
3497 | SH_PFC_FUNCTION(vin1), | |
1627769b LP |
3498 | }; |
3499 | ||
58c229e1 KM |
3500 | static struct pinmux_cfg_reg pinmux_config_regs[] = { |
3501 | { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { | |
3502 | GP_0_31_FN, FN_IP3_17_15, | |
3503 | GP_0_30_FN, FN_IP3_14_12, | |
3504 | GP_0_29_FN, FN_IP3_11_8, | |
3505 | GP_0_28_FN, FN_IP3_7_4, | |
3506 | GP_0_27_FN, FN_IP3_3_0, | |
3507 | GP_0_26_FN, FN_IP2_28_26, | |
3508 | GP_0_25_FN, FN_IP2_25_22, | |
3509 | GP_0_24_FN, FN_IP2_21_18, | |
3510 | GP_0_23_FN, FN_IP2_17_15, | |
3511 | GP_0_22_FN, FN_IP2_14_12, | |
3512 | GP_0_21_FN, FN_IP2_11_9, | |
3513 | GP_0_20_FN, FN_IP2_8_6, | |
3514 | GP_0_19_FN, FN_IP2_5_3, | |
3515 | GP_0_18_FN, FN_IP2_2_0, | |
3516 | GP_0_17_FN, FN_IP1_29_28, | |
3517 | GP_0_16_FN, FN_IP1_27_26, | |
3518 | GP_0_15_FN, FN_IP1_25_22, | |
3519 | GP_0_14_FN, FN_IP1_21_18, | |
3520 | GP_0_13_FN, FN_IP1_17_15, | |
3521 | GP_0_12_FN, FN_IP1_14_12, | |
3522 | GP_0_11_FN, FN_IP1_11_8, | |
3523 | GP_0_10_FN, FN_IP1_7_4, | |
3524 | GP_0_9_FN, FN_IP1_3_0, | |
3525 | GP_0_8_FN, FN_IP0_30_27, | |
3526 | GP_0_7_FN, FN_IP0_26_23, | |
3527 | GP_0_6_FN, FN_IP0_22_20, | |
3528 | GP_0_5_FN, FN_IP0_19_16, | |
3529 | GP_0_4_FN, FN_IP0_15_12, | |
3530 | GP_0_3_FN, FN_IP0_11_9, | |
3531 | GP_0_2_FN, FN_IP0_8_6, | |
3532 | GP_0_1_FN, FN_IP0_5_3, | |
3533 | GP_0_0_FN, FN_IP0_2_0 } | |
3534 | }, | |
3535 | { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { | |
3536 | 0, 0, | |
3537 | 0, 0, | |
3538 | GP_1_29_FN, FN_IP6_13_11, | |
3539 | GP_1_28_FN, FN_IP6_10_9, | |
3540 | GP_1_27_FN, FN_IP6_8_6, | |
3541 | GP_1_26_FN, FN_IP6_5_3, | |
3542 | GP_1_25_FN, FN_IP6_2_0, | |
3543 | GP_1_24_FN, FN_IP5_29_27, | |
3544 | GP_1_23_FN, FN_IP5_26_24, | |
3545 | GP_1_22_FN, FN_IP5_23_21, | |
3546 | GP_1_21_FN, FN_IP5_20_18, | |
3547 | GP_1_20_FN, FN_IP5_17_15, | |
3548 | GP_1_19_FN, FN_IP5_14_13, | |
3549 | GP_1_18_FN, FN_IP5_12_10, | |
3550 | GP_1_17_FN, FN_IP5_9_6, | |
3551 | GP_1_16_FN, FN_IP5_5_3, | |
3552 | GP_1_15_FN, FN_IP5_2_0, | |
3553 | GP_1_14_FN, FN_IP4_29_27, | |
3554 | GP_1_13_FN, FN_IP4_26_24, | |
3555 | GP_1_12_FN, FN_IP4_23_21, | |
3556 | GP_1_11_FN, FN_IP4_20_18, | |
3557 | GP_1_10_FN, FN_IP4_17_15, | |
3558 | GP_1_9_FN, FN_IP4_14_12, | |
3559 | GP_1_8_FN, FN_IP4_11_9, | |
3560 | GP_1_7_FN, FN_IP4_8_6, | |
3561 | GP_1_6_FN, FN_IP4_5_3, | |
3562 | GP_1_5_FN, FN_IP4_2_0, | |
3563 | GP_1_4_FN, FN_IP3_31_29, | |
3564 | GP_1_3_FN, FN_IP3_28_26, | |
3565 | GP_1_2_FN, FN_IP3_25_23, | |
3566 | GP_1_1_FN, FN_IP3_22_20, | |
3567 | GP_1_0_FN, FN_IP3_19_18, } | |
3568 | }, | |
3569 | { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { | |
3570 | 0, 0, | |
3571 | 0, 0, | |
3572 | GP_2_29_FN, FN_IP7_15_13, | |
3573 | GP_2_28_FN, FN_IP7_12_10, | |
3574 | GP_2_27_FN, FN_IP7_9_8, | |
3575 | GP_2_26_FN, FN_IP7_7_6, | |
3576 | GP_2_25_FN, FN_IP7_5_3, | |
3577 | GP_2_24_FN, FN_IP7_2_0, | |
3578 | GP_2_23_FN, FN_IP6_31_29, | |
3579 | GP_2_22_FN, FN_IP6_28_26, | |
3580 | GP_2_21_FN, FN_IP6_25_23, | |
3581 | GP_2_20_FN, FN_IP6_22_20, | |
3582 | GP_2_19_FN, FN_IP6_19_17, | |
3583 | GP_2_18_FN, FN_IP6_16_14, | |
3584 | GP_2_17_FN, FN_VI1_DATA7_VI1_B7, | |
3585 | GP_2_16_FN, FN_IP8_27, | |
3586 | GP_2_15_FN, FN_IP8_26, | |
3587 | GP_2_14_FN, FN_IP8_25_24, | |
3588 | GP_2_13_FN, FN_IP8_23_22, | |
3589 | GP_2_12_FN, FN_IP8_21_20, | |
3590 | GP_2_11_FN, FN_IP8_19_18, | |
3591 | GP_2_10_FN, FN_IP8_17_16, | |
3592 | GP_2_9_FN, FN_IP8_15_14, | |
3593 | GP_2_8_FN, FN_IP8_13_12, | |
3594 | GP_2_7_FN, FN_IP8_11_10, | |
3595 | GP_2_6_FN, FN_IP8_9_8, | |
3596 | GP_2_5_FN, FN_IP8_7_6, | |
3597 | GP_2_4_FN, FN_IP8_5_4, | |
3598 | GP_2_3_FN, FN_IP8_3_2, | |
3599 | GP_2_2_FN, FN_IP8_1_0, | |
3600 | GP_2_1_FN, FN_IP7_30_29, | |
3601 | GP_2_0_FN, FN_IP7_28_27 } | |
3602 | }, | |
3603 | { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { | |
3604 | GP_3_31_FN, FN_IP11_21_18, | |
3605 | GP_3_30_FN, FN_IP11_17_15, | |
3606 | GP_3_29_FN, FN_IP11_14_13, | |
3607 | GP_3_28_FN, FN_IP11_12_11, | |
3608 | GP_3_27_FN, FN_IP11_10_9, | |
3609 | GP_3_26_FN, FN_IP11_8_7, | |
3610 | GP_3_25_FN, FN_IP11_6_5, | |
3611 | GP_3_24_FN, FN_IP11_4, | |
3612 | GP_3_23_FN, FN_IP11_3_0, | |
3613 | GP_3_22_FN, FN_IP10_29_26, | |
3614 | GP_3_21_FN, FN_IP10_25_23, | |
3615 | GP_3_20_FN, FN_IP10_22_19, | |
3616 | GP_3_19_FN, FN_IP10_18_15, | |
3617 | GP_3_18_FN, FN_IP10_14_11, | |
3618 | GP_3_17_FN, FN_IP10_10_7, | |
3619 | GP_3_16_FN, FN_IP10_6_4, | |
3620 | GP_3_15_FN, FN_IP10_3_0, | |
3621 | GP_3_14_FN, FN_IP9_31_28, | |
3622 | GP_3_13_FN, FN_IP9_27_26, | |
3623 | GP_3_12_FN, FN_IP9_25_24, | |
3624 | GP_3_11_FN, FN_IP9_23_22, | |
3625 | GP_3_10_FN, FN_IP9_21_20, | |
3626 | GP_3_9_FN, FN_IP9_19_18, | |
3627 | GP_3_8_FN, FN_IP9_17_16, | |
3628 | GP_3_7_FN, FN_IP9_15_12, | |
3629 | GP_3_6_FN, FN_IP9_11_8, | |
3630 | GP_3_5_FN, FN_IP9_7_6, | |
3631 | GP_3_4_FN, FN_IP9_5_4, | |
3632 | GP_3_3_FN, FN_IP9_3_2, | |
3633 | GP_3_2_FN, FN_IP9_1_0, | |
3634 | GP_3_1_FN, FN_IP8_30_29, | |
3635 | GP_3_0_FN, FN_IP8_28 } | |
3636 | }, | |
3637 | { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { | |
3638 | GP_4_31_FN, FN_IP14_18_16, | |
3639 | GP_4_30_FN, FN_IP14_15_12, | |
3640 | GP_4_29_FN, FN_IP14_11_9, | |
3641 | GP_4_28_FN, FN_IP14_8_6, | |
3642 | GP_4_27_FN, FN_IP14_5_3, | |
3643 | GP_4_26_FN, FN_IP14_2_0, | |
3644 | GP_4_25_FN, FN_IP13_30_29, | |
3645 | GP_4_24_FN, FN_IP13_28_26, | |
3646 | GP_4_23_FN, FN_IP13_25_23, | |
3647 | GP_4_22_FN, FN_IP13_22_19, | |
3648 | GP_4_21_FN, FN_IP13_18_16, | |
3649 | GP_4_20_FN, FN_IP13_15_13, | |
3650 | GP_4_19_FN, FN_IP13_12_10, | |
3651 | GP_4_18_FN, FN_IP13_9_7, | |
3652 | GP_4_17_FN, FN_IP13_6_3, | |
3653 | GP_4_16_FN, FN_IP13_2_0, | |
3654 | GP_4_15_FN, FN_IP12_30_28, | |
3655 | GP_4_14_FN, FN_IP12_27_25, | |
3656 | GP_4_13_FN, FN_IP12_24_23, | |
3657 | GP_4_12_FN, FN_IP12_22_20, | |
3658 | GP_4_11_FN, FN_IP12_19_17, | |
3659 | GP_4_10_FN, FN_IP12_16_14, | |
3660 | GP_4_9_FN, FN_IP12_13_11, | |
3661 | GP_4_8_FN, FN_IP12_10_8, | |
3662 | GP_4_7_FN, FN_IP12_7_6, | |
3663 | GP_4_6_FN, FN_IP12_5_4, | |
3664 | GP_4_5_FN, FN_IP12_3_2, | |
3665 | GP_4_4_FN, FN_IP12_1_0, | |
3666 | GP_4_3_FN, FN_IP11_31_30, | |
3667 | GP_4_2_FN, FN_IP11_29_27, | |
3668 | GP_4_1_FN, FN_IP11_26_24, | |
3669 | GP_4_0_FN, FN_IP11_23_22 } | |
3670 | }, | |
3671 | { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { | |
3672 | GP_5_31_FN, FN_IP7_24_22, | |
3673 | GP_5_30_FN, FN_IP7_21_19, | |
3674 | GP_5_29_FN, FN_IP7_18_16, | |
3675 | GP_5_28_FN, FN_DU_DOTCLKIN2, | |
3676 | GP_5_27_FN, FN_IP7_26_25, | |
3677 | GP_5_26_FN, FN_DU_DOTCLKIN0, | |
3678 | GP_5_25_FN, FN_AVS2, | |
3679 | GP_5_24_FN, FN_AVS1, | |
3680 | GP_5_23_FN, FN_USB2_OVC, | |
3681 | GP_5_22_FN, FN_USB2_PWEN, | |
3682 | GP_5_21_FN, FN_IP16_7, | |
3683 | GP_5_20_FN, FN_IP16_6, | |
3684 | GP_5_19_FN, FN_USB0_OVC_VBUS, | |
3685 | GP_5_18_FN, FN_USB0_PWEN, | |
3686 | GP_5_17_FN, FN_IP16_5_3, | |
3687 | GP_5_16_FN, FN_IP16_2_0, | |
3688 | GP_5_15_FN, FN_IP15_29_28, | |
3689 | GP_5_14_FN, FN_IP15_27_26, | |
3690 | GP_5_13_FN, FN_IP15_25_23, | |
3691 | GP_5_12_FN, FN_IP15_22_20, | |
3692 | GP_5_11_FN, FN_IP15_19_18, | |
3693 | GP_5_10_FN, FN_IP15_17_16, | |
3694 | GP_5_9_FN, FN_IP15_15_14, | |
3695 | GP_5_8_FN, FN_IP15_13_12, | |
3696 | GP_5_7_FN, FN_IP15_11_9, | |
3697 | GP_5_6_FN, FN_IP15_8_6, | |
3698 | GP_5_5_FN, FN_IP15_5_3, | |
3699 | GP_5_4_FN, FN_IP15_2_0, | |
3700 | GP_5_3_FN, FN_IP14_30_28, | |
3701 | GP_5_2_FN, FN_IP14_27_25, | |
3702 | GP_5_1_FN, FN_IP14_24_22, | |
3703 | GP_5_0_FN, FN_IP14_21_19 } | |
3704 | }, | |
3705 | { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, | |
3706 | 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { | |
3707 | /* IP0_31 [1] */ | |
3708 | 0, 0, | |
3709 | /* IP0_30_27 [4] */ | |
9f2edd41 | 3710 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, |
58c229e1 KM |
3711 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, |
3712 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
3713 | /* IP0_26_23 [4] */ | |
c4721249 SK |
3714 | FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, |
3715 | FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, | |
05bcb07b | 3716 | FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, |
58c229e1 | 3717 | /* IP0_22_20 [3] */ |
c4721249 SK |
3718 | FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
3719 | FN_I2C2_SCL_C, 0, 0, | |
58c229e1 KM |
3720 | /* IP0_19_16 [4] */ |
3721 | FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, | |
3722 | FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, | |
3723 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
3724 | /* IP0_15_12 [4] */ | |
3725 | FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, | |
3726 | FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, | |
3727 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
3728 | /* IP0_11_9 [3] */ | |
3729 | FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, | |
3730 | 0, 0, 0, | |
3731 | /* IP0_8_6 [3] */ | |
3732 | FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, | |
3733 | 0, 0, 0, | |
3734 | /* IP0_5_3 [3] */ | |
3735 | FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, | |
3736 | 0, 0, 0, | |
3737 | /* IP0_2_0 [3] */ | |
3738 | FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, | |
3739 | 0, 0, 0, } | |
3740 | }, | |
3741 | { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, | |
3742 | 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { | |
3743 | /* IP1_31_30 [2] */ | |
3744 | 0, 0, 0, 0, | |
3745 | /* IP1_29_28 [2] */ | |
3746 | FN_A1, FN_PWM4, 0, 0, | |
3747 | /* IP1_27_26 [2] */ | |
3748 | FN_A0, FN_PWM3, 0, 0, | |
3749 | /* IP1_25_22 [4] */ | |
3750 | FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, | |
3751 | FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, | |
3752 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
3753 | /* IP1_21_18 [4] */ | |
3754 | FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, | |
3755 | FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, | |
3756 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
3757 | /* IP1_17_15 [3] */ | |
3758 | FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, | |
3759 | FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, | |
3760 | 0, 0, 0, | |
3761 | /* IP1_14_12 [3] */ | |
3762 | FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, | |
3763 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, | |
3764 | 0, 0, | |
3765 | /* IP1_11_8 [4] */ | |
9f2edd41 | 3766 | FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, |
58c229e1 KM |
3767 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, |
3768 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
3769 | /* IP1_7_4 [4] */ | |
9f2edd41 | 3770 | FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, |
58c229e1 KM |
3771 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, |
3772 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
3773 | /* IP1_3_0 [4] */ | |
9f2edd41 | 3774 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, |
58c229e1 KM |
3775 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, |
3776 | 0, 0, 0, 0, 0, 0, 0, 0, 0, } | |
3777 | }, | |
3778 | { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, | |
3779 | 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { | |
3780 | /* IP2_31_29 [3] */ | |
3781 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3782 | /* IP2_28_26 [3] */ | |
3783 | FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, | |
3784 | FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, | |
3785 | /* IP2_25_22 [4] */ | |
3786 | FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, | |
1ddb66cd | 3787 | FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, |
58c229e1 KM |
3788 | 0, 0, 0, 0, 0, 0, 0, 0, |
3789 | /* IP2_21_18 [4] */ | |
3790 | FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, | |
1ddb66cd | 3791 | FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, |
58c229e1 KM |
3792 | 0, 0, 0, 0, 0, 0, 0, 0, |
3793 | /* IP2_17_15 [3] */ | |
3794 | FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, | |
3795 | 0, 0, 0, 0, | |
3796 | /* IP2_14_12 [3] */ | |
3797 | FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, | |
3798 | /* IP2_11_9 [3] */ | |
3799 | FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, | |
3800 | /* IP2_8_6 [3] */ | |
3801 | FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, | |
3802 | /* IP2_5_3 [3] */ | |
3803 | FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, | |
3804 | /* IP2_2_0 [3] */ | |
3805 | FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } | |
3806 | }, | |
3807 | { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, | |
3808 | 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { | |
3809 | /* IP3_31_29 [3] */ | |
3810 | FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, | |
3811 | 0, 0, 0, | |
3812 | /* IP3_28_26 [3] */ | |
3813 | FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, | |
3814 | 0, 0, 0, 0, | |
3815 | /* IP3_25_23 [3] */ | |
3816 | FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, | |
3817 | /* IP3_22_20 [3] */ | |
3818 | FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, | |
3819 | /* IP3_19_18 [2] */ | |
3820 | FN_A16, FN_ATAWR1_N, 0, 0, | |
3821 | /* IP3_17_15 [3] */ | |
3822 | FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, | |
3823 | 0, 0, 0, 0, | |
3824 | /* IP3_14_12 [3] */ | |
3825 | FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, | |
3826 | 0, 0, 0, 0, | |
3827 | /* IP3_11_8 [4] */ | |
3828 | FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, | |
3829 | FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, | |
3830 | FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, | |
3831 | /* IP3_7_4 [4] */ | |
3832 | FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, | |
3833 | FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, | |
3834 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
3835 | /* IP3_3_0 [4] */ | |
3836 | FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, | |
3837 | FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, | |
3838 | 0, 0, 0, 0, 0, 0, 0, 0, } | |
3839 | }, | |
3840 | { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, | |
3841 | 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | |
3842 | /* IP4_31_30 [2] */ | |
3843 | 0, 0, 0, 0, | |
3844 | /* IP4_29_27 [3] */ | |
3845 | FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, | |
3846 | FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, | |
3847 | /* IP4_26_24 [3] */ | |
3848 | FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, | |
3849 | FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, | |
3850 | /* IP4_23_21 [3] */ | |
3851 | FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, | |
3852 | FN_HTX0_B, FN_MSIOF0_SS1_B, 0, | |
3853 | /* IP4_20_18 [3] */ | |
3854 | FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, | |
3855 | FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, | |
3856 | /* IP4_17_15 [3] */ | |
3857 | FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, | |
3858 | 0, 0, 0, | |
3859 | /* IP4_14_12 [3] */ | |
3860 | FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, | |
3861 | FN_VI2_FIELD_B, 0, 0, | |
3862 | /* IP4_11_9 [3] */ | |
3863 | FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, | |
3864 | FN_VI2_CLKENB_B, 0, 0, | |
3865 | /* IP4_8_6 [3] */ | |
3866 | FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, | |
3867 | /* IP4_5_3 [3] */ | |
3868 | FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, | |
3869 | /* IP4_2_0 [3] */ | |
3870 | FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, | |
3871 | } | |
3872 | }, | |
3873 | { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, | |
3874 | 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { | |
3875 | /* IP5_31_30 [2] */ | |
3876 | 0, 0, 0, 0, | |
3877 | /* IP5_29_27 [3] */ | |
3878 | FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, | |
3879 | FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, | |
3880 | /* IP5_26_24 [3] */ | |
3881 | FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, | |
3882 | FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, | |
3883 | FN_MSIOF0_SCK_B, 0, | |
3884 | /* IP5_23_21 [3] */ | |
3885 | FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, | |
3886 | FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, | |
3887 | FN_IERX_C, 0, | |
3888 | /* IP5_20_18 [3] */ | |
3889 | FN_WE0_N, FN_IECLK, FN_CAN_CLK, | |
3890 | FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, | |
3891 | /* IP5_17_15 [3] */ | |
3892 | FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, | |
3893 | FN_INTC_IRQ4_N, 0, 0, | |
3894 | /* IP5_14_13 [2] */ | |
3895 | FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, | |
3896 | /* IP5_12_10 [3] */ | |
3897 | FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, | |
3898 | 0, 0, | |
3899 | /* IP5_9_6 [4] */ | |
3900 | FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, | |
c4721249 SK |
3901 | FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, |
3902 | FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, | |
58c229e1 KM |
3903 | /* IP5_5_3 [3] */ |
3904 | FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, | |
c4721249 SK |
3905 | FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, |
3906 | FN_INTC_EN0_N, FN_I2C1_SCL, | |
58c229e1 KM |
3907 | /* IP5_2_0 [3] */ |
3908 | FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, | |
3909 | FN_VI2_R3, 0, 0, } | |
3910 | }, | |
3911 | { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, | |
3912 | 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { | |
3913 | /* IP6_31_29 [3] */ | |
9f2edd41 | 3914 | FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, |
58c229e1 KM |
3915 | FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, |
3916 | /* IP6_28_26 [3] */ | |
9f2edd41 | 3917 | FN_ETH_LINK, 0, FN_HTX0_E, |
58c229e1 KM |
3918 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, |
3919 | /* IP6_25_23 [3] */ | |
9f2edd41 | 3920 | FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, |
58c229e1 KM |
3921 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, |
3922 | /* IP6_22_20 [3] */ | |
9f2edd41 | 3923 | FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, |
58c229e1 KM |
3924 | FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, |
3925 | /* IP6_19_17 [3] */ | |
9f2edd41 | 3926 | FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, |
c4721249 | 3927 | FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, |
58c229e1 | 3928 | /* IP6_16_14 [3] */ |
9f2edd41 | 3929 | FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, |
c4721249 SK |
3930 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, |
3931 | FN_I2C2_SCL_E, 0, | |
58c229e1 KM |
3932 | /* IP6_13_11 [3] */ |
3933 | FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, | |
3934 | FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, | |
3935 | /* IP6_10_9 [2] */ | |
3936 | FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, | |
3937 | /* IP6_8_6 [3] */ | |
3938 | FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, | |
3939 | FN_SSI_SDATA8_C, 0, 0, 0, | |
3940 | /* IP6_5_3 [3] */ | |
3941 | FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, | |
3942 | FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, | |
3943 | /* IP6_2_0 [3] */ | |
3944 | FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, | |
3945 | FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } | |
3946 | }, | |
3947 | { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, | |
3948 | 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { | |
3949 | /* IP7_31 [1] */ | |
3950 | 0, 0, | |
3951 | /* IP7_30_29 [2] */ | |
9f2edd41 | 3952 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, |
58c229e1 | 3953 | /* IP7_28_27 [2] */ |
9f2edd41 | 3954 | FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, |
58c229e1 | 3955 | /* IP7_26_25 [2] */ |
f0681209 | 3956 | FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, |
58c229e1 KM |
3957 | /* IP7_24_22 [3] */ |
3958 | FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, | |
3959 | 0, 0, 0, | |
3960 | /* IP7_21_19 [3] */ | |
3961 | FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, | |
3962 | FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, | |
3963 | /* IP7_18_16 [3] */ | |
3964 | FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, | |
3965 | FN_GLO_SS_C, 0, 0, 0, | |
3966 | /* IP7_15_13 [3] */ | |
9f2edd41 | 3967 | FN_ETH_MDC, 0, FN_STP_ISD_1_B, |
58c229e1 KM |
3968 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, |
3969 | /* IP7_12_10 [3] */ | |
9f2edd41 | 3970 | FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, |
58c229e1 KM |
3971 | FN_GLO_SCLK_C, 0, 0, 0, |
3972 | /* IP7_9_8 [2] */ | |
9f2edd41 | 3973 | FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, |
58c229e1 | 3974 | /* IP7_7_6 [2] */ |
9f2edd41 | 3975 | FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, |
58c229e1 | 3976 | /* IP7_5_3 [3] */ |
14da999b | 3977 | FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, |
58c229e1 | 3978 | /* IP7_2_0 [3] */ |
9f2edd41 | 3979 | FN_ETH_MDIO, 0, FN_HRTS0_N_E, |
58c229e1 KM |
3980 | FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } |
3981 | }, | |
3982 | { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, | |
3983 | 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, | |
3984 | 2, 2, 2, 2, 2, 2, 2) { | |
3985 | /* IP8_31 [1] */ | |
3986 | 0, 0, | |
3987 | /* IP8_30_29 [2] */ | |
3988 | FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, | |
3989 | /* IP8_28 [1] */ | |
3990 | FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, | |
3991 | /* IP8_27 [1] */ | |
3992 | FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, | |
3993 | /* IP8_26 [1] */ | |
3994 | FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, | |
3995 | /* IP8_25_24 [2] */ | |
3996 | FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, | |
9f2edd41 | 3997 | FN_AVB_MAGIC, 0, |
58c229e1 KM |
3998 | /* IP8_23_22 [2] */ |
3999 | FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, | |
4000 | /* IP8_21_20 [2] */ | |
9f2edd41 | 4001 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, |
58c229e1 | 4002 | /* IP8_19_18 [2] */ |
9f2edd41 | 4003 | FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, |
58c229e1 | 4004 | /* IP8_17_16 [2] */ |
9f2edd41 | 4005 | FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, |
58c229e1 | 4006 | /* IP8_15_14 [2] */ |
9f2edd41 | 4007 | FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, |
58c229e1 | 4008 | /* IP8_13_12 [2] */ |
9f2edd41 | 4009 | FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, |
58c229e1 | 4010 | /* IP8_11_10 [2] */ |
9f2edd41 | 4011 | FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, |
58c229e1 KM |
4012 | /* IP8_9_8 [2] */ |
4013 | FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, | |
4014 | /* IP8_7_6 [2] */ | |
4015 | FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, | |
4016 | /* IP8_5_4 [2] */ | |
4017 | FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, | |
4018 | /* IP8_3_2 [2] */ | |
4019 | FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, | |
4020 | /* IP8_1_0 [2] */ | |
9f2edd41 | 4021 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } |
58c229e1 KM |
4022 | }, |
4023 | { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, | |
4024 | 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { | |
4025 | /* IP9_31_28 [4] */ | |
4026 | FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, | |
c4721249 | 4027 | FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, |
58c229e1 KM |
4028 | FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, |
4029 | /* IP9_27_26 [2] */ | |
9f2edd41 | 4030 | FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, |
58c229e1 | 4031 | /* IP9_25_24 [2] */ |
9f2edd41 | 4032 | FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, |
58c229e1 | 4033 | /* IP9_23_22 [2] */ |
9f2edd41 | 4034 | FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, |
58c229e1 | 4035 | /* IP9_21_20 [2] */ |
9f2edd41 | 4036 | FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, |
58c229e1 | 4037 | /* IP9_19_18 [2] */ |
9f2edd41 | 4038 | FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, |
58c229e1 | 4039 | /* IP9_17_16 [2] */ |
9f2edd41 | 4040 | FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, |
58c229e1 KM |
4041 | /* IP9_15_12 [4] */ |
4042 | FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, | |
c4721249 SK |
4043 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, |
4044 | FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, | |
58c229e1 KM |
4045 | /* IP9_11_8 [4] */ |
4046 | FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, | |
c4721249 SK |
4047 | FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, |
4048 | FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, | |
58c229e1 KM |
4049 | /* IP9_7_6 [2] */ |
4050 | FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, | |
4051 | /* IP9_5_4 [2] */ | |
4052 | FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, | |
4053 | /* IP9_3_2 [2] */ | |
4054 | FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, | |
4055 | /* IP9_1_0 [2] */ | |
4056 | FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } | |
4057 | }, | |
4058 | { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, | |
4059 | 2, 4, 3, 4, 4, 4, 4, 3, 4) { | |
4060 | /* IP10_31_30 [2] */ | |
4061 | 0, 0, 0, 0, | |
4062 | /* IP10_29_26 [4] */ | |
4063 | FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, | |
4064 | FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, | |
4065 | FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, | |
4066 | /* IP10_25_23 [3] */ | |
4067 | FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, | |
4068 | FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, | |
4069 | /* IP10_22_19 [4] */ | |
14da999b | 4070 | FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, |
58c229e1 KM |
4071 | FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, |
4072 | FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, | |
4073 | /* IP10_18_15 [4] */ | |
14da999b | 4074 | FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, |
58c229e1 KM |
4075 | FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, |
4076 | FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, | |
4077 | 0, 0, 0, 0, 0, 0, | |
4078 | /* IP10_14_11 [4] */ | |
4079 | FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, | |
4080 | FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, | |
4081 | FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, | |
4082 | 0, 0, 0, 0, 0, 0, 0, | |
4083 | /* IP10_10_7 [4] */ | |
4084 | FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, | |
4085 | FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, | |
4086 | FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, | |
4087 | 0, 0, 0, 0, 0, 0, 0, | |
4088 | /* IP10_6_4 [3] */ | |
4089 | FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, | |
4090 | FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, | |
4091 | FN_VI3_DATA0_B, 0, | |
4092 | /* IP10_3_0 [4] */ | |
4093 | FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, | |
c4721249 | 4094 | FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, |
58c229e1 KM |
4095 | FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } |
4096 | }, | |
4097 | { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, | |
17babad6 | 4098 | 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { |
58c229e1 KM |
4099 | /* IP11_31_30 [2] */ |
4100 | FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, | |
4101 | /* IP11_29_27 [3] */ | |
7d2b2854 | 4102 | FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, |
14da999b | 4103 | 0, 0, 0, |
58c229e1 | 4104 | /* IP11_26_24 [3] */ |
c4721249 | 4105 | FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, |
58c229e1 KM |
4106 | 0, 0, 0, |
4107 | /* IP11_23_22 [2] */ | |
c4721249 | 4108 | FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, |
58c229e1 KM |
4109 | /* IP11_21_18 [4] */ |
4110 | FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, | |
14da999b | 4111 | 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, |
58c229e1 KM |
4112 | /* IP11_17_15 [3] */ |
4113 | FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, | |
4114 | FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, | |
4115 | /* IP11_14_13 [2] */ | |
4116 | FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, | |
4117 | /* IP11_12_11 [2] */ | |
4118 | FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, | |
4119 | /* IP11_10_9 [2] */ | |
4120 | FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, | |
4121 | /* IP11_8_7 [2] */ | |
4122 | FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, | |
4123 | /* IP11_6_5 [2] */ | |
4124 | FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, | |
4125 | /* IP11_4 [1] */ | |
4126 | FN_SD3_CLK, FN_MMC1_CLK, | |
4127 | /* IP11_3_0 [4] */ | |
4128 | FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, | |
4129 | FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, | |
4130 | FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } | |
4131 | }, | |
4132 | { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, | |
4133 | 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { | |
4134 | /* IP12_31 [1] */ | |
4135 | 0, 0, | |
4136 | /* IP12_30_28 [3] */ | |
4137 | FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, | |
4138 | FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, | |
4139 | FN_CAN_DEBUGOUT4, 0, 0, | |
4140 | /* IP12_27_25 [3] */ | |
4141 | FN_SSI_SCK5, FN_SCIFB1_SCK, | |
4142 | FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, | |
4143 | FN_CAN_DEBUGOUT3, 0, 0, | |
4144 | /* IP12_24_23 [2] */ | |
4145 | FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, | |
4146 | FN_CAN_DEBUGOUT2, | |
4147 | /* IP12_22_20 [3] */ | |
4148 | FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, | |
4149 | FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, | |
4150 | /* IP12_19_17 [3] */ | |
4151 | FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, | |
4152 | FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, | |
4153 | /* IP12_16_14 [3] */ | |
4154 | FN_SSI_SDATA3, FN_STP_ISCLK_0, | |
4155 | FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, | |
4156 | /* IP12_13_11 [3] */ | |
4157 | FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, | |
4158 | FN_CAN_STEP0, 0, 0, 0, | |
4159 | /* IP12_10_8 [3] */ | |
4160 | FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, | |
4161 | FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, | |
4162 | /* IP12_7_6 [2] */ | |
4163 | FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, | |
4164 | /* IP12_5_4 [2] */ | |
4165 | FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, | |
4166 | /* IP12_3_2 [2] */ | |
4167 | FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, | |
4168 | /* IP12_1_0 [2] */ | |
4169 | FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } | |
4170 | }, | |
4171 | { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, | |
4172 | 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { | |
4173 | /* IP13_31 [1] */ | |
4174 | 0, 0, | |
4175 | /* IP13_30_29 [2] */ | |
4176 | FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, | |
4177 | /* IP13_28_26 [3] */ | |
4178 | FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, | |
4179 | FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, | |
4180 | /* IP13_25_23 [3] */ | |
4181 | FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, | |
4182 | FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, | |
4183 | /* IP13_22_19 [4] */ | |
4184 | FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, | |
4185 | FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, | |
14da999b | 4186 | 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, |
58c229e1 KM |
4187 | /* IP13_18_16 [3] */ |
4188 | FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, | |
4189 | FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, | |
4190 | /* IP13_15_13 [3] */ | |
4191 | FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, | |
4192 | FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, | |
4193 | /* IP13_12_10 [3] */ | |
14da999b | 4194 | FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, |
58c229e1 KM |
4195 | FN_CAN_DEBUGOUT8, 0, 0, |
4196 | /* IP13_9_7 [3] */ | |
4197 | FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, | |
4198 | FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, | |
4199 | /* IP13_6_3 [4] */ | |
14da999b | 4200 | FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, |
58c229e1 | 4201 | FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, |
14da999b | 4202 | FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, |
58c229e1 KM |
4203 | /* IP13_2_0 [3] */ |
4204 | FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, | |
4205 | FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } | |
4206 | }, | |
4207 | { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, | |
4208 | 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { | |
4209 | /* IP14_30 [1] */ | |
4210 | 0, 0, | |
4211 | /* IP14_30_28 [3] */ | |
bcec7475 | 4212 | FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, |
58c229e1 KM |
4213 | FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, |
4214 | FN_HRTS0_N_C, 0, | |
4215 | /* IP14_27_25 [3] */ | |
4216 | FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, | |
4217 | FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, | |
4218 | /* IP14_24_22 [3] */ | |
4219 | FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, | |
4220 | FN_LCDOUT9, 0, 0, 0, | |
4221 | /* IP14_21_19 [3] */ | |
4222 | FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, | |
4223 | FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, | |
4224 | /* IP14_18_16 [3] */ | |
bcec7475 | 4225 | FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, |
58c229e1 KM |
4226 | FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, |
4227 | /* IP14_15_12 [4] */ | |
4228 | FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, | |
c4721249 | 4229 | FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, |
58c229e1 KM |
4230 | 0, 0, 0, 0, 0, 0, 0, |
4231 | /* IP14_11_9 [3] */ | |
4232 | FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, | |
4233 | 0, 0, 0, | |
4234 | /* IP14_8_6 [3] */ | |
4235 | FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, | |
4236 | 0, 0, 0, | |
4237 | /* IP14_5_3 [3] */ | |
4238 | FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, | |
c4721249 | 4239 | FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, |
58c229e1 KM |
4240 | /* IP14_2_0 [3] */ |
4241 | FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, | |
4242 | FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, | |
4243 | FN_REMOCON, 0, } | |
4244 | }, | |
4245 | { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, | |
4246 | 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { | |
4247 | /* IP15_31_30 [2] */ | |
4248 | 0, 0, 0, 0, | |
4249 | /* IP15_29_28 [2] */ | |
4250 | FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, | |
4251 | /* IP15_27_26 [2] */ | |
4252 | FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, | |
4253 | /* IP15_25_23 [3] */ | |
4254 | FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, | |
5de880dd | 4255 | FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, |
58c229e1 KM |
4256 | /* IP15_22_20 [3] */ |
4257 | FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, | |
4258 | FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, | |
4259 | /* IP15_19_18 [2] */ | |
4260 | FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, | |
4261 | /* IP15_17_16 [2] */ | |
4262 | FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, | |
4263 | /* IP15_15_14 [2] */ | |
4264 | FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, | |
4265 | /* IP15_13_12 [2] */ | |
4266 | FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, | |
4267 | /* IP15_11_9 [3] */ | |
4268 | FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, | |
4269 | 0, 0, 0, | |
4270 | /* IP15_8_6 [3] */ | |
1ddb66cd | 4271 | FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, |
c4721249 | 4272 | FN_IIC2_SDA, FN_I2C2_SDA, 0, |
58c229e1 | 4273 | /* IP15_5_3 [3] */ |
1ddb66cd | 4274 | FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, |
c4721249 | 4275 | FN_IIC2_SCL, FN_I2C2_SCL, 0, |
58c229e1 | 4276 | /* IP15_2_0 [3] */ |
1ddb66cd | 4277 | FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, |
58c229e1 KM |
4278 | FN_LCDOUT15, FN_SCIF_CLK_B, 0, } |
4279 | }, | |
4280 | { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, | |
4281 | 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { | |
4282 | /* IP16_31_28 [4] */ | |
4283 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4284 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4285 | /* IP16_27_24 [4] */ | |
4286 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4287 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4288 | /* IP16_23_20 [4] */ | |
4289 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4290 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4291 | /* IP16_19_16 [4] */ | |
4292 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4293 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4294 | /* IP16_15_12 [4] */ | |
4295 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4296 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4297 | /* IP16_11_8 [4] */ | |
4298 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4299 | 0, 0, 0, 0, 0, 0, 0, 0, | |
4300 | /* IP16_7 [1] */ | |
4301 | FN_USB1_OVC, FN_TCLK1_B, | |
4302 | /* IP16_6 [1] */ | |
4303 | FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, | |
4304 | /* IP16_5_3 [3] */ | |
4305 | FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, | |
5de880dd | 4306 | FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, |
58c229e1 KM |
4307 | /* IP16_2_0 [3] */ |
4308 | FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, | |
4309 | FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } | |
4310 | }, | |
4311 | { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, | |
4312 | 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, | |
4313 | 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { | |
4314 | /* SEL_SCIF1 [3] */ | |
4315 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, | |
4316 | FN_SEL_SCIF1_4, 0, 0, 0, | |
4317 | /* SEL_SCIFB [2] */ | |
4318 | FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, | |
4319 | /* SEL_SCIFB2 [2] */ | |
4320 | FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, | |
4321 | /* SEL_SCIFB1 [3] */ | |
4322 | FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, | |
4323 | FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, | |
4324 | FN_SEL_SCIFB1_6, 0, | |
4325 | /* SEL_SCIFA1 [2] */ | |
4326 | FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, | |
4327 | FN_SEL_SCIFA1_3, | |
4328 | /* SEL_SCIF0 [1] */ | |
4329 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, | |
4330 | /* SEL_SCIFA [1] */ | |
4331 | FN_SEL_SCFA_0, FN_SEL_SCFA_1, | |
4332 | /* SEL_SOF1 [1] */ | |
4333 | FN_SEL_SOF1_0, FN_SEL_SOF1_1, | |
4334 | /* SEL_SSI7 [2] */ | |
4335 | FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, | |
4336 | /* SEL_SSI6 [1] */ | |
4337 | FN_SEL_SSI6_0, FN_SEL_SSI6_1, | |
4338 | /* SEL_SSI5 [2] */ | |
4339 | FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, | |
4340 | /* SEL_VI3 [1] */ | |
4341 | FN_SEL_VI3_0, FN_SEL_VI3_1, | |
4342 | /* SEL_VI2 [1] */ | |
4343 | FN_SEL_VI2_0, FN_SEL_VI2_1, | |
4344 | /* SEL_VI1 [1] */ | |
4345 | FN_SEL_VI1_0, FN_SEL_VI1_1, | |
4346 | /* SEL_VI0 [1] */ | |
4347 | FN_SEL_VI0_0, FN_SEL_VI0_1, | |
4348 | /* SEL_TSIF1 [2] */ | |
4349 | FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, | |
4350 | /* RESERVED [1] */ | |
4351 | 0, 0, | |
4352 | /* SEL_LBS [1] */ | |
4353 | FN_SEL_LBS_0, FN_SEL_LBS_1, | |
4354 | /* SEL_TSIF0 [2] */ | |
4355 | FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, | |
4356 | /* SEL_SOF3 [1] */ | |
4357 | FN_SEL_SOF3_0, FN_SEL_SOF3_1, | |
4358 | /* SEL_SOF0 [1] */ | |
4359 | FN_SEL_SOF0_0, FN_SEL_SOF0_1, } | |
4360 | }, | |
4361 | { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, | |
17babad6 GL |
4362 | 3, 1, 1, 1, 2, 1, 2, 1, 2, |
4363 | 1, 1, 1, 3, 3, 2, 3, 2, 2) { | |
7f35184b | 4364 | /* RESERVED [3] */ |
58c229e1 | 4365 | 0, 0, 0, 0, 0, 0, 0, 0, |
58c229e1 KM |
4366 | /* SEL_TMU1 [1] */ |
4367 | FN_SEL_TMU1_0, FN_SEL_TMU1_1, | |
4368 | /* SEL_HSCIF1 [1] */ | |
4369 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, | |
4370 | /* SEL_SCIFCLK [1] */ | |
4371 | FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, | |
4372 | /* SEL_CAN0 [2] */ | |
4373 | FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, | |
4374 | /* SEL_CANCLK [1] */ | |
4375 | FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, | |
4376 | /* SEL_SCIFA2 [2] */ | |
4377 | FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, | |
4378 | /* SEL_CAN1 [1] */ | |
4379 | FN_SEL_CAN1_0, FN_SEL_CAN1_1, | |
7f35184b | 4380 | /* RESERVED [2] */ |
17babad6 | 4381 | 0, 0, 0, 0, |
1ddb66cd SK |
4382 | /* SEL_SCIF2 [1] */ |
4383 | FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, | |
58c229e1 KM |
4384 | /* SEL_ADI [1] */ |
4385 | FN_SEL_ADI_0, FN_SEL_ADI_1, | |
4386 | /* SEL_SSP [1] */ | |
4387 | FN_SEL_SSP_0, FN_SEL_SSP_1, | |
4388 | /* SEL_FM [3] */ | |
4389 | FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, | |
4390 | FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, | |
4391 | /* SEL_HSCIF0 [3] */ | |
4392 | FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, | |
4393 | FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, | |
4394 | /* SEL_GPS [2] */ | |
4395 | FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, | |
14da999b SK |
4396 | /* RESERVED [3] */ |
4397 | 0, 0, 0, 0, 0, 0, 0, 0, | |
58c229e1 KM |
4398 | /* SEL_SIM [2] */ |
4399 | FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, | |
4400 | /* SEL_SSI8 [2] */ | |
4401 | FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } | |
4402 | }, | |
4403 | { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, | |
4404 | 1, 1, 2, 4, 4, 2, 2, | |
4405 | 4, 2, 3, 2, 3, 2) { | |
4406 | /* SEL_IICDVFS [1] */ | |
4407 | FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, | |
4408 | /* SEL_IIC0 [1] */ | |
4409 | FN_SEL_IIC0_0, FN_SEL_IIC0_1, | |
7f35184b | 4410 | /* RESERVED [2] */ |
58c229e1 | 4411 | 0, 0, 0, 0, |
7f35184b | 4412 | /* RESERVED [4] */ |
58c229e1 KM |
4413 | 0, 0, 0, 0, 0, 0, 0, 0, |
4414 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7f35184b | 4415 | /* RESERVED [4] */ |
58c229e1 KM |
4416 | 0, 0, 0, 0, 0, 0, 0, 0, |
4417 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7f35184b | 4418 | /* RESERVED [2] */ |
58c229e1 KM |
4419 | 0, 0, 0, 0, |
4420 | /* SEL_IEB [2] */ | |
4421 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, | |
7f35184b | 4422 | /* RESERVED [4] */ |
58c229e1 KM |
4423 | 0, 0, 0, 0, 0, 0, 0, 0, |
4424 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7f35184b | 4425 | /* RESERVED [2] */ |
58c229e1 KM |
4426 | 0, 0, 0, 0, |
4427 | /* SEL_IIC2 [3] */ | |
4428 | FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, | |
4429 | FN_SEL_IIC2_4, 0, 0, 0, | |
4430 | /* SEL_IIC1 [2] */ | |
4431 | FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, | |
4432 | /* SEL_I2C2 [3] */ | |
4433 | FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, | |
4434 | FN_SEL_I2C2_4, 0, 0, 0, | |
4435 | /* SEL_I2C1 [2] */ | |
4436 | FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } | |
4437 | }, | |
58c229e1 KM |
4438 | { }, |
4439 | }; | |
4440 | ||
4441 | const struct sh_pfc_soc_info r8a7790_pinmux_info = { | |
4442 | .name = "r8a77900_pfc", | |
4443 | .unlock_reg = 0xe6060000, /* PMMR */ | |
4444 | ||
58c229e1 KM |
4445 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
4446 | ||
4447 | .pins = pinmux_pins, | |
4448 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
1627769b LP |
4449 | .groups = pinmux_groups, |
4450 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
4451 | .functions = pinmux_functions, | |
4452 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
58c229e1 | 4453 | |
58c229e1 | 4454 | .cfg_regs = pinmux_config_regs, |
58c229e1 KM |
4455 | |
4456 | .gpio_data = pinmux_data, | |
4457 | .gpio_data_size = ARRAY_SIZE(pinmux_data), | |
4458 | }; |