sh-pfc: Fix return value check in sh_pfc_register_pinctrl()
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / gpio.c
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1/*
2 * SuperH Pin Function Controller GPIO driver.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
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11
12#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
b3c185a7 13
1724acfd 14#include <linux/device.h>
b3c185a7 15#include <linux/gpio.h>
90efde22 16#include <linux/init.h>
b3c185a7 17#include <linux/module.h>
ca5481c6 18#include <linux/pinctrl/consumer.h>
90efde22
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19#include <linux/slab.h>
20#include <linux/spinlock.h>
b3c185a7 21
f9165132
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22#include "core.h"
23
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24struct sh_pfc_chip {
25 struct sh_pfc *pfc;
26 struct gpio_chip gpio_chip;
27};
28
29static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
30{
31 return container_of(gc, struct sh_pfc_chip, gpio_chip);
32}
33
34static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
35{
36 return gpio_to_pfc_chip(gc)->pfc;
37}
38
16883814
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39/* -----------------------------------------------------------------------------
40 * Pin GPIOs
41 */
b3c185a7 42
16883814 43static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
b3c185a7 44{
0b73ee5d 45 struct sh_pfc *pfc = gpio_to_pfc(gc);
934cb02b 46 struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset);
0b73ee5d 47
63d57383 48 if (pin == NULL || pin->enum_id == 0)
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49 return -EINVAL;
50
16883814 51 return pinctrl_request_gpio(offset);
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52}
53
16883814 54static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
b3c185a7 55{
16883814 56 return pinctrl_free_gpio(offset);
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57}
58
16883814 59static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value)
b3c185a7 60{
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61 struct pinmux_data_reg *dr;
62 int bit;
b3c185a7 63
0b73ee5d 64 sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
16883814 65 sh_pfc_write_bit(dr, bit, value);
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66}
67
16883814 68static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
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69{
70 return pinctrl_gpio_direction_input(offset);
71}
72
16883814 73static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
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74 int value)
75{
16883814 76 gpio_pin_set_value(gpio_to_pfc(gc), offset, value);
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77
78 return pinctrl_gpio_direction_output(offset);
79}
80
16883814 81static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
b3c185a7 82{
16883814 83 struct sh_pfc *pfc = gpio_to_pfc(gc);
0b73ee5d
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84 struct pinmux_data_reg *dr;
85 int bit;
16883814 86
0b73ee5d 87 sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
16883814 88 return sh_pfc_read_bit(dr, bit);
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89}
90
16883814 91static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
b3c185a7 92{
16883814 93 gpio_pin_set_value(gpio_to_pfc(gc), offset, value);
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94}
95
16883814 96static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
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97{
98 struct sh_pfc *pfc = gpio_to_pfc(gc);
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99 int i, k;
100
101 for (i = 0; i < pfc->info->gpio_irq_size; i++) {
102 unsigned short *gpios = pfc->info->gpio_irq[i].gpios;
103
104 for (k = 0; gpios[k]; k++) {
105 if (gpios[k] == offset)
106 return pfc->info->gpio_irq[i].irq;
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107 }
108 }
109
110 return -ENOSYS;
111}
112
16883814 113static void gpio_pin_setup(struct sh_pfc_chip *chip)
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114{
115 struct sh_pfc *pfc = chip->pfc;
116 struct gpio_chip *gc = &chip->gpio_chip;
117
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118 gc->request = gpio_pin_request;
119 gc->free = gpio_pin_free;
120 gc->direction_input = gpio_pin_direction_input;
121 gc->get = gpio_pin_get;
122 gc->direction_output = gpio_pin_direction_output;
123 gc->set = gpio_pin_set;
124 gc->to_irq = gpio_pin_to_irq;
b3c185a7 125
19bb7fe3 126 gc->label = pfc->info->name;
16883814 127 gc->dev = pfc->dev;
b3c185a7 128 gc->owner = THIS_MODULE;
d7a7ca57 129 gc->base = 0;
63d57383 130 gc->ngpio = pfc->nr_pins;
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131}
132
16883814
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133/* -----------------------------------------------------------------------------
134 * Function GPIOs
135 */
136
137static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
138{
139 struct sh_pfc *pfc = gpio_to_pfc(gc);
a68fdca9 140 unsigned int mark = pfc->info->func_gpios[offset].enum_id;
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141 unsigned long flags;
142 int ret = -EINVAL;
143
144 pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
145
a68fdca9 146 if (mark == 0)
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147 return ret;
148
149 spin_lock_irqsave(&pfc->lock, flags);
150
a68fdca9 151 if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_DRYRUN))
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152 goto done;
153
a68fdca9 154 if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_REQ))
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155 goto done;
156
157 ret = 0;
158
159done:
160 spin_unlock_irqrestore(&pfc->lock, flags);
161 return ret;
162}
163
164static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
165{
166 struct sh_pfc *pfc = gpio_to_pfc(gc);
a68fdca9 167 unsigned int mark = pfc->info->func_gpios[offset].enum_id;
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168 unsigned long flags;
169
170 spin_lock_irqsave(&pfc->lock, flags);
171
a68fdca9 172 sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE);
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173
174 spin_unlock_irqrestore(&pfc->lock, flags);
175}
176
177static void gpio_function_setup(struct sh_pfc_chip *chip)
178{
179 struct sh_pfc *pfc = chip->pfc;
180 struct gpio_chip *gc = &chip->gpio_chip;
181
182 gc->request = gpio_function_request;
183 gc->free = gpio_function_free;
184
185 gc->label = pfc->info->name;
186 gc->owner = THIS_MODULE;
63d57383 187 gc->base = pfc->nr_pins;
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188 gc->ngpio = pfc->info->nr_func_gpios;
189}
190
191/* -----------------------------------------------------------------------------
192 * Register/unregister
193 */
194
195static struct sh_pfc_chip *
196sh_pfc_add_gpiochip(struct sh_pfc *pfc, void(*setup)(struct sh_pfc_chip *))
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197{
198 struct sh_pfc_chip *chip;
199 int ret;
200
1724acfd 201 chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
b3c185a7 202 if (unlikely(!chip))
16883814 203 return ERR_PTR(-ENOMEM);
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204
205 chip->pfc = pfc;
206
16883814 207 setup(chip);
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208
209 ret = gpiochip_add(&chip->gpio_chip);
1724acfd 210 if (unlikely(ret < 0))
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211 return ERR_PTR(ret);
212
213 pr_info("%s handling gpio %u -> %u\n",
214 chip->gpio_chip.label, chip->gpio_chip.base,
215 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
216
217 return chip;
218}
219
220int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
221{
63d57383
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222 const struct pinmux_range *ranges;
223 struct pinmux_range def_range;
16883814 224 struct sh_pfc_chip *chip;
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225 unsigned int nr_ranges;
226 unsigned int i;
247127f9 227 int ret;
16883814 228
63d57383 229 /* Register the real GPIOs chip. */
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230 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
231 if (IS_ERR(chip))
232 return PTR_ERR(chip);
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233
234 pfc->gpio = chip;
b3c185a7 235
63d57383
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236 /* Register the GPIO to pin mappings. */
237 if (pfc->info->ranges == NULL) {
238 def_range.begin = 0;
239 def_range.end = pfc->info->nr_pins - 1;
240 ranges = &def_range;
241 nr_ranges = 1;
242 } else {
243 ranges = pfc->info->ranges;
244 nr_ranges = pfc->info->nr_ranges;
245 }
246
247 for (i = 0; i < nr_ranges; ++i) {
248 const struct pinmux_range *range = &ranges[i];
249
250 ret = gpiochip_add_pin_range(&chip->gpio_chip,
251 dev_name(pfc->dev),
252 range->begin, range->begin,
253 range->end - range->begin + 1);
254 if (ret < 0)
255 return ret;
256 }
247127f9 257
63d57383 258 /* Register the function GPIOs chip. */
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259 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
260 if (IS_ERR(chip))
261 return PTR_ERR(chip);
262
263 pfc->func = chip;
b3c185a7 264
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265 return 0;
266}
267
6f6a4a68 268int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
b3c185a7 269{
16883814 270 int err;
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271 int ret;
272
16883814
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273 ret = gpiochip_remove(&pfc->gpio->gpio_chip);
274 err = gpiochip_remove(&pfc->func->gpio_chip);
b3c185a7 275
16883814 276 return ret < 0 ? ret : err;
b3c185a7 277}