[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / core.c

/*
 * SuperH Pin Function Controller support.
 *
 * Copyright (C) 2008 Magnus Damm
 * Copyright (C) 2009 - 2012 Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "core.h"

static int sh_pfc_map_resources(struct sh_pfc *pfc,
				struct platform_device *pdev)
{
	unsigned int num_windows, num_irqs;
	struct sh_pfc_window *windows;
	unsigned int *irqs = NULL;
	struct resource *res;
	unsigned int i;
	int irq;

	/* Count the MEM and IRQ resources. */
	for (num_windows = 0;; num_windows++) {
		res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
		if (!res)
			break;
	}
	for (num_irqs = 0;; num_irqs++) {
		irq = platform_get_irq(pdev, num_irqs);
		if (irq == -EPROBE_DEFER)
			return irq;
		if (irq < 0)
			break;
	}

	if (num_windows == 0)
		return -EINVAL;

	/* Allocate memory windows and IRQs arrays. */
	windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
			       GFP_KERNEL);
	if (windows == NULL)
		return -ENOMEM;

	pfc->num_windows = num_windows;
	pfc->windows = windows;

	if (num_irqs) {
		irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
				    GFP_KERNEL);
		if (irqs == NULL)
			return -ENOMEM;

		pfc->num_irqs = num_irqs;
		pfc->irqs = irqs;
	}

	/* Fill them. */
	for (i = 0; i < num_windows; i++) {
		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
		windows->phys = res->start;
		windows->size = resource_size(res);
		windows->virt = devm_ioremap_resource(pfc->dev, res);
		if (IS_ERR(windows->virt))
			return -ENOMEM;
		windows++;
	}
	for (i = 0; i < num_irqs; i++)
		*irqs++ = platform_get_irq(pdev, i);

	return 0;
}

static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
{
	struct sh_pfc_window *window;
	phys_addr_t address = reg;
	unsigned int i;

	/* scan through physical windows and convert address */
	for (i = 0; i < pfc->num_windows; i++) {
		window = pfc->windows + i;

		if (address < window->phys)
			continue;

		if (address >= (window->phys + window->size))
			continue;

		return window->virt + (address - window->phys);
	}

	BUG();
	return NULL;
}

int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
{
	unsigned int offset;
	unsigned int i;

	for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
		const struct sh_pfc_pin_range *range = &pfc->ranges[i];

		if (pin <= range->end)
			return pin >= range->start
			     ? offset + pin - range->start : -1;

		offset += range->end - range->start + 1;
	}

	return -EINVAL;
}

static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
{
	switch (reg_width) {
	case 8:
		return ioread8(mapped_reg);
	case 16:
		return ioread16(mapped_reg);
	case 32:
		return ioread32(mapped_reg);
	}

	BUG();
	return 0;
}

void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
			  u32 data)
{
	switch (reg_width) {
	case 8:
		iowrite8(data, mapped_reg);
		return;
	case 16:
		iowrite16(data, mapped_reg);
		return;
	case 32:
		iowrite32(data, mapped_reg);
		return;
	}

	BUG();
}

static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
				     const struct pinmux_cfg_reg *crp,
				     unsigned int in_pos,
				     void __iomem **mapped_regp, u32 *maskp,
				     unsigned int *posp)
{
	unsigned int k;

	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);

	if (crp->field_width) {
		*maskp = (1 << crp->field_width) - 1;
		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
	} else {
		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
		*posp = crp->reg_width;
		for (k = 0; k <= in_pos; k++)
			*posp -= crp->var_field_width[k];
	}
}

static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
				    const struct pinmux_cfg_reg *crp,
				    unsigned int field, u32 value)
{
	void __iomem *mapped_reg;
	unsigned int pos;
	u32 mask, data;

	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);

	dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
		"r_width = %u, f_width = %u\n",
		crp->reg, value, field, crp->reg_width, crp->field_width);

	mask = ~(mask << pos);
	value = value << pos;

	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
	data &= mask;
	data |= value;

	if (pfc->info->unlock_reg)
		sh_pfc_write_raw_reg(
			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
			~data);

	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}

static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
				 const struct pinmux_cfg_reg **crp,
				 unsigned int *fieldp, u32 *valuep)
{
	unsigned int k = 0;

	while (1) {
		const struct pinmux_cfg_reg *config_reg =
			pfc->info->cfg_regs + k;
		unsigned int r_width = config_reg->reg_width;
		unsigned int f_width = config_reg->field_width;
		unsigned int curr_width;
		unsigned int bit_pos;
		unsigned int pos = 0;
		unsigned int m = 0;

		if (!r_width)
			break;

		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
			u32 ncomb;
			u32 n;

			if (f_width)
				curr_width = f_width;
			else
				curr_width = config_reg->var_field_width[m];

			ncomb = 1 << curr_width;
			for (n = 0; n < ncomb; n++) {
				if (config_reg->enum_ids[pos + n] == enum_id) {
					*crp = config_reg;
					*fieldp = m;
					*valuep = n;
					return 0;
				}
			}
			pos += ncomb;
			m++;
		}
		k++;
	}

	return -EINVAL;
}

static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
			      u16 *enum_idp)
{
	const u16 *data = pfc->info->pinmux_data;
	unsigned int k;

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < pfc->info->pinmux_data_size; k++) {
		if (data[k] == mark) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
		mark);
	return -EINVAL;
}

int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
	const struct pinmux_range *range;
	int pos = 0;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &pfc->info->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &pfc->info->input;
		break;

	default:
		return -EINVAL;
	}

	/* Iterate over all the configuration fields we need to update. */
	while (1) {
		const struct pinmux_cfg_reg *cr;
		unsigned int field;
		u16 enum_id;
		u32 value;
		int in_range;
		int ret;

		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
		if (pos < 0)
			return pos;

		if (!enum_id)
			break;

		/* Check if the configuration field selects a function. If it
		 * doesn't, skip the field if it's not applicable to the
		 * requested pinmux type.
		 */
		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
		if (!in_range) {
			if (pinmux_type == PINMUX_TYPE_FUNCTION) {
				/* Functions are allowed to modify all
				 * fields.
				 */
				in_range = 1;
			} else if (pinmux_type != PINMUX_TYPE_GPIO) {
				/* Input/output types can only modify fields
				 * that correspond to their respective ranges.
				 */
				in_range = sh_pfc_enum_in_range(enum_id, range);

				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			}
			/* GPIOs are only allowed to modify function fields. */
		}

		if (!in_range)
			continue;

		ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
		if (ret < 0)
			return ret;

		sh_pfc_write_config_reg(pfc, cr, field, value);
	}

	return 0;
}

static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
	struct sh_pfc_pin_range *range;
	unsigned int nr_ranges;
	unsigned int i;

	if (pfc->info->pins[0].pin == (u16)-1) {
		/* Pin number -1 denotes that the SoC doesn't report pin numbers
		 * in its pin arrays yet. Consider the pin numbers range as
		 * continuous and allocate a single range.
		 */
		pfc->nr_ranges = 1;
		pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
					   GFP_KERNEL);
		if (pfc->ranges == NULL)
			return -ENOMEM;

		pfc->ranges->start = 0;
		pfc->ranges->end = pfc->info->nr_pins - 1;
		pfc->nr_gpio_pins = pfc->info->nr_pins;

		return 0;
	}

	/* Count, allocate and fill the ranges. The PFC SoC data pins array must
	 * be sorted by pin numbers, and pins without a GPIO port must come
	 * last.
	 */
	for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
		if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
			nr_ranges++;
	}

	pfc->nr_ranges = nr_ranges;
	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
				   GFP_KERNEL);
	if (pfc->ranges == NULL)
		return -ENOMEM;

	range = pfc->ranges;
	range->start = pfc->info->pins[0].pin;

	for (i = 1; i < pfc->info->nr_pins; ++i) {
		if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
			continue;

		range->end = pfc->info->pins[i-1].pin;
		if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
			pfc->nr_gpio_pins = range->end + 1;

		range++;
		range->start = pfc->info->pins[i].pin;
	}

	range->end = pfc->info->pins[i-1].pin;
	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
		pfc->nr_gpio_pins = range->end + 1;

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id sh_pfc_of_table[] = {
#ifdef CONFIG_PINCTRL_PFC_EMEV2
	{
		.compatible = "renesas,pfc-emev2",
		.data = &emev2_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	{
		.compatible = "renesas,pfc-r8a73a4",
		.data = &r8a73a4_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{
		.compatible = "renesas,pfc-r8a7740",
		.data = &r8a7740_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
	{
		.compatible = "renesas,pfc-r8a7778",
		.data = &r8a7778_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{
		.compatible = "renesas,pfc-r8a7779",
		.data = &r8a7779_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7790
	{
		.compatible = "renesas,pfc-r8a7790",
		.data = &r8a7790_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7791
	{
		.compatible = "renesas,pfc-r8a7791",
		.data = &r8a7791_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7793
	{
		.compatible = "renesas,pfc-r8a7793",
		.data = &r8a7793_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7794
	{
		.compatible = "renesas,pfc-r8a7794",
		.data = &r8a7794_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7795
	{
		.compatible = "renesas,pfc-r8a7795",
		.data = &r8a7795_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{
		.compatible = "renesas,pfc-sh73a0",
		.data = &sh73a0_pinmux_info,
	},
#endif
	{ },
};
MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
#endif

static int sh_pfc_probe(struct platform_device *pdev)
{
	const struct platform_device_id *platid = platform_get_device_id(pdev);
#ifdef CONFIG_OF
	struct device_node *np = pdev->dev.of_node;
#endif
	const struct sh_pfc_soc_info *info;
	struct sh_pfc *pfc;
	int ret;

#ifdef CONFIG_OF
	if (np)
		info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
	else
#endif
		info = platid ? (const void *)platid->driver_data : NULL;

	if (info == NULL)
		return -ENODEV;

	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
	if (pfc == NULL)
		return -ENOMEM;

	pfc->info = info;
	pfc->dev = &pdev->dev;

	ret = sh_pfc_map_resources(pfc, pdev);
	if (unlikely(ret < 0))
		return ret;

	spin_lock_init(&pfc->lock);

	if (info->ops && info->ops->init) {
		ret = info->ops->init(pfc);
		if (ret < 0)
			return ret;
	}

	pinctrl_provide_dummies();

	ret = sh_pfc_init_ranges(pfc);
	if (ret < 0)
		return ret;

	/*
	 * Initialize pinctrl bindings first
	 */
	ret = sh_pfc_register_pinctrl(pfc);
	if (unlikely(ret != 0))
		return ret;

#ifdef CONFIG_GPIO_SH_PFC
	/*
	 * Then the GPIO chip
	 */
	ret = sh_pfc_register_gpiochip(pfc);
	if (unlikely(ret != 0)) {
		/*
		 * If the GPIO chip fails to come up we still leave the
		 * PFC state as it is, given that there are already
		 * extant users of it that have succeeded by this point.
		 */
		dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
	}
#endif

	platform_set_drvdata(pdev, pfc);

	dev_info(pfc->dev, "%s support registered\n", info->name);

	return 0;
}

static int sh_pfc_remove(struct platform_device *pdev)
{
	struct sh_pfc *pfc = platform_get_drvdata(pdev);

#ifdef CONFIG_GPIO_SH_PFC
	sh_pfc_unregister_gpiochip(pfc);
#endif
	sh_pfc_unregister_pinctrl(pfc);

	return 0;
}

static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_SH7203
	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7264
	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7269
	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7720
	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7722
	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7723
	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7724
	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7734
	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7757
	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7785
	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7786
	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SHX3
	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
#endif
	{ "sh-pfc", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);

static struct platform_driver sh_pfc_driver = {
	.probe		= sh_pfc_probe,
	.remove		= sh_pfc_remove,
	.id_table	= sh_pfc_id_table,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = of_match_ptr(sh_pfc_of_table),
	},
};

static int __init sh_pfc_init(void)
{
	return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);

static void __exit sh_pfc_exit(void)
{
	platform_driver_unregister(&sh_pfc_driver);
}
module_exit(sh_pfc_exit);

MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2967dab1	1	/*
b3c185a7	2	* SuperH Pin Function Controller support.
2967dab1 MD	3	*
2967dab1 MD	4	* Copyright (C) 2008 Magnus Damm
b3c185a7	5	* Copyright (C) 2009 - 2012 Paul Mundt
2967dab1 MD	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
c6193eac LP	11
c6193eac LP	12	#define DRV_NAME "sh-pfc"
b72421d8	13
90efde22	14	#include <linux/bitops.h>
2967dab1	15	#include <linux/err.h>
90efde22	16	#include <linux/errno.h>
2967dab1	17	#include <linux/io.h>
b0e10211	18	#include <linux/ioport.h>
90efde22 LP	19	#include <linux/kernel.h>
90efde22 LP	20	#include <linux/module.h>
fe1c9a82 LP	21	#include <linux/of.h>
fe1c9a82 LP	22	#include <linux/of_device.h>
ca5481c6	23	#include <linux/pinctrl/machine.h>
c6193eac	24	#include <linux/platform_device.h>
90efde22	25	#include <linux/slab.h>
b0e10211	26
f9165132 LP	27	#include "core.h"
f9165132 LP	28
70c8f01a LP	29	static int sh_pfc_map_resources(struct sh_pfc *pfc,
70c8f01a LP	30	struct platform_device *pdev)
b0e10211	31	{
c7977ec4	32	unsigned int num_windows, num_irqs;
70c8f01a LP	33	struct sh_pfc_window *windows;
70c8f01a LP	34	unsigned int *irqs = NULL;
b0e10211	35	struct resource *res;
70c8f01a	36	unsigned int i;
c7977ec4	37	int irq;
70c8f01a LP	38
70c8f01a LP	39	/* Count the MEM and IRQ resources. */
c7977ec4 GU	40	for (num_windows = 0;; num_windows++) {
	41	res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
	42	if (!res)
70c8f01a	43	break;
c7977ec4 GU	44	}
	45	for (num_irqs = 0;; num_irqs++) {
	46	irq = platform_get_irq(pdev, num_irqs);
	47	if (irq == -EPROBE_DEFER)
	48	return irq;
	49	if (irq < 0)
70c8f01a	50	break;
70c8f01a	51	}
b0e10211	52
70c8f01a	53	if (num_windows == 0)
bee9f22b	54	return -EINVAL;
b0e10211	55
70c8f01a LP	56	/* Allocate memory windows and IRQs arrays. */
	57	windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
	58	GFP_KERNEL);
	59	if (windows == NULL)
1724acfd	60	return -ENOMEM;
b0e10211	61
70c8f01a LP	62	pfc->num_windows = num_windows;
70c8f01a LP	63	pfc->windows = windows;
973931ae	64
70c8f01a LP	65	if (num_irqs) {
	66	irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
	67	GFP_KERNEL);
	68	if (irqs == NULL)
1724acfd	69	return -ENOMEM;
70c8f01a LP	70
	71	pfc->num_irqs = num_irqs;
	72	pfc->irqs = irqs;
	73	}
	74
	75	/* Fill them. */
c7977ec4 GU	76	for (i = 0; i < num_windows; i++) {
	77	res = platform_get_resource(pdev, IORESOURCE_MEM, i);
	78	windows->phys = res->start;
	79	windows->size = resource_size(res);
	80	windows->virt = devm_ioremap_resource(pfc->dev, res);
	81	if (IS_ERR(windows->virt))
	82	return -ENOMEM;
	83	windows++;
b0e10211	84	}
c7977ec4 GU	85	for (i = 0; i < num_irqs; i++)
c7977ec4 GU	86	*irqs++ = platform_get_irq(pdev, i);
b0e10211 MD	87
b0e10211 MD	88	return 0;
b0e10211 MD	89	}
b0e10211 MD	90
1f34de05	91	static void __iomem sh_pfc_phys_to_virt(struct sh_pfc pfc, u32 reg)
b0e10211	92	{
4aeacd5b	93	struct sh_pfc_window *window;
1f34de05	94	phys_addr_t address = reg;
bee9f22b	95	unsigned int i;
b0e10211 MD	96
b0e10211 MD	97	/* scan through physical windows and convert address */
bee9f22b	98	for (i = 0; i < pfc->num_windows; i++) {
5b46ac3a	99	window = pfc->windows + i;
b0e10211 MD	100
	101	if (address < window->phys)
	102	continue;
	103
	104	if (address >= (window->phys + window->size))
	105	continue;
	106
	107	return window->virt + (address - window->phys);
	108	}
	109
bee9f22b	110	BUG();
1960d580	111	return NULL;
b0e10211	112	}
2967dab1	113
1a0039dc	114	int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
934cb02b	115	{
63d57383 LP	116	unsigned int offset;
	117	unsigned int i;
	118
acac8ed5 LP	119	for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
acac8ed5 LP	120	const struct sh_pfc_pin_range *range = &pfc->ranges[i];
63d57383 LP	121
63d57383 LP	122	if (pin <= range->end)
acac8ed5 LP	123	return pin >= range->start
acac8ed5 LP	124	? offset + pin - range->start : -1;
63d57383	125
acac8ed5	126	offset += range->end - range->start + 1;
63d57383 LP	127	}
63d57383 LP	128
b705c054	129	return -EINVAL;
934cb02b LP	130	}
934cb02b LP	131
533743dc	132	static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
2967dab1 MD	133	{
	134	if (enum_id < r->begin)
	135	return 0;
	136
	137	if (enum_id > r->end)
	138	return 0;
	139
	140	return 1;
	141	}
	142
cef28a28	143	u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
3292094e MD	144	{
	145	switch (reg_width) {
	146	case 8:
b0e10211	147	return ioread8(mapped_reg);
3292094e	148	case 16:
b0e10211	149	return ioread16(mapped_reg);
3292094e	150	case 32:
b0e10211	151	return ioread32(mapped_reg);
3292094e MD	152	}
	153
	154	BUG();
	155	return 0;
	156	}
	157
cef28a28	158	void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
fc88936a	159	u32 data)
3292094e MD	160	{
	161	switch (reg_width) {
	162	case 8:
b0e10211	163	iowrite8(data, mapped_reg);
3292094e MD	164	return;
3292094e MD	165	case 16:
b0e10211	166	iowrite16(data, mapped_reg);
3292094e MD	167	return;
3292094e MD	168	case 32:
b0e10211	169	iowrite32(data, mapped_reg);
3292094e MD	170	return;
	171	}
	172
	173	BUG();
	174	}
	175
4aeacd5b	176	static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
cd3c1bee	177	const struct pinmux_cfg_reg *crp,
cef28a28	178	unsigned int in_pos,
fc88936a	179	void __iomem *mapped_regp, u32 maskp,
cef28a28	180	unsigned int *posp)
2967dab1	181	{
8d72a7fc	182	unsigned int k;
f78a26f5	183
4aeacd5b	184	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
2967dab1	185
f78a26f5 MD	186	if (crp->field_width) {
	187	*maskp = (1 << crp->field_width) - 1;
	188	posp = crp->reg_width - ((in_pos + 1) crp->field_width);
	189	} else {
	190	*maskp = (1 << crp->var_field_width[in_pos]) - 1;
	191	*posp = crp->reg_width;
	192	for (k = 0; k <= in_pos; k++)
	193	*posp -= crp->var_field_width[k];
	194	}
18925e11 MD	195	}
18925e11 MD	196
4aeacd5b	197	static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
cd3c1bee	198	const struct pinmux_cfg_reg *crp,
cef28a28	199	unsigned int field, u32 value)
0fc64cc0	200	{
18925e11	201	void __iomem *mapped_reg;
cef28a28	202	unsigned int pos;
fc88936a	203	u32 mask, data;
0fc64cc0	204
4aeacd5b	205	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1	206
1f34de05	207	dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
dc700715	208	"r_width = %u, f_width = %u\n",
9a643c9a	209	crp->reg, value, field, crp->reg_width, crp->field_width);
0fc64cc0 MD	210
	211	mask = ~(mask << pos);
	212	value = value << pos;
2967dab1	213
4aeacd5b	214	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
e499ada8 MD	215	data &= mask;
	216	data \|= value;
	217
19bb7fe3	218	if (pfc->info->unlock_reg)
4aeacd5b	219	sh_pfc_write_raw_reg(
19bb7fe3	220	sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
4aeacd5b	221	~data);
e499ada8	222
4aeacd5b	223	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
2967dab1 MD	224	}
2967dab1 MD	225
533743dc	226	static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
cef28a28 GU	227	const struct pinmux_cfg_reg **crp,
cef28a28 GU	228	unsigned int fieldp, u32 valuep)
2967dab1	229	{
cef28a28	230	unsigned int k = 0;
2967dab1	231
2967dab1	232	while (1) {
cef28a28 GU	233	const struct pinmux_cfg_reg *config_reg =
	234	pfc->info->cfg_regs + k;
	235	unsigned int r_width = config_reg->reg_width;
	236	unsigned int f_width = config_reg->field_width;
	237	unsigned int curr_width;
	238	unsigned int bit_pos;
	239	unsigned int pos = 0;
	240	unsigned int m = 0;
2967dab1 MD	241
	242	if (!r_width)
	243	break;
f78a26f5	244
f78a26f5	245	for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
cef28a28 GU	246	u32 ncomb;
	247	u32 n;
	248
f78a26f5 MD	249	if (f_width)
	250	curr_width = f_width;
	251	else
	252	curr_width = config_reg->var_field_width[m];
	253
	254	ncomb = 1 << curr_width;
	255	for (n = 0; n < ncomb; n++) {
	256	if (config_reg->enum_ids[pos + n] == enum_id) {
	257	*crp = config_reg;
	258	*fieldp = m;
	259	*valuep = n;
f78a26f5 MD	260	return 0;
f78a26f5 MD	261	}
2967dab1	262	}
f78a26f5 MD	263	pos += ncomb;
f78a26f5 MD	264	m++;
2967dab1 MD	265	}
	266	k++;
	267	}
	268
b705c054	269	return -EINVAL;
2967dab1 MD	270	}
2967dab1 MD	271
533743dc LP	272	static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
533743dc LP	273	u16 *enum_idp)
2967dab1	274	{
b8b47d67	275	const u16 *data = pfc->info->pinmux_data;
8d72a7fc	276	unsigned int k;
2967dab1	277
2967dab1 MD	278	if (pos) {
	279	*enum_idp = data[pos + 1];
	280	return pos + 1;
	281	}
	282
b8b47d67	283	for (k = 0; k < pfc->info->pinmux_data_size; k++) {
a68fdca9	284	if (data[k] == mark) {
2967dab1 MD	285	*enum_idp = data[k + 1];
	286	return k + 1;
	287	}
	288	}
	289
9a643c9a LP	290	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
9a643c9a LP	291	mark);
b705c054	292	return -EINVAL;
2967dab1 MD	293	}
2967dab1 MD	294
861601de	295	int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
2967dab1	296	{
cd3c1bee	297	const struct pinmux_range *range;
cef28a28	298	int pos = 0;
2967dab1 MD	299
2967dab1 MD	300	switch (pinmux_type) {
e3c47051	301	case PINMUX_TYPE_GPIO:
2967dab1 MD	302	case PINMUX_TYPE_FUNCTION:
	303	range = NULL;
	304	break;
	305
	306	case PINMUX_TYPE_OUTPUT:
19bb7fe3	307	range = &pfc->info->output;
2967dab1 MD	308	break;
	309
	310	case PINMUX_TYPE_INPUT:
19bb7fe3	311	range = &pfc->info->input;
2967dab1 MD	312	break;
2967dab1 MD	313
2967dab1	314	default:
b705c054	315	return -EINVAL;
2967dab1 MD	316	}
2967dab1 MD	317
e3c47051	318	/* Iterate over all the configuration fields we need to update. */
2967dab1	319	while (1) {
cef28a28 GU	320	const struct pinmux_cfg_reg *cr;
	321	unsigned int field;
	322	u16 enum_id;
	323	u32 value;
	324	int in_range;
	325	int ret;
	326
a68fdca9	327	pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
b705c054 LP	328	if (pos < 0)
b705c054 LP	329	return pos;
2967dab1 MD	330
	331	if (!enum_id)
	332	break;
	333
e3c47051 LP	334	/* Check if the configuration field selects a function. If it
	335	* doesn't, skip the field if it's not applicable to the
	336	* requested pinmux type.
	337	*/
19bb7fe3	338	in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
50dd3145	339	if (!in_range) {
e3c47051 LP	340	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
	341	/* Functions are allowed to modify all
	342	* fields.
	343	*/
	344	in_range = 1;
	345	} else if (pinmux_type != PINMUX_TYPE_GPIO) {
	346	/* Input/output types can only modify fields
	347	* that correspond to their respective ranges.
50dd3145	348	*/
4aeacd5b	349	in_range = sh_pfc_enum_in_range(enum_id, range);
50dd3145 MD	350
	351	/*
	352	* special case pass through for fixed
	353	* input-only or output-only pins without
	354	* function enum register association.
	355	*/
	356	if (in_range && enum_id == range->force)
	357	continue;
50dd3145	358	}
e3c47051	359	/* GPIOs are only allowed to modify function fields. */
42eed42b MD	360	}
42eed42b MD	361
2967dab1 MD	362	if (!in_range)
	363	continue;
	364
b705c054 LP	365	ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
	366	if (ret < 0)
	367	return ret;
2967dab1	368
861601de	369	sh_pfc_write_config_reg(pfc, cr, field, value);
2967dab1 MD	370	}
	371
	372	return 0;
2967dab1 MD	373	}
2967dab1 MD	374
acac8ed5 LP	375	static int sh_pfc_init_ranges(struct sh_pfc *pfc)
	376	{
	377	struct sh_pfc_pin_range *range;
	378	unsigned int nr_ranges;
	379	unsigned int i;
	380
	381	if (pfc->info->pins[0].pin == (u16)-1) {
	382	/* Pin number -1 denotes that the SoC doesn't report pin numbers
	383	* in its pin arrays yet. Consider the pin numbers range as
	384	* continuous and allocate a single range.
	385	*/
	386	pfc->nr_ranges = 1;
	387	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
	388	GFP_KERNEL);
	389	if (pfc->ranges == NULL)
	390	return -ENOMEM;
	391
	392	pfc->ranges->start = 0;
	393	pfc->ranges->end = pfc->info->nr_pins - 1;
	394	pfc->nr_gpio_pins = pfc->info->nr_pins;
	395
	396	return 0;
	397	}
	398
4f82e3ee LP	399	/* Count, allocate and fill the ranges. The PFC SoC data pins array must
	400	* be sorted by pin numbers, and pins without a GPIO port must come
	401	* last.
	402	*/
acac8ed5 LP	403	for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
	404	if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
	405	nr_ranges++;
	406	}
	407
	408	pfc->nr_ranges = nr_ranges;
	409	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(pfc->ranges) nr_ranges,
	410	GFP_KERNEL);
	411	if (pfc->ranges == NULL)
	412	return -ENOMEM;
	413
	414	range = pfc->ranges;
	415	range->start = pfc->info->pins[0].pin;
	416
	417	for (i = 1; i < pfc->info->nr_pins; ++i) {
4f82e3ee LP	418	if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
	419	continue;
	420
	421	range->end = pfc->info->pins[i-1].pin;
	422	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
	423	pfc->nr_gpio_pins = range->end + 1;
	424
	425	range++;
	426	range->start = pfc->info->pins[i].pin;
acac8ed5 LP	427	}
	428
	429	range->end = pfc->info->pins[i-1].pin;
4f82e3ee LP	430	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
4f82e3ee LP	431	pfc->nr_gpio_pins = range->end + 1;
acac8ed5 LP	432
	433	return 0;
	434	}
	435
fe1c9a82 LP	436	#ifdef CONFIG_OF
fe1c9a82 LP	437	static const struct of_device_id sh_pfc_of_table[] = {
1e7d5d84 NS	438	#ifdef CONFIG_PINCTRL_PFC_EMEV2
	439	{
	440	.compatible = "renesas,pfc-emev2",
	441	.data = &emev2_pinmux_info,
	442	},
	443	#endif
fe1c9a82 LP	444	#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	445	{
	446	.compatible = "renesas,pfc-r8a73a4",
	447	.data = &r8a73a4_pinmux_info,
	448	},
	449	#endif
	450	#ifdef CONFIG_PINCTRL_PFC_R8A7740
	451	{
	452	.compatible = "renesas,pfc-r8a7740",
	453	.data = &r8a7740_pinmux_info,
	454	},
	455	#endif
	456	#ifdef CONFIG_PINCTRL_PFC_R8A7778
	457	{
	458	.compatible = "renesas,pfc-r8a7778",
	459	.data = &r8a7778_pinmux_info,
	460	},
	461	#endif
	462	#ifdef CONFIG_PINCTRL_PFC_R8A7779
	463	{
	464	.compatible = "renesas,pfc-r8a7779",
	465	.data = &r8a7779_pinmux_info,
	466	},
	467	#endif
	468	#ifdef CONFIG_PINCTRL_PFC_R8A7790
	469	{
	470	.compatible = "renesas,pfc-r8a7790",
	471	.data = &r8a7790_pinmux_info,
	472	},
	473	#endif
50884519 HN	474	#ifdef CONFIG_PINCTRL_PFC_R8A7791
	475	{
	476	.compatible = "renesas,pfc-r8a7791",
	477	.data = &r8a7791_pinmux_info,
	478	},
	479	#endif
19e1e98f UH	480	#ifdef CONFIG_PINCTRL_PFC_R8A7793
	481	{
	482	.compatible = "renesas,pfc-r8a7793",
	483	.data = &r8a7793_pinmux_info,
	484	},
	485	#endif
43c4436e HN	486	#ifdef CONFIG_PINCTRL_PFC_R8A7794
	487	{
	488	.compatible = "renesas,pfc-r8a7794",
	489	.data = &r8a7794_pinmux_info,
	490	},
	491	#endif
0b0ffc96 TK	492	#ifdef CONFIG_PINCTRL_PFC_R8A7795
	493	{
	494	.compatible = "renesas,pfc-r8a7795",
	495	.data = &r8a7795_pinmux_info,
	496	},
	497	#endif
fe1c9a82 LP	498	#ifdef CONFIG_PINCTRL_PFC_SH73A0
	499	{
	500	.compatible = "renesas,pfc-sh73a0",
	501	.data = &sh73a0_pinmux_info,
	502	},
	503	#endif
	504	{ },
	505	};
	506	MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
	507	#endif
	508
c6193eac	509	static int sh_pfc_probe(struct platform_device *pdev)
2967dab1	510	{
fe1c9a82 LP	511	const struct platform_device_id *platid = platform_get_device_id(pdev);
	512	#ifdef CONFIG_OF
	513	struct device_node *np = pdev->dev.of_node;
	514	#endif
cd3c1bee	515	const struct sh_pfc_soc_info *info;
c6193eac	516	struct sh_pfc *pfc;
0fc64cc0	517	int ret;
2967dab1	518
fe1c9a82 LP	519	#ifdef CONFIG_OF
	520	if (np)
	521	info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
	522	else
	523	#endif
	524	info = platid ? (const void *)platid->driver_data : NULL;
	525
19bb7fe3	526	if (info == NULL)
c6193eac	527	return -ENODEV;
2967dab1	528
8c43fcc7	529	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
c6193eac LP	530	if (pfc == NULL)
c6193eac LP	531	return -ENOMEM;
d4e62d00	532
19bb7fe3	533	pfc->info = info;
c6193eac LP	534	pfc->dev = &pdev->dev;
c6193eac LP	535
70c8f01a	536	ret = sh_pfc_map_resources(pfc, pdev);
c6193eac	537	if (unlikely(ret < 0))
b0e10211 MD	538	return ret;
b0e10211 MD	539
c6193eac	540	spin_lock_init(&pfc->lock);
69edbba0	541
0c151062 LP	542	if (info->ops && info->ops->init) {
	543	ret = info->ops->init(pfc);
	544	if (ret < 0)
	545	return ret;
	546	}
	547
ca5481c6	548	pinctrl_provide_dummies();
b0e10211	549
acac8ed5 LP	550	ret = sh_pfc_init_ranges(pfc);
	551	if (ret < 0)
	552	return ret;
	553
ca5481c6 PM	554	/*
	555	* Initialize pinctrl bindings first
	556	*/
c6193eac	557	ret = sh_pfc_register_pinctrl(pfc);
f9492fda	558	if (unlikely(ret != 0))
0a332c96	559	return ret;
ca5481c6	560
6f6a4a68	561	#ifdef CONFIG_GPIO_SH_PFC
ca5481c6 PM	562	/*
	563	* Then the GPIO chip
	564	*/
c6193eac	565	ret = sh_pfc_register_gpiochip(pfc);
6f6a4a68	566	if (unlikely(ret != 0)) {
ca5481c6 PM	567	/*
	568	* If the GPIO chip fails to come up we still leave the
	569	* PFC state as it is, given that there are already
	570	* extant users of it that have succeeded by this point.
	571	*/
9a643c9a	572	dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
b3c185a7	573	}
6f6a4a68	574	#endif
b72421d8	575
c6193eac LP	576	platform_set_drvdata(pdev, pfc);
c6193eac LP	577
9a643c9a	578	dev_info(pfc->dev, "%s support registered\n", info->name);
ca5481c6	579
b3c185a7	580	return 0;
b72421d8	581	}
6f6a4a68	582
c6193eac LP	583	static int sh_pfc_remove(struct platform_device *pdev)
	584	{
	585	struct sh_pfc *pfc = platform_get_drvdata(pdev);
	586
	587	#ifdef CONFIG_GPIO_SH_PFC
	588	sh_pfc_unregister_gpiochip(pfc);
	589	#endif
	590	sh_pfc_unregister_pinctrl(pfc);
	591
c6193eac LP	592	return 0;
	593	}
	594
	595	static const struct platform_device_id sh_pfc_id_table[] = {
ccda552e LP	596	#ifdef CONFIG_PINCTRL_PFC_SH7203
	597	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
	598	#endif
a8d42fc4 LP	599	#ifdef CONFIG_PINCTRL_PFC_SH7264
	600	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
	601	#endif
f5e811f2 LP	602	#ifdef CONFIG_PINCTRL_PFC_SH7269
	603	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
	604	#endif
74cad605 LP	605	#ifdef CONFIG_PINCTRL_PFC_SH7720
74cad605 LP	606	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
f5e25ae5 LP	607	#endif
	608	#ifdef CONFIG_PINCTRL_PFC_SH7722
	609	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
d05afa0a LP	610	#endif
	611	#ifdef CONFIG_PINCTRL_PFC_SH7723
	612	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
0ff25bab LP	613	#endif
	614	#ifdef CONFIG_PINCTRL_PFC_SH7724
	615	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
ac1ebc21 LP	616	#endif
	617	#ifdef CONFIG_PINCTRL_PFC_SH7734
	618	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
0bb92677 LP	619	#endif
	620	#ifdef CONFIG_PINCTRL_PFC_SH7757
	621	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
a56398e9 LP	622	#endif
	623	#ifdef CONFIG_PINCTRL_PFC_SH7785
	624	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
d2a31bdd LP	625	#endif
	626	#ifdef CONFIG_PINCTRL_PFC_SH7786
	627	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
d5d9a818 LP	628	#endif
	629	#ifdef CONFIG_PINCTRL_PFC_SHX3
	630	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
d5b1521a	631	#endif
c6193eac LP	632	{ "sh-pfc", 0 },
	633	{ },
	634	};
	635	MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
	636
	637	static struct platform_driver sh_pfc_driver = {
	638	.probe = sh_pfc_probe,
	639	.remove = sh_pfc_remove,
	640	.id_table = sh_pfc_id_table,
	641	.driver = {
	642	.name = DRV_NAME,
fe1c9a82	643	.of_match_table = of_match_ptr(sh_pfc_of_table),
c6193eac LP	644	},
	645	};
	646
40ee6fce LP	647	static int __init sh_pfc_init(void)
	648	{
	649	return platform_driver_register(&sh_pfc_driver);
c6193eac	650	}
40ee6fce	651	postcore_initcall(sh_pfc_init);
c6193eac LP	652
	653	static void __exit sh_pfc_exit(void)
	654	{
	655	platform_driver_unregister(&sh_pfc_driver);
	656	}
	657	module_exit(sh_pfc_exit);
	658
6f6a4a68 LP	659	MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
	660	MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
	661	MODULE_LICENSE("GPL v2");