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pinctrl: sh-pfc: checker: Add ioctrl register checks
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / core.c
CommitLineData
63b6d7e7 1// SPDX-License-Identifier: GPL-2.0
2967dab1 2/*
a43647b6
PG		 3 * Pin Control and GPIO driver for SuperH Pin Function Controller.
4 *
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
2967dab1
MD		 6 *
7 * Copyright (C) 2008 Magnus Damm
b3c185a7 8 * Copyright (C) 2009 - 2012 Paul Mundt
2967dab1 9 */
c6193eac
LP		 10
11#define DRV_NAME "sh-pfc"
b72421d8 12
90efde22 13#include <linux/bitops.h>
2967dab1 14#include <linux/err.h>
90efde22 15#include <linux/errno.h>
2967dab1 16#include <linux/io.h>
b0e10211 17#include <linux/ioport.h>
90efde22 18#include <linux/kernel.h>
a43647b6 19#include <linux/init.h>
fe1c9a82
LP		 20#include <linux/of.h>
21#include <linux/of_device.h>
ca5481c6 22#include <linux/pinctrl/machine.h>
c6193eac 23#include <linux/platform_device.h>
8843797d 24#include <linux/psci.h>
90efde22 25#include <linux/slab.h>
f2bc0756 26#include <linux/sys_soc.h>
b0e10211 27
f9165132
LP		 28#include "core.h"
29
70c8f01a
LP		 30static int sh_pfc_map_resources(struct sh_pfc *pfc,
31 struct platform_device *pdev)
b0e10211 32{
70c8f01a
LP		 33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
ad7fe1a1 35 unsigned int num_windows;
b0e10211 36 struct resource *res;
70c8f01a 37 unsigned int i;
ad7fe1a1 38 int num_irqs;
70c8f01a
LP		 39
40 /* Count the MEM and IRQ resources. */
c7977ec4
GU		 41 for (num_windows = 0;; num_windows++) {
42 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
43 if (!res)
70c8f01a 44 break;
c7977ec4 45 }
70c8f01a 46 if (num_windows == 0)
bee9f22b 47 return -EINVAL;
b0e10211 48
ad7fe1a1
GU		 49 num_irqs = platform_irq_count(pdev);
50 if (num_irqs < 0)
51 return num_irqs;
52
70c8f01a 53 /* Allocate memory windows and IRQs arrays. */
a86854d0 54 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
70c8f01a
LP		 55 GFP_KERNEL);
56 if (windows == NULL)
1724acfd 57 return -ENOMEM;
b0e10211 58
70c8f01a
LP		 59 pfc->num_windows = num_windows;
60 pfc->windows = windows;
973931ae 61
70c8f01a 62 if (num_irqs) {
a86854d0 63 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
70c8f01a
LP		 64 GFP_KERNEL);
65 if (irqs == NULL)
1724acfd 66 return -ENOMEM;
70c8f01a
LP		 67
68 pfc->num_irqs = num_irqs;
69 pfc->irqs = irqs;
70 }
71
72 /* Fill them. */
c7977ec4
GU		 73 for (i = 0; i < num_windows; i++) {
74 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
75 windows->phys = res->start;
76 windows->size = resource_size(res);
77 windows->virt = devm_ioremap_resource(pfc->dev, res);
78 if (IS_ERR(windows->virt))
79 return -ENOMEM;
80 windows++;
b0e10211 81 }
c7977ec4
GU		 82 for (i = 0; i < num_irqs; i++)
83 *irqs++ = platform_get_irq(pdev, i);
b0e10211
MD		 84
85 return 0;
b0e10211
MD		 86}
87
1f34de05 88static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
b0e10211 89{
4aeacd5b 90 struct sh_pfc_window *window;
1f34de05 91 phys_addr_t address = reg;
bee9f22b 92 unsigned int i;
b0e10211
MD		 93
94 /* scan through physical windows and convert address */
bee9f22b 95 for (i = 0; i < pfc->num_windows; i++) {
5b46ac3a 96 window = pfc->windows + i;
b0e10211
MD		 97
98 if (address < window->phys)
99 continue;
100
101 if (address >= (window->phys + window->size))
102 continue;
103
104 return window->virt + (address - window->phys);
105 }
106
bee9f22b 107 BUG();
1960d580 108 return NULL;
b0e10211 109}
2967dab1 110
1a0039dc 111int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
934cb02b 112{
63d57383
LP		 113 unsigned int offset;
114 unsigned int i;
115
acac8ed5
LP		 116 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
117 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
63d57383
LP		 118
119 if (pin <= range->end)
acac8ed5
LP		 120 return pin >= range->start
121 ? offset + pin - range->start : -1;
63d57383 122
acac8ed5 123 offset += range->end - range->start + 1;
63d57383
LP		 124 }
125
b705c054 126 return -EINVAL;
934cb02b
LP		 127}
128
533743dc 129static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
2967dab1
MD		 130{
131 if (enum_id < r->begin)
132 return 0;
133
134 if (enum_id > r->end)
135 return 0;
136
137 return 1;
138}
139
cef28a28 140u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
3292094e
MD		 141{
142 switch (reg_width) {
143 case 8:
b0e10211 144 return ioread8(mapped_reg);
3292094e 145 case 16:
b0e10211 146 return ioread16(mapped_reg);
3292094e 147 case 32:
b0e10211 148 return ioread32(mapped_reg);
3292094e
MD		 149 }
150
151 BUG();
152 return 0;
153}
154
cef28a28 155void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
fc88936a 156 u32 data)
3292094e
MD		 157{
158 switch (reg_width) {
159 case 8:
b0e10211 160 iowrite8(data, mapped_reg);
3292094e
MD		 161 return;
162 case 16:
b0e10211 163 iowrite16(data, mapped_reg);
3292094e
MD		 164 return;
165 case 32:
b0e10211 166 iowrite32(data, mapped_reg);
3292094e
MD		 167 return;
168 }
169
170 BUG();
171}
172
e16a2c7a 173u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
3caa7d8c 174{
e16a2c7a 175 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
3caa7d8c
LP		 176}
177
e16a2c7a 178void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
3caa7d8c
LP		 179{
180 if (pfc->info->unlock_reg)
181 sh_pfc_write_raw_reg(
182 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
183 ~data);
184
e16a2c7a 185 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
3caa7d8c
LP		 186}
187
4aeacd5b 188static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
cd3c1bee 189 const struct pinmux_cfg_reg *crp,
cef28a28 190 unsigned int in_pos,
fc88936a 191 void __iomem **mapped_regp, u32 *maskp,
cef28a28 192 unsigned int *posp)
2967dab1 193{
8d72a7fc 194 unsigned int k;
f78a26f5 195
4aeacd5b 196 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
2967dab1 197
f78a26f5
MD		 198 if (crp->field_width) {
199 *maskp = (1 << crp->field_width) - 1;
200 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
201 } else {
202 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
203 *posp = crp->reg_width;
204 for (k = 0; k <= in_pos; k++)
205 *posp -= crp->var_field_width[k];
206 }
18925e11
MD		 207}
208
4aeacd5b 209static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
cd3c1bee 210 const struct pinmux_cfg_reg *crp,
cef28a28 211 unsigned int field, u32 value)
0fc64cc0 212{
18925e11 213 void __iomem *mapped_reg;
cef28a28 214 unsigned int pos;
fc88936a 215 u32 mask, data;
0fc64cc0 216
4aeacd5b 217 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1 218
1f34de05 219 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
dc700715 220 "r_width = %u, f_width = %u\n",
ce16e8dd 221 crp->reg, value, field, crp->reg_width, hweight32(mask));
0fc64cc0
MD		 222
223 mask = ~(mask << pos);
224 value = value << pos;
2967dab1 225
4aeacd5b 226 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
e499ada8
MD		 227 data &= mask;
228 data |= value;
229
19bb7fe3 230 if (pfc->info->unlock_reg)
4aeacd5b 231 sh_pfc_write_raw_reg(
19bb7fe3 232 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
4aeacd5b 233 ~data);
e499ada8 234
4aeacd5b 235 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
2967dab1
MD		 236}
237
533743dc 238static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
cef28a28
GU		 239 const struct pinmux_cfg_reg **crp,
240 unsigned int *fieldp, u32 *valuep)
2967dab1 241{
cef28a28 242 unsigned int k = 0;
2967dab1 243
2967dab1 244 while (1) {
cef28a28
GU		 245 const struct pinmux_cfg_reg *config_reg =
246 pfc->info->cfg_regs + k;
247 unsigned int r_width = config_reg->reg_width;
248 unsigned int f_width = config_reg->field_width;
249 unsigned int curr_width;
250 unsigned int bit_pos;
251 unsigned int pos = 0;
252 unsigned int m = 0;
2967dab1
MD		 253
254 if (!r_width)
255 break;
f78a26f5 256
f78a26f5 257 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
cef28a28
GU		 258 u32 ncomb;
259 u32 n;
260
f78a26f5
MD		 261 if (f_width)
262 curr_width = f_width;
263 else
264 curr_width = config_reg->var_field_width[m];
265
266 ncomb = 1 << curr_width;
267 for (n = 0; n < ncomb; n++) {
268 if (config_reg->enum_ids[pos + n] == enum_id) {
269 *crp = config_reg;
270 *fieldp = m;
271 *valuep = n;
f78a26f5
MD		 272 return 0;
273 }
2967dab1 274 }
f78a26f5
MD		 275 pos += ncomb;
276 m++;
2967dab1
MD		 277 }
278 k++;
279 }
280
b705c054 281 return -EINVAL;
2967dab1
MD		 282}
283
533743dc
LP		 284static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
285 u16 *enum_idp)
2967dab1 286{
b8b47d67 287 const u16 *data = pfc->info->pinmux_data;
8d72a7fc 288 unsigned int k;
2967dab1 289
2967dab1
MD		 290 if (pos) {
291 *enum_idp = data[pos + 1];
292 return pos + 1;
293 }
294
b8b47d67 295 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
a68fdca9 296 if (data[k] == mark) {
2967dab1
MD		 297 *enum_idp = data[k + 1];
298 return k + 1;
299 }
300 }
301
9a643c9a
LP		 302 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
303 mark);
b705c054 304 return -EINVAL;
2967dab1
MD		 305}
306
861601de 307int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
2967dab1 308{
cd3c1bee 309 const struct pinmux_range *range;
cef28a28 310 int pos = 0;
2967dab1
MD		 311
312 switch (pinmux_type) {
e3c47051 313 case PINMUX_TYPE_GPIO:
2967dab1
MD		 314 case PINMUX_TYPE_FUNCTION:
315 range = NULL;
316 break;
317
318 case PINMUX_TYPE_OUTPUT:
19bb7fe3 319 range = &pfc->info->output;
2967dab1
MD		 320 break;
321
322 case PINMUX_TYPE_INPUT:
19bb7fe3 323 range = &pfc->info->input;
2967dab1
MD		 324 break;
325
2967dab1 326 default:
b705c054 327 return -EINVAL;
2967dab1
MD		 328 }
329
e3c47051 330 /* Iterate over all the configuration fields we need to update. */
2967dab1 331 while (1) {
cef28a28
GU		 332 const struct pinmux_cfg_reg *cr;
333 unsigned int field;
334 u16 enum_id;
335 u32 value;
336 int in_range;
337 int ret;
338
a68fdca9 339 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
b705c054
LP		 340 if (pos < 0)
341 return pos;
2967dab1
MD		 342
343 if (!enum_id)
344 break;
345
e3c47051
LP		 346 /* Check if the configuration field selects a function. If it
347 * doesn't, skip the field if it's not applicable to the
348 * requested pinmux type.
349 */
19bb7fe3 350 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
50dd3145 351 if (!in_range) {
e3c47051
LP		 352 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
353 /* Functions are allowed to modify all
354 * fields.
355 */
356 in_range = 1;
357 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
358 /* Input/output types can only modify fields
359 * that correspond to their respective ranges.
50dd3145 360 */
4aeacd5b 361 in_range = sh_pfc_enum_in_range(enum_id, range);
50dd3145
MD		 362
363 /*
364 * special case pass through for fixed
365 * input-only or output-only pins without
366 * function enum register association.
367 */
368 if (in_range && enum_id == range->force)
369 continue;
50dd3145 370 }
e3c47051 371 /* GPIOs are only allowed to modify function fields. */
42eed42b
MD		 372 }
373
2967dab1
MD		 374 if (!in_range)
375 continue;
376
b705c054
LP		 377 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
378 if (ret < 0)
379 return ret;
2967dab1 380
861601de 381 sh_pfc_write_config_reg(pfc, cr, field, value);
2967dab1
MD		 382 }
383
384 return 0;
2967dab1
MD		 385}
386
acdb1245
GU		 387const struct pinmux_bias_reg *
388sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
389 unsigned int *bit)
390{
391 unsigned int i, j;
392
393 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
394 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
395 if (pfc->info->bias_regs[i].pins[j] == pin) {
396 *bit = j;
397 return &pfc->info->bias_regs[i];
398 }
399 }
400 }
401
402 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
403
404 return NULL;
405}
406
acac8ed5
LP		 407static int sh_pfc_init_ranges(struct sh_pfc *pfc)
408{
409 struct sh_pfc_pin_range *range;
410 unsigned int nr_ranges;
411 unsigned int i;
412
413 if (pfc->info->pins[0].pin == (u16)-1) {
414 /* Pin number -1 denotes that the SoC doesn't report pin numbers
415 * in its pin arrays yet. Consider the pin numbers range as
416 * continuous and allocate a single range.
417 */
418 pfc->nr_ranges = 1;
419 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
420 GFP_KERNEL);
421 if (pfc->ranges == NULL)
422 return -ENOMEM;
423
424 pfc->ranges->start = 0;
425 pfc->ranges->end = pfc->info->nr_pins - 1;
426 pfc->nr_gpio_pins = pfc->info->nr_pins;
427
428 return 0;
429 }
430
4f82e3ee
LP		 431 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
432 * be sorted by pin numbers, and pins without a GPIO port must come
433 * last.
434 */
acac8ed5
LP		 435 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
436 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
437 nr_ranges++;
438 }
439
440 pfc->nr_ranges = nr_ranges;
a86854d0 441 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
acac8ed5
LP		 442 GFP_KERNEL);
443 if (pfc->ranges == NULL)
444 return -ENOMEM;
445
446 range = pfc->ranges;
447 range->start = pfc->info->pins[0].pin;
448
449 for (i = 1; i < pfc->info->nr_pins; ++i) {
4f82e3ee
LP		 450 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
451 continue;
452
453 range->end = pfc->info->pins[i-1].pin;
454 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
455 pfc->nr_gpio_pins = range->end + 1;
456
457 range++;
458 range->start = pfc->info->pins[i].pin;
acac8ed5
LP		 459 }
460
461 range->end = pfc->info->pins[i-1].pin;
4f82e3ee
LP		 462 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
463 pfc->nr_gpio_pins = range->end + 1;
acac8ed5
LP		 464
465 return 0;
466}
467
fe1c9a82
LP		 468#ifdef CONFIG_OF
469static const struct of_device_id sh_pfc_of_table[] = {
1e7d5d84
NS		 470#ifdef CONFIG_PINCTRL_PFC_EMEV2
471 {
472 .compatible = "renesas,pfc-emev2",
473 .data = &emev2_pinmux_info,
474 },
475#endif
fe1c9a82
LP		 476#ifdef CONFIG_PINCTRL_PFC_R8A73A4
477 {
478 .compatible = "renesas,pfc-r8a73a4",
479 .data = &r8a73a4_pinmux_info,
480 },
481#endif
482#ifdef CONFIG_PINCTRL_PFC_R8A7740
483 {
484 .compatible = "renesas,pfc-r8a7740",
485 .data = &r8a7740_pinmux_info,
486 },
487#endif
8df62701
SS		 488#ifdef CONFIG_PINCTRL_PFC_R8A7743
489 {
490 .compatible = "renesas,pfc-r8a7743",
491 .data = &r8a7743_pinmux_info,
492 },
493#endif
d7097b97
BD		 494#ifdef CONFIG_PINCTRL_PFC_R8A7744
495 {
496 .compatible = "renesas,pfc-r8a7744",
497 .data = &r8a7744_pinmux_info,
498 },
499#endif
c8bac70f
SS		 500#ifdef CONFIG_PINCTRL_PFC_R8A7745
501 {
502 .compatible = "renesas,pfc-r8a7745",
503 .data = &r8a7745_pinmux_info,
504 },
505#endif
73dacc34
BD		 506#ifdef CONFIG_PINCTRL_PFC_R8A77470
507 {
508 .compatible = "renesas,pfc-r8a77470",
509 .data = &r8a77470_pinmux_info,
510 },
511#endif
91d627a7
BD		 512#ifdef CONFIG_PINCTRL_PFC_R8A774A1
513 {
514 .compatible = "renesas,pfc-r8a774a1",
515 .data = &r8a774a1_pinmux_info,
516 },
517#endif
271ff378
BD		 518#ifdef CONFIG_PINCTRL_PFC_R8A774B1
519 {
520 .compatible = "renesas,pfc-r8a774b1",
521 .data = &r8a774b1_pinmux_info,
522 },
523#endif
9f2b76a2
FC		 524#ifdef CONFIG_PINCTRL_PFC_R8A774C0
525 {
526 .compatible = "renesas,pfc-r8a774c0",
527 .data = &r8a774c0_pinmux_info,
528 },
529#endif
fe1c9a82
LP		 530#ifdef CONFIG_PINCTRL_PFC_R8A7778
531 {
532 .compatible = "renesas,pfc-r8a7778",
533 .data = &r8a7778_pinmux_info,
534 },
535#endif
536#ifdef CONFIG_PINCTRL_PFC_R8A7779
537 {
538 .compatible = "renesas,pfc-r8a7779",
539 .data = &r8a7779_pinmux_info,
540 },
541#endif
542#ifdef CONFIG_PINCTRL_PFC_R8A7790
543 {
544 .compatible = "renesas,pfc-r8a7790",
545 .data = &r8a7790_pinmux_info,
546 },
547#endif
50884519
HN		 548#ifdef CONFIG_PINCTRL_PFC_R8A7791
549 {
550 .compatible = "renesas,pfc-r8a7791",
551 .data = &r8a7791_pinmux_info,
552 },
553#endif
2cf59e0c
SS		 554#ifdef CONFIG_PINCTRL_PFC_R8A7792
555 {
556 .compatible = "renesas,pfc-r8a7792",
557 .data = &r8a7792_pinmux_info,
558 },
559#endif
19e1e98f
UH		 560#ifdef CONFIG_PINCTRL_PFC_R8A7793
561 {
562 .compatible = "renesas,pfc-r8a7793",
563 .data = &r8a7793_pinmux_info,
564 },
565#endif
43c4436e
HN		 566#ifdef CONFIG_PINCTRL_PFC_R8A7794
567 {
568 .compatible = "renesas,pfc-r8a7794",
569 .data = &r8a7794_pinmux_info,
570 },
571#endif
f2bc0756
GU		 572/* Both r8a7795 entries must be present to make sanity checks work */
573#ifdef CONFIG_PINCTRL_PFC_R8A77950
0b0ffc96
TK		 574 {
575 .compatible = "renesas,pfc-r8a7795",
f2bc0756 576 .data = &r8a77950_pinmux_info,
0b0ffc96 577 },
f2bc0756
GU		 578#endif
579#ifdef CONFIG_PINCTRL_PFC_R8A77951
6161b39a 580 {
f2bc0756
GU		 581 .compatible = "renesas,pfc-r8a7795",
582 .data = &r8a77951_pinmux_info,
6161b39a 583 },
0b0ffc96 584#endif
d15ca3a3 585#ifdef CONFIG_PINCTRL_PFC_R8A77960
f9aece73
TK		 586 {
587 .compatible = "renesas,pfc-r8a7796",
d15ca3a3 588 .data = &r8a77960_pinmux_info,
f9aece73
TK		 589 },
590#endif
708c69e9
GU		 591#ifdef CONFIG_PINCTRL_PFC_R8A77961
592 {
593 .compatible = "renesas,pfc-r8a77961",
594 .data = &r8a77961_pinmux_info,
595 },
596#endif
490e687e
JM		 597#ifdef CONFIG_PINCTRL_PFC_R8A77965
598 {
599 .compatible = "renesas,pfc-r8a77965",
600 .data = &r8a77965_pinmux_info,
601 },
602#endif
b92ac66a
SS		 603#ifdef CONFIG_PINCTRL_PFC_R8A77970
604 {
605 .compatible = "renesas,pfc-r8a77970",
606 .data = &r8a77970_pinmux_info,
607 },
608#endif
f5912524
SS		 609#ifdef CONFIG_PINCTRL_PFC_R8A77980
610 {
611 .compatible = "renesas,pfc-r8a77980",
612 .data = &r8a77980_pinmux_info,
613 },
614#endif
6d4036a1
TK		 615#ifdef CONFIG_PINCTRL_PFC_R8A77990
616 {
617 .compatible = "renesas,pfc-r8a77990",
618 .data = &r8a77990_pinmux_info,
619 },
620#endif
794a6711
TK		 621#ifdef CONFIG_PINCTRL_PFC_R8A77995
622 {
623 .compatible = "renesas,pfc-r8a77995",
624 .data = &r8a77995_pinmux_info,
625 },
626#endif
fe1c9a82
LP		 627#ifdef CONFIG_PINCTRL_PFC_SH73A0
628 {
629 .compatible = "renesas,pfc-sh73a0",
630 .data = &sh73a0_pinmux_info,
631 },
632#endif
633 { },
634};
fe1c9a82
LP		 635#endif
636
8843797d
GU		 637#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
638static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
639{
640}
641
642static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
643{
644 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
645}
646
647static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
648{
649 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
650}
651
652static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
653 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
654{
655 unsigned int i, n = 0;
656
657 if (pfc->info->cfg_regs)
658 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
659 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
660
661 if (pfc->info->drive_regs)
662 for (i = 0; pfc->info->drive_regs[i].reg; i++)
663 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
664
665 if (pfc->info->bias_regs)
666 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
667 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
668 if (pfc->info->bias_regs[i].pud)
669 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
670 }
671
672 if (pfc->info->ioctrl_regs)
673 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
674 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
675
676 return n;
677}
678
679static int sh_pfc_suspend_init(struct sh_pfc *pfc)
680{
681 unsigned int n;
682
683 /* This is the best we can do to check for the presence of PSCI */
684 if (!psci_ops.cpu_suspend)
685 return 0;
686
687 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
688 if (!n)
689 return 0;
690
691 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
692 sizeof(*pfc->saved_regs),
693 GFP_KERNEL);
694 if (!pfc->saved_regs)
695 return -ENOMEM;
696
697 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
698 return 0;
699}
700
701static int sh_pfc_suspend_noirq(struct device *dev)
702{
703 struct sh_pfc *pfc = dev_get_drvdata(dev);
704
705 if (pfc->saved_regs)
706 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
707 return 0;
708}
709
710static int sh_pfc_resume_noirq(struct device *dev)
711{
712 struct sh_pfc *pfc = dev_get_drvdata(dev);
713
714 if (pfc->saved_regs)
715 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
716 return 0;
717}
718
719static const struct dev_pm_ops sh_pfc_pm = {
720 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
721};
722#define DEV_PM_OPS &sh_pfc_pm
723#else
724static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
725#define DEV_PM_OPS NULL
726#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
727
6161b39a 728#ifdef DEBUG
3c261864 729#define SH_PFC_MAX_REGS 300
12d057ba 730#define SH_PFC_MAX_ENUMS 3000
3c261864 731
26471693
GU		 732static unsigned int sh_pfc_errors __initdata = 0;
733static unsigned int sh_pfc_warnings __initdata = 0;
3c261864
GU		 734static u32 *sh_pfc_regs __initdata = NULL;
735static u32 sh_pfc_num_regs __initdata = 0;
12d057ba
GU		 736static u16 *sh_pfc_enums __initdata = NULL;
737static u32 sh_pfc_num_enums __initdata = 0;
26471693 738
c3f8dcee
GU		 739#define sh_pfc_err(fmt, ...) \
740 do { \
741 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
742 sh_pfc_errors++; \
743 } while (0)
744#define sh_pfc_warn(fmt, ...) \
745 do { \
746 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
747 sh_pfc_warnings++; \
748 } while (0)
749
80cde64f 750static bool __init is0s(const u16 *enum_ids, unsigned int n)
6161b39a
GU		 751{
752 unsigned int i;
753
754 for (i = 0; i < n; i++)
755 if (enum_ids[i])
756 return false;
757
758 return true;
759}
760
1251887c
GU		 761static bool __init same_name(const char *a, const char *b)
762{
763 if (!a || !b)
764 return false;
765
766 return !strcmp(a, b);
767}
768
3c261864
GU		 769static void __init sh_pfc_check_reg(const char *drvname, u32 reg)
770{
771 unsigned int i;
772
773 for (i = 0; i < sh_pfc_num_regs; i++)
774 if (reg == sh_pfc_regs[i]) {
775 sh_pfc_err("reg 0x%x conflict\n", reg);
776 return;
777 }
778
779 if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
780 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
781 return;
782 }
783
784 sh_pfc_regs[sh_pfc_num_regs++] = reg;
785}
786
12d057ba
GU		 787static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
788{
789 unsigned int i;
790
791 for (i = 0; i < sh_pfc_num_enums; i++) {
792 if (enum_id == sh_pfc_enums[i])
793 return -EINVAL;
794 }
795
796 if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
797 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
798 return 0;
799 }
800
801 sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
802 return 0;
803}
804
805static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
806 const u16 *enums, unsigned int n)
807{
808 unsigned int i;
809
810 for (i = 0; i < n; i++) {
811 if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
812 sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
813 enums[i]);
814 }
815}
816
08df16e0
GU		 817static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,
818 u32 reg, unsigned int pin)
819{
820 const char *drvname = info->name;
821 unsigned int i;
822
823 if (pin == SH_PFC_PIN_NONE)
824 return;
825
826 for (i = 0; i < info->nr_pins; i++) {
827 if (pin == info->pins[i].pin)
828 return;
829 }
830
831 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
832}
833
80cde64f
GU		 834static void __init sh_pfc_check_cfg_reg(const char *drvname,
835 const struct pinmux_cfg_reg *cfg_reg)
6161b39a
GU		 836{
837 unsigned int i, n, rw, fw;
838
3c261864
GU		 839 sh_pfc_check_reg(drvname, cfg_reg->reg);
840
6161b39a 841 if (cfg_reg->field_width) {
12d057ba
GU		 842 n = cfg_reg->reg_width / cfg_reg->field_width;
843 /* Skip field checks (done at build time) */
844 goto check_enum_ids;
6161b39a
GU		 845 }
846
847 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
c3f8dcee
GU		 848 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw))
849 sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
850 cfg_reg->reg, rw, rw + fw - 1);
6161b39a
GU		 851 n += 1 << fw;
852 rw += fw;
853 }
854
c3f8dcee
GU		 855 if (rw != cfg_reg->reg_width)
856 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
857 cfg_reg->reg, rw, cfg_reg->reg_width);
fa4d3671 858
c3f8dcee
GU		 859 if (n != cfg_reg->nr_enum_ids)
860 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
861 cfg_reg->reg, cfg_reg->nr_enum_ids, n);
12d057ba
GU		 862
863check_enum_ids:
864 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
6161b39a
GU		 865}
866
08df16e0
GU		 867static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
868 const struct pinmux_drive_reg *drive)
869{
870 const char *drvname = info->name;
871 unsigned long seen = 0, mask;
872 unsigned int i;
873
874 sh_pfc_check_reg(info->name, drive->reg);
875 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
876 const struct pinmux_drive_reg_field *field = &drive->fields[i];
877
878 if (!field->pin && !field->offset && !field->size)
879 continue;
880
881 mask = GENMASK(field->offset + field->size, field->offset);
882 if (mask & seen)
883 sh_pfc_err("drive_reg 0x%x: field %u overlap\n",
884 drive->reg, i);
885 seen |= mask;
886
887 sh_pfc_check_pin(info, drive->reg, field->pin);
888 }
889}
890
8990cd29
GU		 891static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
892 const struct pinmux_bias_reg *bias)
893{
894 unsigned int i;
895
896 sh_pfc_check_reg(info->name, bias->puen);
897 if (bias->pud)
898 sh_pfc_check_reg(info->name, bias->pud);
899 for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
900 sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
901}
902
80cde64f 903static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
6161b39a 904{
6161b39a
GU		 905 const char *drvname = info->name;
906 unsigned int *refcnts;
907 unsigned int i, j, k;
908
909 pr_info("Checking %s\n", drvname);
3c261864 910 sh_pfc_num_regs = 0;
12d057ba 911 sh_pfc_num_enums = 0;
6161b39a 912
542ffc9e
GU		 913 /* Check pins */
914 for (i = 0; i < info->nr_pins; i++) {
4ef30dc7
GU		 915 const struct sh_pfc_pin *pin = &info->pins[i];
916
917 if (!pin->name) {
918 sh_pfc_err("empty pin %u\n", i);
919 continue;
920 }
542ffc9e 921 for (j = 0; j < i; j++) {
4ef30dc7
GU		 922 const struct sh_pfc_pin *pin2 = &info->pins[j];
923
924 if (same_name(pin->name, pin2->name))
925 sh_pfc_err("pin %s: name conflict\n",
926 pin->name);
542ffc9e 927
4ef30dc7 928 if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
c3f8dcee 929 sh_pfc_err("pin %s/%s: pin %u conflict\n",
4ef30dc7 930 pin->name, pin2->name, pin->pin);
542ffc9e 931
4ef30dc7 932 if (pin->enum_id && pin->enum_id == pin2->enum_id)
c3f8dcee 933 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
4ef30dc7
GU		 934 pin->name, pin2->name,
935 pin->enum_id);
542ffc9e
GU		 936 }
937 }
938
6161b39a
GU		 939 /* Check groups and functions */
940 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
941 if (!refcnts)
942 return;
943
944 for (i = 0; i < info->nr_functions; i++) {
a95b077d
GU		 945 const struct sh_pfc_function *func = &info->functions[i];
946
3dd5fd79 947 if (!func->name) {
c3f8dcee 948 sh_pfc_err("empty function %u\n", i);
3dd5fd79
GU		 949 continue;
950 }
a95b077d
GU		 951 for (j = 0; j < i; j++) {
952 if (same_name(func->name, info->functions[j].name))
953 sh_pfc_err("function %s: name conflict\n",
954 func->name);
955 }
6161b39a
GU		 956 for (j = 0; j < func->nr_groups; j++) {
957 for (k = 0; k < info->nr_groups; k++) {
1251887c
GU		 958 if (same_name(func->groups[j],
959 info->groups[k].name)) {
6161b39a
GU		 960 refcnts[k]++;
961 break;
962 }
963 }
964
c3f8dcee
GU		 965 if (k == info->nr_groups)
966 sh_pfc_err("function %s: group %s not found\n",
967 func->name, func->groups[j]);
6161b39a
GU		 968 }
969 }
970
971 for (i = 0; i < info->nr_groups; i++) {
40c8e4aa
GU		 972 const struct sh_pfc_pin_group *group = &info->groups[i];
973
974 if (!group->name) {
c3f8dcee 975 sh_pfc_err("empty group %u\n", i);
3dd5fd79
GU		 976 continue;
977 }
40c8e4aa
GU		 978 for (j = 0; j < i; j++) {
979 if (same_name(group->name, info->groups[j].name))
980 sh_pfc_err("group %s: name conflict\n",
981 group->name);
982 }
c3f8dcee 983 if (!refcnts[i])
40c8e4aa 984 sh_pfc_err("orphan group %s\n", group->name);
c3f8dcee
GU		 985 else if (refcnts[i] > 1)
986 sh_pfc_warn("group %s referenced by %u functions\n",
40c8e4aa 987 group->name, refcnts[i]);
6161b39a
GU		 988 }
989
990 kfree(refcnts);
991
992 /* Check config register descriptions */
993 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
994 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
08df16e0
GU		 995
996 /* Check drive strength registers */
997 for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)
998 sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
8990cd29
GU		 999
1000 /* Check bias registers */
1001 for (i = 0; info->bias_regs && info->bias_regs[i].puen; i++)
1002 sh_pfc_check_bias_reg(info, &info->bias_regs[i]);
4bd7d16a
GU		 1003
1004 /* Check ioctrl registers */
1005 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1006 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg);
6161b39a
GU		 1007}
1008
80cde64f 1009static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
6161b39a
GU		 1010{
1011 unsigned int i;
1012
3c261864
GU		 1013 sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1014 GFP_KERNEL);
1015 if (!sh_pfc_regs)
1016 return;
1017
12d057ba
GU		 1018 sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1019 GFP_KERNEL);
1020 if (!sh_pfc_enums)
1021 goto free_regs;
1022
6161b39a
GU		 1023 pr_warn("Checking builtin pinmux tables\n");
1024
1025 for (i = 0; pdrv->id_table[i].name[0]; i++)
1026 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1027
1028#ifdef CONFIG_OF
1029 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1030 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1031#endif
1032
1033 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
1034 sh_pfc_warnings);
3c261864 1035
12d057ba
GU		 1036 kfree(sh_pfc_enums);
1037free_regs:
3c261864 1038 kfree(sh_pfc_regs);
6161b39a
GU		 1039}
1040
1041#else /* !DEBUG */
1042static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1043#endif /* !DEBUG */
1044
f2bc0756
GU		 1045#ifdef CONFIG_OF
1046static const void *sh_pfc_quirk_match(void)
1047{
1048#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
1049 defined(CONFIG_PINCTRL_PFC_R8A77951)
1050 const struct soc_device_attribute *match;
1051 static const struct soc_device_attribute quirks[] = {
1052 {
1053 .soc_id = "r8a7795", .revision = "ES1.*",
1054 .data = &r8a77950_pinmux_info,
1055 },
1056 {
1057 .soc_id = "r8a7795",
1058 .data = &r8a77951_pinmux_info,
1059 },
1060
1061 { /* sentinel */ }
1062 };
1063
1064 match = soc_device_match(quirks);
1065 if (match)
1066 return match->data ?: ERR_PTR(-ENODEV);
1067#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
1068
1069 return NULL;
1070}
1071#endif /* CONFIG_OF */
1072
c6193eac 1073static int sh_pfc_probe(struct platform_device *pdev)
2967dab1 1074{
cd3c1bee 1075 const struct sh_pfc_soc_info *info;
c6193eac 1076 struct sh_pfc *pfc;
0fc64cc0 1077 int ret;
2967dab1 1078
fe1c9a82 1079#ifdef CONFIG_OF
f2bc0756
GU		 1080 if (pdev->dev.of_node) {
1081 info = sh_pfc_quirk_match();
1082 if (IS_ERR(info))
1083 return PTR_ERR(info);
1084
1085 if (!info)
1086 info = of_device_get_match_data(&pdev->dev);
1087 } else
fe1c9a82 1088#endif
35406b1f 1089 info = (const void *)platform_get_device_id(pdev)->driver_data;
2967dab1 1090
8c43fcc7 1091 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
c6193eac
LP		 1092 if (pfc == NULL)
1093 return -ENOMEM;
d4e62d00 1094
19bb7fe3 1095 pfc->info = info;
c6193eac
LP		 1096 pfc->dev = &pdev->dev;
1097
70c8f01a 1098 ret = sh_pfc_map_resources(pfc, pdev);
c6193eac 1099 if (unlikely(ret < 0))
b0e10211
MD		 1100 return ret;
1101
c6193eac 1102 spin_lock_init(&pfc->lock);
69edbba0 1103
0c151062
LP		 1104 if (info->ops && info->ops->init) {
1105 ret = info->ops->init(pfc);
1106 if (ret < 0)
1107 return ret;
3091ae77
GU		 1108
1109 /* .init() may have overridden pfc->info */
1110 info = pfc->info;
0c151062
LP		 1111 }
1112
8843797d
GU		 1113 ret = sh_pfc_suspend_init(pfc);
1114 if (ret)
1115 return ret;
1116
0129801b
WS		 1117 /* Enable dummy states for those platforms without pinctrl support */
1118 if (!of_have_populated_dt())
1119 pinctrl_provide_dummies();
b0e10211 1120
acac8ed5
LP		 1121 ret = sh_pfc_init_ranges(pfc);
1122 if (ret < 0)
1123 return ret;
1124
ca5481c6
PM		 1125 /*
1126 * Initialize pinctrl bindings first
1127 */
c6193eac 1128 ret = sh_pfc_register_pinctrl(pfc);
f9492fda 1129 if (unlikely(ret != 0))
0a332c96 1130 return ret;
ca5481c6 1131
abc60d48 1132#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
ca5481c6
PM		 1133 /*
1134 * Then the GPIO chip
1135 */
c6193eac 1136 ret = sh_pfc_register_gpiochip(pfc);
6f6a4a68 1137 if (unlikely(ret != 0)) {
ca5481c6
PM		 1138 /*
1139 * If the GPIO chip fails to come up we still leave the
1140 * PFC state as it is, given that there are already
1141 * extant users of it that have succeeded by this point.
1142 */
9a643c9a 1143 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
b3c185a7 1144 }
6f6a4a68 1145#endif
b72421d8 1146
c6193eac
LP		 1147 platform_set_drvdata(pdev, pfc);
1148
9a643c9a 1149 dev_info(pfc->dev, "%s support registered\n", info->name);
ca5481c6 1150
b3c185a7 1151 return 0;
b72421d8 1152}
6f6a4a68 1153
c6193eac 1154static const struct platform_device_id sh_pfc_id_table[] = {
ccda552e
LP		 1155#ifdef CONFIG_PINCTRL_PFC_SH7203
1156 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1157#endif
a8d42fc4
LP		 1158#ifdef CONFIG_PINCTRL_PFC_SH7264
1159 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1160#endif
f5e811f2
LP		 1161#ifdef CONFIG_PINCTRL_PFC_SH7269
1162 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1163#endif
74cad605
LP		 1164#ifdef CONFIG_PINCTRL_PFC_SH7720
1165 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
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LP		 1166#endif
1167#ifdef CONFIG_PINCTRL_PFC_SH7722
1168 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
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LP		 1169#endif
1170#ifdef CONFIG_PINCTRL_PFC_SH7723
1171 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
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LP		 1172#endif
1173#ifdef CONFIG_PINCTRL_PFC_SH7724
1174 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
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LP		 1175#endif
1176#ifdef CONFIG_PINCTRL_PFC_SH7734
1177 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
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LP		 1178#endif
1179#ifdef CONFIG_PINCTRL_PFC_SH7757
1180 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
a56398e9
LP		 1181#endif
1182#ifdef CONFIG_PINCTRL_PFC_SH7785
1183 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
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LP		 1184#endif
1185#ifdef CONFIG_PINCTRL_PFC_SH7786
1186 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
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LP		 1187#endif
1188#ifdef CONFIG_PINCTRL_PFC_SHX3
1189 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
d5b1521a 1190#endif
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LP		 1191 { },
1192};
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LP		 1193
1194static struct platform_driver sh_pfc_driver = {
1195 .probe = sh_pfc_probe,
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LP		 1196 .id_table = sh_pfc_id_table,
1197 .driver = {
1198 .name = DRV_NAME,
fe1c9a82 1199 .of_match_table = of_match_ptr(sh_pfc_of_table),
8843797d 1200 .pm = DEV_PM_OPS,
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LP		 1201 },
1202};
1203
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LP		 1204static int __init sh_pfc_init(void)
1205{
6161b39a 1206 sh_pfc_check_driver(&sh_pfc_driver);
40ee6fce 1207 return platform_driver_register(&sh_pfc_driver);
c6193eac 1208}
40ee6fce 1209postcore_initcall(sh_pfc_init);
Linux 6.x block layer and io_uring tree(s)