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pinctrl: sh-pfc: Add check for empty pinmux groups/functions
[linux-2.6-block.git] / drivers / pinctrl / sh-pfc / core.c
CommitLineData
63b6d7e7 1// SPDX-License-Identifier: GPL-2.0
2967dab1 2/*
a43647b6
PG		 3 * Pin Control and GPIO driver for SuperH Pin Function Controller.
4 *
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
2967dab1
MD		 6 *
7 * Copyright (C) 2008 Magnus Damm
b3c185a7 8 * Copyright (C) 2009 - 2012 Paul Mundt
2967dab1 9 */
c6193eac
LP		 10
11#define DRV_NAME "sh-pfc"
b72421d8 12
90efde22 13#include <linux/bitops.h>
2967dab1 14#include <linux/err.h>
90efde22 15#include <linux/errno.h>
2967dab1 16#include <linux/io.h>
b0e10211 17#include <linux/ioport.h>
90efde22 18#include <linux/kernel.h>
a43647b6 19#include <linux/init.h>
fe1c9a82
LP		 20#include <linux/of.h>
21#include <linux/of_device.h>
ca5481c6 22#include <linux/pinctrl/machine.h>
c6193eac 23#include <linux/platform_device.h>
8843797d 24#include <linux/psci.h>
90efde22 25#include <linux/slab.h>
b0e10211 26
f9165132
LP		 27#include "core.h"
28
70c8f01a
LP		 29static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev)
b0e10211 31{
c7977ec4 32 unsigned int num_windows, num_irqs;
70c8f01a
LP		 33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
b0e10211 35 struct resource *res;
70c8f01a 36 unsigned int i;
c7977ec4 37 int irq;
70c8f01a
LP		 38
39 /* Count the MEM and IRQ resources. */
c7977ec4
GU		 40 for (num_windows = 0;; num_windows++) {
41 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
42 if (!res)
70c8f01a 43 break;
c7977ec4
GU		 44 }
45 for (num_irqs = 0;; num_irqs++) {
46 irq = platform_get_irq(pdev, num_irqs);
47 if (irq == -EPROBE_DEFER)
48 return irq;
49 if (irq < 0)
70c8f01a 50 break;
70c8f01a 51 }
b0e10211 52
70c8f01a 53 if (num_windows == 0)
bee9f22b 54 return -EINVAL;
b0e10211 55
70c8f01a 56 /* Allocate memory windows and IRQs arrays. */
a86854d0 57 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
70c8f01a
LP		 58 GFP_KERNEL);
59 if (windows == NULL)
1724acfd 60 return -ENOMEM;
b0e10211 61
70c8f01a
LP		 62 pfc->num_windows = num_windows;
63 pfc->windows = windows;
973931ae 64
70c8f01a 65 if (num_irqs) {
a86854d0 66 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
70c8f01a
LP		 67 GFP_KERNEL);
68 if (irqs == NULL)
1724acfd 69 return -ENOMEM;
70c8f01a
LP		 70
71 pfc->num_irqs = num_irqs;
72 pfc->irqs = irqs;
73 }
74
75 /* Fill them. */
c7977ec4
GU		 76 for (i = 0; i < num_windows; i++) {
77 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
78 windows->phys = res->start;
79 windows->size = resource_size(res);
80 windows->virt = devm_ioremap_resource(pfc->dev, res);
81 if (IS_ERR(windows->virt))
82 return -ENOMEM;
83 windows++;
b0e10211 84 }
c7977ec4
GU		 85 for (i = 0; i < num_irqs; i++)
86 *irqs++ = platform_get_irq(pdev, i);
b0e10211
MD		 87
88 return 0;
b0e10211
MD		 89}
90
1f34de05 91static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
b0e10211 92{
4aeacd5b 93 struct sh_pfc_window *window;
1f34de05 94 phys_addr_t address = reg;
bee9f22b 95 unsigned int i;
b0e10211
MD		 96
97 /* scan through physical windows and convert address */
bee9f22b 98 for (i = 0; i < pfc->num_windows; i++) {
5b46ac3a 99 window = pfc->windows + i;
b0e10211
MD		 100
101 if (address < window->phys)
102 continue;
103
104 if (address >= (window->phys + window->size))
105 continue;
106
107 return window->virt + (address - window->phys);
108 }
109
bee9f22b 110 BUG();
1960d580 111 return NULL;
b0e10211 112}
2967dab1 113
1a0039dc 114int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
934cb02b 115{
63d57383
LP		 116 unsigned int offset;
117 unsigned int i;
118
acac8ed5
LP		 119 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
120 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
63d57383
LP		 121
122 if (pin <= range->end)
acac8ed5
LP		 123 return pin >= range->start
124 ? offset + pin - range->start : -1;
63d57383 125
acac8ed5 126 offset += range->end - range->start + 1;
63d57383
LP		 127 }
128
b705c054 129 return -EINVAL;
934cb02b
LP		 130}
131
533743dc 132static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
2967dab1
MD		 133{
134 if (enum_id < r->begin)
135 return 0;
136
137 if (enum_id > r->end)
138 return 0;
139
140 return 1;
141}
142
cef28a28 143u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
3292094e
MD		 144{
145 switch (reg_width) {
146 case 8:
b0e10211 147 return ioread8(mapped_reg);
3292094e 148 case 16:
b0e10211 149 return ioread16(mapped_reg);
3292094e 150 case 32:
b0e10211 151 return ioread32(mapped_reg);
3292094e
MD		 152 }
153
154 BUG();
155 return 0;
156}
157
cef28a28 158void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
fc88936a 159 u32 data)
3292094e
MD		 160{
161 switch (reg_width) {
162 case 8:
b0e10211 163 iowrite8(data, mapped_reg);
3292094e
MD		 164 return;
165 case 16:
b0e10211 166 iowrite16(data, mapped_reg);
3292094e
MD		 167 return;
168 case 32:
b0e10211 169 iowrite32(data, mapped_reg);
3292094e
MD		 170 return;
171 }
172
173 BUG();
174}
175
e16a2c7a 176u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
3caa7d8c 177{
e16a2c7a 178 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
3caa7d8c
LP		 179}
180
e16a2c7a 181void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
3caa7d8c
LP		 182{
183 if (pfc->info->unlock_reg)
184 sh_pfc_write_raw_reg(
185 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
186 ~data);
187
e16a2c7a 188 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
3caa7d8c
LP		 189}
190
4aeacd5b 191static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
cd3c1bee 192 const struct pinmux_cfg_reg *crp,
cef28a28 193 unsigned int in_pos,
fc88936a 194 void __iomem **mapped_regp, u32 *maskp,
cef28a28 195 unsigned int *posp)
2967dab1 196{
8d72a7fc 197 unsigned int k;
f78a26f5 198
4aeacd5b 199 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
2967dab1 200
f78a26f5
MD		 201 if (crp->field_width) {
202 *maskp = (1 << crp->field_width) - 1;
203 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
204 } else {
205 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
206 *posp = crp->reg_width;
207 for (k = 0; k <= in_pos; k++)
208 *posp -= crp->var_field_width[k];
209 }
18925e11
MD		 210}
211
4aeacd5b 212static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
cd3c1bee 213 const struct pinmux_cfg_reg *crp,
cef28a28 214 unsigned int field, u32 value)
0fc64cc0 215{
18925e11 216 void __iomem *mapped_reg;
cef28a28 217 unsigned int pos;
fc88936a 218 u32 mask, data;
0fc64cc0 219
4aeacd5b 220 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1 221
1f34de05 222 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
dc700715 223 "r_width = %u, f_width = %u\n",
ce16e8dd 224 crp->reg, value, field, crp->reg_width, hweight32(mask));
0fc64cc0
MD		 225
226 mask = ~(mask << pos);
227 value = value << pos;
2967dab1 228
4aeacd5b 229 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
e499ada8
MD		 230 data &= mask;
231 data |= value;
232
19bb7fe3 233 if (pfc->info->unlock_reg)
4aeacd5b 234 sh_pfc_write_raw_reg(
19bb7fe3 235 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
4aeacd5b 236 ~data);
e499ada8 237
4aeacd5b 238 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
2967dab1
MD		 239}
240
533743dc 241static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
cef28a28
GU		 242 const struct pinmux_cfg_reg **crp,
243 unsigned int *fieldp, u32 *valuep)
2967dab1 244{
cef28a28 245 unsigned int k = 0;
2967dab1 246
2967dab1 247 while (1) {
cef28a28
GU		 248 const struct pinmux_cfg_reg *config_reg =
249 pfc->info->cfg_regs + k;
250 unsigned int r_width = config_reg->reg_width;
251 unsigned int f_width = config_reg->field_width;
252 unsigned int curr_width;
253 unsigned int bit_pos;
254 unsigned int pos = 0;
255 unsigned int m = 0;
2967dab1
MD		 256
257 if (!r_width)
258 break;
f78a26f5 259
f78a26f5 260 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
cef28a28
GU		 261 u32 ncomb;
262 u32 n;
263
f78a26f5
MD		 264 if (f_width)
265 curr_width = f_width;
266 else
267 curr_width = config_reg->var_field_width[m];
268
269 ncomb = 1 << curr_width;
270 for (n = 0; n < ncomb; n++) {
271 if (config_reg->enum_ids[pos + n] == enum_id) {
272 *crp = config_reg;
273 *fieldp = m;
274 *valuep = n;
f78a26f5
MD		 275 return 0;
276 }
2967dab1 277 }
f78a26f5
MD		 278 pos += ncomb;
279 m++;
2967dab1
MD		 280 }
281 k++;
282 }
283
b705c054 284 return -EINVAL;
2967dab1
MD		 285}
286
533743dc
LP		 287static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
288 u16 *enum_idp)
2967dab1 289{
b8b47d67 290 const u16 *data = pfc->info->pinmux_data;
8d72a7fc 291 unsigned int k;
2967dab1 292
2967dab1
MD		 293 if (pos) {
294 *enum_idp = data[pos + 1];
295 return pos + 1;
296 }
297
b8b47d67 298 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
a68fdca9 299 if (data[k] == mark) {
2967dab1
MD		 300 *enum_idp = data[k + 1];
301 return k + 1;
302 }
303 }
304
9a643c9a
LP		 305 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
306 mark);
b705c054 307 return -EINVAL;
2967dab1
MD		 308}
309
861601de 310int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
2967dab1 311{
cd3c1bee 312 const struct pinmux_range *range;
cef28a28 313 int pos = 0;
2967dab1
MD		 314
315 switch (pinmux_type) {
e3c47051 316 case PINMUX_TYPE_GPIO:
2967dab1
MD		 317 case PINMUX_TYPE_FUNCTION:
318 range = NULL;
319 break;
320
321 case PINMUX_TYPE_OUTPUT:
19bb7fe3 322 range = &pfc->info->output;
2967dab1
MD		 323 break;
324
325 case PINMUX_TYPE_INPUT:
19bb7fe3 326 range = &pfc->info->input;
2967dab1
MD		 327 break;
328
2967dab1 329 default:
b705c054 330 return -EINVAL;
2967dab1
MD		 331 }
332
e3c47051 333 /* Iterate over all the configuration fields we need to update. */
2967dab1 334 while (1) {
cef28a28
GU		 335 const struct pinmux_cfg_reg *cr;
336 unsigned int field;
337 u16 enum_id;
338 u32 value;
339 int in_range;
340 int ret;
341
a68fdca9 342 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
b705c054
LP		 343 if (pos < 0)
344 return pos;
2967dab1
MD		 345
346 if (!enum_id)
347 break;
348
e3c47051
LP		 349 /* Check if the configuration field selects a function. If it
350 * doesn't, skip the field if it's not applicable to the
351 * requested pinmux type.
352 */
19bb7fe3 353 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
50dd3145 354 if (!in_range) {
e3c47051
LP		 355 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
356 /* Functions are allowed to modify all
357 * fields.
358 */
359 in_range = 1;
360 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
361 /* Input/output types can only modify fields
362 * that correspond to their respective ranges.
50dd3145 363 */
4aeacd5b 364 in_range = sh_pfc_enum_in_range(enum_id, range);
50dd3145
MD		 365
366 /*
367 * special case pass through for fixed
368 * input-only or output-only pins without
369 * function enum register association.
370 */
371 if (in_range && enum_id == range->force)
372 continue;
50dd3145 373 }
e3c47051 374 /* GPIOs are only allowed to modify function fields. */
42eed42b
MD		 375 }
376
2967dab1
MD		 377 if (!in_range)
378 continue;
379
b705c054
LP		 380 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
381 if (ret < 0)
382 return ret;
2967dab1 383
861601de 384 sh_pfc_write_config_reg(pfc, cr, field, value);
2967dab1
MD		 385 }
386
387 return 0;
2967dab1
MD		 388}
389
acdb1245
GU		 390const struct pinmux_bias_reg *
391sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
392 unsigned int *bit)
393{
394 unsigned int i, j;
395
396 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
397 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
398 if (pfc->info->bias_regs[i].pins[j] == pin) {
399 *bit = j;
400 return &pfc->info->bias_regs[i];
401 }
402 }
403 }
404
405 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
406
407 return NULL;
408}
409
acac8ed5
LP		 410static int sh_pfc_init_ranges(struct sh_pfc *pfc)
411{
412 struct sh_pfc_pin_range *range;
413 unsigned int nr_ranges;
414 unsigned int i;
415
416 if (pfc->info->pins[0].pin == (u16)-1) {
417 /* Pin number -1 denotes that the SoC doesn't report pin numbers
418 * in its pin arrays yet. Consider the pin numbers range as
419 * continuous and allocate a single range.
420 */
421 pfc->nr_ranges = 1;
422 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
423 GFP_KERNEL);
424 if (pfc->ranges == NULL)
425 return -ENOMEM;
426
427 pfc->ranges->start = 0;
428 pfc->ranges->end = pfc->info->nr_pins - 1;
429 pfc->nr_gpio_pins = pfc->info->nr_pins;
430
431 return 0;
432 }
433
4f82e3ee
LP		 434 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
435 * be sorted by pin numbers, and pins without a GPIO port must come
436 * last.
437 */
acac8ed5
LP		 438 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
439 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
440 nr_ranges++;
441 }
442
443 pfc->nr_ranges = nr_ranges;
a86854d0 444 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
acac8ed5
LP		 445 GFP_KERNEL);
446 if (pfc->ranges == NULL)
447 return -ENOMEM;
448
449 range = pfc->ranges;
450 range->start = pfc->info->pins[0].pin;
451
452 for (i = 1; i < pfc->info->nr_pins; ++i) {
4f82e3ee
LP		 453 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
454 continue;
455
456 range->end = pfc->info->pins[i-1].pin;
457 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
458 pfc->nr_gpio_pins = range->end + 1;
459
460 range++;
461 range->start = pfc->info->pins[i].pin;
acac8ed5
LP		 462 }
463
464 range->end = pfc->info->pins[i-1].pin;
4f82e3ee
LP		 465 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
466 pfc->nr_gpio_pins = range->end + 1;
acac8ed5
LP		 467
468 return 0;
469}
470
fe1c9a82
LP		 471#ifdef CONFIG_OF
472static const struct of_device_id sh_pfc_of_table[] = {
1e7d5d84
NS		 473#ifdef CONFIG_PINCTRL_PFC_EMEV2
474 {
475 .compatible = "renesas,pfc-emev2",
476 .data = &emev2_pinmux_info,
477 },
478#endif
fe1c9a82
LP		 479#ifdef CONFIG_PINCTRL_PFC_R8A73A4
480 {
481 .compatible = "renesas,pfc-r8a73a4",
482 .data = &r8a73a4_pinmux_info,
483 },
484#endif
485#ifdef CONFIG_PINCTRL_PFC_R8A7740
486 {
487 .compatible = "renesas,pfc-r8a7740",
488 .data = &r8a7740_pinmux_info,
489 },
490#endif
8df62701
SS		 491#ifdef CONFIG_PINCTRL_PFC_R8A7743
492 {
493 .compatible = "renesas,pfc-r8a7743",
494 .data = &r8a7743_pinmux_info,
495 },
496#endif
d7097b97
BD		 497#ifdef CONFIG_PINCTRL_PFC_R8A7744
498 {
499 .compatible = "renesas,pfc-r8a7744",
500 .data = &r8a7744_pinmux_info,
501 },
502#endif
c8bac70f
SS		 503#ifdef CONFIG_PINCTRL_PFC_R8A7745
504 {
505 .compatible = "renesas,pfc-r8a7745",
506 .data = &r8a7745_pinmux_info,
507 },
508#endif
73dacc34
BD		 509#ifdef CONFIG_PINCTRL_PFC_R8A77470
510 {
511 .compatible = "renesas,pfc-r8a77470",
512 .data = &r8a77470_pinmux_info,
513 },
514#endif
91d627a7
BD		 515#ifdef CONFIG_PINCTRL_PFC_R8A774A1
516 {
517 .compatible = "renesas,pfc-r8a774a1",
518 .data = &r8a774a1_pinmux_info,
519 },
520#endif
9f2b76a2
FC		 521#ifdef CONFIG_PINCTRL_PFC_R8A774C0
522 {
523 .compatible = "renesas,pfc-r8a774c0",
524 .data = &r8a774c0_pinmux_info,
525 },
526#endif
fe1c9a82
LP		 527#ifdef CONFIG_PINCTRL_PFC_R8A7778
528 {
529 .compatible = "renesas,pfc-r8a7778",
530 .data = &r8a7778_pinmux_info,
531 },
532#endif
533#ifdef CONFIG_PINCTRL_PFC_R8A7779
534 {
535 .compatible = "renesas,pfc-r8a7779",
536 .data = &r8a7779_pinmux_info,
537 },
538#endif
539#ifdef CONFIG_PINCTRL_PFC_R8A7790
540 {
541 .compatible = "renesas,pfc-r8a7790",
542 .data = &r8a7790_pinmux_info,
543 },
544#endif
50884519
HN		 545#ifdef CONFIG_PINCTRL_PFC_R8A7791
546 {
547 .compatible = "renesas,pfc-r8a7791",
548 .data = &r8a7791_pinmux_info,
549 },
550#endif
2cf59e0c
SS		 551#ifdef CONFIG_PINCTRL_PFC_R8A7792
552 {
553 .compatible = "renesas,pfc-r8a7792",
554 .data = &r8a7792_pinmux_info,
555 },
556#endif
19e1e98f
UH		 557#ifdef CONFIG_PINCTRL_PFC_R8A7793
558 {
559 .compatible = "renesas,pfc-r8a7793",
560 .data = &r8a7793_pinmux_info,
561 },
562#endif
43c4436e
HN		 563#ifdef CONFIG_PINCTRL_PFC_R8A7794
564 {
565 .compatible = "renesas,pfc-r8a7794",
566 .data = &r8a7794_pinmux_info,
567 },
568#endif
0b0ffc96
TK		 569#ifdef CONFIG_PINCTRL_PFC_R8A7795
570 {
571 .compatible = "renesas,pfc-r8a7795",
572 .data = &r8a7795_pinmux_info,
573 },
6161b39a
GU		 574#ifdef DEBUG
575 {
576 /* For sanity checks only (nothing matches against this) */
577 .compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */
578 .data = &r8a7795es1_pinmux_info,
579 },
580#endif /* DEBUG */
0b0ffc96 581#endif
f9aece73
TK		 582#ifdef CONFIG_PINCTRL_PFC_R8A7796
583 {
584 .compatible = "renesas,pfc-r8a7796",
585 .data = &r8a7796_pinmux_info,
586 },
587#endif
490e687e
JM		 588#ifdef CONFIG_PINCTRL_PFC_R8A77965
589 {
590 .compatible = "renesas,pfc-r8a77965",
591 .data = &r8a77965_pinmux_info,
592 },
593#endif
b92ac66a
SS		 594#ifdef CONFIG_PINCTRL_PFC_R8A77970
595 {
596 .compatible = "renesas,pfc-r8a77970",
597 .data = &r8a77970_pinmux_info,
598 },
599#endif
f5912524
SS		 600#ifdef CONFIG_PINCTRL_PFC_R8A77980
601 {
602 .compatible = "renesas,pfc-r8a77980",
603 .data = &r8a77980_pinmux_info,
604 },
605#endif
6d4036a1
TK		 606#ifdef CONFIG_PINCTRL_PFC_R8A77990
607 {
608 .compatible = "renesas,pfc-r8a77990",
609 .data = &r8a77990_pinmux_info,
610 },
611#endif
794a6711
TK		 612#ifdef CONFIG_PINCTRL_PFC_R8A77995
613 {
614 .compatible = "renesas,pfc-r8a77995",
615 .data = &r8a77995_pinmux_info,
616 },
617#endif
fe1c9a82
LP		 618#ifdef CONFIG_PINCTRL_PFC_SH73A0
619 {
620 .compatible = "renesas,pfc-sh73a0",
621 .data = &sh73a0_pinmux_info,
622 },
623#endif
624 { },
625};
fe1c9a82
LP		 626#endif
627
8843797d
GU		 628#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
629static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
630{
631}
632
633static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
634{
635 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
636}
637
638static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
639{
640 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
641}
642
643static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
644 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
645{
646 unsigned int i, n = 0;
647
648 if (pfc->info->cfg_regs)
649 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
650 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
651
652 if (pfc->info->drive_regs)
653 for (i = 0; pfc->info->drive_regs[i].reg; i++)
654 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
655
656 if (pfc->info->bias_regs)
657 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
658 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
659 if (pfc->info->bias_regs[i].pud)
660 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
661 }
662
663 if (pfc->info->ioctrl_regs)
664 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
665 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
666
667 return n;
668}
669
670static int sh_pfc_suspend_init(struct sh_pfc *pfc)
671{
672 unsigned int n;
673
674 /* This is the best we can do to check for the presence of PSCI */
675 if (!psci_ops.cpu_suspend)
676 return 0;
677
678 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
679 if (!n)
680 return 0;
681
682 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
683 sizeof(*pfc->saved_regs),
684 GFP_KERNEL);
685 if (!pfc->saved_regs)
686 return -ENOMEM;
687
688 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
689 return 0;
690}
691
692static int sh_pfc_suspend_noirq(struct device *dev)
693{
694 struct sh_pfc *pfc = dev_get_drvdata(dev);
695
696 if (pfc->saved_regs)
697 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
698 return 0;
699}
700
701static int sh_pfc_resume_noirq(struct device *dev)
702{
703 struct sh_pfc *pfc = dev_get_drvdata(dev);
704
705 if (pfc->saved_regs)
706 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
707 return 0;
708}
709
710static const struct dev_pm_ops sh_pfc_pm = {
711 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
712};
713#define DEV_PM_OPS &sh_pfc_pm
714#else
715static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
716#define DEV_PM_OPS NULL
717#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
718
6161b39a 719#ifdef DEBUG
80cde64f 720static bool __init is0s(const u16 *enum_ids, unsigned int n)
6161b39a
GU		 721{
722 unsigned int i;
723
724 for (i = 0; i < n; i++)
725 if (enum_ids[i])
726 return false;
727
728 return true;
729}
730
80cde64f
GU		 731static unsigned int sh_pfc_errors __initdata = 0;
732static unsigned int sh_pfc_warnings __initdata = 0;
6161b39a 733
80cde64f
GU		 734static void __init sh_pfc_check_cfg_reg(const char *drvname,
735 const struct pinmux_cfg_reg *cfg_reg)
6161b39a
GU		 736{
737 unsigned int i, n, rw, fw;
738
739 if (cfg_reg->field_width) {
740 /* Checked at build time */
741 return;
742 }
743
744 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
745 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
746 pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
747 drvname, cfg_reg->reg, rw, rw + fw - 1);
748 sh_pfc_warnings++;
749 }
750 n += 1 << fw;
751 rw += fw;
752 }
753
754 if (rw != cfg_reg->reg_width) {
755 pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
756 drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
757 sh_pfc_errors++;
fa4d3671
GU		 758 }
759
760 if (n != cfg_reg->nr_enum_ids) {
761 pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
762 drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
763 sh_pfc_errors++;
6161b39a
GU		 764 }
765}
766
80cde64f 767static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
6161b39a
GU		 768{
769 const struct sh_pfc_function *func;
770 const char *drvname = info->name;
771 unsigned int *refcnts;
772 unsigned int i, j, k;
773
774 pr_info("Checking %s\n", drvname);
775
776 /* Check groups and functions */
777 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
778 if (!refcnts)
779 return;
780
781 for (i = 0; i < info->nr_functions; i++) {
782 func = &info->functions[i];
3dd5fd79
GU		 783 if (!func->name) {
784 pr_err("%s: empty function %u\n", drvname, i);
785 sh_pfc_errors++;
786 continue;
787 }
6161b39a
GU		 788 for (j = 0; j < func->nr_groups; j++) {
789 for (k = 0; k < info->nr_groups; k++) {
3dd5fd79
GU		 790 if (info->groups[k].name &&
791 !strcmp(func->groups[j],
6161b39a
GU		 792 info->groups[k].name)) {
793 refcnts[k]++;
794 break;
795 }
796 }
797
798 if (k == info->nr_groups) {
799 pr_err("%s: function %s: group %s not found\n",
800 drvname, func->name, func->groups[j]);
801 sh_pfc_errors++;
802 }
803 }
804 }
805
806 for (i = 0; i < info->nr_groups; i++) {
3dd5fd79
GU		 807 if (!info->groups[i].name) {
808 pr_err("%s: empty group %u\n", drvname, i);
809 sh_pfc_errors++;
810 continue;
811 }
6161b39a
GU		 812 if (!refcnts[i]) {
813 pr_err("%s: orphan group %s\n", drvname,
814 info->groups[i].name);
815 sh_pfc_errors++;
816 } else if (refcnts[i] > 1) {
5f304f8c
GU		 817 pr_warn("%s: group %s referenced by %u functions\n",
818 drvname, info->groups[i].name, refcnts[i]);
6161b39a
GU		 819 sh_pfc_warnings++;
820 }
821 }
822
823 kfree(refcnts);
824
825 /* Check config register descriptions */
826 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
827 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
828}
829
80cde64f 830static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
6161b39a
GU		 831{
832 unsigned int i;
833
834 pr_warn("Checking builtin pinmux tables\n");
835
836 for (i = 0; pdrv->id_table[i].name[0]; i++)
837 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
838
839#ifdef CONFIG_OF
840 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
841 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
842#endif
843
844 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
845 sh_pfc_warnings);
846}
847
848#else /* !DEBUG */
849static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
850#endif /* !DEBUG */
851
c6193eac 852static int sh_pfc_probe(struct platform_device *pdev)
2967dab1 853{
fe1c9a82
LP		 854#ifdef CONFIG_OF
855 struct device_node *np = pdev->dev.of_node;
856#endif
cd3c1bee 857 const struct sh_pfc_soc_info *info;
c6193eac 858 struct sh_pfc *pfc;
0fc64cc0 859 int ret;
2967dab1 860
fe1c9a82
LP		 861#ifdef CONFIG_OF
862 if (np)
331207af 863 info = of_device_get_match_data(&pdev->dev);
fe1c9a82
LP		 864 else
865#endif
35406b1f 866 info = (const void *)platform_get_device_id(pdev)->driver_data;
2967dab1 867
8c43fcc7 868 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
c6193eac
LP		 869 if (pfc == NULL)
870 return -ENOMEM;
d4e62d00 871
19bb7fe3 872 pfc->info = info;
c6193eac
LP		 873 pfc->dev = &pdev->dev;
874
70c8f01a 875 ret = sh_pfc_map_resources(pfc, pdev);
c6193eac 876 if (unlikely(ret < 0))
b0e10211
MD		 877 return ret;
878
c6193eac 879 spin_lock_init(&pfc->lock);
69edbba0 880
0c151062
LP		 881 if (info->ops && info->ops->init) {
882 ret = info->ops->init(pfc);
883 if (ret < 0)
884 return ret;
3091ae77
GU		 885
886 /* .init() may have overridden pfc->info */
887 info = pfc->info;
0c151062
LP		 888 }
889
8843797d
GU		 890 ret = sh_pfc_suspend_init(pfc);
891 if (ret)
892 return ret;
893
0129801b
WS		 894 /* Enable dummy states for those platforms without pinctrl support */
895 if (!of_have_populated_dt())
896 pinctrl_provide_dummies();
b0e10211 897
acac8ed5
LP		 898 ret = sh_pfc_init_ranges(pfc);
899 if (ret < 0)
900 return ret;
901
ca5481c6
PM		 902 /*
903 * Initialize pinctrl bindings first
904 */
c6193eac 905 ret = sh_pfc_register_pinctrl(pfc);
f9492fda 906 if (unlikely(ret != 0))
0a332c96 907 return ret;
ca5481c6 908
abc60d48 909#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
ca5481c6
PM		 910 /*
911 * Then the GPIO chip
912 */
c6193eac 913 ret = sh_pfc_register_gpiochip(pfc);
6f6a4a68 914 if (unlikely(ret != 0)) {
ca5481c6
PM		 915 /*
916 * If the GPIO chip fails to come up we still leave the
917 * PFC state as it is, given that there are already
918 * extant users of it that have succeeded by this point.
919 */
9a643c9a 920 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
b3c185a7 921 }
6f6a4a68 922#endif
b72421d8 923
c6193eac
LP		 924 platform_set_drvdata(pdev, pfc);
925
9a643c9a 926 dev_info(pfc->dev, "%s support registered\n", info->name);
ca5481c6 927
b3c185a7 928 return 0;
b72421d8 929}
6f6a4a68 930
c6193eac 931static const struct platform_device_id sh_pfc_id_table[] = {
ccda552e
LP		 932#ifdef CONFIG_PINCTRL_PFC_SH7203
933 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
934#endif
a8d42fc4
LP		 935#ifdef CONFIG_PINCTRL_PFC_SH7264
936 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
937#endif
f5e811f2
LP		 938#ifdef CONFIG_PINCTRL_PFC_SH7269
939 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
940#endif
74cad605
LP		 941#ifdef CONFIG_PINCTRL_PFC_SH7720
942 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
f5e25ae5
LP		 943#endif
944#ifdef CONFIG_PINCTRL_PFC_SH7722
945 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
d05afa0a
LP		 946#endif
947#ifdef CONFIG_PINCTRL_PFC_SH7723
948 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
0ff25bab
LP		 949#endif
950#ifdef CONFIG_PINCTRL_PFC_SH7724
951 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
ac1ebc21
LP		 952#endif
953#ifdef CONFIG_PINCTRL_PFC_SH7734
954 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
0bb92677
LP		 955#endif
956#ifdef CONFIG_PINCTRL_PFC_SH7757
957 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
a56398e9
LP		 958#endif
959#ifdef CONFIG_PINCTRL_PFC_SH7785
960 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
d2a31bdd
LP		 961#endif
962#ifdef CONFIG_PINCTRL_PFC_SH7786
963 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
d5d9a818
LP		 964#endif
965#ifdef CONFIG_PINCTRL_PFC_SHX3
966 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
d5b1521a 967#endif
c6193eac
LP		 968 { },
969};
c6193eac
LP		 970
971static struct platform_driver sh_pfc_driver = {
972 .probe = sh_pfc_probe,
c6193eac
LP		 973 .id_table = sh_pfc_id_table,
974 .driver = {
975 .name = DRV_NAME,
fe1c9a82 976 .of_match_table = of_match_ptr(sh_pfc_of_table),
8843797d 977 .pm = DEV_PM_OPS,
c6193eac
LP		 978 },
979};
980
40ee6fce
LP		 981static int __init sh_pfc_init(void)
982{
6161b39a 983 sh_pfc_check_driver(&sh_pfc_driver);
40ee6fce 984 return platform_driver_register(&sh_pfc_driver);
c6193eac 985}
40ee6fce 986postcore_initcall(sh_pfc_init);
Linux 6.x block layer and io_uring tree(s)