Commit | Line | Data |
---|---|---|
2967dab1 | 1 | /* |
a43647b6 PG |
2 | * Pin Control and GPIO driver for SuperH Pin Function Controller. |
3 | * | |
4 | * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart | |
2967dab1 MD |
5 | * |
6 | * Copyright (C) 2008 Magnus Damm | |
b3c185a7 | 7 | * Copyright (C) 2009 - 2012 Paul Mundt |
2967dab1 MD |
8 | * |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
c6193eac LP |
13 | |
14 | #define DRV_NAME "sh-pfc" | |
b72421d8 | 15 | |
90efde22 | 16 | #include <linux/bitops.h> |
2967dab1 | 17 | #include <linux/err.h> |
90efde22 | 18 | #include <linux/errno.h> |
2967dab1 | 19 | #include <linux/io.h> |
b0e10211 | 20 | #include <linux/ioport.h> |
90efde22 | 21 | #include <linux/kernel.h> |
a43647b6 | 22 | #include <linux/init.h> |
fe1c9a82 LP |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
ca5481c6 | 25 | #include <linux/pinctrl/machine.h> |
c6193eac | 26 | #include <linux/platform_device.h> |
8843797d | 27 | #include <linux/psci.h> |
90efde22 | 28 | #include <linux/slab.h> |
b0e10211 | 29 | |
f9165132 LP |
30 | #include "core.h" |
31 | ||
70c8f01a LP |
32 | static int sh_pfc_map_resources(struct sh_pfc *pfc, |
33 | struct platform_device *pdev) | |
b0e10211 | 34 | { |
c7977ec4 | 35 | unsigned int num_windows, num_irqs; |
70c8f01a LP |
36 | struct sh_pfc_window *windows; |
37 | unsigned int *irqs = NULL; | |
b0e10211 | 38 | struct resource *res; |
70c8f01a | 39 | unsigned int i; |
c7977ec4 | 40 | int irq; |
70c8f01a LP |
41 | |
42 | /* Count the MEM and IRQ resources. */ | |
c7977ec4 GU |
43 | for (num_windows = 0;; num_windows++) { |
44 | res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows); | |
45 | if (!res) | |
70c8f01a | 46 | break; |
c7977ec4 GU |
47 | } |
48 | for (num_irqs = 0;; num_irqs++) { | |
49 | irq = platform_get_irq(pdev, num_irqs); | |
50 | if (irq == -EPROBE_DEFER) | |
51 | return irq; | |
52 | if (irq < 0) | |
70c8f01a | 53 | break; |
70c8f01a | 54 | } |
b0e10211 | 55 | |
70c8f01a | 56 | if (num_windows == 0) |
bee9f22b | 57 | return -EINVAL; |
b0e10211 | 58 | |
70c8f01a | 59 | /* Allocate memory windows and IRQs arrays. */ |
a86854d0 | 60 | windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows), |
70c8f01a LP |
61 | GFP_KERNEL); |
62 | if (windows == NULL) | |
1724acfd | 63 | return -ENOMEM; |
b0e10211 | 64 | |
70c8f01a LP |
65 | pfc->num_windows = num_windows; |
66 | pfc->windows = windows; | |
973931ae | 67 | |
70c8f01a | 68 | if (num_irqs) { |
a86854d0 | 69 | irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs), |
70c8f01a LP |
70 | GFP_KERNEL); |
71 | if (irqs == NULL) | |
1724acfd | 72 | return -ENOMEM; |
70c8f01a LP |
73 | |
74 | pfc->num_irqs = num_irqs; | |
75 | pfc->irqs = irqs; | |
76 | } | |
77 | ||
78 | /* Fill them. */ | |
c7977ec4 GU |
79 | for (i = 0; i < num_windows; i++) { |
80 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | |
81 | windows->phys = res->start; | |
82 | windows->size = resource_size(res); | |
83 | windows->virt = devm_ioremap_resource(pfc->dev, res); | |
84 | if (IS_ERR(windows->virt)) | |
85 | return -ENOMEM; | |
86 | windows++; | |
b0e10211 | 87 | } |
c7977ec4 GU |
88 | for (i = 0; i < num_irqs; i++) |
89 | *irqs++ = platform_get_irq(pdev, i); | |
b0e10211 MD |
90 | |
91 | return 0; | |
b0e10211 MD |
92 | } |
93 | ||
1f34de05 | 94 | static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) |
b0e10211 | 95 | { |
4aeacd5b | 96 | struct sh_pfc_window *window; |
1f34de05 | 97 | phys_addr_t address = reg; |
bee9f22b | 98 | unsigned int i; |
b0e10211 MD |
99 | |
100 | /* scan through physical windows and convert address */ | |
bee9f22b | 101 | for (i = 0; i < pfc->num_windows; i++) { |
5b46ac3a | 102 | window = pfc->windows + i; |
b0e10211 MD |
103 | |
104 | if (address < window->phys) | |
105 | continue; | |
106 | ||
107 | if (address >= (window->phys + window->size)) | |
108 | continue; | |
109 | ||
110 | return window->virt + (address - window->phys); | |
111 | } | |
112 | ||
bee9f22b | 113 | BUG(); |
1960d580 | 114 | return NULL; |
b0e10211 | 115 | } |
2967dab1 | 116 | |
1a0039dc | 117 | int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) |
934cb02b | 118 | { |
63d57383 LP |
119 | unsigned int offset; |
120 | unsigned int i; | |
121 | ||
acac8ed5 LP |
122 | for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { |
123 | const struct sh_pfc_pin_range *range = &pfc->ranges[i]; | |
63d57383 LP |
124 | |
125 | if (pin <= range->end) | |
acac8ed5 LP |
126 | return pin >= range->start |
127 | ? offset + pin - range->start : -1; | |
63d57383 | 128 | |
acac8ed5 | 129 | offset += range->end - range->start + 1; |
63d57383 LP |
130 | } |
131 | ||
b705c054 | 132 | return -EINVAL; |
934cb02b LP |
133 | } |
134 | ||
533743dc | 135 | static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) |
2967dab1 MD |
136 | { |
137 | if (enum_id < r->begin) | |
138 | return 0; | |
139 | ||
140 | if (enum_id > r->end) | |
141 | return 0; | |
142 | ||
143 | return 1; | |
144 | } | |
145 | ||
cef28a28 | 146 | u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) |
3292094e MD |
147 | { |
148 | switch (reg_width) { | |
149 | case 8: | |
b0e10211 | 150 | return ioread8(mapped_reg); |
3292094e | 151 | case 16: |
b0e10211 | 152 | return ioread16(mapped_reg); |
3292094e | 153 | case 32: |
b0e10211 | 154 | return ioread32(mapped_reg); |
3292094e MD |
155 | } |
156 | ||
157 | BUG(); | |
158 | return 0; | |
159 | } | |
160 | ||
cef28a28 | 161 | void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, |
fc88936a | 162 | u32 data) |
3292094e MD |
163 | { |
164 | switch (reg_width) { | |
165 | case 8: | |
b0e10211 | 166 | iowrite8(data, mapped_reg); |
3292094e MD |
167 | return; |
168 | case 16: | |
b0e10211 | 169 | iowrite16(data, mapped_reg); |
3292094e MD |
170 | return; |
171 | case 32: | |
b0e10211 | 172 | iowrite32(data, mapped_reg); |
3292094e MD |
173 | return; |
174 | } | |
175 | ||
176 | BUG(); | |
177 | } | |
178 | ||
e16a2c7a | 179 | u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) |
3caa7d8c | 180 | { |
e16a2c7a | 181 | return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32); |
3caa7d8c LP |
182 | } |
183 | ||
e16a2c7a | 184 | void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) |
3caa7d8c LP |
185 | { |
186 | if (pfc->info->unlock_reg) | |
187 | sh_pfc_write_raw_reg( | |
188 | sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, | |
189 | ~data); | |
190 | ||
e16a2c7a | 191 | sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data); |
3caa7d8c LP |
192 | } |
193 | ||
4aeacd5b | 194 | static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, |
cd3c1bee | 195 | const struct pinmux_cfg_reg *crp, |
cef28a28 | 196 | unsigned int in_pos, |
fc88936a | 197 | void __iomem **mapped_regp, u32 *maskp, |
cef28a28 | 198 | unsigned int *posp) |
2967dab1 | 199 | { |
8d72a7fc | 200 | unsigned int k; |
f78a26f5 | 201 | |
4aeacd5b | 202 | *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); |
2967dab1 | 203 | |
f78a26f5 MD |
204 | if (crp->field_width) { |
205 | *maskp = (1 << crp->field_width) - 1; | |
206 | *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); | |
207 | } else { | |
208 | *maskp = (1 << crp->var_field_width[in_pos]) - 1; | |
209 | *posp = crp->reg_width; | |
210 | for (k = 0; k <= in_pos; k++) | |
211 | *posp -= crp->var_field_width[k]; | |
212 | } | |
18925e11 MD |
213 | } |
214 | ||
4aeacd5b | 215 | static void sh_pfc_write_config_reg(struct sh_pfc *pfc, |
cd3c1bee | 216 | const struct pinmux_cfg_reg *crp, |
cef28a28 | 217 | unsigned int field, u32 value) |
0fc64cc0 | 218 | { |
18925e11 | 219 | void __iomem *mapped_reg; |
cef28a28 | 220 | unsigned int pos; |
fc88936a | 221 | u32 mask, data; |
0fc64cc0 | 222 | |
4aeacd5b | 223 | sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 224 | |
1f34de05 | 225 | dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " |
dc700715 | 226 | "r_width = %u, f_width = %u\n", |
9a643c9a | 227 | crp->reg, value, field, crp->reg_width, crp->field_width); |
0fc64cc0 MD |
228 | |
229 | mask = ~(mask << pos); | |
230 | value = value << pos; | |
2967dab1 | 231 | |
4aeacd5b | 232 | data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); |
e499ada8 MD |
233 | data &= mask; |
234 | data |= value; | |
235 | ||
19bb7fe3 | 236 | if (pfc->info->unlock_reg) |
4aeacd5b | 237 | sh_pfc_write_raw_reg( |
19bb7fe3 | 238 | sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, |
4aeacd5b | 239 | ~data); |
e499ada8 | 240 | |
4aeacd5b | 241 | sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); |
2967dab1 MD |
242 | } |
243 | ||
533743dc | 244 | static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, |
cef28a28 GU |
245 | const struct pinmux_cfg_reg **crp, |
246 | unsigned int *fieldp, u32 *valuep) | |
2967dab1 | 247 | { |
cef28a28 | 248 | unsigned int k = 0; |
2967dab1 | 249 | |
2967dab1 | 250 | while (1) { |
cef28a28 GU |
251 | const struct pinmux_cfg_reg *config_reg = |
252 | pfc->info->cfg_regs + k; | |
253 | unsigned int r_width = config_reg->reg_width; | |
254 | unsigned int f_width = config_reg->field_width; | |
255 | unsigned int curr_width; | |
256 | unsigned int bit_pos; | |
257 | unsigned int pos = 0; | |
258 | unsigned int m = 0; | |
2967dab1 MD |
259 | |
260 | if (!r_width) | |
261 | break; | |
f78a26f5 | 262 | |
f78a26f5 | 263 | for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { |
cef28a28 GU |
264 | u32 ncomb; |
265 | u32 n; | |
266 | ||
f78a26f5 MD |
267 | if (f_width) |
268 | curr_width = f_width; | |
269 | else | |
270 | curr_width = config_reg->var_field_width[m]; | |
271 | ||
272 | ncomb = 1 << curr_width; | |
273 | for (n = 0; n < ncomb; n++) { | |
274 | if (config_reg->enum_ids[pos + n] == enum_id) { | |
275 | *crp = config_reg; | |
276 | *fieldp = m; | |
277 | *valuep = n; | |
f78a26f5 MD |
278 | return 0; |
279 | } | |
2967dab1 | 280 | } |
f78a26f5 MD |
281 | pos += ncomb; |
282 | m++; | |
2967dab1 MD |
283 | } |
284 | k++; | |
285 | } | |
286 | ||
b705c054 | 287 | return -EINVAL; |
2967dab1 MD |
288 | } |
289 | ||
533743dc LP |
290 | static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, |
291 | u16 *enum_idp) | |
2967dab1 | 292 | { |
b8b47d67 | 293 | const u16 *data = pfc->info->pinmux_data; |
8d72a7fc | 294 | unsigned int k; |
2967dab1 | 295 | |
2967dab1 MD |
296 | if (pos) { |
297 | *enum_idp = data[pos + 1]; | |
298 | return pos + 1; | |
299 | } | |
300 | ||
b8b47d67 | 301 | for (k = 0; k < pfc->info->pinmux_data_size; k++) { |
a68fdca9 | 302 | if (data[k] == mark) { |
2967dab1 MD |
303 | *enum_idp = data[k + 1]; |
304 | return k + 1; | |
305 | } | |
306 | } | |
307 | ||
9a643c9a LP |
308 | dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", |
309 | mark); | |
b705c054 | 310 | return -EINVAL; |
2967dab1 MD |
311 | } |
312 | ||
861601de | 313 | int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) |
2967dab1 | 314 | { |
cd3c1bee | 315 | const struct pinmux_range *range; |
cef28a28 | 316 | int pos = 0; |
2967dab1 MD |
317 | |
318 | switch (pinmux_type) { | |
e3c47051 | 319 | case PINMUX_TYPE_GPIO: |
2967dab1 MD |
320 | case PINMUX_TYPE_FUNCTION: |
321 | range = NULL; | |
322 | break; | |
323 | ||
324 | case PINMUX_TYPE_OUTPUT: | |
19bb7fe3 | 325 | range = &pfc->info->output; |
2967dab1 MD |
326 | break; |
327 | ||
328 | case PINMUX_TYPE_INPUT: | |
19bb7fe3 | 329 | range = &pfc->info->input; |
2967dab1 MD |
330 | break; |
331 | ||
2967dab1 | 332 | default: |
b705c054 | 333 | return -EINVAL; |
2967dab1 MD |
334 | } |
335 | ||
e3c47051 | 336 | /* Iterate over all the configuration fields we need to update. */ |
2967dab1 | 337 | while (1) { |
cef28a28 GU |
338 | const struct pinmux_cfg_reg *cr; |
339 | unsigned int field; | |
340 | u16 enum_id; | |
341 | u32 value; | |
342 | int in_range; | |
343 | int ret; | |
344 | ||
a68fdca9 | 345 | pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); |
b705c054 LP |
346 | if (pos < 0) |
347 | return pos; | |
2967dab1 MD |
348 | |
349 | if (!enum_id) | |
350 | break; | |
351 | ||
e3c47051 LP |
352 | /* Check if the configuration field selects a function. If it |
353 | * doesn't, skip the field if it's not applicable to the | |
354 | * requested pinmux type. | |
355 | */ | |
19bb7fe3 | 356 | in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); |
50dd3145 | 357 | if (!in_range) { |
e3c47051 LP |
358 | if (pinmux_type == PINMUX_TYPE_FUNCTION) { |
359 | /* Functions are allowed to modify all | |
360 | * fields. | |
361 | */ | |
362 | in_range = 1; | |
363 | } else if (pinmux_type != PINMUX_TYPE_GPIO) { | |
364 | /* Input/output types can only modify fields | |
365 | * that correspond to their respective ranges. | |
50dd3145 | 366 | */ |
4aeacd5b | 367 | in_range = sh_pfc_enum_in_range(enum_id, range); |
50dd3145 MD |
368 | |
369 | /* | |
370 | * special case pass through for fixed | |
371 | * input-only or output-only pins without | |
372 | * function enum register association. | |
373 | */ | |
374 | if (in_range && enum_id == range->force) | |
375 | continue; | |
50dd3145 | 376 | } |
e3c47051 | 377 | /* GPIOs are only allowed to modify function fields. */ |
42eed42b MD |
378 | } |
379 | ||
2967dab1 MD |
380 | if (!in_range) |
381 | continue; | |
382 | ||
b705c054 LP |
383 | ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); |
384 | if (ret < 0) | |
385 | return ret; | |
2967dab1 | 386 | |
861601de | 387 | sh_pfc_write_config_reg(pfc, cr, field, value); |
2967dab1 MD |
388 | } |
389 | ||
390 | return 0; | |
2967dab1 MD |
391 | } |
392 | ||
acdb1245 GU |
393 | const struct pinmux_bias_reg * |
394 | sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, | |
395 | unsigned int *bit) | |
396 | { | |
397 | unsigned int i, j; | |
398 | ||
399 | for (i = 0; pfc->info->bias_regs[i].puen; i++) { | |
400 | for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { | |
401 | if (pfc->info->bias_regs[i].pins[j] == pin) { | |
402 | *bit = j; | |
403 | return &pfc->info->bias_regs[i]; | |
404 | } | |
405 | } | |
406 | } | |
407 | ||
408 | WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); | |
409 | ||
410 | return NULL; | |
411 | } | |
412 | ||
acac8ed5 LP |
413 | static int sh_pfc_init_ranges(struct sh_pfc *pfc) |
414 | { | |
415 | struct sh_pfc_pin_range *range; | |
416 | unsigned int nr_ranges; | |
417 | unsigned int i; | |
418 | ||
419 | if (pfc->info->pins[0].pin == (u16)-1) { | |
420 | /* Pin number -1 denotes that the SoC doesn't report pin numbers | |
421 | * in its pin arrays yet. Consider the pin numbers range as | |
422 | * continuous and allocate a single range. | |
423 | */ | |
424 | pfc->nr_ranges = 1; | |
425 | pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), | |
426 | GFP_KERNEL); | |
427 | if (pfc->ranges == NULL) | |
428 | return -ENOMEM; | |
429 | ||
430 | pfc->ranges->start = 0; | |
431 | pfc->ranges->end = pfc->info->nr_pins - 1; | |
432 | pfc->nr_gpio_pins = pfc->info->nr_pins; | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
4f82e3ee LP |
437 | /* Count, allocate and fill the ranges. The PFC SoC data pins array must |
438 | * be sorted by pin numbers, and pins without a GPIO port must come | |
439 | * last. | |
440 | */ | |
acac8ed5 LP |
441 | for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { |
442 | if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) | |
443 | nr_ranges++; | |
444 | } | |
445 | ||
446 | pfc->nr_ranges = nr_ranges; | |
a86854d0 | 447 | pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges), |
acac8ed5 LP |
448 | GFP_KERNEL); |
449 | if (pfc->ranges == NULL) | |
450 | return -ENOMEM; | |
451 | ||
452 | range = pfc->ranges; | |
453 | range->start = pfc->info->pins[0].pin; | |
454 | ||
455 | for (i = 1; i < pfc->info->nr_pins; ++i) { | |
4f82e3ee LP |
456 | if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) |
457 | continue; | |
458 | ||
459 | range->end = pfc->info->pins[i-1].pin; | |
460 | if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) | |
461 | pfc->nr_gpio_pins = range->end + 1; | |
462 | ||
463 | range++; | |
464 | range->start = pfc->info->pins[i].pin; | |
acac8ed5 LP |
465 | } |
466 | ||
467 | range->end = pfc->info->pins[i-1].pin; | |
4f82e3ee LP |
468 | if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) |
469 | pfc->nr_gpio_pins = range->end + 1; | |
acac8ed5 LP |
470 | |
471 | return 0; | |
472 | } | |
473 | ||
fe1c9a82 LP |
474 | #ifdef CONFIG_OF |
475 | static const struct of_device_id sh_pfc_of_table[] = { | |
1e7d5d84 NS |
476 | #ifdef CONFIG_PINCTRL_PFC_EMEV2 |
477 | { | |
478 | .compatible = "renesas,pfc-emev2", | |
479 | .data = &emev2_pinmux_info, | |
480 | }, | |
481 | #endif | |
fe1c9a82 LP |
482 | #ifdef CONFIG_PINCTRL_PFC_R8A73A4 |
483 | { | |
484 | .compatible = "renesas,pfc-r8a73a4", | |
485 | .data = &r8a73a4_pinmux_info, | |
486 | }, | |
487 | #endif | |
488 | #ifdef CONFIG_PINCTRL_PFC_R8A7740 | |
489 | { | |
490 | .compatible = "renesas,pfc-r8a7740", | |
491 | .data = &r8a7740_pinmux_info, | |
492 | }, | |
493 | #endif | |
8df62701 SS |
494 | #ifdef CONFIG_PINCTRL_PFC_R8A7743 |
495 | { | |
496 | .compatible = "renesas,pfc-r8a7743", | |
497 | .data = &r8a7743_pinmux_info, | |
498 | }, | |
499 | #endif | |
c8bac70f SS |
500 | #ifdef CONFIG_PINCTRL_PFC_R8A7745 |
501 | { | |
502 | .compatible = "renesas,pfc-r8a7745", | |
503 | .data = &r8a7745_pinmux_info, | |
504 | }, | |
505 | #endif | |
73dacc34 BD |
506 | #ifdef CONFIG_PINCTRL_PFC_R8A77470 |
507 | { | |
508 | .compatible = "renesas,pfc-r8a77470", | |
509 | .data = &r8a77470_pinmux_info, | |
510 | }, | |
511 | #endif | |
91d627a7 BD |
512 | #ifdef CONFIG_PINCTRL_PFC_R8A774A1 |
513 | { | |
514 | .compatible = "renesas,pfc-r8a774a1", | |
515 | .data = &r8a774a1_pinmux_info, | |
516 | }, | |
517 | #endif | |
fe1c9a82 LP |
518 | #ifdef CONFIG_PINCTRL_PFC_R8A7778 |
519 | { | |
520 | .compatible = "renesas,pfc-r8a7778", | |
521 | .data = &r8a7778_pinmux_info, | |
522 | }, | |
523 | #endif | |
524 | #ifdef CONFIG_PINCTRL_PFC_R8A7779 | |
525 | { | |
526 | .compatible = "renesas,pfc-r8a7779", | |
527 | .data = &r8a7779_pinmux_info, | |
528 | }, | |
529 | #endif | |
530 | #ifdef CONFIG_PINCTRL_PFC_R8A7790 | |
531 | { | |
532 | .compatible = "renesas,pfc-r8a7790", | |
533 | .data = &r8a7790_pinmux_info, | |
534 | }, | |
535 | #endif | |
50884519 HN |
536 | #ifdef CONFIG_PINCTRL_PFC_R8A7791 |
537 | { | |
538 | .compatible = "renesas,pfc-r8a7791", | |
539 | .data = &r8a7791_pinmux_info, | |
540 | }, | |
541 | #endif | |
2cf59e0c SS |
542 | #ifdef CONFIG_PINCTRL_PFC_R8A7792 |
543 | { | |
544 | .compatible = "renesas,pfc-r8a7792", | |
545 | .data = &r8a7792_pinmux_info, | |
546 | }, | |
547 | #endif | |
19e1e98f UH |
548 | #ifdef CONFIG_PINCTRL_PFC_R8A7793 |
549 | { | |
550 | .compatible = "renesas,pfc-r8a7793", | |
551 | .data = &r8a7793_pinmux_info, | |
552 | }, | |
553 | #endif | |
43c4436e HN |
554 | #ifdef CONFIG_PINCTRL_PFC_R8A7794 |
555 | { | |
556 | .compatible = "renesas,pfc-r8a7794", | |
557 | .data = &r8a7794_pinmux_info, | |
558 | }, | |
559 | #endif | |
0b0ffc96 TK |
560 | #ifdef CONFIG_PINCTRL_PFC_R8A7795 |
561 | { | |
562 | .compatible = "renesas,pfc-r8a7795", | |
563 | .data = &r8a7795_pinmux_info, | |
564 | }, | |
565 | #endif | |
f9aece73 TK |
566 | #ifdef CONFIG_PINCTRL_PFC_R8A7796 |
567 | { | |
568 | .compatible = "renesas,pfc-r8a7796", | |
569 | .data = &r8a7796_pinmux_info, | |
570 | }, | |
571 | #endif | |
490e687e JM |
572 | #ifdef CONFIG_PINCTRL_PFC_R8A77965 |
573 | { | |
574 | .compatible = "renesas,pfc-r8a77965", | |
575 | .data = &r8a77965_pinmux_info, | |
576 | }, | |
577 | #endif | |
b92ac66a SS |
578 | #ifdef CONFIG_PINCTRL_PFC_R8A77970 |
579 | { | |
580 | .compatible = "renesas,pfc-r8a77970", | |
581 | .data = &r8a77970_pinmux_info, | |
582 | }, | |
583 | #endif | |
f5912524 SS |
584 | #ifdef CONFIG_PINCTRL_PFC_R8A77980 |
585 | { | |
586 | .compatible = "renesas,pfc-r8a77980", | |
587 | .data = &r8a77980_pinmux_info, | |
588 | }, | |
589 | #endif | |
6d4036a1 TK |
590 | #ifdef CONFIG_PINCTRL_PFC_R8A77990 |
591 | { | |
592 | .compatible = "renesas,pfc-r8a77990", | |
593 | .data = &r8a77990_pinmux_info, | |
594 | }, | |
595 | #endif | |
794a6711 TK |
596 | #ifdef CONFIG_PINCTRL_PFC_R8A77995 |
597 | { | |
598 | .compatible = "renesas,pfc-r8a77995", | |
599 | .data = &r8a77995_pinmux_info, | |
600 | }, | |
601 | #endif | |
fe1c9a82 LP |
602 | #ifdef CONFIG_PINCTRL_PFC_SH73A0 |
603 | { | |
604 | .compatible = "renesas,pfc-sh73a0", | |
605 | .data = &sh73a0_pinmux_info, | |
606 | }, | |
607 | #endif | |
608 | { }, | |
609 | }; | |
fe1c9a82 LP |
610 | #endif |
611 | ||
8843797d GU |
612 | #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) |
613 | static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) | |
614 | { | |
615 | } | |
616 | ||
617 | static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) | |
618 | { | |
619 | pfc->saved_regs[idx] = sh_pfc_read(pfc, reg); | |
620 | } | |
621 | ||
622 | static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) | |
623 | { | |
624 | sh_pfc_write(pfc, reg, pfc->saved_regs[idx]); | |
625 | } | |
626 | ||
627 | static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc, | |
628 | void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx)) | |
629 | { | |
630 | unsigned int i, n = 0; | |
631 | ||
632 | if (pfc->info->cfg_regs) | |
633 | for (i = 0; pfc->info->cfg_regs[i].reg; i++) | |
634 | do_reg(pfc, pfc->info->cfg_regs[i].reg, n++); | |
635 | ||
636 | if (pfc->info->drive_regs) | |
637 | for (i = 0; pfc->info->drive_regs[i].reg; i++) | |
638 | do_reg(pfc, pfc->info->drive_regs[i].reg, n++); | |
639 | ||
640 | if (pfc->info->bias_regs) | |
641 | for (i = 0; pfc->info->bias_regs[i].puen; i++) { | |
642 | do_reg(pfc, pfc->info->bias_regs[i].puen, n++); | |
643 | if (pfc->info->bias_regs[i].pud) | |
644 | do_reg(pfc, pfc->info->bias_regs[i].pud, n++); | |
645 | } | |
646 | ||
647 | if (pfc->info->ioctrl_regs) | |
648 | for (i = 0; pfc->info->ioctrl_regs[i].reg; i++) | |
649 | do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++); | |
650 | ||
651 | return n; | |
652 | } | |
653 | ||
654 | static int sh_pfc_suspend_init(struct sh_pfc *pfc) | |
655 | { | |
656 | unsigned int n; | |
657 | ||
658 | /* This is the best we can do to check for the presence of PSCI */ | |
659 | if (!psci_ops.cpu_suspend) | |
660 | return 0; | |
661 | ||
662 | n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg); | |
663 | if (!n) | |
664 | return 0; | |
665 | ||
666 | pfc->saved_regs = devm_kmalloc_array(pfc->dev, n, | |
667 | sizeof(*pfc->saved_regs), | |
668 | GFP_KERNEL); | |
669 | if (!pfc->saved_regs) | |
670 | return -ENOMEM; | |
671 | ||
672 | dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n); | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static int sh_pfc_suspend_noirq(struct device *dev) | |
677 | { | |
678 | struct sh_pfc *pfc = dev_get_drvdata(dev); | |
679 | ||
680 | if (pfc->saved_regs) | |
681 | sh_pfc_walk_regs(pfc, sh_pfc_save_reg); | |
682 | return 0; | |
683 | } | |
684 | ||
685 | static int sh_pfc_resume_noirq(struct device *dev) | |
686 | { | |
687 | struct sh_pfc *pfc = dev_get_drvdata(dev); | |
688 | ||
689 | if (pfc->saved_regs) | |
690 | sh_pfc_walk_regs(pfc, sh_pfc_restore_reg); | |
691 | return 0; | |
692 | } | |
693 | ||
694 | static const struct dev_pm_ops sh_pfc_pm = { | |
695 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq) | |
696 | }; | |
697 | #define DEV_PM_OPS &sh_pfc_pm | |
698 | #else | |
699 | static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } | |
700 | #define DEV_PM_OPS NULL | |
701 | #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ | |
702 | ||
c6193eac | 703 | static int sh_pfc_probe(struct platform_device *pdev) |
2967dab1 | 704 | { |
fe1c9a82 LP |
705 | #ifdef CONFIG_OF |
706 | struct device_node *np = pdev->dev.of_node; | |
707 | #endif | |
cd3c1bee | 708 | const struct sh_pfc_soc_info *info; |
c6193eac | 709 | struct sh_pfc *pfc; |
0fc64cc0 | 710 | int ret; |
2967dab1 | 711 | |
fe1c9a82 LP |
712 | #ifdef CONFIG_OF |
713 | if (np) | |
331207af | 714 | info = of_device_get_match_data(&pdev->dev); |
fe1c9a82 LP |
715 | else |
716 | #endif | |
35406b1f | 717 | info = (const void *)platform_get_device_id(pdev)->driver_data; |
2967dab1 | 718 | |
8c43fcc7 | 719 | pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); |
c6193eac LP |
720 | if (pfc == NULL) |
721 | return -ENOMEM; | |
d4e62d00 | 722 | |
19bb7fe3 | 723 | pfc->info = info; |
c6193eac LP |
724 | pfc->dev = &pdev->dev; |
725 | ||
70c8f01a | 726 | ret = sh_pfc_map_resources(pfc, pdev); |
c6193eac | 727 | if (unlikely(ret < 0)) |
b0e10211 MD |
728 | return ret; |
729 | ||
c6193eac | 730 | spin_lock_init(&pfc->lock); |
69edbba0 | 731 | |
0c151062 LP |
732 | if (info->ops && info->ops->init) { |
733 | ret = info->ops->init(pfc); | |
734 | if (ret < 0) | |
735 | return ret; | |
3091ae77 GU |
736 | |
737 | /* .init() may have overridden pfc->info */ | |
738 | info = pfc->info; | |
0c151062 LP |
739 | } |
740 | ||
8843797d GU |
741 | ret = sh_pfc_suspend_init(pfc); |
742 | if (ret) | |
743 | return ret; | |
744 | ||
0129801b WS |
745 | /* Enable dummy states for those platforms without pinctrl support */ |
746 | if (!of_have_populated_dt()) | |
747 | pinctrl_provide_dummies(); | |
b0e10211 | 748 | |
acac8ed5 LP |
749 | ret = sh_pfc_init_ranges(pfc); |
750 | if (ret < 0) | |
751 | return ret; | |
752 | ||
ca5481c6 PM |
753 | /* |
754 | * Initialize pinctrl bindings first | |
755 | */ | |
c6193eac | 756 | ret = sh_pfc_register_pinctrl(pfc); |
f9492fda | 757 | if (unlikely(ret != 0)) |
0a332c96 | 758 | return ret; |
ca5481c6 | 759 | |
abc60d48 | 760 | #ifdef CONFIG_PINCTRL_SH_PFC_GPIO |
ca5481c6 PM |
761 | /* |
762 | * Then the GPIO chip | |
763 | */ | |
c6193eac | 764 | ret = sh_pfc_register_gpiochip(pfc); |
6f6a4a68 | 765 | if (unlikely(ret != 0)) { |
ca5481c6 PM |
766 | /* |
767 | * If the GPIO chip fails to come up we still leave the | |
768 | * PFC state as it is, given that there are already | |
769 | * extant users of it that have succeeded by this point. | |
770 | */ | |
9a643c9a | 771 | dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); |
b3c185a7 | 772 | } |
6f6a4a68 | 773 | #endif |
b72421d8 | 774 | |
c6193eac LP |
775 | platform_set_drvdata(pdev, pfc); |
776 | ||
9a643c9a | 777 | dev_info(pfc->dev, "%s support registered\n", info->name); |
ca5481c6 | 778 | |
b3c185a7 | 779 | return 0; |
b72421d8 | 780 | } |
6f6a4a68 | 781 | |
c6193eac | 782 | static const struct platform_device_id sh_pfc_id_table[] = { |
ccda552e LP |
783 | #ifdef CONFIG_PINCTRL_PFC_SH7203 |
784 | { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, | |
785 | #endif | |
a8d42fc4 LP |
786 | #ifdef CONFIG_PINCTRL_PFC_SH7264 |
787 | { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info }, | |
788 | #endif | |
f5e811f2 LP |
789 | #ifdef CONFIG_PINCTRL_PFC_SH7269 |
790 | { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, | |
791 | #endif | |
74cad605 LP |
792 | #ifdef CONFIG_PINCTRL_PFC_SH7720 |
793 | { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, | |
f5e25ae5 LP |
794 | #endif |
795 | #ifdef CONFIG_PINCTRL_PFC_SH7722 | |
796 | { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info }, | |
d05afa0a LP |
797 | #endif |
798 | #ifdef CONFIG_PINCTRL_PFC_SH7723 | |
799 | { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info }, | |
0ff25bab LP |
800 | #endif |
801 | #ifdef CONFIG_PINCTRL_PFC_SH7724 | |
802 | { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, | |
ac1ebc21 LP |
803 | #endif |
804 | #ifdef CONFIG_PINCTRL_PFC_SH7734 | |
805 | { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info }, | |
0bb92677 LP |
806 | #endif |
807 | #ifdef CONFIG_PINCTRL_PFC_SH7757 | |
808 | { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info }, | |
a56398e9 LP |
809 | #endif |
810 | #ifdef CONFIG_PINCTRL_PFC_SH7785 | |
811 | { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info }, | |
d2a31bdd LP |
812 | #endif |
813 | #ifdef CONFIG_PINCTRL_PFC_SH7786 | |
814 | { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info }, | |
d5d9a818 LP |
815 | #endif |
816 | #ifdef CONFIG_PINCTRL_PFC_SHX3 | |
817 | { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, | |
d5b1521a | 818 | #endif |
c6193eac LP |
819 | { }, |
820 | }; | |
c6193eac LP |
821 | |
822 | static struct platform_driver sh_pfc_driver = { | |
823 | .probe = sh_pfc_probe, | |
c6193eac LP |
824 | .id_table = sh_pfc_id_table, |
825 | .driver = { | |
826 | .name = DRV_NAME, | |
fe1c9a82 | 827 | .of_match_table = of_match_ptr(sh_pfc_of_table), |
8843797d | 828 | .pm = DEV_PM_OPS, |
c6193eac LP |
829 | }, |
830 | }; | |
831 | ||
40ee6fce LP |
832 | static int __init sh_pfc_init(void) |
833 | { | |
834 | return platform_driver_register(&sh_pfc_driver); | |
c6193eac | 835 | } |
40ee6fce | 836 | postcore_initcall(sh_pfc_init); |