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221173a3 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
30574f0d TA |
2 | /* |
3 | * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. | |
4 | * | |
5 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
6 | * http://www.samsung.com | |
7 | * Copyright (c) 2012 Linaro Ltd | |
8 | * http://www.linaro.org | |
9 | * | |
10 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
30574f0d TA |
11 | */ |
12 | ||
13 | #ifndef __PINCTRL_SAMSUNG_H | |
14 | #define __PINCTRL_SAMSUNG_H | |
15 | ||
16 | #include <linux/pinctrl/pinctrl.h> | |
17 | #include <linux/pinctrl/pinmux.h> | |
18 | #include <linux/pinctrl/pinconf.h> | |
19 | #include <linux/pinctrl/consumer.h> | |
20 | #include <linux/pinctrl/machine.h> | |
21 | ||
1c5fb66a | 22 | #include <linux/gpio/driver.h> |
d3a7b9e3 | 23 | |
30574f0d TA |
24 | /** |
25 | * enum pincfg_type - possible pin configuration types supported. | |
499147c9 TF |
26 | * @PINCFG_TYPE_FUNC: Function configuration. |
27 | * @PINCFG_TYPE_DAT: Pin value configuration. | |
30574f0d TA |
28 | * @PINCFG_TYPE_PUD: Pull up/down configuration. |
29 | * @PINCFG_TYPE_DRV: Drive strength configuration. | |
30 | * @PINCFG_TYPE_CON_PDN: Pin function in power down mode. | |
31 | * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode. | |
32 | */ | |
33 | enum pincfg_type { | |
499147c9 TF |
34 | PINCFG_TYPE_FUNC, |
35 | PINCFG_TYPE_DAT, | |
30574f0d TA |
36 | PINCFG_TYPE_PUD, |
37 | PINCFG_TYPE_DRV, | |
38 | PINCFG_TYPE_CON_PDN, | |
39 | PINCFG_TYPE_PUD_PDN, | |
499147c9 TF |
40 | |
41 | PINCFG_TYPE_NUM | |
30574f0d TA |
42 | }; |
43 | ||
44 | /* | |
45 | * pin configuration (pull up/down and drive strength) type and its value are | |
46 | * packed together into a 16-bits. The upper 8-bits represent the configuration | |
47 | * type and the lower 8-bits hold the value of the configuration type. | |
48 | */ | |
49 | #define PINCFG_TYPE_MASK 0xFF | |
50 | #define PINCFG_VALUE_SHIFT 8 | |
51 | #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) | |
52 | #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) | |
53 | #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) | |
54 | #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ | |
55 | PINCFG_VALUE_SHIFT) | |
3eb12bce KK |
56 | /* |
57 | * Values for the pin CON register, choosing pin function. | |
58 | * The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210, | |
59 | * Exynos ARMv7, Exynos ARMv8, Tesla FSD. | |
60 | */ | |
61 | #define PIN_CON_FUNC_INPUT 0x0 | |
62 | #define PIN_CON_FUNC_OUTPUT 0x1 | |
63 | ||
30574f0d TA |
64 | /** |
65 | * enum eint_type - possible external interrupt types. | |
66 | * @EINT_TYPE_NONE: bank does not support external interrupts | |
67 | * @EINT_TYPE_GPIO: bank supportes external gpio interrupts | |
68 | * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts | |
a04b07c0 | 69 | * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts |
30574f0d TA |
70 | * |
71 | * Samsung GPIO controller groups all the available pins into banks. The pins | |
72 | * in a pin bank can support external gpio interrupts or external wakeup | |
73 | * interrupts or no interrupts at all. From a software perspective, the only | |
74 | * difference between external gpio and external wakeup interrupts is that | |
75 | * the wakeup interrupts can additionally wakeup the system if it is in | |
76 | * suspended state. | |
77 | */ | |
78 | enum eint_type { | |
79 | EINT_TYPE_NONE, | |
80 | EINT_TYPE_GPIO, | |
81 | EINT_TYPE_WKUP, | |
a04b07c0 | 82 | EINT_TYPE_WKUP_MUX, |
30574f0d TA |
83 | }; |
84 | ||
85 | /* maximum length of a pin in pin descriptor (example: "gpa0-0") */ | |
86 | #define PIN_NAME_LENGTH 10 | |
87 | ||
88 | #define PIN_GROUP(n, p, f) \ | |
89 | { \ | |
90 | .name = n, \ | |
91 | .pins = p, \ | |
92 | .num_pins = ARRAY_SIZE(p), \ | |
93 | .func = f \ | |
94 | } | |
95 | ||
96 | #define PMX_FUNC(n, g) \ | |
97 | { \ | |
98 | .name = n, \ | |
99 | .groups = g, \ | |
100 | .num_groups = ARRAY_SIZE(g), \ | |
101 | } | |
102 | ||
103 | struct samsung_pinctrl_drv_data; | |
104 | ||
499147c9 TF |
105 | /** |
106 | * struct samsung_pin_bank_type: pin bank type description | |
107 | * @fld_width: widths of configuration bitfields (0 if unavailable) | |
43fc9e7f | 108 | * @reg_offset: offsets of configuration registers (don't care of width is 0) |
499147c9 TF |
109 | */ |
110 | struct samsung_pin_bank_type { | |
111 | u8 fld_width[PINCFG_TYPE_NUM]; | |
43fc9e7f | 112 | u8 reg_offset[PINCFG_TYPE_NUM]; |
499147c9 TF |
113 | }; |
114 | ||
8100cf47 TF |
115 | /** |
116 | * struct samsung_pin_bank_data: represent a controller pin-bank (init data). | |
117 | * @type: type of the bank (register offsets and bitfield widths) | |
118 | * @pctl_offset: starting offset of the pin-bank registers. | |
8b1bd11c | 119 | * @pctl_res_idx: index of base address for pin-bank registers. |
8100cf47 TF |
120 | * @nr_pins: number of pins included in this bank. |
121 | * @eint_func: function to set in CON register to configure pin as EINT. | |
122 | * @eint_type: type of the external interrupt supported by the bank. | |
123 | * @eint_mask: bit mask of pins which support EINT function. | |
124 | * @eint_offset: SoC-specific EINT register or interrupt offset of bank. | |
884fdaa5 JK |
125 | * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank. |
126 | * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. | |
127 | * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. | |
8100cf47 TF |
128 | * @name: name to be prefixed for each pin in this pin bank. |
129 | */ | |
130 | struct samsung_pin_bank_data { | |
131 | const struct samsung_pin_bank_type *type; | |
132 | u32 pctl_offset; | |
8b1bd11c | 133 | u8 pctl_res_idx; |
8100cf47 TF |
134 | u8 nr_pins; |
135 | u8 eint_func; | |
136 | enum eint_type eint_type; | |
137 | u32 eint_mask; | |
138 | u32 eint_offset; | |
884fdaa5 JK |
139 | u32 eint_con_offset; |
140 | u32 eint_mask_offset; | |
141 | u32 eint_pend_offset; | |
8100cf47 TF |
142 | const char *name; |
143 | }; | |
144 | ||
30574f0d TA |
145 | /** |
146 | * struct samsung_pin_bank: represent a controller pin-bank. | |
499147c9 | 147 | * @type: type of the bank (register offsets and bitfield widths) |
8b1bd11c | 148 | * @pctl_base: base address of the pin-bank registers |
88f2324f | 149 | * @pctl_offset: starting offset of the pin-bank registers. |
30574f0d | 150 | * @nr_pins: number of pins included in this bank. |
8b1bd11c | 151 | * @eint_base: base address of the pin-bank EINT registers. |
61dd7261 | 152 | * @eint_func: function to set in CON register to configure pin as EINT. |
30574f0d | 153 | * @eint_type: type of the external interrupt supported by the bank. |
61dd7261 | 154 | * @eint_mask: bit mask of pins which support EINT function. |
8100cf47 | 155 | * @eint_offset: SoC-specific EINT register or interrupt offset of bank. |
884fdaa5 JK |
156 | * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank. |
157 | * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. | |
158 | * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. | |
30574f0d | 159 | * @name: name to be prefixed for each pin in this pin bank. |
bf128c1f | 160 | * @id: id of the bank, propagated to the pin range. |
8100cf47 TF |
161 | * @pin_base: starting pin number of the bank. |
162 | * @soc_priv: per-bank private data for SoC-specific code. | |
ab663789 | 163 | * @of_node: OF node of the bank. |
6defe9a0 | 164 | * @drvdata: link to controller driver data |
595be726 | 165 | * @irq_domain: IRQ domain of the bank. |
d3a7b9e3 TF |
166 | * @gpio_chip: GPIO chip of the bank. |
167 | * @grange: linux gpio pin range supported by this bank. | |
0d3d30db | 168 | * @irq_chip: link to irq chip for external gpio and wakeup interrupts. |
19846950 | 169 | * @slock: spinlock protecting bank registers |
d9f99863 | 170 | * @pm_save: saved register values during suspend |
30574f0d TA |
171 | */ |
172 | struct samsung_pin_bank { | |
94ce944b | 173 | const struct samsung_pin_bank_type *type; |
8b1bd11c | 174 | void __iomem *pctl_base; |
30574f0d | 175 | u32 pctl_offset; |
30574f0d | 176 | u8 nr_pins; |
8b1bd11c | 177 | void __iomem *eint_base; |
61dd7261 | 178 | u8 eint_func; |
30574f0d | 179 | enum eint_type eint_type; |
61dd7261 | 180 | u32 eint_mask; |
1b6056d6 | 181 | u32 eint_offset; |
884fdaa5 JK |
182 | u32 eint_con_offset; |
183 | u32 eint_mask_offset; | |
184 | u32 eint_pend_offset; | |
8100cf47 | 185 | const char *name; |
bf128c1f | 186 | u32 id; |
8100cf47 TF |
187 | |
188 | u32 pin_base; | |
3385474c | 189 | void *soc_priv; |
492fca28 | 190 | struct fwnode_handle *fwnode; |
6defe9a0 | 191 | struct samsung_pinctrl_drv_data *drvdata; |
595be726 | 192 | struct irq_domain *irq_domain; |
d3a7b9e3 TF |
193 | struct gpio_chip gpio_chip; |
194 | struct pinctrl_gpio_range grange; | |
0d3d30db | 195 | struct exynos_irq_chip *irq_chip; |
1f306ecb | 196 | raw_spinlock_t slock; |
d9f99863 DA |
197 | |
198 | u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ | |
30574f0d TA |
199 | }; |
200 | ||
1fc8ad86 MS |
201 | /** |
202 | * struct samsung_retention_data: runtime pin-bank retention control data. | |
203 | * @regs: array of PMU registers to control pad retention. | |
204 | * @nr_regs: number of registers in @regs array. | |
205 | * @value: value to store to registers to turn off retention. | |
206 | * @refcnt: atomic counter if retention control affects more than one bank. | |
207 | * @priv: retention control code private data | |
208 | * @enable: platform specific callback to enter retention mode. | |
209 | * @disable: platform specific callback to exit retention mode. | |
210 | **/ | |
211 | struct samsung_retention_ctrl { | |
212 | const u32 *regs; | |
213 | int nr_regs; | |
214 | u32 value; | |
215 | atomic_t *refcnt; | |
216 | void *priv; | |
217 | void (*enable)(struct samsung_pinctrl_drv_data *); | |
218 | void (*disable)(struct samsung_pinctrl_drv_data *); | |
219 | }; | |
220 | ||
221 | /** | |
222 | * struct samsung_retention_data: represent a pin-bank retention control data. | |
223 | * @regs: array of PMU registers to control pad retention. | |
224 | * @nr_regs: number of registers in @regs array. | |
225 | * @value: value to store to registers to turn off retention. | |
226 | * @refcnt: atomic counter if retention control affects more than one bank. | |
227 | * @init: platform specific callback to initialize retention control. | |
228 | **/ | |
229 | struct samsung_retention_data { | |
230 | const u32 *regs; | |
231 | int nr_regs; | |
232 | u32 value; | |
233 | atomic_t *refcnt; | |
234 | struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *, | |
235 | const struct samsung_retention_data *); | |
236 | }; | |
237 | ||
30574f0d TA |
238 | /** |
239 | * struct samsung_pin_ctrl: represent a pin controller. | |
240 | * @pin_banks: list of pin banks included in this controller. | |
241 | * @nr_banks: number of pin banks. | |
8b1bd11c | 242 | * @nr_ext_resources: number of the extra base address for pin banks. |
1fc8ad86 | 243 | * @retention_data: configuration data for retention control. |
30574f0d TA |
244 | * @eint_gpio_init: platform specific callback to setup the external gpio |
245 | * interrupts for the controller. | |
246 | * @eint_wkup_init: platform specific callback to setup the external wakeup | |
247 | * interrupts for the controller. | |
00d6fff3 KK |
248 | * @suspend: platform specific suspend callback, executed during pin controller |
249 | * device suspend, see samsung_pinctrl_suspend() | |
250 | * @resume: platform specific resume callback, executed during pin controller | |
251 | * device suspend, see samsung_pinctrl_resume() | |
a8be2af0 KK |
252 | * |
253 | * External wakeup interrupts must define at least eint_wkup_init, | |
254 | * retention_data and suspend in order for proper suspend/resume to work. | |
30574f0d TA |
255 | */ |
256 | struct samsung_pin_ctrl { | |
8100cf47 | 257 | const struct samsung_pin_bank_data *pin_banks; |
12cdd579 | 258 | unsigned int nr_banks; |
52d0ed00 | 259 | unsigned int nr_ext_resources; |
1fc8ad86 | 260 | const struct samsung_retention_data *retention_data; |
30574f0d | 261 | |
30574f0d TA |
262 | int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); |
263 | int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); | |
21c21993 TF |
264 | void (*suspend)(struct samsung_pinctrl_drv_data *); |
265 | void (*resume)(struct samsung_pinctrl_drv_data *); | |
30574f0d TA |
266 | }; |
267 | ||
268 | /** | |
269 | * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. | |
d9f99863 | 270 | * @node: global list node |
cee7413d KK |
271 | * @virt_base: register base address of the controller; this will be equal |
272 | * to each bank samsung_pin_bank->pctl_base and used on legacy | |
273 | * platforms (like S3C24XX or S3C64XX) which has to access the base | |
274 | * through samsung_pinctrl_drv_data, not samsung_pin_bank). | |
30574f0d TA |
275 | * @dev: device instance representing the controller. |
276 | * @irq: interrpt number used by the controller to notify gpio interrupts. | |
f9c74474 | 277 | * @pclk: optional bus clock if required for accessing registers |
30574f0d TA |
278 | * @ctrl: pin controller instance managed by the driver. |
279 | * @pctl: pin controller descriptor registered with the pinctrl subsystem. | |
280 | * @pctl_dev: cookie representing pinctrl device instance. | |
281 | * @pin_groups: list of pin groups available to the driver. | |
282 | * @nr_groups: number of such pin groups. | |
283 | * @pmx_functions: list of pin functions available to the driver. | |
284 | * @nr_function: number of such pin functions. | |
1bf00d7a | 285 | * @nr_pins: number of pins supported by the controller. |
1fc8ad86 | 286 | * @retention_ctrl: retention control runtime data. |
00d6fff3 KK |
287 | * @suspend: platform specific suspend callback, executed during pin controller |
288 | * device suspend, see samsung_pinctrl_suspend() | |
289 | * @resume: platform specific resume callback, executed during pin controller | |
290 | * device suspend, see samsung_pinctrl_resume() | |
30574f0d TA |
291 | */ |
292 | struct samsung_pinctrl_drv_data { | |
d9f99863 | 293 | struct list_head node; |
cee7413d | 294 | void __iomem *virt_base; |
30574f0d TA |
295 | struct device *dev; |
296 | int irq; | |
f9c74474 | 297 | struct clk *pclk; |
30574f0d | 298 | |
30574f0d TA |
299 | struct pinctrl_desc pctl; |
300 | struct pinctrl_dev *pctl_dev; | |
301 | ||
302 | const struct samsung_pin_group *pin_groups; | |
303 | unsigned int nr_groups; | |
304 | const struct samsung_pmx_func *pmx_functions; | |
305 | unsigned int nr_functions; | |
1bf00d7a TF |
306 | |
307 | struct samsung_pin_bank *pin_banks; | |
12cdd579 | 308 | unsigned int nr_banks; |
1bf00d7a TF |
309 | unsigned int nr_pins; |
310 | ||
1fc8ad86 MS |
311 | struct samsung_retention_ctrl *retention_ctrl; |
312 | ||
1bf00d7a TF |
313 | void (*suspend)(struct samsung_pinctrl_drv_data *); |
314 | void (*resume)(struct samsung_pinctrl_drv_data *); | |
30574f0d TA |
315 | }; |
316 | ||
93b0beae KK |
317 | /** |
318 | * struct samsung_pinctrl_of_match_data: OF match device specific configuration data. | |
319 | * @ctrl: array of pin controller data. | |
320 | * @num_ctrl: size of array @ctrl. | |
321 | */ | |
322 | struct samsung_pinctrl_of_match_data { | |
323 | const struct samsung_pin_ctrl *ctrl; | |
324 | unsigned int num_ctrl; | |
325 | }; | |
326 | ||
30574f0d TA |
327 | /** |
328 | * struct samsung_pin_group: represent group of pins of a pinmux function. | |
329 | * @name: name of the pin group, used to lookup the group. | |
330 | * @pins: the pins included in this group. | |
331 | * @num_pins: number of pins included in this group. | |
332 | * @func: the function number to be programmed when selected. | |
333 | */ | |
334 | struct samsung_pin_group { | |
335 | const char *name; | |
336 | const unsigned int *pins; | |
337 | u8 num_pins; | |
338 | u8 func; | |
339 | }; | |
340 | ||
341 | /** | |
342 | * struct samsung_pmx_func: represent a pin function. | |
343 | * @name: name of the pin function, used to lookup the function. | |
344 | * @groups: one or more names of pin groups that provide this function. | |
345 | * @num_groups: number of groups included in @groups. | |
346 | */ | |
347 | struct samsung_pmx_func { | |
348 | const char *name; | |
349 | const char **groups; | |
350 | u8 num_groups; | |
9a2c1c3b | 351 | u32 val; |
30574f0d TA |
352 | }; |
353 | ||
354 | /* list of all exported SoC specific data */ | |
93b0beae KK |
355 | extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; |
356 | extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; | |
357 | extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data; | |
358 | extern const struct samsung_pinctrl_of_match_data exynos5250_of_data; | |
359 | extern const struct samsung_pinctrl_of_match_data exynos5260_of_data; | |
360 | extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; | |
361 | extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; | |
362 | extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; | |
363 | extern const struct samsung_pinctrl_of_match_data exynos7_of_data; | |
b0ef7b1a | 364 | extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; |
cdd3d945 | 365 | extern const struct samsung_pinctrl_of_match_data exynos850_of_data; |
02725b0c | 366 | extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; |
6cf96df7 | 367 | extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; |
0d1b662c | 368 | extern const struct samsung_pinctrl_of_match_data fsd_of_data; |
4a8be01a | 369 | extern const struct samsung_pinctrl_of_match_data gs101_of_data; |
93b0beae KK |
370 | extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; |
371 | extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; | |
372 | extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; | |
373 | extern const struct samsung_pinctrl_of_match_data s3c2440_of_data; | |
374 | extern const struct samsung_pinctrl_of_match_data s3c2450_of_data; | |
375 | extern const struct samsung_pinctrl_of_match_data s5pv210_of_data; | |
30574f0d TA |
376 | |
377 | #endif /* __PINCTRL_SAMSUNG_H */ |