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221173a3 KK |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. | |
4 | // | |
5 | // Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
6 | // http://www.samsung.com | |
7 | // Copyright (c) 2012 Linaro Ltd | |
8 | // http://www.linaro.org | |
9 | // | |
10 | // Author: Thomas Abraham <thomas.ab@samsung.com> | |
11 | // | |
12 | // This driver implements the Samsung pinctrl driver. It supports setting up of | |
13 | // pinmux and pinconf configurations. The gpiolib interface is also included. | |
14 | // External interrupt (gpio and wakeup) support are not included in this driver | |
15 | // but provides extensions to which platform specific implementation of the gpio | |
16 | // and wakeup interrupts can be hooked to. | |
30574f0d | 17 | |
f9c74474 | 18 | #include <linux/clk.h> |
30574f0d | 19 | #include <linux/err.h> |
1c5fb66a | 20 | #include <linux/gpio/driver.h> |
2420cd5f AS |
21 | #include <linux/init.h> |
22 | #include <linux/io.h> | |
a19fe2d4 | 23 | #include <linux/irqdomain.h> |
060f03e9 | 24 | #include <linux/of.h> |
2420cd5f AS |
25 | #include <linux/platform_device.h> |
26 | #include <linux/property.h> | |
27 | #include <linux/seq_file.h> | |
28 | #include <linux/slab.h> | |
19846950 | 29 | #include <linux/spinlock.h> |
30574f0d | 30 | |
ebe629a3 | 31 | #include "../core.h" |
30574f0d TA |
32 | #include "pinctrl-samsung.h" |
33 | ||
8b1bd11c CC |
34 | /* maximum number of the memory resources */ |
35 | #define SAMSUNG_PINCTRL_NUM_RESOURCES 2 | |
36 | ||
30574f0d | 37 | /* list of all possible config options supported */ |
d5fd5da2 | 38 | static struct pin_config { |
9a2c1c3b TF |
39 | const char *property; |
40 | enum pincfg_type param; | |
41 | } cfg_params[] = { | |
30574f0d TA |
42 | { "samsung,pin-pud", PINCFG_TYPE_PUD }, |
43 | { "samsung,pin-drv", PINCFG_TYPE_DRV }, | |
44 | { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN }, | |
45 | { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN }, | |
2700bc01 | 46 | { "samsung,pin-val", PINCFG_TYPE_DAT }, |
30574f0d TA |
47 | }; |
48 | ||
30574f0d TA |
49 | static int samsung_get_group_count(struct pinctrl_dev *pctldev) |
50 | { | |
9a2c1c3b | 51 | struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); |
30574f0d | 52 | |
9a2c1c3b | 53 | return pmx->nr_groups; |
30574f0d TA |
54 | } |
55 | ||
30574f0d | 56 | static const char *samsung_get_group_name(struct pinctrl_dev *pctldev, |
9a2c1c3b | 57 | unsigned group) |
30574f0d | 58 | { |
9a2c1c3b | 59 | struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); |
30574f0d | 60 | |
9a2c1c3b | 61 | return pmx->pin_groups[group].name; |
30574f0d TA |
62 | } |
63 | ||
30574f0d | 64 | static int samsung_get_group_pins(struct pinctrl_dev *pctldev, |
9a2c1c3b TF |
65 | unsigned group, |
66 | const unsigned **pins, | |
67 | unsigned *num_pins) | |
30574f0d | 68 | { |
9a2c1c3b TF |
69 | struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev); |
70 | ||
71 | *pins = pmx->pin_groups[group].pins; | |
72 | *num_pins = pmx->pin_groups[group].num_pins; | |
30574f0d | 73 | |
30574f0d TA |
74 | return 0; |
75 | } | |
76 | ||
9a2c1c3b TF |
77 | static int reserve_map(struct device *dev, struct pinctrl_map **map, |
78 | unsigned *reserved_maps, unsigned *num_maps, | |
79 | unsigned reserve) | |
80 | { | |
81 | unsigned old_num = *reserved_maps; | |
82 | unsigned new_num = *num_maps + reserve; | |
83 | struct pinctrl_map *new_map; | |
30574f0d | 84 | |
9a2c1c3b TF |
85 | if (old_num >= new_num) |
86 | return 0; | |
30574f0d | 87 | |
9a2c1c3b | 88 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); |
fa5c0f46 | 89 | if (!new_map) |
30574f0d | 90 | return -ENOMEM; |
30574f0d | 91 | |
9a2c1c3b TF |
92 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); |
93 | ||
94 | *map = new_map; | |
95 | *reserved_maps = new_num; | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, | |
101 | unsigned *num_maps, const char *group, | |
102 | const char *function) | |
103 | { | |
104 | if (WARN_ON(*num_maps == *reserved_maps)) | |
105 | return -ENOSPC; | |
106 | ||
107 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
108 | (*map)[*num_maps].data.mux.group = group; | |
109 | (*map)[*num_maps].data.mux.function = function; | |
110 | (*num_maps)++; | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | static int add_map_configs(struct device *dev, struct pinctrl_map **map, | |
116 | unsigned *reserved_maps, unsigned *num_maps, | |
117 | const char *group, unsigned long *configs, | |
118 | unsigned num_configs) | |
119 | { | |
120 | unsigned long *dup_configs; | |
121 | ||
122 | if (WARN_ON(*num_maps == *reserved_maps)) | |
123 | return -ENOSPC; | |
124 | ||
125 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
126 | GFP_KERNEL); | |
fa5c0f46 | 127 | if (!dup_configs) |
9a2c1c3b | 128 | return -ENOMEM; |
30574f0d | 129 | |
9a2c1c3b TF |
130 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; |
131 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
132 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
133 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
134 | (*num_maps)++; | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | static int add_config(struct device *dev, unsigned long **configs, | |
140 | unsigned *num_configs, unsigned long config) | |
141 | { | |
142 | unsigned old_num = *num_configs; | |
143 | unsigned new_num = old_num + 1; | |
144 | unsigned long *new_configs; | |
145 | ||
146 | new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, | |
147 | GFP_KERNEL); | |
fa5c0f46 | 148 | if (!new_configs) |
9a2c1c3b | 149 | return -ENOMEM; |
30574f0d | 150 | |
9a2c1c3b TF |
151 | new_configs[old_num] = config; |
152 | ||
153 | *configs = new_configs; | |
154 | *num_configs = new_num; | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
159 | static void samsung_dt_free_map(struct pinctrl_dev *pctldev, | |
160 | struct pinctrl_map *map, | |
161 | unsigned num_maps) | |
162 | { | |
163 | int i; | |
164 | ||
165 | for (i = 0; i < num_maps; i++) | |
166 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) | |
167 | kfree(map[i].data.configs.configs); | |
168 | ||
169 | kfree(map); | |
170 | } | |
171 | ||
172 | static int samsung_dt_subnode_to_map(struct samsung_pinctrl_drv_data *drvdata, | |
173 | struct device *dev, | |
174 | struct device_node *np, | |
175 | struct pinctrl_map **map, | |
176 | unsigned *reserved_maps, | |
177 | unsigned *num_maps) | |
178 | { | |
179 | int ret, i; | |
180 | u32 val; | |
181 | unsigned long config; | |
182 | unsigned long *configs = NULL; | |
183 | unsigned num_configs = 0; | |
184 | unsigned reserve; | |
185 | struct property *prop; | |
186 | const char *group; | |
187 | bool has_func = false; | |
188 | ||
189 | ret = of_property_read_u32(np, "samsung,pin-function", &val); | |
190 | if (!ret) | |
191 | has_func = true; | |
192 | ||
193 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | |
194 | ret = of_property_read_u32(np, cfg_params[i].property, &val); | |
195 | if (!ret) { | |
196 | config = PINCFG_PACK(cfg_params[i].param, val); | |
197 | ret = add_config(dev, &configs, &num_configs, config); | |
198 | if (ret < 0) | |
199 | goto exit; | |
200 | /* EINVAL=missing, which is fine since it's optional */ | |
201 | } else if (ret != -EINVAL) { | |
202 | dev_err(dev, "could not parse property %s\n", | |
203 | cfg_params[i].property); | |
204 | } | |
30574f0d TA |
205 | } |
206 | ||
9a2c1c3b TF |
207 | reserve = 0; |
208 | if (has_func) | |
209 | reserve++; | |
210 | if (num_configs) | |
211 | reserve++; | |
212 | ret = of_property_count_strings(np, "samsung,pins"); | |
213 | if (ret < 0) { | |
214 | dev_err(dev, "could not parse property samsung,pins\n"); | |
215 | goto exit; | |
216 | } | |
217 | reserve *= ret; | |
218 | ||
219 | ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); | |
220 | if (ret < 0) | |
221 | goto exit; | |
222 | ||
223 | of_property_for_each_string(np, "samsung,pins", prop, group) { | |
224 | if (has_func) { | |
225 | ret = add_map_mux(map, reserved_maps, | |
226 | num_maps, group, np->full_name); | |
227 | if (ret < 0) | |
228 | goto exit; | |
30574f0d | 229 | } |
30574f0d | 230 | |
9a2c1c3b TF |
231 | if (num_configs) { |
232 | ret = add_map_configs(dev, map, reserved_maps, | |
233 | num_maps, group, configs, | |
234 | num_configs); | |
235 | if (ret < 0) | |
236 | goto exit; | |
237 | } | |
30574f0d TA |
238 | } |
239 | ||
9a2c1c3b | 240 | ret = 0; |
30574f0d | 241 | |
9a2c1c3b TF |
242 | exit: |
243 | kfree(configs); | |
244 | return ret; | |
30574f0d TA |
245 | } |
246 | ||
9a2c1c3b TF |
247 | static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, |
248 | struct device_node *np_config, | |
249 | struct pinctrl_map **map, | |
250 | unsigned *num_maps) | |
251 | { | |
252 | struct samsung_pinctrl_drv_data *drvdata; | |
253 | unsigned reserved_maps; | |
254 | struct device_node *np; | |
255 | int ret; | |
256 | ||
257 | drvdata = pinctrl_dev_get_drvdata(pctldev); | |
258 | ||
259 | reserved_maps = 0; | |
260 | *map = NULL; | |
261 | *num_maps = 0; | |
262 | ||
263 | if (!of_get_child_count(np_config)) | |
264 | return samsung_dt_subnode_to_map(drvdata, pctldev->dev, | |
265 | np_config, map, | |
266 | &reserved_maps, | |
267 | num_maps); | |
268 | ||
269 | for_each_child_of_node(np_config, np) { | |
270 | ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map, | |
271 | &reserved_maps, num_maps); | |
272 | if (ret < 0) { | |
273 | samsung_dt_free_map(pctldev, *map, *num_maps); | |
a322b337 | 274 | of_node_put(np); |
9a2c1c3b | 275 | return ret; |
30574f0d | 276 | } |
9a2c1c3b | 277 | } |
30574f0d | 278 | |
9a2c1c3b | 279 | return 0; |
30574f0d TA |
280 | } |
281 | ||
4e21264a CP |
282 | #ifdef CONFIG_DEBUG_FS |
283 | /* Forward declaration which can be used by samsung_pin_dbg_show */ | |
284 | static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
285 | unsigned long *config); | |
286 | static const char * const reg_names[] = {"CON", "DAT", "PUD", "DRV", "CON_PDN", | |
287 | "PUD_PDN"}; | |
288 | ||
289 | static void samsung_pin_dbg_show(struct pinctrl_dev *pctldev, | |
290 | struct seq_file *s, unsigned int pin) | |
291 | { | |
292 | enum pincfg_type cfg_type; | |
293 | unsigned long config; | |
294 | int ret; | |
295 | ||
296 | for (cfg_type = 0; cfg_type < PINCFG_TYPE_NUM; cfg_type++) { | |
297 | config = PINCFG_PACK(cfg_type, 0); | |
298 | ret = samsung_pinconf_get(pctldev, pin, &config); | |
299 | if (ret < 0) | |
300 | continue; | |
301 | ||
302 | seq_printf(s, " %s(0x%lx)", reg_names[cfg_type], | |
303 | PINCFG_UNPACK_VALUE(config)); | |
304 | } | |
305 | } | |
306 | #endif | |
307 | ||
30574f0d | 308 | /* list of pinctrl callbacks for the pinctrl core */ |
022ab148 | 309 | static const struct pinctrl_ops samsung_pctrl_ops = { |
30574f0d TA |
310 | .get_groups_count = samsung_get_group_count, |
311 | .get_group_name = samsung_get_group_name, | |
312 | .get_group_pins = samsung_get_group_pins, | |
313 | .dt_node_to_map = samsung_dt_node_to_map, | |
314 | .dt_free_map = samsung_dt_free_map, | |
4e21264a CP |
315 | #ifdef CONFIG_DEBUG_FS |
316 | .pin_dbg_show = samsung_pin_dbg_show, | |
317 | #endif | |
30574f0d TA |
318 | }; |
319 | ||
320 | /* check if the selector is a valid pin function selector */ | |
321 | static int samsung_get_functions_count(struct pinctrl_dev *pctldev) | |
322 | { | |
323 | struct samsung_pinctrl_drv_data *drvdata; | |
324 | ||
325 | drvdata = pinctrl_dev_get_drvdata(pctldev); | |
326 | return drvdata->nr_functions; | |
327 | } | |
328 | ||
329 | /* return the name of the pin function specified */ | |
330 | static const char *samsung_pinmux_get_fname(struct pinctrl_dev *pctldev, | |
331 | unsigned selector) | |
332 | { | |
333 | struct samsung_pinctrl_drv_data *drvdata; | |
334 | ||
335 | drvdata = pinctrl_dev_get_drvdata(pctldev); | |
336 | return drvdata->pmx_functions[selector].name; | |
337 | } | |
338 | ||
339 | /* return the groups associated for the specified function selector */ | |
340 | static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev, | |
341 | unsigned selector, const char * const **groups, | |
342 | unsigned * const num_groups) | |
343 | { | |
344 | struct samsung_pinctrl_drv_data *drvdata; | |
345 | ||
346 | drvdata = pinctrl_dev_get_drvdata(pctldev); | |
347 | *groups = drvdata->pmx_functions[selector].groups; | |
348 | *num_groups = drvdata->pmx_functions[selector].num_groups; | |
349 | return 0; | |
350 | } | |
351 | ||
352 | /* | |
353 | * given a pin number that is local to a pin controller, find out the pin bank | |
354 | * and the register base of the pin bank. | |
355 | */ | |
62f14c0e TF |
356 | static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, |
357 | unsigned pin, void __iomem **reg, u32 *offset, | |
30574f0d TA |
358 | struct samsung_pin_bank **bank) |
359 | { | |
30574f0d TA |
360 | struct samsung_pin_bank *b; |
361 | ||
1bf00d7a | 362 | b = drvdata->pin_banks; |
30574f0d TA |
363 | |
364 | while ((pin >= b->pin_base) && | |
365 | ((b->pin_base + b->nr_pins - 1) < pin)) | |
366 | b++; | |
367 | ||
8b1bd11c | 368 | *reg = b->pctl_base + b->pctl_offset; |
30574f0d TA |
369 | *offset = pin - b->pin_base; |
370 | if (bank) | |
371 | *bank = b; | |
30574f0d TA |
372 | } |
373 | ||
374 | /* enable or disable a pinmux function */ | |
f9c74474 AD |
375 | static int samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, |
376 | unsigned group) | |
30574f0d TA |
377 | { |
378 | struct samsung_pinctrl_drv_data *drvdata; | |
94ce944b | 379 | const struct samsung_pin_bank_type *type; |
30574f0d TA |
380 | struct samsung_pin_bank *bank; |
381 | void __iomem *reg; | |
9a2c1c3b | 382 | u32 mask, shift, data, pin_offset; |
19846950 | 383 | unsigned long flags; |
9a2c1c3b TF |
384 | const struct samsung_pmx_func *func; |
385 | const struct samsung_pin_group *grp; | |
f9c74474 | 386 | int ret; |
30574f0d TA |
387 | |
388 | drvdata = pinctrl_dev_get_drvdata(pctldev); | |
9a2c1c3b TF |
389 | func = &drvdata->pmx_functions[selector]; |
390 | grp = &drvdata->pin_groups[group]; | |
30574f0d | 391 | |
8aec97de | 392 | pin_to_reg_bank(drvdata, grp->pins[0], ®, &pin_offset, &bank); |
9a2c1c3b TF |
393 | type = bank->type; |
394 | mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; | |
395 | shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC]; | |
396 | if (shift >= 32) { | |
397 | /* Some banks have two config registers */ | |
398 | shift -= 32; | |
399 | reg += 4; | |
400 | } | |
30574f0d | 401 | |
f9c74474 AD |
402 | ret = clk_enable(drvdata->pclk); |
403 | if (ret) { | |
404 | dev_err(pctldev->dev, "failed to enable clock for setup\n"); | |
405 | return ret; | |
406 | } | |
407 | ||
1f306ecb | 408 | raw_spin_lock_irqsave(&bank->slock, flags); |
19846950 | 409 | |
9a2c1c3b TF |
410 | data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); |
411 | data &= ~(mask << shift); | |
991efb0f | 412 | data |= func->val << shift; |
9a2c1c3b | 413 | writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); |
19846950 | 414 | |
1f306ecb | 415 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
f9c74474 AD |
416 | |
417 | clk_disable(drvdata->pclk); | |
418 | ||
419 | return 0; | |
30574f0d TA |
420 | } |
421 | ||
422 | /* enable a specified pinmux by writing to registers */ | |
03e9f0ca LW |
423 | static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev, |
424 | unsigned selector, | |
425 | unsigned group) | |
30574f0d | 426 | { |
f9c74474 | 427 | return samsung_pinmux_setup(pctldev, selector, group); |
30574f0d TA |
428 | } |
429 | ||
30574f0d | 430 | /* list of pinmux callbacks for the pinmux vertical in pinctrl core */ |
022ab148 | 431 | static const struct pinmux_ops samsung_pinmux_ops = { |
30574f0d TA |
432 | .get_functions_count = samsung_get_functions_count, |
433 | .get_function_name = samsung_pinmux_get_fname, | |
434 | .get_function_groups = samsung_pinmux_get_groups, | |
03e9f0ca | 435 | .set_mux = samsung_pinmux_set_mux, |
30574f0d TA |
436 | }; |
437 | ||
438 | /* set or get the pin config settings for a specified pin */ | |
439 | static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, | |
440 | unsigned long *config, bool set) | |
441 | { | |
442 | struct samsung_pinctrl_drv_data *drvdata; | |
94ce944b | 443 | const struct samsung_pin_bank_type *type; |
30574f0d TA |
444 | struct samsung_pin_bank *bank; |
445 | void __iomem *reg_base; | |
446 | enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); | |
447 | u32 data, width, pin_offset, mask, shift; | |
448 | u32 cfg_value, cfg_reg; | |
19846950 | 449 | unsigned long flags; |
f9c74474 | 450 | int ret; |
30574f0d TA |
451 | |
452 | drvdata = pinctrl_dev_get_drvdata(pctldev); | |
8aec97de | 453 | pin_to_reg_bank(drvdata, pin, ®_base, &pin_offset, &bank); |
499147c9 | 454 | type = bank->type; |
30574f0d | 455 | |
499147c9 | 456 | if (cfg_type >= PINCFG_TYPE_NUM || !type->fld_width[cfg_type]) |
7c367d3d TF |
457 | return -EINVAL; |
458 | ||
499147c9 | 459 | width = type->fld_width[cfg_type]; |
43fc9e7f | 460 | cfg_reg = type->reg_offset[cfg_type]; |
499147c9 | 461 | |
f9c74474 AD |
462 | ret = clk_enable(drvdata->pclk); |
463 | if (ret) { | |
464 | dev_err(drvdata->dev, "failed to enable clock\n"); | |
465 | return ret; | |
466 | } | |
467 | ||
1f306ecb | 468 | raw_spin_lock_irqsave(&bank->slock, flags); |
19846950 | 469 | |
30574f0d TA |
470 | mask = (1 << width) - 1; |
471 | shift = pin_offset * width; | |
472 | data = readl(reg_base + cfg_reg); | |
473 | ||
474 | if (set) { | |
475 | cfg_value = PINCFG_UNPACK_VALUE(*config); | |
476 | data &= ~(mask << shift); | |
477 | data |= (cfg_value << shift); | |
478 | writel(data, reg_base + cfg_reg); | |
479 | } else { | |
480 | data >>= shift; | |
481 | data &= mask; | |
482 | *config = PINCFG_PACK(cfg_type, data); | |
483 | } | |
19846950 | 484 | |
1f306ecb | 485 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
19846950 | 486 | |
f9c74474 AD |
487 | clk_disable(drvdata->pclk); |
488 | ||
30574f0d TA |
489 | return 0; |
490 | } | |
491 | ||
492 | /* set the pin config settings for a specified pin */ | |
493 | static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
03b054e9 | 494 | unsigned long *configs, unsigned num_configs) |
30574f0d | 495 | { |
03b054e9 SY |
496 | int i, ret; |
497 | ||
498 | for (i = 0; i < num_configs; i++) { | |
499 | ret = samsung_pinconf_rw(pctldev, pin, &configs[i], true); | |
500 | if (ret < 0) | |
501 | return ret; | |
502 | } /* for each config */ | |
503 | ||
504 | return 0; | |
30574f0d TA |
505 | } |
506 | ||
507 | /* get the pin config settings for a specified pin */ | |
508 | static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
509 | unsigned long *config) | |
510 | { | |
511 | return samsung_pinconf_rw(pctldev, pin, config, false); | |
512 | } | |
513 | ||
514 | /* set the pin config settings for a specified pin group */ | |
515 | static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
516 | unsigned group, unsigned long *configs, |
517 | unsigned num_configs) | |
30574f0d TA |
518 | { |
519 | struct samsung_pinctrl_drv_data *drvdata; | |
520 | const unsigned int *pins; | |
521 | unsigned int cnt; | |
522 | ||
523 | drvdata = pinctrl_dev_get_drvdata(pctldev); | |
524 | pins = drvdata->pin_groups[group].pins; | |
525 | ||
526 | for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) | |
03b054e9 | 527 | samsung_pinconf_set(pctldev, pins[cnt], configs, num_configs); |
30574f0d TA |
528 | |
529 | return 0; | |
530 | } | |
531 | ||
532 | /* get the pin config settings for a specified pin group */ | |
533 | static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev, | |
534 | unsigned int group, unsigned long *config) | |
535 | { | |
536 | struct samsung_pinctrl_drv_data *drvdata; | |
537 | const unsigned int *pins; | |
538 | ||
539 | drvdata = pinctrl_dev_get_drvdata(pctldev); | |
540 | pins = drvdata->pin_groups[group].pins; | |
541 | samsung_pinconf_get(pctldev, pins[0], config); | |
542 | return 0; | |
543 | } | |
544 | ||
545 | /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ | |
022ab148 | 546 | static const struct pinconf_ops samsung_pinconf_ops = { |
30574f0d TA |
547 | .pin_config_get = samsung_pinconf_get, |
548 | .pin_config_set = samsung_pinconf_set, | |
549 | .pin_config_group_get = samsung_pinconf_group_get, | |
550 | .pin_config_group_set = samsung_pinconf_group_set, | |
551 | }; | |
552 | ||
d9ff0eb9 YN |
553 | /* |
554 | * The samsung_gpio_set_vlaue() should be called with "bank->slock" held | |
555 | * to avoid race condition. | |
556 | */ | |
557 | static void samsung_gpio_set_value(struct gpio_chip *gc, | |
558 | unsigned offset, int value) | |
30574f0d | 559 | { |
9f57f81c | 560 | struct samsung_pin_bank *bank = gpiochip_get_data(gc); |
94ce944b | 561 | const struct samsung_pin_bank_type *type = bank->type; |
30574f0d | 562 | void __iomem *reg; |
d3a7b9e3 | 563 | u32 data; |
30574f0d | 564 | |
8b1bd11c | 565 | reg = bank->pctl_base + bank->pctl_offset; |
30574f0d | 566 | |
43fc9e7f | 567 | data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); |
d3a7b9e3 | 568 | data &= ~(1 << offset); |
30574f0d | 569 | if (value) |
d3a7b9e3 | 570 | data |= 1 << offset; |
43fc9e7f | 571 | writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]); |
d9ff0eb9 YN |
572 | } |
573 | ||
574 | /* gpiolib gpio_set callback function */ | |
575 | static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) | |
576 | { | |
577 | struct samsung_pin_bank *bank = gpiochip_get_data(gc); | |
f9c74474 | 578 | struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; |
d9ff0eb9 | 579 | unsigned long flags; |
19846950 | 580 | |
f9c74474 AD |
581 | if (clk_enable(drvdata->pclk)) { |
582 | dev_err(drvdata->dev, "failed to enable clock\n"); | |
583 | return; | |
584 | } | |
585 | ||
1f306ecb | 586 | raw_spin_lock_irqsave(&bank->slock, flags); |
d9ff0eb9 | 587 | samsung_gpio_set_value(gc, offset, value); |
1f306ecb | 588 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
f9c74474 AD |
589 | |
590 | clk_disable(drvdata->pclk); | |
30574f0d TA |
591 | } |
592 | ||
593 | /* gpiolib gpio_get callback function */ | |
594 | static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset) | |
595 | { | |
1b09c2b8 | 596 | const void __iomem *reg; |
d3a7b9e3 | 597 | u32 data; |
9f57f81c | 598 | struct samsung_pin_bank *bank = gpiochip_get_data(gc); |
94ce944b | 599 | const struct samsung_pin_bank_type *type = bank->type; |
f9c74474 AD |
600 | struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; |
601 | int ret; | |
62f14c0e | 602 | |
8b1bd11c | 603 | reg = bank->pctl_base + bank->pctl_offset; |
30574f0d | 604 | |
f9c74474 AD |
605 | ret = clk_enable(drvdata->pclk); |
606 | if (ret) { | |
607 | dev_err(drvdata->dev, "failed to enable clock\n"); | |
608 | return ret; | |
609 | } | |
610 | ||
43fc9e7f | 611 | data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); |
d3a7b9e3 | 612 | data >>= offset; |
30574f0d | 613 | data &= 1; |
f9c74474 AD |
614 | |
615 | clk_disable(drvdata->pclk); | |
616 | ||
30574f0d TA |
617 | return data; |
618 | } | |
619 | ||
620 | /* | |
d9ff0eb9 YN |
621 | * The samsung_gpio_set_direction() should be called with "bank->slock" held |
622 | * to avoid race condition. | |
18c28caa TF |
623 | * The calls to gpio_direction_output() and gpio_direction_input() |
624 | * leads to this function call. | |
30574f0d | 625 | */ |
18c28caa TF |
626 | static int samsung_gpio_set_direction(struct gpio_chip *gc, |
627 | unsigned offset, bool input) | |
628 | { | |
94ce944b | 629 | const struct samsung_pin_bank_type *type; |
18c28caa | 630 | struct samsung_pin_bank *bank; |
18c28caa TF |
631 | void __iomem *reg; |
632 | u32 data, mask, shift; | |
18c28caa | 633 | |
9f57f81c | 634 | bank = gpiochip_get_data(gc); |
18c28caa | 635 | type = bank->type; |
18c28caa | 636 | |
8b1bd11c CC |
637 | reg = bank->pctl_base + bank->pctl_offset |
638 | + type->reg_offset[PINCFG_TYPE_FUNC]; | |
18c28caa TF |
639 | |
640 | mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; | |
641 | shift = offset * type->fld_width[PINCFG_TYPE_FUNC]; | |
642 | if (shift >= 32) { | |
643 | /* Some banks have two config registers */ | |
644 | shift -= 32; | |
645 | reg += 4; | |
646 | } | |
647 | ||
18c28caa TF |
648 | data = readl(reg); |
649 | data &= ~(mask << shift); | |
650 | if (!input) | |
3eb12bce | 651 | data |= PIN_CON_FUNC_OUTPUT << shift; |
18c28caa TF |
652 | writel(data, reg); |
653 | ||
18c28caa TF |
654 | return 0; |
655 | } | |
656 | ||
657 | /* gpiolib gpio_direction_input callback function. */ | |
30574f0d TA |
658 | static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset) |
659 | { | |
d9ff0eb9 | 660 | struct samsung_pin_bank *bank = gpiochip_get_data(gc); |
f9c74474 | 661 | struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; |
d9ff0eb9 YN |
662 | unsigned long flags; |
663 | int ret; | |
664 | ||
f9c74474 AD |
665 | ret = clk_enable(drvdata->pclk); |
666 | if (ret) { | |
667 | dev_err(drvdata->dev, "failed to enable clock\n"); | |
668 | return ret; | |
669 | } | |
670 | ||
1f306ecb | 671 | raw_spin_lock_irqsave(&bank->slock, flags); |
d9ff0eb9 | 672 | ret = samsung_gpio_set_direction(gc, offset, true); |
1f306ecb | 673 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
f9c74474 AD |
674 | |
675 | clk_disable(drvdata->pclk); | |
676 | ||
d9ff0eb9 | 677 | return ret; |
30574f0d TA |
678 | } |
679 | ||
18c28caa | 680 | /* gpiolib gpio_direction_output callback function. */ |
30574f0d TA |
681 | static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, |
682 | int value) | |
683 | { | |
d9ff0eb9 | 684 | struct samsung_pin_bank *bank = gpiochip_get_data(gc); |
f9c74474 | 685 | struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; |
d9ff0eb9 YN |
686 | unsigned long flags; |
687 | int ret; | |
688 | ||
f9c74474 AD |
689 | ret = clk_enable(drvdata->pclk); |
690 | if (ret) { | |
691 | dev_err(drvdata->dev, "failed to enable clock\n"); | |
692 | return ret; | |
693 | } | |
694 | ||
1f306ecb | 695 | raw_spin_lock_irqsave(&bank->slock, flags); |
d9ff0eb9 YN |
696 | samsung_gpio_set_value(gc, offset, value); |
697 | ret = samsung_gpio_set_direction(gc, offset, false); | |
1f306ecb | 698 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
d9ff0eb9 | 699 | |
f9c74474 AD |
700 | clk_disable(drvdata->pclk); |
701 | ||
d9ff0eb9 | 702 | return ret; |
30574f0d TA |
703 | } |
704 | ||
a19fe2d4 | 705 | /* |
03a13546 | 706 | * gpiod_to_irq() callback function. Creates a mapping between a GPIO pin |
a19fe2d4 TF |
707 | * and a virtual IRQ, if not already present. |
708 | */ | |
709 | static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
710 | { | |
9f57f81c | 711 | struct samsung_pin_bank *bank = gpiochip_get_data(gc); |
a19fe2d4 TF |
712 | unsigned int virq; |
713 | ||
714 | if (!bank->irq_domain) | |
715 | return -ENXIO; | |
716 | ||
717 | virq = irq_create_mapping(bank->irq_domain, offset); | |
718 | ||
719 | return (virq) ? : -ENXIO; | |
720 | } | |
721 | ||
bf128c1f MM |
722 | static int samsung_add_pin_ranges(struct gpio_chip *gc) |
723 | { | |
724 | struct samsung_pin_bank *bank = gpiochip_get_data(gc); | |
725 | ||
726 | bank->grange.name = bank->name; | |
727 | bank->grange.id = bank->id; | |
8aec97de | 728 | bank->grange.pin_base = bank->pin_base; |
bf128c1f MM |
729 | bank->grange.base = gc->base; |
730 | bank->grange.npins = bank->nr_pins; | |
731 | bank->grange.gc = &bank->gpio_chip; | |
732 | pinctrl_add_gpio_range(bank->drvdata->pctl_dev, &bank->grange); | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
9a2c1c3b TF |
737 | static struct samsung_pin_group *samsung_pinctrl_create_groups( |
738 | struct device *dev, | |
739 | struct samsung_pinctrl_drv_data *drvdata, | |
740 | unsigned int *cnt) | |
30574f0d | 741 | { |
9a2c1c3b TF |
742 | struct pinctrl_desc *ctrldesc = &drvdata->pctl; |
743 | struct samsung_pin_group *groups, *grp; | |
744 | const struct pinctrl_pin_desc *pdesc; | |
745 | int i; | |
746 | ||
a86854d0 | 747 | groups = devm_kcalloc(dev, ctrldesc->npins, sizeof(*groups), |
9a2c1c3b TF |
748 | GFP_KERNEL); |
749 | if (!groups) | |
750 | return ERR_PTR(-EINVAL); | |
751 | grp = groups; | |
752 | ||
753 | pdesc = ctrldesc->pins; | |
754 | for (i = 0; i < ctrldesc->npins; ++i, ++pdesc, ++grp) { | |
755 | grp->name = pdesc->name; | |
756 | grp->pins = &pdesc->number; | |
757 | grp->num_pins = 1; | |
758 | } | |
759 | ||
760 | *cnt = ctrldesc->npins; | |
761 | return groups; | |
762 | } | |
30574f0d | 763 | |
9a2c1c3b TF |
764 | static int samsung_pinctrl_create_function(struct device *dev, |
765 | struct samsung_pinctrl_drv_data *drvdata, | |
766 | struct device_node *func_np, | |
767 | struct samsung_pmx_func *func) | |
768 | { | |
769 | int npins; | |
770 | int ret; | |
771 | int i; | |
772 | ||
773 | if (of_property_read_u32(func_np, "samsung,pin-function", &func->val)) | |
774 | return 0; | |
775 | ||
776 | npins = of_property_count_strings(func_np, "samsung,pins"); | |
777 | if (npins < 1) { | |
f5292d06 | 778 | dev_err(dev, "invalid pin list in %pOFn node", func_np); |
30574f0d TA |
779 | return -EINVAL; |
780 | } | |
781 | ||
9a2c1c3b TF |
782 | func->name = func_np->full_name; |
783 | ||
a86854d0 | 784 | func->groups = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL); |
9a2c1c3b | 785 | if (!func->groups) |
30574f0d | 786 | return -ENOMEM; |
30574f0d | 787 | |
9a2c1c3b TF |
788 | for (i = 0; i < npins; ++i) { |
789 | const char *gname; | |
790 | ||
791 | ret = of_property_read_string_index(func_np, "samsung,pins", | |
792 | i, &gname); | |
793 | if (ret) { | |
794 | dev_err(dev, | |
f5292d06 RH |
795 | "failed to read pin name %d from %pOFn node\n", |
796 | i, func_np); | |
9a2c1c3b | 797 | return ret; |
30574f0d | 798 | } |
9a2c1c3b TF |
799 | |
800 | func->groups[i] = gname; | |
30574f0d TA |
801 | } |
802 | ||
9a2c1c3b TF |
803 | func->num_groups = npins; |
804 | return 1; | |
30574f0d TA |
805 | } |
806 | ||
9a2c1c3b TF |
807 | static struct samsung_pmx_func *samsung_pinctrl_create_functions( |
808 | struct device *dev, | |
809 | struct samsung_pinctrl_drv_data *drvdata, | |
810 | unsigned int *cnt) | |
30574f0d | 811 | { |
9a2c1c3b | 812 | struct samsung_pmx_func *functions, *func; |
30574f0d TA |
813 | struct device_node *dev_np = dev->of_node; |
814 | struct device_node *cfg_np; | |
9a2c1c3b | 815 | unsigned int func_cnt = 0; |
30574f0d TA |
816 | int ret; |
817 | ||
9a2c1c3b TF |
818 | /* |
819 | * Iterate over all the child nodes of the pin controller node | |
820 | * and create pin groups and pin function lists. | |
821 | */ | |
822 | for_each_child_of_node(dev_np, cfg_np) { | |
823 | struct device_node *func_np; | |
30574f0d | 824 | |
9a2c1c3b TF |
825 | if (!of_get_child_count(cfg_np)) { |
826 | if (!of_find_property(cfg_np, | |
827 | "samsung,pin-function", NULL)) | |
828 | continue; | |
829 | ++func_cnt; | |
830 | continue; | |
831 | } | |
832 | ||
833 | for_each_child_of_node(cfg_np, func_np) { | |
834 | if (!of_find_property(func_np, | |
835 | "samsung,pin-function", NULL)) | |
836 | continue; | |
837 | ++func_cnt; | |
838 | } | |
30574f0d | 839 | } |
30574f0d | 840 | |
a86854d0 | 841 | functions = devm_kcalloc(dev, func_cnt, sizeof(*functions), |
9a2c1c3b | 842 | GFP_KERNEL); |
fa5c0f46 | 843 | if (!functions) |
1f7b8eae | 844 | return ERR_PTR(-ENOMEM); |
30574f0d TA |
845 | func = functions; |
846 | ||
847 | /* | |
848 | * Iterate over all the child nodes of the pin controller node | |
849 | * and create pin groups and pin function lists. | |
850 | */ | |
9a2c1c3b | 851 | func_cnt = 0; |
30574f0d | 852 | for_each_child_of_node(dev_np, cfg_np) { |
9a2c1c3b TF |
853 | struct device_node *func_np; |
854 | ||
855 | if (!of_get_child_count(cfg_np)) { | |
856 | ret = samsung_pinctrl_create_function(dev, drvdata, | |
857 | cfg_np, func); | |
a322b337 KK |
858 | if (ret < 0) { |
859 | of_node_put(cfg_np); | |
9a2c1c3b | 860 | return ERR_PTR(ret); |
a322b337 | 861 | } |
9a2c1c3b TF |
862 | if (ret > 0) { |
863 | ++func; | |
864 | ++func_cnt; | |
865 | } | |
30574f0d | 866 | continue; |
9a2c1c3b | 867 | } |
30574f0d | 868 | |
9a2c1c3b TF |
869 | for_each_child_of_node(cfg_np, func_np) { |
870 | ret = samsung_pinctrl_create_function(dev, drvdata, | |
871 | func_np, func); | |
a322b337 KK |
872 | if (ret < 0) { |
873 | of_node_put(func_np); | |
874 | of_node_put(cfg_np); | |
9a2c1c3b | 875 | return ERR_PTR(ret); |
a322b337 | 876 | } |
9a2c1c3b TF |
877 | if (ret > 0) { |
878 | ++func; | |
879 | ++func_cnt; | |
880 | } | |
30574f0d | 881 | } |
9a2c1c3b | 882 | } |
30574f0d | 883 | |
9a2c1c3b TF |
884 | *cnt = func_cnt; |
885 | return functions; | |
886 | } | |
30574f0d | 887 | |
9a2c1c3b TF |
888 | /* |
889 | * Parse the information about all the available pin groups and pin functions | |
890 | * from device node of the pin-controller. A pin group is formed with all | |
891 | * the pins listed in the "samsung,pins" property. | |
892 | */ | |
30574f0d | 893 | |
9a2c1c3b TF |
894 | static int samsung_pinctrl_parse_dt(struct platform_device *pdev, |
895 | struct samsung_pinctrl_drv_data *drvdata) | |
896 | { | |
897 | struct device *dev = &pdev->dev; | |
898 | struct samsung_pin_group *groups; | |
899 | struct samsung_pmx_func *functions; | |
900 | unsigned int grp_cnt = 0, func_cnt = 0; | |
901 | ||
902 | groups = samsung_pinctrl_create_groups(dev, drvdata, &grp_cnt); | |
903 | if (IS_ERR(groups)) { | |
904 | dev_err(dev, "failed to parse pin groups\n"); | |
905 | return PTR_ERR(groups); | |
906 | } | |
907 | ||
908 | functions = samsung_pinctrl_create_functions(dev, drvdata, &func_cnt); | |
909 | if (IS_ERR(functions)) { | |
910 | dev_err(dev, "failed to parse pin functions\n"); | |
44a074ff | 911 | return PTR_ERR(functions); |
30574f0d TA |
912 | } |
913 | ||
914 | drvdata->pin_groups = groups; | |
915 | drvdata->nr_groups = grp_cnt; | |
916 | drvdata->pmx_functions = functions; | |
9a2c1c3b | 917 | drvdata->nr_functions = func_cnt; |
30574f0d TA |
918 | |
919 | return 0; | |
920 | } | |
921 | ||
922 | /* register the pinctrl interface with the pinctrl subsystem */ | |
150632b0 GKH |
923 | static int samsung_pinctrl_register(struct platform_device *pdev, |
924 | struct samsung_pinctrl_drv_data *drvdata) | |
30574f0d TA |
925 | { |
926 | struct pinctrl_desc *ctrldesc = &drvdata->pctl; | |
927 | struct pinctrl_pin_desc *pindesc, *pdesc; | |
928 | struct samsung_pin_bank *pin_bank; | |
929 | char *pin_names; | |
930 | int pin, bank, ret; | |
931 | ||
932 | ctrldesc->name = "samsung-pinctrl"; | |
933 | ctrldesc->owner = THIS_MODULE; | |
934 | ctrldesc->pctlops = &samsung_pctrl_ops; | |
935 | ctrldesc->pmxops = &samsung_pinmux_ops; | |
936 | ctrldesc->confops = &samsung_pinconf_ops; | |
937 | ||
a86854d0 KC |
938 | pindesc = devm_kcalloc(&pdev->dev, |
939 | drvdata->nr_pins, sizeof(*pindesc), | |
940 | GFP_KERNEL); | |
fa5c0f46 | 941 | if (!pindesc) |
30574f0d | 942 | return -ENOMEM; |
30574f0d | 943 | ctrldesc->pins = pindesc; |
1bf00d7a | 944 | ctrldesc->npins = drvdata->nr_pins; |
30574f0d TA |
945 | |
946 | /* dynamically populate the pin number and pin name for pindesc */ | |
947 | for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) | |
8aec97de | 948 | pdesc->number = pin; |
30574f0d TA |
949 | |
950 | /* | |
951 | * allocate space for storing the dynamically generated names for all | |
952 | * the pins which belong to this pin-controller. | |
953 | */ | |
a86854d0 KC |
954 | pin_names = devm_kzalloc(&pdev->dev, |
955 | array3_size(sizeof(char), PIN_NAME_LENGTH, | |
956 | drvdata->nr_pins), | |
957 | GFP_KERNEL); | |
fa5c0f46 | 958 | if (!pin_names) |
30574f0d | 959 | return -ENOMEM; |
30574f0d TA |
960 | |
961 | /* for each pin, the name of the pin is pin-bank name + pin number */ | |
1bf00d7a TF |
962 | for (bank = 0; bank < drvdata->nr_banks; bank++) { |
963 | pin_bank = &drvdata->pin_banks[bank]; | |
bf128c1f | 964 | pin_bank->id = bank; |
30574f0d TA |
965 | for (pin = 0; pin < pin_bank->nr_pins; pin++) { |
966 | sprintf(pin_names, "%s-%d", pin_bank->name, pin); | |
967 | pdesc = pindesc + pin_bank->pin_base + pin; | |
968 | pdesc->name = pin_names; | |
969 | pin_names += PIN_NAME_LENGTH; | |
970 | } | |
971 | } | |
972 | ||
529301c1 TF |
973 | ret = samsung_pinctrl_parse_dt(pdev, drvdata); |
974 | if (ret) | |
975 | return ret; | |
976 | ||
2aca5c59 MM |
977 | ret = devm_pinctrl_register_and_init(&pdev->dev, ctrldesc, drvdata, |
978 | &drvdata->pctl_dev); | |
979 | if (ret) { | |
30574f0d | 980 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); |
2aca5c59 | 981 | return ret; |
30574f0d TA |
982 | } |
983 | ||
30574f0d TA |
984 | return 0; |
985 | } | |
986 | ||
1abd18d1 CK |
987 | /* unregister the pinctrl interface with the pinctrl subsystem */ |
988 | static int samsung_pinctrl_unregister(struct platform_device *pdev, | |
989 | struct samsung_pinctrl_drv_data *drvdata) | |
990 | { | |
991 | struct samsung_pin_bank *bank = drvdata->pin_banks; | |
992 | int i; | |
993 | ||
994 | for (i = 0; i < drvdata->nr_banks; ++i, ++bank) | |
995 | pinctrl_remove_gpio_range(drvdata->pctl_dev, &bank->grange); | |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
d3a7b9e3 | 1000 | static const struct gpio_chip samsung_gpiolib_chip = { |
98c85d58 JG |
1001 | .request = gpiochip_generic_request, |
1002 | .free = gpiochip_generic_free, | |
d3a7b9e3 TF |
1003 | .set = samsung_gpio_set, |
1004 | .get = samsung_gpio_get, | |
1005 | .direction_input = samsung_gpio_direction_input, | |
1006 | .direction_output = samsung_gpio_direction_output, | |
a19fe2d4 | 1007 | .to_irq = samsung_gpio_to_irq, |
bf128c1f | 1008 | .add_pin_ranges = samsung_add_pin_ranges, |
d3a7b9e3 TF |
1009 | .owner = THIS_MODULE, |
1010 | }; | |
1011 | ||
30574f0d | 1012 | /* register the gpiolib interface with the gpiolib subsystem */ |
150632b0 GKH |
1013 | static int samsung_gpiolib_register(struct platform_device *pdev, |
1014 | struct samsung_pinctrl_drv_data *drvdata) | |
30574f0d | 1015 | { |
1bf00d7a | 1016 | struct samsung_pin_bank *bank = drvdata->pin_banks; |
30574f0d TA |
1017 | struct gpio_chip *gc; |
1018 | int ret; | |
d3a7b9e3 TF |
1019 | int i; |
1020 | ||
1bf00d7a | 1021 | for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { |
d3a7b9e3 TF |
1022 | bank->gpio_chip = samsung_gpiolib_chip; |
1023 | ||
1024 | gc = &bank->gpio_chip; | |
deb79167 | 1025 | gc->base = -1; /* Dynamic allocation */ |
d3a7b9e3 | 1026 | gc->ngpio = bank->nr_pins; |
58383c78 | 1027 | gc->parent = &pdev->dev; |
492fca28 | 1028 | gc->fwnode = bank->fwnode; |
d3a7b9e3 TF |
1029 | gc->label = bank->name; |
1030 | ||
f69ae4f5 | 1031 | ret = devm_gpiochip_add_data(&pdev->dev, gc, bank); |
d3a7b9e3 TF |
1032 | if (ret) { |
1033 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", | |
1034 | gc->label, ret); | |
f69ae4f5 | 1035 | return ret; |
d3a7b9e3 | 1036 | } |
30574f0d TA |
1037 | } |
1038 | ||
1039 | return 0; | |
30574f0d TA |
1040 | } |
1041 | ||
93b0beae KK |
1042 | static const struct samsung_pin_ctrl * |
1043 | samsung_pinctrl_get_soc_data_for_of_alias(struct platform_device *pdev) | |
1044 | { | |
1045 | struct device_node *node = pdev->dev.of_node; | |
1046 | const struct samsung_pinctrl_of_match_data *of_data; | |
1047 | int id; | |
1048 | ||
1049 | id = of_alias_get_id(node, "pinctrl"); | |
1050 | if (id < 0) { | |
1051 | dev_err(&pdev->dev, "failed to get alias id\n"); | |
1052 | return NULL; | |
1053 | } | |
1054 | ||
1055 | of_data = of_device_get_match_data(&pdev->dev); | |
1056 | if (id >= of_data->num_ctrl) { | |
1057 | dev_err(&pdev->dev, "invalid alias id %d\n", id); | |
1058 | return NULL; | |
1059 | } | |
1060 | ||
1061 | return &(of_data->ctrl[id]); | |
1062 | } | |
1063 | ||
954445c7 | 1064 | static void samsung_banks_node_put(struct samsung_pinctrl_drv_data *d) |
50ebd19e KK |
1065 | { |
1066 | struct samsung_pin_bank *bank; | |
1067 | unsigned int i; | |
1068 | ||
1069 | bank = d->pin_banks; | |
1070 | for (i = 0; i < d->nr_banks; ++i, ++bank) | |
492fca28 | 1071 | fwnode_handle_put(bank->fwnode); |
50ebd19e KK |
1072 | } |
1073 | ||
a29681b0 KK |
1074 | /* |
1075 | * Iterate over all driver pin banks to find one matching the name of node, | |
1076 | * skipping optional "-gpio" node suffix. When found, assign node to the bank. | |
1077 | */ | |
954445c7 | 1078 | static void samsung_banks_node_get(struct device *dev, struct samsung_pinctrl_drv_data *d) |
a29681b0 KK |
1079 | { |
1080 | const char *suffix = "-gpio-bank"; | |
1081 | struct samsung_pin_bank *bank; | |
492fca28 | 1082 | struct fwnode_handle *child; |
a29681b0 KK |
1083 | /* Pin bank names are up to 4 characters */ |
1084 | char node_name[20]; | |
1085 | unsigned int i; | |
1086 | size_t len; | |
1087 | ||
1088 | bank = d->pin_banks; | |
1089 | for (i = 0; i < d->nr_banks; ++i, ++bank) { | |
1090 | strscpy(node_name, bank->name, sizeof(node_name)); | |
1091 | len = strlcat(node_name, suffix, sizeof(node_name)); | |
1092 | if (len >= sizeof(node_name)) { | |
1093 | dev_err(dev, "Too long pin bank name '%s', ignoring\n", | |
1094 | bank->name); | |
1095 | continue; | |
1096 | } | |
1097 | ||
492fca28 AS |
1098 | for_each_gpiochip_node(dev, child) { |
1099 | struct device_node *np = to_of_node(child); | |
1100 | ||
1101 | if (of_node_name_eq(np, node_name)) | |
a29681b0 | 1102 | break; |
492fca28 | 1103 | if (of_node_name_eq(np, bank->name)) |
a29681b0 KK |
1104 | break; |
1105 | } | |
1106 | ||
1107 | if (child) | |
492fca28 | 1108 | bank->fwnode = child; |
a29681b0 KK |
1109 | else |
1110 | dev_warn(dev, "Missing node for bank %s - invalid DTB\n", | |
1111 | bank->name); | |
1112 | /* child reference dropped in samsung_drop_banks_of_node() */ | |
1113 | } | |
1114 | } | |
1115 | ||
30574f0d | 1116 | /* retrieve the soc specific data */ |
1bf00d7a TF |
1117 | static const struct samsung_pin_ctrl * |
1118 | samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, | |
1119 | struct platform_device *pdev) | |
30574f0d | 1120 | { |
8100cf47 | 1121 | const struct samsung_pin_bank_data *bdata; |
1bf00d7a | 1122 | const struct samsung_pin_ctrl *ctrl; |
40ba6227 | 1123 | struct samsung_pin_bank *bank; |
8b1bd11c CC |
1124 | struct resource *res; |
1125 | void __iomem *virt_base[SAMSUNG_PINCTRL_NUM_RESOURCES]; | |
52d0ed00 | 1126 | unsigned int i; |
30574f0d | 1127 | |
93b0beae KK |
1128 | ctrl = samsung_pinctrl_get_soc_data_for_of_alias(pdev); |
1129 | if (!ctrl) | |
87993273 | 1130 | return ERR_PTR(-ENOENT); |
40ba6227 | 1131 | |
1bf00d7a TF |
1132 | d->suspend = ctrl->suspend; |
1133 | d->resume = ctrl->resume; | |
1bf00d7a | 1134 | d->nr_banks = ctrl->nr_banks; |
8100cf47 TF |
1135 | d->pin_banks = devm_kcalloc(&pdev->dev, d->nr_banks, |
1136 | sizeof(*d->pin_banks), GFP_KERNEL); | |
1137 | if (!d->pin_banks) | |
1138 | return ERR_PTR(-ENOMEM); | |
1bf00d7a | 1139 | |
8b1bd11c CC |
1140 | if (ctrl->nr_ext_resources + 1 > SAMSUNG_PINCTRL_NUM_RESOURCES) |
1141 | return ERR_PTR(-EINVAL); | |
1142 | ||
1143 | for (i = 0; i < ctrl->nr_ext_resources + 1; i++) { | |
1144 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | |
59f34e80 AH |
1145 | if (!res) { |
1146 | dev_err(&pdev->dev, "failed to get mem%d resource\n", i); | |
1147 | return ERR_PTR(-EINVAL); | |
1148 | } | |
1149 | virt_base[i] = devm_ioremap(&pdev->dev, res->start, | |
1150 | resource_size(res)); | |
1151 | if (!virt_base[i]) { | |
1152 | dev_err(&pdev->dev, "failed to ioremap %pR\n", res); | |
1153 | return ERR_PTR(-EIO); | |
1154 | } | |
8b1bd11c CC |
1155 | } |
1156 | ||
1bf00d7a | 1157 | bank = d->pin_banks; |
8100cf47 TF |
1158 | bdata = ctrl->pin_banks; |
1159 | for (i = 0; i < ctrl->nr_banks; ++i, ++bdata, ++bank) { | |
1160 | bank->type = bdata->type; | |
1161 | bank->pctl_offset = bdata->pctl_offset; | |
1162 | bank->nr_pins = bdata->nr_pins; | |
1163 | bank->eint_func = bdata->eint_func; | |
1164 | bank->eint_type = bdata->eint_type; | |
1165 | bank->eint_mask = bdata->eint_mask; | |
1166 | bank->eint_offset = bdata->eint_offset; | |
884fdaa5 JK |
1167 | bank->eint_con_offset = bdata->eint_con_offset; |
1168 | bank->eint_mask_offset = bdata->eint_mask_offset; | |
1169 | bank->eint_pend_offset = bdata->eint_pend_offset; | |
8100cf47 TF |
1170 | bank->name = bdata->name; |
1171 | ||
1f306ecb | 1172 | raw_spin_lock_init(&bank->slock); |
6defe9a0 | 1173 | bank->drvdata = d; |
1bf00d7a TF |
1174 | bank->pin_base = d->nr_pins; |
1175 | d->nr_pins += bank->nr_pins; | |
8b1bd11c CC |
1176 | |
1177 | bank->eint_base = virt_base[0]; | |
1178 | bank->pctl_base = virt_base[bdata->pctl_res_idx]; | |
40ba6227 | 1179 | } |
cee7413d KK |
1180 | /* |
1181 | * Legacy platforms should provide only one resource with IO memory. | |
1182 | * Store it as virt_base because legacy driver needs to access it | |
1183 | * through samsung_pinctrl_drv_data. | |
1184 | */ | |
1185 | d->virt_base = virt_base[0]; | |
40ba6227 | 1186 | |
954445c7 | 1187 | samsung_banks_node_get(&pdev->dev, d); |
ab663789 | 1188 | |
40ba6227 | 1189 | return ctrl; |
30574f0d TA |
1190 | } |
1191 | ||
150632b0 | 1192 | static int samsung_pinctrl_probe(struct platform_device *pdev) |
30574f0d TA |
1193 | { |
1194 | struct samsung_pinctrl_drv_data *drvdata; | |
1bf00d7a | 1195 | const struct samsung_pin_ctrl *ctrl; |
30574f0d | 1196 | struct device *dev = &pdev->dev; |
30574f0d TA |
1197 | int ret; |
1198 | ||
30574f0d | 1199 | drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); |
b09eed7f | 1200 | if (!drvdata) |
30574f0d | 1201 | return -ENOMEM; |
6defe9a0 TF |
1202 | |
1203 | ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev); | |
87993273 | 1204 | if (IS_ERR(ctrl)) { |
6defe9a0 | 1205 | dev_err(&pdev->dev, "driver data not available\n"); |
87993273 | 1206 | return PTR_ERR(ctrl); |
6defe9a0 | 1207 | } |
30574f0d TA |
1208 | drvdata->dev = dev; |
1209 | ||
a382d568 LP |
1210 | ret = platform_get_irq_optional(pdev, 0); |
1211 | if (ret < 0 && ret != -ENXIO) | |
1212 | return ret; | |
1213 | if (ret > 0) | |
1214 | drvdata->irq = ret; | |
30574f0d | 1215 | |
1fc8ad86 MS |
1216 | if (ctrl->retention_data) { |
1217 | drvdata->retention_ctrl = ctrl->retention_data->init(drvdata, | |
1218 | ctrl->retention_data); | |
50ebd19e KK |
1219 | if (IS_ERR(drvdata->retention_ctrl)) { |
1220 | ret = PTR_ERR(drvdata->retention_ctrl); | |
1221 | goto err_put_banks; | |
1222 | } | |
1fc8ad86 MS |
1223 | } |
1224 | ||
f9c74474 AD |
1225 | drvdata->pclk = devm_clk_get_optional_prepared(dev, "pclk"); |
1226 | if (IS_ERR(drvdata->pclk)) { | |
1227 | ret = PTR_ERR(drvdata->pclk); | |
1228 | goto err_put_banks; | |
1229 | } | |
1230 | ||
1abd18d1 | 1231 | ret = samsung_pinctrl_register(pdev, drvdata); |
30574f0d | 1232 | if (ret) |
50ebd19e | 1233 | goto err_put_banks; |
30574f0d | 1234 | |
30574f0d TA |
1235 | if (ctrl->eint_gpio_init) |
1236 | ctrl->eint_gpio_init(drvdata); | |
1237 | if (ctrl->eint_wkup_init) | |
1238 | ctrl->eint_wkup_init(drvdata); | |
1239 | ||
152a81a0 SK |
1240 | ret = samsung_gpiolib_register(pdev, drvdata); |
1241 | if (ret) | |
1242 | goto err_unregister; | |
1243 | ||
2aca5c59 MM |
1244 | ret = pinctrl_enable(drvdata->pctl_dev); |
1245 | if (ret) | |
1246 | goto err_unregister; | |
1247 | ||
30574f0d | 1248 | platform_set_drvdata(pdev, drvdata); |
d9f99863 | 1249 | |
30574f0d | 1250 | return 0; |
50ebd19e KK |
1251 | |
1252 | err_unregister: | |
1253 | samsung_pinctrl_unregister(pdev, drvdata); | |
1254 | err_put_banks: | |
954445c7 | 1255 | samsung_banks_node_put(drvdata); |
50ebd19e | 1256 | return ret; |
30574f0d TA |
1257 | } |
1258 | ||
84a3fce5 | 1259 | /* |
2b24efa8 | 1260 | * samsung_pinctrl_suspend - save pinctrl state for suspend |
d9f99863 DA |
1261 | * |
1262 | * Save data for all banks handled by this device. | |
1263 | */ | |
304c92e8 | 1264 | static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) |
d9f99863 | 1265 | { |
2b24efa8 | 1266 | struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); |
d9f99863 DA |
1267 | int i; |
1268 | ||
f9c74474 AD |
1269 | i = clk_enable(drvdata->pclk); |
1270 | if (i) { | |
1271 | dev_err(drvdata->dev, | |
1272 | "failed to enable clock for saving state\n"); | |
1273 | return i; | |
1274 | } | |
1275 | ||
1bf00d7a TF |
1276 | for (i = 0; i < drvdata->nr_banks; i++) { |
1277 | struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; | |
1b09c2b8 | 1278 | const void __iomem *reg = bank->pctl_base + bank->pctl_offset; |
94ce944b TF |
1279 | const u8 *offs = bank->type->reg_offset; |
1280 | const u8 *widths = bank->type->fld_width; | |
d9f99863 DA |
1281 | enum pincfg_type type; |
1282 | ||
1283 | /* Registers without a powerdown config aren't lost */ | |
1284 | if (!widths[PINCFG_TYPE_CON_PDN]) | |
1285 | continue; | |
1286 | ||
1287 | for (type = 0; type < PINCFG_TYPE_NUM; type++) | |
1288 | if (widths[type]) | |
1289 | bank->pm_save[type] = readl(reg + offs[type]); | |
1290 | ||
1291 | if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { | |
1292 | /* Some banks have two config registers */ | |
1293 | bank->pm_save[PINCFG_TYPE_NUM] = | |
1294 | readl(reg + offs[PINCFG_TYPE_FUNC] + 4); | |
1295 | pr_debug("Save %s @ %p (con %#010x %08x)\n", | |
1296 | bank->name, reg, | |
1297 | bank->pm_save[PINCFG_TYPE_FUNC], | |
1298 | bank->pm_save[PINCFG_TYPE_NUM]); | |
1299 | } else { | |
1300 | pr_debug("Save %s @ %p (con %#010x)\n", bank->name, | |
1301 | reg, bank->pm_save[PINCFG_TYPE_FUNC]); | |
1302 | } | |
1303 | } | |
21c21993 | 1304 | |
f9c74474 AD |
1305 | clk_disable(drvdata->pclk); |
1306 | ||
1bf00d7a TF |
1307 | if (drvdata->suspend) |
1308 | drvdata->suspend(drvdata); | |
1fc8ad86 MS |
1309 | if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable) |
1310 | drvdata->retention_ctrl->enable(drvdata); | |
2b24efa8 MS |
1311 | |
1312 | return 0; | |
d9f99863 DA |
1313 | } |
1314 | ||
84a3fce5 | 1315 | /* |
2b24efa8 | 1316 | * samsung_pinctrl_resume - restore pinctrl state from suspend |
d9f99863 DA |
1317 | * |
1318 | * Restore one of the banks that was saved during suspend. | |
1319 | * | |
1320 | * We don't bother doing anything complicated to avoid glitching lines since | |
1321 | * we're called before pad retention is turned off. | |
1322 | */ | |
304c92e8 | 1323 | static int __maybe_unused samsung_pinctrl_resume(struct device *dev) |
d9f99863 | 1324 | { |
2b24efa8 | 1325 | struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); |
f9c74474 | 1326 | int ret; |
d9f99863 DA |
1327 | int i; |
1328 | ||
f9c74474 AD |
1329 | /* |
1330 | * enable clock before the callback, as we don't want to have to deal | |
1331 | * with callback cleanup on clock failures. | |
1332 | */ | |
1333 | ret = clk_enable(drvdata->pclk); | |
1334 | if (ret) { | |
1335 | dev_err(drvdata->dev, | |
1336 | "failed to enable clock for restoring state\n"); | |
1337 | return ret; | |
1338 | } | |
1339 | ||
1bf00d7a TF |
1340 | if (drvdata->resume) |
1341 | drvdata->resume(drvdata); | |
21c21993 | 1342 | |
1bf00d7a TF |
1343 | for (i = 0; i < drvdata->nr_banks; i++) { |
1344 | struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; | |
8b1bd11c | 1345 | void __iomem *reg = bank->pctl_base + bank->pctl_offset; |
94ce944b TF |
1346 | const u8 *offs = bank->type->reg_offset; |
1347 | const u8 *widths = bank->type->fld_width; | |
d9f99863 DA |
1348 | enum pincfg_type type; |
1349 | ||
1350 | /* Registers without a powerdown config aren't lost */ | |
1351 | if (!widths[PINCFG_TYPE_CON_PDN]) | |
1352 | continue; | |
1353 | ||
1354 | if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { | |
1355 | /* Some banks have two config registers */ | |
1356 | pr_debug("%s @ %p (con %#010x %08x => %#010x %08x)\n", | |
1357 | bank->name, reg, | |
1358 | readl(reg + offs[PINCFG_TYPE_FUNC]), | |
1359 | readl(reg + offs[PINCFG_TYPE_FUNC] + 4), | |
1360 | bank->pm_save[PINCFG_TYPE_FUNC], | |
1361 | bank->pm_save[PINCFG_TYPE_NUM]); | |
1362 | writel(bank->pm_save[PINCFG_TYPE_NUM], | |
1363 | reg + offs[PINCFG_TYPE_FUNC] + 4); | |
1364 | } else { | |
1365 | pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name, | |
1366 | reg, readl(reg + offs[PINCFG_TYPE_FUNC]), | |
1367 | bank->pm_save[PINCFG_TYPE_FUNC]); | |
1368 | } | |
1369 | for (type = 0; type < PINCFG_TYPE_NUM; type++) | |
1370 | if (widths[type]) | |
1371 | writel(bank->pm_save[type], reg + offs[type]); | |
1372 | } | |
1fc8ad86 | 1373 | |
f9c74474 AD |
1374 | clk_disable(drvdata->pclk); |
1375 | ||
1fc8ad86 MS |
1376 | if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable) |
1377 | drvdata->retention_ctrl->disable(drvdata); | |
d9f99863 DA |
1378 | |
1379 | return 0; | |
1380 | } | |
d9f99863 | 1381 | |
30574f0d | 1382 | static const struct of_device_id samsung_pinctrl_dt_match[] = { |
cfa76ddf | 1383 | #ifdef CONFIG_PINCTRL_EXYNOS_ARM |
d97f5b98 | 1384 | { .compatible = "samsung,exynos3250-pinctrl", |
93b0beae | 1385 | .data = &exynos3250_of_data }, |
b533c868 | 1386 | { .compatible = "samsung,exynos4210-pinctrl", |
93b0beae | 1387 | .data = &exynos4210_of_data }, |
b533c868 | 1388 | { .compatible = "samsung,exynos4x12-pinctrl", |
93b0beae | 1389 | .data = &exynos4x12_of_data }, |
f67faf48 | 1390 | { .compatible = "samsung,exynos5250-pinctrl", |
93b0beae | 1391 | .data = &exynos5250_of_data }, |
9a8b6079 | 1392 | { .compatible = "samsung,exynos5260-pinctrl", |
93b0beae | 1393 | .data = &exynos5260_of_data }, |
023e06df | 1394 | { .compatible = "samsung,exynos5410-pinctrl", |
93b0beae | 1395 | .data = &exynos5410_of_data }, |
983dbeb3 | 1396 | { .compatible = "samsung,exynos5420-pinctrl", |
93b0beae | 1397 | .data = &exynos5420_of_data }, |
608a26a7 | 1398 | { .compatible = "samsung,s5pv210-pinctrl", |
93b0beae | 1399 | .data = &s5pv210_of_data }, |
cfa76ddf KK |
1400 | #endif |
1401 | #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 | |
4a8be01a PG |
1402 | { .compatible = "google,gs101-pinctrl", |
1403 | .data = &gs101_of_data }, | |
cfa76ddf | 1404 | { .compatible = "samsung,exynos5433-pinctrl", |
93b0beae | 1405 | .data = &exynos5433_of_data }, |
50cea0cf | 1406 | { .compatible = "samsung,exynos7-pinctrl", |
93b0beae | 1407 | .data = &exynos7_of_data }, |
b0ef7b1a DV |
1408 | { .compatible = "samsung,exynos7885-pinctrl", |
1409 | .data = &exynos7885_of_data }, | |
cdd3d945 SP |
1410 | { .compatible = "samsung,exynos850-pinctrl", |
1411 | .data = &exynos850_of_data }, | |
02725b0c CP |
1412 | { .compatible = "samsung,exynosautov9-pinctrl", |
1413 | .data = &exynosautov9_of_data }, | |
6cf96df7 JK |
1414 | { .compatible = "samsung,exynosautov920-pinctrl", |
1415 | .data = &exynosautov920_of_data }, | |
0d1b662c AA |
1416 | { .compatible = "tesla,fsd-pinctrl", |
1417 | .data = &fsd_of_data }, | |
61dd7261 TF |
1418 | #endif |
1419 | #ifdef CONFIG_PINCTRL_S3C64XX | |
1420 | { .compatible = "samsung,s3c64xx-pinctrl", | |
93b0beae | 1421 | .data = &s3c64xx_of_data }, |
d5517bec | 1422 | #endif |
30574f0d TA |
1423 | {}, |
1424 | }; | |
30574f0d | 1425 | |
2b24efa8 MS |
1426 | static const struct dev_pm_ops samsung_pinctrl_pm_ops = { |
1427 | SET_LATE_SYSTEM_SLEEP_PM_OPS(samsung_pinctrl_suspend, | |
1428 | samsung_pinctrl_resume) | |
1429 | }; | |
1430 | ||
30574f0d TA |
1431 | static struct platform_driver samsung_pinctrl_driver = { |
1432 | .probe = samsung_pinctrl_probe, | |
1433 | .driver = { | |
1434 | .name = "samsung-pinctrl", | |
606fca94 | 1435 | .of_match_table = samsung_pinctrl_dt_match, |
a0ee2ac0 | 1436 | .suppress_bind_attrs = true, |
2b24efa8 | 1437 | .pm = &samsung_pinctrl_pm_ops, |
30574f0d TA |
1438 | }, |
1439 | }; | |
1440 | ||
1441 | static int __init samsung_pinctrl_drv_register(void) | |
1442 | { | |
1443 | return platform_driver_register(&samsung_pinctrl_driver); | |
1444 | } | |
1445 | postcore_initcall(samsung_pinctrl_drv_register); |