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Merge tag 'chrome-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/olof...
[linux-2.6-block.git] / drivers / pinctrl / samsung / pinctrl-s3c64xx.c
CommitLineData
61dd7261
TF		 1/*
2 * S3C64xx specific support for pinctrl-samsung driver.
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Based on pinctrl-exynos.c, please see the file for original copyrights.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This file contains the Samsung S3C64xx specific information required by the
14 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
15 * external gpio and wakeup interrupt support.
16 */
17
18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/interrupt.h>
21#include <linux/irqdomain.h>
22#include <linux/irq.h>
23#include <linux/of_irq.h>
24#include <linux/io.h>
a0d4262a 25#include <linux/irqchip/chained_irq.h>
61dd7261
TF		 26#include <linux/slab.h>
27#include <linux/err.h>
28
61dd7261
TF		 29#include "pinctrl-samsung.h"
30
31#define NUM_EINT0 28
32#define NUM_EINT0_IRQ 4
33#define EINT_MAX_PER_REG 16
34#define EINT_MAX_PER_GROUP 16
35
36/* External GPIO and wakeup interrupt related definitions */
37#define SVC_GROUP_SHIFT 4
38#define SVC_GROUP_MASK 0xf
39#define SVC_NUM_MASK 0xf
40#define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \
41 SVC_GROUP_MASK)
42
43#define EINT12CON_REG 0x200
44#define EINT12MASK_REG 0x240
45#define EINT12PEND_REG 0x260
46
47#define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP))
48#define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP)
49#define EINT_REG(g) (4 * ((g) / 2))
50
51#define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i)))
52#define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i)))
53#define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i)))
54
55#define SERVICE_REG 0x284
56#define SERVICEPEND_REG 0x288
57
58#define EINT0CON0_REG 0x900
59#define EINT0MASK_REG 0x920
60#define EINT0PEND_REG 0x924
61
62/* S3C64xx specific external interrupt trigger types */
63#define EINT_LEVEL_LOW 0
64#define EINT_LEVEL_HIGH 1
65#define EINT_EDGE_FALLING 2
66#define EINT_EDGE_RISING 4
67#define EINT_EDGE_BOTH 6
68#define EINT_CON_MASK 0xF
69#define EINT_CON_LEN 4
70
94ce944b 71static const struct samsung_pin_bank_type bank_type_4bit_off = {
61dd7261
TF		 72 .fld_width = { 4, 1, 2, 0, 2, 2, },
73 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
74};
75
94ce944b 76static const struct samsung_pin_bank_type bank_type_4bit_alive = {
61dd7261
TF		 77 .fld_width = { 4, 1, 2, },
78 .reg_offset = { 0x00, 0x04, 0x08, },
79};
80
94ce944b 81static const struct samsung_pin_bank_type bank_type_4bit2_off = {
61dd7261
TF		 82 .fld_width = { 4, 1, 2, 0, 2, 2, },
83 .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
84};
85
94ce944b 86static const struct samsung_pin_bank_type bank_type_4bit2_alive = {
61dd7261
TF		 87 .fld_width = { 4, 1, 2, },
88 .reg_offset = { 0x00, 0x08, 0x0c, },
89};
90
94ce944b 91static const struct samsung_pin_bank_type bank_type_2bit_off = {
61dd7261
TF		 92 .fld_width = { 2, 1, 2, 0, 2, 2, },
93 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
94};
95
94ce944b 96static const struct samsung_pin_bank_type bank_type_2bit_alive = {
61dd7261
TF		 97 .fld_width = { 2, 1, 2, },
98 .reg_offset = { 0x00, 0x04, 0x08, },
99};
100
101#define PIN_BANK_4BIT(pins, reg, id) \
102 { \
103 .type = &bank_type_4bit_off, \
104 .pctl_offset = reg, \
105 .nr_pins = pins, \
106 .eint_type = EINT_TYPE_NONE, \
107 .name = id \
108 }
109
110#define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \
111 { \
112 .type = &bank_type_4bit_off, \
113 .pctl_offset = reg, \
114 .nr_pins = pins, \
115 .eint_type = EINT_TYPE_GPIO, \
116 .eint_func = 7, \
117 .eint_mask = (1 << (pins)) - 1, \
118 .eint_offset = eoffs, \
119 .name = id \
120 }
121
122#define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \
123 { \
124 .type = &bank_type_4bit_alive,\
125 .pctl_offset = reg, \
126 .nr_pins = pins, \
127 .eint_type = EINT_TYPE_WKUP, \
128 .eint_func = 3, \
129 .eint_mask = emask, \
130 .eint_offset = eoffs, \
131 .name = id \
132 }
133
134#define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \
135 { \
136 .type = &bank_type_4bit2_off, \
137 .pctl_offset = reg, \
138 .nr_pins = pins, \
139 .eint_type = EINT_TYPE_GPIO, \
140 .eint_func = 7, \
141 .eint_mask = (1 << (pins)) - 1, \
142 .eint_offset = eoffs, \
143 .name = id \
144 }
145
146#define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \
147 { \
148 .type = &bank_type_4bit2_alive,\
149 .pctl_offset = reg, \
150 .nr_pins = pins, \
151 .eint_type = EINT_TYPE_WKUP, \
152 .eint_func = 3, \
153 .eint_mask = emask, \
154 .eint_offset = eoffs, \
155 .name = id \
156 }
157
158#define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \
159 { \
160 .type = &bank_type_4bit2_alive,\
161 .pctl_offset = reg, \
162 .nr_pins = pins, \
163 .eint_type = EINT_TYPE_NONE, \
164 .name = id \
165 }
166
167#define PIN_BANK_2BIT(pins, reg, id) \
168 { \
169 .type = &bank_type_2bit_off, \
170 .pctl_offset = reg, \
171 .nr_pins = pins, \
172 .eint_type = EINT_TYPE_NONE, \
173 .name = id \
174 }
175
176#define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \
177 { \
178 .type = &bank_type_2bit_off, \
179 .pctl_offset = reg, \
180 .nr_pins = pins, \
181 .eint_type = EINT_TYPE_GPIO, \
182 .eint_func = 3, \
183 .eint_mask = emask, \
184 .eint_offset = eoffs, \
185 .name = id \
186 }
187
188#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \
189 { \
190 .type = &bank_type_2bit_alive,\
191 .pctl_offset = reg, \
192 .nr_pins = pins, \
193 .eint_type = EINT_TYPE_WKUP, \
194 .eint_func = 2, \
195 .eint_mask = (1 << (pins)) - 1, \
196 .eint_offset = eoffs, \
197 .name = id \
198 }
199
200/**
201 * struct s3c64xx_eint0_data: EINT0 common data
202 * @drvdata: pin controller driver data
203 * @domains: IRQ domains of particular EINT0 interrupts
204 * @pins: pin offsets inside of banks of particular EINT0 interrupts
205 */
206struct s3c64xx_eint0_data {
207 struct samsung_pinctrl_drv_data *drvdata;
208 struct irq_domain *domains[NUM_EINT0];
209 u8 pins[NUM_EINT0];
210};
211
212/**
213 * struct s3c64xx_eint0_domain_data: EINT0 per-domain data
214 * @bank: pin bank related to the domain
215 * @eints: EINT0 interrupts related to the domain
216 */
217struct s3c64xx_eint0_domain_data {
218 struct samsung_pin_bank *bank;
219 u8 eints[];
220};
221
222/**
223 * struct s3c64xx_eint_gpio_data: GPIO EINT data
224 * @drvdata: pin controller driver data
225 * @domains: array of domains related to EINT interrupt groups
226 */
227struct s3c64xx_eint_gpio_data {
228 struct samsung_pinctrl_drv_data *drvdata;
229 struct irq_domain *domains[];
230};
231
232/*
233 * Common functions for S3C64xx EINT configuration
234 */
235
236static int s3c64xx_irq_get_trigger(unsigned int type)
237{
238 int trigger;
239
240 switch (type) {
241 case IRQ_TYPE_EDGE_RISING:
242 trigger = EINT_EDGE_RISING;
243 break;
244 case IRQ_TYPE_EDGE_FALLING:
245 trigger = EINT_EDGE_FALLING;
246 break;
247 case IRQ_TYPE_EDGE_BOTH:
248 trigger = EINT_EDGE_BOTH;
249 break;
250 case IRQ_TYPE_LEVEL_HIGH:
251 trigger = EINT_LEVEL_HIGH;
252 break;
253 case IRQ_TYPE_LEVEL_LOW:
254 trigger = EINT_LEVEL_LOW;
255 break;
256 default:
257 return -EINVAL;
258 }
259
260 return trigger;
261}
262
f66eb498 263static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
61dd7261
TF		 264{
265 /* Edge- and level-triggered interrupts need different handlers */
266 if (type & IRQ_TYPE_EDGE_BOTH)
f66eb498 267 irq_set_handler_locked(d, handle_edge_irq);
61dd7261 268 else
f66eb498 269 irq_set_handler_locked(d, handle_level_irq);
61dd7261
TF		 270}
271
272static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
273 struct samsung_pin_bank *bank, int pin)
274{
94ce944b 275 const struct samsung_pin_bank_type *bank_type = bank->type;
61dd7261
TF		 276 unsigned long flags;
277 void __iomem *reg;
278 u8 shift;
279 u32 mask;
280 u32 val;
281
282 /* Make sure that pin is configured as interrupt */
283 reg = d->virt_base + bank->pctl_offset;
284 shift = pin;
285 if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
286 /* 4-bit bank type with 2 con regs */
287 reg += 4;
288 shift -= 8;
289 }
290
291 shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
292 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
293
294 spin_lock_irqsave(&bank->slock, flags);
295
296 val = readl(reg);
297 val &= ~(mask << shift);
298 val |= bank->eint_func << shift;
299 writel(val, reg);
300
301 spin_unlock_irqrestore(&bank->slock, flags);
302}
303
304/*
305 * Functions for EINT GPIO configuration (EINT groups 1-9)
306 */
307
308static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
309{
310 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
311 struct samsung_pinctrl_drv_data *d = bank->drvdata;
312 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
313 void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
314 u32 val;
315
316 val = readl(reg);
317 if (mask)
318 val |= 1 << index;
319 else
320 val &= ~(1 << index);
321 writel(val, reg);
322}
323
324static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)
325{
326 s3c64xx_gpio_irq_set_mask(irqd, false);
327}
328
329static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
330{
331 s3c64xx_gpio_irq_set_mask(irqd, true);
332}
333
334static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
335{
336 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
337 struct samsung_pinctrl_drv_data *d = bank->drvdata;
338 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
339 void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
340
341 writel(1 << index, reg);
342}
343
344static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
345{
346 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
347 struct samsung_pinctrl_drv_data *d = bank->drvdata;
348 void __iomem *reg;
349 int trigger;
350 u8 shift;
351 u32 val;
352
353 trigger = s3c64xx_irq_get_trigger(type);
354 if (trigger < 0) {
355 pr_err("unsupported external interrupt type\n");
356 return -EINVAL;
357 }
358
f66eb498 359 s3c64xx_irq_set_handler(irqd, type);
61dd7261
TF		 360
361 /* Set up interrupt trigger */
362 reg = d->virt_base + EINTCON_REG(bank->eint_offset);
363 shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
364 shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
365
366 val = readl(reg);
367 val &= ~(EINT_CON_MASK << shift);
368 val |= trigger << shift;
369 writel(val, reg);
370
371 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
372
373 return 0;
374}
375
376/*
377 * irq_chip for gpio interrupts.
378 */
379static struct irq_chip s3c64xx_gpio_irq_chip = {
380 .name = "GPIO",
381 .irq_unmask = s3c64xx_gpio_irq_unmask,
382 .irq_mask = s3c64xx_gpio_irq_mask,
383 .irq_ack = s3c64xx_gpio_irq_ack,
384 .irq_set_type = s3c64xx_gpio_irq_set_type,
385};
386
387static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
388 irq_hw_number_t hw)
389{
390 struct samsung_pin_bank *bank = h->host_data;
391
392 if (!(bank->eint_mask & (1 << hw)))
393 return -EINVAL;
394
395 irq_set_chip_and_handler(virq,
396 &s3c64xx_gpio_irq_chip, handle_level_irq);
397 irq_set_chip_data(virq, bank);
61dd7261
TF		 398
399 return 0;
400}
401
402/*
403 * irq domain callbacks for external gpio interrupt controller.
404 */
405static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
406 .map = s3c64xx_gpio_irq_map,
407 .xlate = irq_domain_xlate_twocell,
408};
409
bd0b9ac4 410static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
61dd7261 411{
5663bb27
JL		 412 struct irq_chip *chip = irq_desc_get_chip(desc);
413 struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
61dd7261
TF		 414 struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
415
416 chained_irq_enter(chip, desc);
417
418 do {
419 unsigned int svc;
420 unsigned int group;
421 unsigned int pin;
422 unsigned int virq;
423
424 svc = readl(drvdata->virt_base + SERVICE_REG);
425 group = SVC_GROUP(svc);
426 pin = svc & SVC_NUM_MASK;
427
428 if (!group)
429 break;
430
431 /* Group 1 is used for two pin banks */
432 if (group == 1) {
433 if (pin < 8)
434 group = 0;
435 else
436 pin -= 8;
437 }
438
439 virq = irq_linear_revmap(data->domains[group], pin);
440 /*
441 * Something must be really wrong if an unmapped EINT
442 * was unmasked...
443 */
444 BUG_ON(!virq);
445
446 generic_handle_irq(virq);
447 } while (1);
448
449 chained_irq_exit(chip, desc);
450}
451
452/**
453 * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
454 * @d: driver data of samsung pinctrl driver.
455 */
456static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
457{
458 struct s3c64xx_eint_gpio_data *data;
459 struct samsung_pin_bank *bank;
460 struct device *dev = d->dev;
461 unsigned int nr_domains;
462 unsigned int i;
463
464 if (!d->irq) {
465 dev_err(dev, "irq number not available\n");
466 return -EINVAL;
467 }
468
469 nr_domains = 0;
1bf00d7a
TF		 470 bank = d->pin_banks;
471 for (i = 0; i < d->nr_banks; ++i, ++bank) {
61dd7261
TF		 472 unsigned int nr_eints;
473 unsigned int mask;
474
475 if (bank->eint_type != EINT_TYPE_GPIO)
476 continue;
477
478 mask = bank->eint_mask;
479 nr_eints = fls(mask);
480
481 bank->irq_domain = irq_domain_add_linear(bank->of_node,
482 nr_eints, &s3c64xx_gpio_irqd_ops, bank);
483 if (!bank->irq_domain) {
484 dev_err(dev, "gpio irq domain add failed\n");
485 return -ENXIO;
486 }
487
488 ++nr_domains;
489 }
490
491 data = devm_kzalloc(dev, sizeof(*data)
492 + nr_domains * sizeof(*data->domains), GFP_KERNEL);
493 if (!data) {
494 dev_err(dev, "failed to allocate handler data\n");
495 return -ENOMEM;
496 }
497 data->drvdata = d;
498
1bf00d7a 499 bank = d->pin_banks;
61dd7261 500 nr_domains = 0;
1bf00d7a 501 for (i = 0; i < d->nr_banks; ++i, ++bank) {
61dd7261
TF		 502 if (bank->eint_type != EINT_TYPE_GPIO)
503 continue;
504
505 data->domains[nr_domains++] = bank->irq_domain;
506 }
507
623a650e 508 irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data);
61dd7261
TF		 509
510 return 0;
511}
512
513/*
514 * Functions for configuration of EINT0 wake-up interrupts
515 */
516
517static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
518{
519 struct s3c64xx_eint0_domain_data *ddata =
520 irq_data_get_irq_chip_data(irqd);
521 struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
522 u32 val;
523
524 val = readl(d->virt_base + EINT0MASK_REG);
525 if (mask)
526 val |= 1 << ddata->eints[irqd->hwirq];
527 else
528 val &= ~(1 << ddata->eints[irqd->hwirq]);
529 writel(val, d->virt_base + EINT0MASK_REG);
530}
531
532static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
533{
534 s3c64xx_eint0_irq_set_mask(irqd, false);
535}
536
537static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)
538{
539 s3c64xx_eint0_irq_set_mask(irqd, true);
540}
541
542static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
543{
544 struct s3c64xx_eint0_domain_data *ddata =
545 irq_data_get_irq_chip_data(irqd);
546 struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
547
548 writel(1 << ddata->eints[irqd->hwirq],
549 d->virt_base + EINT0PEND_REG);
550}
551
552static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
553{
554 struct s3c64xx_eint0_domain_data *ddata =
555 irq_data_get_irq_chip_data(irqd);
556 struct samsung_pin_bank *bank = ddata->bank;
557 struct samsung_pinctrl_drv_data *d = bank->drvdata;
558 void __iomem *reg;
559 int trigger;
560 u8 shift;
561 u32 val;
562
563 trigger = s3c64xx_irq_get_trigger(type);
564 if (trigger < 0) {
565 pr_err("unsupported external interrupt type\n");
566 return -EINVAL;
567 }
568
f66eb498 569 s3c64xx_irq_set_handler(irqd, type);
61dd7261
TF		 570
571 /* Set up interrupt trigger */
572 reg = d->virt_base + EINT0CON0_REG;
573 shift = ddata->eints[irqd->hwirq];
574 if (shift >= EINT_MAX_PER_REG) {
575 reg += 4;
576 shift -= EINT_MAX_PER_REG;
577 }
578 shift = EINT_CON_LEN * (shift / 2);
579
580 val = readl(reg);
581 val &= ~(EINT_CON_MASK << shift);
582 val |= trigger << shift;
583 writel(val, reg);
584
585 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
586
587 return 0;
588}
589
590/*
591 * irq_chip for wakeup interrupts
592 */
593static struct irq_chip s3c64xx_eint0_irq_chip = {
594 .name = "EINT0",
595 .irq_unmask = s3c64xx_eint0_irq_unmask,
596 .irq_mask = s3c64xx_eint0_irq_mask,
597 .irq_ack = s3c64xx_eint0_irq_ack,
598 .irq_set_type = s3c64xx_eint0_irq_set_type,
599};
600
5663bb27 601static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
61dd7261 602{
5663bb27
JL		 603 struct irq_chip *chip = irq_desc_get_chip(desc);
604 struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
61dd7261
TF		 605 struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
606 unsigned int pend, mask;
607
608 chained_irq_enter(chip, desc);
609
610 pend = readl(drvdata->virt_base + EINT0PEND_REG);
611 mask = readl(drvdata->virt_base + EINT0MASK_REG);
612
613 pend = pend & range & ~mask;
614 pend &= range;
615
616 while (pend) {
5663bb27 617 unsigned int virq, irq;
61dd7261
TF		 618
619 irq = fls(pend) - 1;
620 pend &= ~(1 << irq);
61dd7261
TF		 621 virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);
622 /*
623 * Something must be really wrong if an unmapped EINT
624 * was unmasked...
625 */
626 BUG_ON(!virq);
627
628 generic_handle_irq(virq);
629 }
630
631 chained_irq_exit(chip, desc);
632}
633
bd0b9ac4 634static void s3c64xx_demux_eint0_3(struct irq_desc *desc)
61dd7261 635{
5663bb27 636 s3c64xx_irq_demux_eint(desc, 0xf);
61dd7261
TF		 637}
638
bd0b9ac4 639static void s3c64xx_demux_eint4_11(struct irq_desc *desc)
61dd7261 640{
5663bb27 641 s3c64xx_irq_demux_eint(desc, 0xff0);
61dd7261
TF		 642}
643
bd0b9ac4 644static void s3c64xx_demux_eint12_19(struct irq_desc *desc)
61dd7261 645{
5663bb27 646 s3c64xx_irq_demux_eint(desc, 0xff000);
61dd7261
TF		 647}
648
bd0b9ac4 649static void s3c64xx_demux_eint20_27(struct irq_desc *desc)
61dd7261 650{
5663bb27 651 s3c64xx_irq_demux_eint(desc, 0xff00000);
61dd7261
TF		 652}
653
654static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
655 s3c64xx_demux_eint0_3,
656 s3c64xx_demux_eint4_11,
657 s3c64xx_demux_eint12_19,
658 s3c64xx_demux_eint20_27,
659};
660
661static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
662 irq_hw_number_t hw)
663{
664 struct s3c64xx_eint0_domain_data *ddata = h->host_data;
665 struct samsung_pin_bank *bank = ddata->bank;
666
667 if (!(bank->eint_mask & (1 << hw)))
668 return -EINVAL;
669
670 irq_set_chip_and_handler(virq,
671 &s3c64xx_eint0_irq_chip, handle_level_irq);
672 irq_set_chip_data(virq, ddata);
61dd7261
TF		 673
674 return 0;
675}
676
677/*
678 * irq domain callbacks for external wakeup interrupt controller.
679 */
680static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = {
681 .map = s3c64xx_eint0_irq_map,
682 .xlate = irq_domain_xlate_twocell,
683};
684
685/* list of external wakeup controllers supported */
686static const struct of_device_id s3c64xx_eint0_irq_ids[] = {
687 { .compatible = "samsung,s3c64xx-wakeup-eint", },
688 { }
689};
690
691/**
692 * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
693 * @d: driver data of samsung pinctrl driver.
694 */
695static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
696{
697 struct device *dev = d->dev;
698 struct device_node *eint0_np = NULL;
699 struct device_node *np;
700 struct samsung_pin_bank *bank;
701 struct s3c64xx_eint0_data *data;
702 unsigned int i;
703
704 for_each_child_of_node(dev->of_node, np) {
705 if (of_match_node(s3c64xx_eint0_irq_ids, np)) {
706 eint0_np = np;
707 break;
708 }
709 }
710 if (!eint0_np)
711 return -ENODEV;
712
713 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
714 if (!data) {
715 dev_err(dev, "could not allocate memory for wkup eint data\n");
716 return -ENOMEM;
717 }
718 data->drvdata = d;
719
720 for (i = 0; i < NUM_EINT0_IRQ; ++i) {
721 unsigned int irq;
722
723 irq = irq_of_parse_and_map(eint0_np, i);
724 if (!irq) {
725 dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
726 return -ENXIO;
727 }
728
623a650e
TG		 729 irq_set_chained_handler_and_data(irq,
730 s3c64xx_eint0_handlers[i],
731 data);
61dd7261
TF		 732 }
733
1bf00d7a
TF		 734 bank = d->pin_banks;
735 for (i = 0; i < d->nr_banks; ++i, ++bank) {
61dd7261
TF		 736 struct s3c64xx_eint0_domain_data *ddata;
737 unsigned int nr_eints;
738 unsigned int mask;
739 unsigned int irq;
740 unsigned int pin;
741
742 if (bank->eint_type != EINT_TYPE_WKUP)
743 continue;
744
745 mask = bank->eint_mask;
746 nr_eints = fls(mask);
747
748 ddata = devm_kzalloc(dev,
749 sizeof(*ddata) + nr_eints, GFP_KERNEL);
750 if (!ddata) {
751 dev_err(dev, "failed to allocate domain data\n");
752 return -ENOMEM;
753 }
754 ddata->bank = bank;
755
756 bank->irq_domain = irq_domain_add_linear(bank->of_node,
757 nr_eints, &s3c64xx_eint0_irqd_ops, ddata);
758 if (!bank->irq_domain) {
759 dev_err(dev, "wkup irq domain add failed\n");
760 return -ENXIO;
761 }
762
763 irq = bank->eint_offset;
764 mask = bank->eint_mask;
765 for (pin = 0; mask; ++pin, mask >>= 1) {
766 if (!(mask & 1))
767 continue;
768 data->domains[irq] = bank->irq_domain;
769 data->pins[irq] = pin;
770 ddata->eints[pin] = irq;
771 ++irq;
772 }
773 }
774
775 return 0;
776}
777
778/* pin banks of s3c64xx pin-controller 0 */
8100cf47 779static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
61dd7261
TF		 780 PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
781 PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
782 PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
783 PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
784 PIN_BANK_4BIT(5, 0x080, "gpe"),
785 PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
786 PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
787 PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
788 PIN_BANK_2BIT(16, 0x100, "gpi"),
789 PIN_BANK_2BIT(12, 0x120, "gpj"),
790 PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
791 PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
792 PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
793 PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
794 PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
795 PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
796 PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),
797};
798
799/*
800 * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
801 * one gpio/pin-mux/pinconfig controller.
802 */
1bf00d7a 803const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
61dd7261
TF		 804 {
805 /* pin-controller instance 1 data */
806 .pin_banks = s3c64xx_pin_banks0,
807 .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
808 .eint_gpio_init = s3c64xx_eint_gpio_init,
809 .eint_wkup_init = s3c64xx_eint_eint0_init,
61dd7261
TF		 810 },
811};
Linux 6.x block layer and io_uring tree(s)