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c4c4637e LP |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Renesas RZ/G2L Pin Control and GPIO driver core | |
4 | * | |
5 | * Copyright (C) 2021 Renesas Electronics Corporation. | |
6 | */ | |
7 | ||
04d231b9 | 8 | #include <linux/bitfield.h> |
c4c4637e LP |
9 | #include <linux/bitops.h> |
10 | #include <linux/clk.h> | |
11 | #include <linux/gpio/driver.h> | |
db2e5f21 | 12 | #include <linux/interrupt.h> |
2fb98ab4 | 13 | #include <linux/io.h> |
c4c4637e | 14 | #include <linux/module.h> |
661efa22 | 15 | #include <linux/mutex.h> |
060f03e9 | 16 | #include <linux/of.h> |
db2e5f21 | 17 | #include <linux/of_irq.h> |
060f03e9 | 18 | #include <linux/platform_device.h> |
2fb98ab4 AS |
19 | #include <linux/seq_file.h> |
20 | #include <linux/spinlock.h> | |
21 | ||
22 | #include <linux/pinctrl/consumer.h> | |
c4c4637e LP |
23 | #include <linux/pinctrl/pinconf-generic.h> |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinctrl.h> | |
26 | #include <linux/pinctrl/pinmux.h> | |
c4c4637e LP |
27 | |
28 | #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> | |
29 | ||
30 | #include "../core.h" | |
31 | #include "../pinconf.h" | |
32 | #include "../pinmux.h" | |
33 | ||
34 | #define DRV_NAME "pinctrl-rzg2l" | |
35 | ||
36 | /* | |
37 | * Use 16 lower bits [15:0] for pin identifier | |
38 | * Use 16 higher bits [31:16] for pin mux function | |
39 | */ | |
40 | #define MUX_PIN_ID_MASK GENMASK(15, 0) | |
41 | #define MUX_FUNC_MASK GENMASK(31, 16) | |
c4c4637e LP |
42 | |
43 | /* PIN capabilities */ | |
adb613f8 LP |
44 | #define PIN_CFG_IOLH_A BIT(0) |
45 | #define PIN_CFG_IOLH_B BIT(1) | |
46 | #define PIN_CFG_SR BIT(2) | |
47 | #define PIN_CFG_IEN BIT(3) | |
48 | #define PIN_CFG_PUPD BIT(4) | |
49 | #define PIN_CFG_IO_VMC_SD0 BIT(5) | |
50 | #define PIN_CFG_IO_VMC_SD1 BIT(6) | |
51 | #define PIN_CFG_IO_VMC_QSPI BIT(7) | |
52 | #define PIN_CFG_IO_VMC_ETH0 BIT(8) | |
53 | #define PIN_CFG_IO_VMC_ETH1 BIT(9) | |
54 | #define PIN_CFG_FILONOFF BIT(10) | |
55 | #define PIN_CFG_FILNUM BIT(11) | |
56 | #define PIN_CFG_FILCLKSEL BIT(12) | |
ae5b425f CB |
57 | #define PIN_CFG_IOLH_C BIT(13) |
58 | #define PIN_CFG_SOFT_PS BIT(14) | |
1bbc8ee4 | 59 | #define PIN_CFG_OEN BIT(15) |
fea58424 LP |
60 | #define PIN_CFG_VARIABLE BIT(16) |
61 | #define PIN_CFG_NOGPIO_INT BIT(17) | |
adb613f8 | 62 | |
c6a088e5 CB |
63 | #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ |
64 | (PIN_CFG_IOLH_##group | \ | |
c4c4637e LP |
65 | PIN_CFG_PUPD | \ |
66 | PIN_CFG_FILONOFF | \ | |
67 | PIN_CFG_FILNUM | \ | |
68 | PIN_CFG_FILCLKSEL) | |
69 | ||
c6a088e5 CB |
70 | #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ |
71 | PIN_CFG_SR) | |
72 | ||
73 | #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ | |
74 | PIN_CFG_SOFT_PS) | |
75 | ||
c4c4637e LP |
76 | #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ |
77 | PIN_CFG_FILONOFF | \ | |
78 | PIN_CFG_FILNUM | \ | |
79 | PIN_CFG_FILCLKSEL) | |
80 | ||
15e4ae4f | 81 | #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) |
04d231b9 LP |
82 | #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) |
83 | #define PIN_CFG_MASK GENMASK(19, 0) | |
15e4ae4f | 84 | |
fea58424 LP |
85 | /* |
86 | * m indicates the bitmap of supported pins, a is the register index | |
87 | * and f is pin configuration capabilities supported. | |
88 | */ | |
89 | #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ | |
90 | FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ | |
91 | FIELD_PREP_CONST(PIN_CFG_MASK, (f))) | |
92 | ||
93 | /* | |
94 | * n indicates number of pins in the port, a is the register index | |
95 | * and f is pin configuration capabilities supported. | |
96 | */ | |
97 | #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) | |
c4c4637e LP |
98 | |
99 | /* | |
15e4ae4f | 100 | * BIT(63) indicates dedicated pin, p is the register index while |
c4c4637e LP |
101 | * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits |
102 | * (b * 8) and f is the pin configuration capabilities supported. | |
103 | */ | |
15e4ae4f | 104 | #define RZG2L_SINGLE_PIN BIT_ULL(63) |
04d231b9 LP |
105 | #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) |
106 | #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) | |
107 | ||
c4c4637e | 108 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ |
04d231b9 LP |
109 | FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ |
110 | FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ | |
111 | FIELD_PREP_CONST(PIN_CFG_MASK, (f))) | |
77e18969 | 112 | |
77e18969 | 113 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ |
04d231b9 LP |
114 | FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ |
115 | FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) | |
77e18969 CB |
116 | |
117 | #define P(off) (0x0000 + (off)) | |
118 | #define PM(off) (0x0100 + (off) * 2) | |
119 | #define PMC(off) (0x0200 + (off)) | |
120 | #define PFC(off) (0x0400 + (off) * 4) | |
121 | #define PIN(off) (0x0800 + (off)) | |
122 | #define IOLH(off) (0x1000 + (off) * 8) | |
123 | #define IEN(off) (0x1800 + (off) * 8) | |
124 | #define ISEL(off) (0x2C00 + (off) * 8) | |
1f89aa90 | 125 | #define SD_CH(off, ch) ((off) + (ch) * 4) |
51996952 | 126 | #define ETH_POC(off, ch) ((off) + (ch) * 4) |
c4c4637e | 127 | #define QSPI (0x3008) |
1bbc8ee4 | 128 | #define ETH_MODE (0x3018) |
c4c4637e | 129 | |
51996952 | 130 | #define PVDD_2500 2 /* I/O domain voltage 2.5V */ |
c4c4637e LP |
131 | #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ |
132 | #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ | |
133 | ||
134 | #define PWPR_B0WI BIT(7) /* Bit Write Disable */ | |
135 | #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ | |
136 | ||
137 | #define PM_MASK 0x03 | |
c4c4637e LP |
138 | #define PFC_MASK 0x07 |
139 | #define IEN_MASK 0x01 | |
adb613f8 | 140 | #define IOLH_MASK 0x03 |
c4c4637e LP |
141 | |
142 | #define PM_INPUT 0x1 | |
143 | #define PM_OUTPUT 0x2 | |
144 | ||
145 | #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) | |
146 | #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) | |
147 | ||
db2e5f21 LP |
148 | #define RZG2L_TINT_MAX_INTERRUPT 32 |
149 | #define RZG2L_TINT_IRQ_START_INDEX 9 | |
150 | #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) | |
151 | ||
254203f9 CB |
152 | /* Read/write 8 bits register */ |
153 | #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ | |
154 | do { \ | |
155 | if (_read) \ | |
156 | _val = readb(_addr); \ | |
157 | else \ | |
158 | writeb(_val, _addr); \ | |
159 | } while (0) | |
160 | ||
161 | /* Read/write 16 bits register */ | |
162 | #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \ | |
163 | do { \ | |
164 | if (_read) \ | |
165 | _val = readw(_addr); \ | |
166 | else \ | |
167 | writew(_val, _addr); \ | |
168 | } while (0) | |
169 | ||
170 | /* Read/write 32 bits register */ | |
171 | #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \ | |
172 | do { \ | |
173 | if (_read) \ | |
174 | _val = readl(_addr); \ | |
175 | else \ | |
176 | writel(_val, _addr); \ | |
177 | } while (0) | |
178 | ||
1f89aa90 CB |
179 | /** |
180 | * struct rzg2l_register_offsets - specific register offsets | |
181 | * @pwpr: PWPR register offset | |
182 | * @sd_ch: SD_CH register offset | |
51996952 | 183 | * @eth_poc: ETH_POC register offset |
1f89aa90 CB |
184 | */ |
185 | struct rzg2l_register_offsets { | |
186 | u16 pwpr; | |
187 | u16 sd_ch; | |
51996952 | 188 | u16 eth_poc; |
1f89aa90 CB |
189 | }; |
190 | ||
cca38201 CB |
191 | /** |
192 | * enum rzg2l_iolh_index - starting indices in IOLH specific arrays | |
ae5b425f CB |
193 | * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source |
194 | * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source | |
cca38201 CB |
195 | * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source |
196 | * @RZG2L_IOLH_IDX_MAX: maximum index | |
197 | */ | |
198 | enum rzg2l_iolh_index { | |
ae5b425f CB |
199 | RZG2L_IOLH_IDX_1V8 = 0, |
200 | RZG2L_IOLH_IDX_2V5 = 4, | |
201 | RZG2L_IOLH_IDX_3V3 = 8, | |
202 | RZG2L_IOLH_IDX_MAX = 12, | |
cca38201 CB |
203 | }; |
204 | ||
205 | /* Maximum number of driver strength entries per power source. */ | |
206 | #define RZG2L_IOLH_MAX_DS_ENTRIES (4) | |
207 | ||
1f89aa90 CB |
208 | /** |
209 | * struct rzg2l_hwcfg - hardware configuration data structure | |
210 | * @regs: hardware specific register offsets | |
cca38201 | 211 | * @iolh_groupa_ua: IOLH group A uA specific values |
ae5b425f CB |
212 | * @iolh_groupb_ua: IOLH group B uA specific values |
213 | * @iolh_groupc_ua: IOLH group C uA specific values | |
cca38201 | 214 | * @iolh_groupb_oi: IOLH group B output impedance specific values |
ae5b425f | 215 | * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) |
35a3610e | 216 | * @func_base: base number for port function (see register PFC) |
1bbc8ee4 CB |
217 | * @oen_max_pin: the maximum pin number supporting output enable |
218 | * @oen_max_port: the maximum port number supporting output enable | |
1f89aa90 CB |
219 | */ |
220 | struct rzg2l_hwcfg { | |
221 | const struct rzg2l_register_offsets regs; | |
cca38201 | 222 | u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; |
ae5b425f CB |
223 | u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; |
224 | u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; | |
cca38201 | 225 | u16 iolh_groupb_oi[4]; |
ae5b425f | 226 | bool drive_strength_ua; |
35a3610e | 227 | u8 func_base; |
1bbc8ee4 CB |
228 | u8 oen_max_pin; |
229 | u8 oen_max_port; | |
1f89aa90 CB |
230 | }; |
231 | ||
c4c4637e LP |
232 | struct rzg2l_dedicated_configs { |
233 | const char *name; | |
15e4ae4f | 234 | u64 config; |
c4c4637e LP |
235 | }; |
236 | ||
fea58424 LP |
237 | /** |
238 | * struct rzg2l_variable_pin_cfg - pin data cfg | |
239 | * @cfg: port pin configuration | |
240 | * @port: port number | |
241 | * @pin: port pin | |
242 | */ | |
243 | struct rzg2l_variable_pin_cfg { | |
244 | u32 cfg:20; | |
245 | u32 port:5; | |
246 | u32 pin:3; | |
247 | }; | |
248 | ||
c4c4637e LP |
249 | struct rzg2l_pinctrl_data { |
250 | const char * const *port_pins; | |
15e4ae4f | 251 | const u64 *port_pin_configs; |
00dfe298 | 252 | unsigned int n_ports; |
84c580e9 | 253 | const struct rzg2l_dedicated_configs *dedicated_pins; |
c4c4637e LP |
254 | unsigned int n_port_pins; |
255 | unsigned int n_dedicated_pins; | |
1f89aa90 | 256 | const struct rzg2l_hwcfg *hwcfg; |
fea58424 LP |
257 | const struct rzg2l_variable_pin_cfg *variable_pin_cfg; |
258 | unsigned int n_variable_pin_cfg; | |
c4c4637e LP |
259 | }; |
260 | ||
ae5b425f CB |
261 | /** |
262 | * struct rzg2l_pinctrl_pin_settings - pin data | |
263 | * @power_source: power source | |
264 | * @drive_strength_ua: drive strength (in micro amps) | |
265 | */ | |
266 | struct rzg2l_pinctrl_pin_settings { | |
267 | u16 power_source; | |
268 | u16 drive_strength_ua; | |
269 | }; | |
270 | ||
254203f9 CB |
271 | /** |
272 | * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) | |
273 | * @p: P registers cache | |
274 | * @pm: PM registers cache | |
275 | * @pmc: PMC registers cache | |
276 | * @pfc: PFC registers cache | |
277 | * @iolh: IOLH registers cache | |
278 | * @ien: IEN registers cache | |
279 | * @sd_ch: SD_CH registers cache | |
280 | * @eth_poc: ET_POC registers cache | |
281 | * @eth_mode: ETH_MODE register cache | |
282 | * @qspi: QSPI registers cache | |
283 | */ | |
284 | struct rzg2l_pinctrl_reg_cache { | |
285 | u8 *p; | |
286 | u16 *pm; | |
287 | u8 *pmc; | |
288 | u32 *pfc; | |
289 | u32 *iolh[2]; | |
290 | u32 *ien[2]; | |
291 | u8 sd_ch[2]; | |
292 | u8 eth_poc[2]; | |
293 | u8 eth_mode; | |
294 | u8 qspi; | |
295 | }; | |
296 | ||
c4c4637e LP |
297 | struct rzg2l_pinctrl { |
298 | struct pinctrl_dev *pctl; | |
299 | struct pinctrl_desc desc; | |
300 | struct pinctrl_pin_desc *pins; | |
301 | ||
302 | const struct rzg2l_pinctrl_data *data; | |
303 | void __iomem *base; | |
304 | struct device *dev; | |
c4c4637e | 305 | |
254203f9 CB |
306 | struct clk *clk; |
307 | ||
c4c4637e LP |
308 | struct gpio_chip gpio_chip; |
309 | struct pinctrl_gpio_range gpio_range; | |
db2e5f21 | 310 | DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); |
661efa22 | 311 | spinlock_t bitmap_lock; /* protect tint_slot bitmap */ |
db2e5f21 | 312 | unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; |
c4c4637e | 313 | |
661efa22 BD |
314 | spinlock_t lock; /* lock read/write registers */ |
315 | struct mutex mutex; /* serialize adding groups and functions */ | |
ae5b425f CB |
316 | |
317 | struct rzg2l_pinctrl_pin_settings *settings; | |
254203f9 CB |
318 | struct rzg2l_pinctrl_reg_cache *cache; |
319 | struct rzg2l_pinctrl_reg_cache *dedicated_cache; | |
320 | atomic_t wakeup_path; | |
c4c4637e LP |
321 | }; |
322 | ||
ae5b425f CB |
323 | static const u16 available_ps[] = { 1800, 2500, 3300 }; |
324 | ||
fea58424 LP |
325 | #ifdef CONFIG_RISCV |
326 | static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, | |
327 | u64 pincfg, | |
328 | unsigned int port, | |
329 | u8 pin) | |
330 | { | |
331 | unsigned int i; | |
332 | ||
333 | for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { | |
334 | if (pctrl->data->variable_pin_cfg[i].port == port && | |
335 | pctrl->data->variable_pin_cfg[i].pin == pin) | |
336 | return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { | |
343 | { | |
344 | .port = 20, | |
345 | .pin = 0, | |
346 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
347 | PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | | |
348 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, | |
349 | }, | |
350 | { | |
351 | .port = 20, | |
352 | .pin = 1, | |
353 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
354 | PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | | |
355 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, | |
356 | }, | |
357 | { | |
358 | .port = 20, | |
359 | .pin = 2, | |
360 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
361 | PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | | |
362 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, | |
363 | }, | |
364 | { | |
365 | .port = 20, | |
366 | .pin = 3, | |
367 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
368 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, | |
369 | }, | |
370 | { | |
371 | .port = 20, | |
372 | .pin = 4, | |
373 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
374 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, | |
375 | }, | |
376 | { | |
377 | .port = 20, | |
378 | .pin = 5, | |
379 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
380 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, | |
381 | }, | |
382 | { | |
383 | .port = 20, | |
384 | .pin = 6, | |
385 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
386 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, | |
387 | }, | |
388 | { | |
389 | .port = 20, | |
390 | .pin = 7, | |
391 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
392 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, | |
393 | }, | |
394 | { | |
395 | .port = 23, | |
396 | .pin = 1, | |
397 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
398 | PIN_CFG_NOGPIO_INT | |
399 | }, | |
400 | { | |
401 | .port = 23, | |
402 | .pin = 2, | |
403 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
404 | PIN_CFG_NOGPIO_INT, | |
405 | }, | |
406 | { | |
407 | .port = 23, | |
408 | .pin = 3, | |
409 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
410 | PIN_CFG_NOGPIO_INT, | |
411 | }, | |
412 | { | |
413 | .port = 23, | |
414 | .pin = 4, | |
415 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
416 | PIN_CFG_NOGPIO_INT, | |
417 | }, | |
418 | { | |
419 | .port = 23, | |
420 | .pin = 5, | |
421 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, | |
422 | }, | |
423 | { | |
424 | .port = 24, | |
425 | .pin = 0, | |
426 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, | |
427 | }, | |
428 | { | |
429 | .port = 24, | |
430 | .pin = 1, | |
431 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
432 | PIN_CFG_NOGPIO_INT, | |
433 | }, | |
434 | { | |
435 | .port = 24, | |
436 | .pin = 2, | |
437 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
438 | PIN_CFG_NOGPIO_INT, | |
439 | }, | |
440 | { | |
441 | .port = 24, | |
442 | .pin = 3, | |
443 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
444 | PIN_CFG_NOGPIO_INT, | |
445 | }, | |
446 | { | |
447 | .port = 24, | |
448 | .pin = 4, | |
449 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
450 | PIN_CFG_NOGPIO_INT, | |
451 | }, | |
452 | { | |
453 | .port = 24, | |
454 | .pin = 5, | |
455 | .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
456 | PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | | |
457 | PIN_CFG_NOGPIO_INT, | |
458 | }, | |
459 | }; | |
460 | #endif | |
461 | ||
c4c4637e | 462 | static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, |
77e18969 | 463 | u8 pin, u8 off, u8 func) |
c4c4637e | 464 | { |
1f89aa90 | 465 | const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; |
c4c4637e LP |
466 | unsigned long flags; |
467 | u32 reg; | |
468 | ||
469 | spin_lock_irqsave(&pctrl->lock, flags); | |
470 | ||
471 | /* Set pin to 'Non-use (Hi-Z input protection)' */ | |
77e18969 | 472 | reg = readw(pctrl->base + PM(off)); |
c4c4637e | 473 | reg &= ~(PM_MASK << (pin * 2)); |
77e18969 | 474 | writew(reg, pctrl->base + PM(off)); |
c4c4637e LP |
475 | |
476 | /* Temporarily switch to GPIO mode with PMC register */ | |
77e18969 CB |
477 | reg = readb(pctrl->base + PMC(off)); |
478 | writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); | |
c4c4637e LP |
479 | |
480 | /* Set the PWPR register to allow PFC register to write */ | |
1f89aa90 CB |
481 | writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ |
482 | writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ | |
c4c4637e LP |
483 | |
484 | /* Select Pin function mode with PFC register */ | |
77e18969 | 485 | reg = readl(pctrl->base + PFC(off)); |
c4c4637e | 486 | reg &= ~(PFC_MASK << (pin * 4)); |
77e18969 | 487 | writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); |
c4c4637e LP |
488 | |
489 | /* Set the PWPR register to be write-protected */ | |
1f89aa90 CB |
490 | writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ |
491 | writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ | |
c4c4637e LP |
492 | |
493 | /* Switch to Peripheral pin function with PMC register */ | |
77e18969 CB |
494 | reg = readb(pctrl->base + PMC(off)); |
495 | writeb(reg | BIT(pin), pctrl->base + PMC(off)); | |
c4c4637e LP |
496 | |
497 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
498 | }; | |
499 | ||
500 | static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, | |
501 | unsigned int func_selector, | |
502 | unsigned int group_selector) | |
503 | { | |
504 | struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
35a3610e | 505 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; |
c4c4637e LP |
506 | struct function_desc *func; |
507 | unsigned int i, *psel_val; | |
508 | struct group_desc *group; | |
731b30f6 | 509 | const unsigned int *pins; |
c4c4637e LP |
510 | |
511 | func = pinmux_generic_get_function(pctldev, func_selector); | |
512 | if (!func) | |
513 | return -EINVAL; | |
514 | group = pinctrl_generic_get_group(pctldev, group_selector); | |
515 | if (!group) | |
516 | return -EINVAL; | |
517 | ||
518 | psel_val = func->data; | |
fc7d3b60 | 519 | pins = group->grp.pins; |
c4c4637e | 520 | |
fc7d3b60 | 521 | for (i = 0; i < group->grp.npins; i++) { |
15e4ae4f | 522 | u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; |
77e18969 CB |
523 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
524 | u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); | |
525 | ||
526 | dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", | |
35a3610e | 527 | RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); |
77e18969 | 528 | |
35a3610e | 529 | rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); |
c4c4637e LP |
530 | } |
531 | ||
532 | return 0; | |
533 | }; | |
534 | ||
535 | static int rzg2l_map_add_config(struct pinctrl_map *map, | |
536 | const char *group_or_pin, | |
537 | enum pinctrl_map_type type, | |
538 | unsigned long *configs, | |
539 | unsigned int num_configs) | |
540 | { | |
541 | unsigned long *cfgs; | |
542 | ||
543 | cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), | |
544 | GFP_KERNEL); | |
545 | if (!cfgs) | |
546 | return -ENOMEM; | |
547 | ||
548 | map->type = type; | |
549 | map->data.configs.group_or_pin = group_or_pin; | |
550 | map->data.configs.configs = cfgs; | |
551 | map->data.configs.num_configs = num_configs; | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
557 | struct device_node *np, | |
bfc374a1 | 558 | struct device_node *parent, |
c4c4637e LP |
559 | struct pinctrl_map **map, |
560 | unsigned int *num_maps, | |
561 | unsigned int *index) | |
562 | { | |
563 | struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
564 | struct pinctrl_map *maps = *map; | |
565 | unsigned int nmaps = *num_maps; | |
566 | unsigned long *configs = NULL; | |
567 | unsigned int *pins, *psel_val; | |
568 | unsigned int num_pinmux = 0; | |
569 | unsigned int idx = *index; | |
570 | unsigned int num_pins, i; | |
571 | unsigned int num_configs; | |
572 | struct property *pinmux; | |
573 | struct property *prop; | |
574 | int ret, gsel, fsel; | |
575 | const char **pin_fn; | |
bfc374a1 | 576 | const char *name; |
c4c4637e LP |
577 | const char *pin; |
578 | ||
579 | pinmux = of_find_property(np, "pinmux", NULL); | |
580 | if (pinmux) | |
581 | num_pinmux = pinmux->length / sizeof(u32); | |
582 | ||
583 | ret = of_property_count_strings(np, "pins"); | |
584 | if (ret == -EINVAL) { | |
585 | num_pins = 0; | |
586 | } else if (ret < 0) { | |
587 | dev_err(pctrl->dev, "Invalid pins list in DT\n"); | |
588 | return ret; | |
589 | } else { | |
590 | num_pins = ret; | |
591 | } | |
592 | ||
593 | if (!num_pinmux && !num_pins) | |
594 | return 0; | |
595 | ||
596 | if (num_pinmux && num_pins) { | |
597 | dev_err(pctrl->dev, | |
598 | "DT node must contain either a pinmux or pins and not both\n"); | |
599 | return -EINVAL; | |
600 | } | |
601 | ||
602 | ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); | |
603 | if (ret < 0) | |
604 | return ret; | |
605 | ||
606 | if (num_pins && !num_configs) { | |
607 | dev_err(pctrl->dev, "DT node must contain a config\n"); | |
608 | ret = -ENODEV; | |
609 | goto done; | |
610 | } | |
611 | ||
d3aaa720 | 612 | if (num_pinmux) { |
c4c4637e | 613 | nmaps += 1; |
d3aaa720 CB |
614 | if (num_configs) |
615 | nmaps += 1; | |
616 | } | |
c4c4637e LP |
617 | |
618 | if (num_pins) | |
619 | nmaps += num_pins; | |
620 | ||
621 | maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); | |
622 | if (!maps) { | |
623 | ret = -ENOMEM; | |
624 | goto done; | |
625 | } | |
626 | ||
627 | *map = maps; | |
628 | *num_maps = nmaps; | |
629 | if (num_pins) { | |
630 | of_property_for_each_string(np, "pins", prop, pin) { | |
631 | ret = rzg2l_map_add_config(&maps[idx], pin, | |
632 | PIN_MAP_TYPE_CONFIGS_PIN, | |
633 | configs, num_configs); | |
634 | if (ret < 0) | |
635 | goto done; | |
636 | ||
637 | idx++; | |
638 | } | |
639 | ret = 0; | |
640 | goto done; | |
641 | } | |
642 | ||
643 | pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); | |
644 | psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), | |
645 | GFP_KERNEL); | |
646 | pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); | |
647 | if (!pins || !psel_val || !pin_fn) { | |
648 | ret = -ENOMEM; | |
649 | goto done; | |
650 | } | |
651 | ||
652 | /* Collect pin locations and mux settings from DT properties */ | |
653 | for (i = 0; i < num_pinmux; ++i) { | |
654 | u32 value; | |
655 | ||
656 | ret = of_property_read_u32_index(np, "pinmux", i, &value); | |
657 | if (ret) | |
658 | goto done; | |
04d231b9 LP |
659 | pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); |
660 | psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); | |
c4c4637e LP |
661 | } |
662 | ||
bfc374a1 BD |
663 | if (parent) { |
664 | name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", | |
665 | parent, np); | |
666 | if (!name) { | |
667 | ret = -ENOMEM; | |
668 | goto done; | |
669 | } | |
670 | } else { | |
671 | name = np->name; | |
672 | } | |
673 | ||
bd433c25 CB |
674 | if (num_configs) { |
675 | ret = rzg2l_map_add_config(&maps[idx], name, | |
676 | PIN_MAP_TYPE_CONFIGS_GROUP, | |
677 | configs, num_configs); | |
678 | if (ret < 0) | |
679 | goto done; | |
680 | ||
681 | idx++; | |
682 | } | |
683 | ||
661efa22 BD |
684 | mutex_lock(&pctrl->mutex); |
685 | ||
c4c4637e | 686 | /* Register a single pin group listing all the pins we read from DT */ |
bfc374a1 | 687 | gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); |
c4c4637e LP |
688 | if (gsel < 0) { |
689 | ret = gsel; | |
661efa22 | 690 | goto unlock; |
c4c4637e LP |
691 | } |
692 | ||
693 | /* | |
694 | * Register a single group function where the 'data' is an array PSEL | |
695 | * register values read from DT. | |
696 | */ | |
bfc374a1 BD |
697 | pin_fn[0] = name; |
698 | fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); | |
c4c4637e LP |
699 | if (fsel < 0) { |
700 | ret = fsel; | |
701 | goto remove_group; | |
702 | } | |
703 | ||
661efa22 BD |
704 | mutex_unlock(&pctrl->mutex); |
705 | ||
c4c4637e | 706 | maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; |
bfc374a1 BD |
707 | maps[idx].data.mux.group = name; |
708 | maps[idx].data.mux.function = name; | |
c4c4637e LP |
709 | idx++; |
710 | ||
711 | dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); | |
712 | ret = 0; | |
713 | goto done; | |
714 | ||
715 | remove_group: | |
716 | pinctrl_generic_remove_group(pctldev, gsel); | |
661efa22 BD |
717 | unlock: |
718 | mutex_unlock(&pctrl->mutex); | |
c4c4637e LP |
719 | done: |
720 | *index = idx; | |
721 | kfree(configs); | |
722 | return ret; | |
723 | } | |
724 | ||
725 | static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, | |
726 | struct pinctrl_map *map, | |
727 | unsigned int num_maps) | |
728 | { | |
729 | unsigned int i; | |
730 | ||
731 | if (!map) | |
732 | return; | |
733 | ||
734 | for (i = 0; i < num_maps; ++i) { | |
735 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || | |
736 | map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
737 | kfree(map[i].data.configs.configs); | |
738 | } | |
739 | kfree(map); | |
740 | } | |
741 | ||
742 | static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, | |
743 | struct device_node *np, | |
744 | struct pinctrl_map **map, | |
745 | unsigned int *num_maps) | |
746 | { | |
747 | struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
748 | struct device_node *child; | |
749 | unsigned int index; | |
750 | int ret; | |
751 | ||
752 | *map = NULL; | |
753 | *num_maps = 0; | |
754 | index = 0; | |
755 | ||
756 | for_each_child_of_node(np, child) { | |
bfc374a1 | 757 | ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, |
c4c4637e LP |
758 | num_maps, &index); |
759 | if (ret < 0) { | |
760 | of_node_put(child); | |
761 | goto done; | |
762 | } | |
763 | } | |
764 | ||
765 | if (*num_maps == 0) { | |
bfc374a1 | 766 | ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, |
c4c4637e LP |
767 | num_maps, &index); |
768 | if (ret < 0) | |
769 | goto done; | |
770 | } | |
771 | ||
772 | if (*num_maps) | |
773 | return 0; | |
774 | ||
775 | dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); | |
776 | ret = -EINVAL; | |
777 | ||
778 | done: | |
41a87e78 | 779 | rzg2l_dt_free_map(pctldev, *map, *num_maps); |
c4c4637e LP |
780 | |
781 | return ret; | |
782 | } | |
783 | ||
7f13a429 | 784 | static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, |
15e4ae4f | 785 | u64 cfg, u32 port, u8 bit) |
7f13a429 | 786 | { |
15e4ae4f | 787 | u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); |
77e18969 | 788 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); |
15e4ae4f | 789 | u64 data; |
7f13a429 | 790 | |
15e4ae4f | 791 | if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) |
7f13a429 LP |
792 | return -EINVAL; |
793 | ||
794 | data = pctrl->data->port_pin_configs[port]; | |
77e18969 | 795 | if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) |
7f13a429 LP |
796 | return -EINVAL; |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
d1189991 LP |
801 | static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, |
802 | u8 bit, u32 mask) | |
803 | { | |
804 | void __iomem *addr = pctrl->base + offset; | |
805 | ||
806 | /* handle _L/_H for 32-bit register read/write */ | |
807 | if (bit >= 4) { | |
808 | bit -= 4; | |
809 | addr += 4; | |
810 | } | |
811 | ||
812 | return (readl(addr) >> (bit * 8)) & mask; | |
813 | } | |
814 | ||
815 | static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, | |
816 | u8 bit, u32 mask, u32 val) | |
817 | { | |
818 | void __iomem *addr = pctrl->base + offset; | |
819 | unsigned long flags; | |
820 | u32 reg; | |
821 | ||
822 | /* handle _L/_H for 32-bit register read/write */ | |
823 | if (bit >= 4) { | |
824 | bit -= 4; | |
825 | addr += 4; | |
826 | } | |
827 | ||
828 | spin_lock_irqsave(&pctrl->lock, flags); | |
829 | reg = readl(addr) & ~(mask << (bit * 8)); | |
830 | writel(reg | (val << (bit * 8)), addr); | |
831 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
832 | } | |
833 | ||
ae5b425f CB |
834 | static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) |
835 | { | |
836 | if (caps & PIN_CFG_IO_VMC_SD0) | |
837 | return SD_CH(regs->sd_ch, 0); | |
838 | if (caps & PIN_CFG_IO_VMC_SD1) | |
839 | return SD_CH(regs->sd_ch, 1); | |
51996952 CB |
840 | if (caps & PIN_CFG_IO_VMC_ETH0) |
841 | return ETH_POC(regs->eth_poc, 0); | |
842 | if (caps & PIN_CFG_IO_VMC_ETH1) | |
843 | return ETH_POC(regs->eth_poc, 1); | |
ae5b425f CB |
844 | if (caps & PIN_CFG_IO_VMC_QSPI) |
845 | return QSPI; | |
846 | ||
847 | return -EINVAL; | |
848 | } | |
849 | ||
850 | static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) | |
851 | { | |
852 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; | |
853 | const struct rzg2l_register_offsets *regs = &hwcfg->regs; | |
854 | int pwr_reg; | |
51996952 | 855 | u8 val; |
ae5b425f CB |
856 | |
857 | if (caps & PIN_CFG_SOFT_PS) | |
858 | return pctrl->settings[pin].power_source; | |
859 | ||
860 | pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); | |
861 | if (pwr_reg < 0) | |
862 | return pwr_reg; | |
863 | ||
51996952 CB |
864 | val = readb(pctrl->base + pwr_reg); |
865 | switch (val) { | |
866 | case PVDD_1800: | |
867 | return 1800; | |
868 | case PVDD_2500: | |
869 | return 2500; | |
870 | case PVDD_3300: | |
871 | return 3300; | |
872 | default: | |
873 | /* Should not happen. */ | |
874 | return -EINVAL; | |
875 | } | |
ae5b425f CB |
876 | } |
877 | ||
878 | static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) | |
879 | { | |
880 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; | |
881 | const struct rzg2l_register_offsets *regs = &hwcfg->regs; | |
882 | int pwr_reg; | |
51996952 | 883 | u8 val; |
ae5b425f CB |
884 | |
885 | if (caps & PIN_CFG_SOFT_PS) { | |
886 | pctrl->settings[pin].power_source = ps; | |
887 | return 0; | |
888 | } | |
889 | ||
51996952 CB |
890 | switch (ps) { |
891 | case 1800: | |
892 | val = PVDD_1800; | |
893 | break; | |
894 | case 2500: | |
895 | val = PVDD_2500; | |
896 | break; | |
897 | case 3300: | |
898 | val = PVDD_3300; | |
899 | break; | |
900 | default: | |
901 | return -EINVAL; | |
902 | } | |
903 | ||
ae5b425f CB |
904 | pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); |
905 | if (pwr_reg < 0) | |
906 | return pwr_reg; | |
907 | ||
51996952 | 908 | writeb(val, pctrl->base + pwr_reg); |
ae5b425f CB |
909 | pctrl->settings[pin].power_source = ps; |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
914 | static bool rzg2l_ps_is_supported(u16 ps) | |
915 | { | |
916 | unsigned int i; | |
917 | ||
918 | for (i = 0; i < ARRAY_SIZE(available_ps); i++) { | |
919 | if (available_ps[i] == ps) | |
920 | return true; | |
921 | } | |
922 | ||
923 | return false; | |
924 | } | |
925 | ||
926 | static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) | |
927 | { | |
928 | unsigned int i; | |
929 | ||
930 | for (i = 0; i < ARRAY_SIZE(available_ps); i++) { | |
931 | if (available_ps[i] == ps) | |
932 | break; | |
933 | } | |
934 | ||
935 | /* | |
936 | * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have | |
937 | * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source | |
938 | */ | |
939 | return i * RZG2L_IOLH_MAX_DS_ENTRIES; | |
940 | } | |
941 | ||
942 | static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) | |
943 | { | |
944 | if (caps & PIN_CFG_IOLH_A) | |
945 | return hwcfg->iolh_groupa_ua[val]; | |
946 | ||
947 | if (caps & PIN_CFG_IOLH_B) | |
948 | return hwcfg->iolh_groupb_ua[val]; | |
949 | ||
950 | if (caps & PIN_CFG_IOLH_C) | |
951 | return hwcfg->iolh_groupc_ua[val]; | |
952 | ||
953 | /* Should not happen. */ | |
954 | return 0; | |
955 | } | |
956 | ||
957 | static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, | |
958 | enum rzg2l_iolh_index ps_index, u16 ua) | |
959 | { | |
960 | const u16 *array = NULL; | |
961 | unsigned int i; | |
962 | ||
963 | if (caps & PIN_CFG_IOLH_A) | |
964 | array = &hwcfg->iolh_groupa_ua[ps_index]; | |
965 | ||
966 | if (caps & PIN_CFG_IOLH_B) | |
967 | array = &hwcfg->iolh_groupb_ua[ps_index]; | |
968 | ||
969 | if (caps & PIN_CFG_IOLH_C) | |
970 | array = &hwcfg->iolh_groupc_ua[ps_index]; | |
971 | ||
972 | if (!array) | |
973 | return -EINVAL; | |
974 | ||
975 | for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { | |
976 | if (array[i] == ua) | |
977 | return i; | |
978 | } | |
979 | ||
980 | return -EINVAL; | |
981 | } | |
982 | ||
983 | static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, | |
984 | enum rzg2l_iolh_index iolh_idx, | |
985 | u16 ds) | |
986 | { | |
987 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; | |
988 | const u16 *array = NULL; | |
989 | unsigned int i; | |
990 | ||
991 | if (caps & PIN_CFG_IOLH_A) | |
992 | array = hwcfg->iolh_groupa_ua; | |
993 | ||
994 | if (caps & PIN_CFG_IOLH_B) | |
995 | array = hwcfg->iolh_groupb_ua; | |
996 | ||
997 | if (caps & PIN_CFG_IOLH_C) | |
998 | array = hwcfg->iolh_groupc_ua; | |
999 | ||
1000 | /* Should not happen. */ | |
1001 | if (!array) | |
1002 | return false; | |
1003 | ||
1004 | if (!array[iolh_idx]) | |
1005 | return false; | |
1006 | ||
1007 | for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { | |
1008 | if (array[iolh_idx + i] == ds) | |
1009 | return true; | |
1010 | } | |
1011 | ||
1012 | return false; | |
1013 | } | |
1014 | ||
1bbc8ee4 CB |
1015 | static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin) |
1016 | { | |
1017 | if (!(caps & PIN_CFG_OEN)) | |
1018 | return false; | |
1019 | ||
1020 | if (pin > max_pin) | |
1021 | return false; | |
1022 | ||
1023 | return true; | |
1024 | } | |
1025 | ||
1026 | static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) | |
1027 | { | |
1028 | if (pin) | |
1029 | pin *= 2; | |
1030 | ||
1031 | if (offset / RZG2L_PINS_PER_PORT == max_port) | |
1032 | pin += 1; | |
1033 | ||
1034 | return pin; | |
1035 | } | |
1036 | ||
1037 | static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) | |
1038 | { | |
1039 | u8 max_port = pctrl->data->hwcfg->oen_max_port; | |
1040 | u8 max_pin = pctrl->data->hwcfg->oen_max_pin; | |
1041 | u8 bit; | |
1042 | ||
1043 | if (!rzg2l_oen_is_supported(caps, pin, max_pin)) | |
1044 | return 0; | |
1045 | ||
1046 | bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); | |
1047 | ||
1048 | return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); | |
1049 | } | |
1050 | ||
1051 | static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) | |
1052 | { | |
1053 | u8 max_port = pctrl->data->hwcfg->oen_max_port; | |
1054 | u8 max_pin = pctrl->data->hwcfg->oen_max_pin; | |
1055 | unsigned long flags; | |
1056 | u8 val, bit; | |
1057 | ||
1058 | if (!rzg2l_oen_is_supported(caps, pin, max_pin)) | |
1059 | return -EINVAL; | |
1060 | ||
1061 | bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); | |
1062 | ||
1063 | spin_lock_irqsave(&pctrl->lock, flags); | |
1064 | val = readb(pctrl->base + ETH_MODE); | |
1065 | if (oen) | |
1066 | val &= ~BIT(bit); | |
1067 | else | |
1068 | val |= BIT(bit); | |
1069 | writeb(val, pctrl->base + ETH_MODE); | |
1070 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
c4c4637e LP |
1075 | static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, |
1076 | unsigned int _pin, | |
1077 | unsigned long *config) | |
1078 | { | |
1079 | struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
1080 | enum pin_config_param param = pinconf_to_config_param(*config); | |
1f89aa90 | 1081 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; |
c4c4637e | 1082 | const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; |
15e4ae4f | 1083 | u64 *pin_data = pin->drv_data; |
c4c4637e | 1084 | unsigned int arg = 0; |
77e18969 | 1085 | u32 off, cfg; |
ae5b425f | 1086 | int ret; |
77e18969 | 1087 | u8 bit; |
c4c4637e LP |
1088 | |
1089 | if (!pin_data) | |
1090 | return -EINVAL; | |
1091 | ||
77e18969 | 1092 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
04d231b9 | 1093 | cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); |
c4c4637e | 1094 | if (*pin_data & RZG2L_SINGLE_PIN) { |
04d231b9 | 1095 | bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); |
7f13a429 | 1096 | } else { |
7f13a429 LP |
1097 | bit = RZG2L_PIN_ID_TO_PIN(_pin); |
1098 | ||
1099 | if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) | |
1100 | return -EINVAL; | |
c4c4637e LP |
1101 | } |
1102 | ||
1103 | switch (param) { | |
1104 | case PIN_CONFIG_INPUT_ENABLE: | |
1105 | if (!(cfg & PIN_CFG_IEN)) | |
1106 | return -EINVAL; | |
77e18969 | 1107 | arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); |
5223c511 LP |
1108 | if (!arg) |
1109 | return -EINVAL; | |
c4c4637e LP |
1110 | break; |
1111 | ||
1bbc8ee4 CB |
1112 | case PIN_CONFIG_OUTPUT_ENABLE: |
1113 | arg = rzg2l_read_oen(pctrl, cfg, _pin, bit); | |
1114 | if (!arg) | |
1115 | return -EINVAL; | |
1116 | break; | |
1117 | ||
ae5b425f CB |
1118 | case PIN_CONFIG_POWER_SOURCE: |
1119 | ret = rzg2l_get_power_source(pctrl, _pin, cfg); | |
1120 | if (ret < 0) | |
1121 | return ret; | |
1122 | arg = ret; | |
c4c4637e | 1123 | break; |
c4c4637e | 1124 | |
adb613f8 LP |
1125 | case PIN_CONFIG_DRIVE_STRENGTH: { |
1126 | unsigned int index; | |
1127 | ||
ae5b425f | 1128 | if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) |
adb613f8 LP |
1129 | return -EINVAL; |
1130 | ||
77e18969 | 1131 | index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); |
ae5b425f CB |
1132 | /* |
1133 | * Drive strenght mA is supported only by group A and only | |
1134 | * for 3V3 port source. | |
1135 | */ | |
cca38201 | 1136 | arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; |
adb613f8 LP |
1137 | break; |
1138 | } | |
1139 | ||
ae5b425f CB |
1140 | case PIN_CONFIG_DRIVE_STRENGTH_UA: { |
1141 | enum rzg2l_iolh_index iolh_idx; | |
1142 | u8 val; | |
1143 | ||
1144 | if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || | |
1145 | !hwcfg->drive_strength_ua) | |
1146 | return -EINVAL; | |
1147 | ||
1148 | ret = rzg2l_get_power_source(pctrl, _pin, cfg); | |
1149 | if (ret < 0) | |
1150 | return ret; | |
1151 | iolh_idx = rzg2l_ps_to_iolh_idx(ret); | |
1152 | val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); | |
1153 | arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); | |
1154 | break; | |
1155 | } | |
1156 | ||
adb613f8 LP |
1157 | case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { |
1158 | unsigned int index; | |
1159 | ||
ae5b425f | 1160 | if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) |
adb613f8 LP |
1161 | return -EINVAL; |
1162 | ||
77e18969 | 1163 | index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); |
cca38201 | 1164 | arg = hwcfg->iolh_groupb_oi[index]; |
adb613f8 LP |
1165 | break; |
1166 | } | |
1167 | ||
c4c4637e LP |
1168 | default: |
1169 | return -ENOTSUPP; | |
1170 | } | |
1171 | ||
1172 | *config = pinconf_to_config_packed(param, arg); | |
1173 | ||
1174 | return 0; | |
1175 | }; | |
1176 | ||
1177 | static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, | |
1178 | unsigned int _pin, | |
1179 | unsigned long *_configs, | |
1180 | unsigned int num_configs) | |
1181 | { | |
1182 | struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
1183 | const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; | |
1f89aa90 | 1184 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; |
ae5b425f | 1185 | struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; |
15e4ae4f | 1186 | u64 *pin_data = pin->drv_data; |
c4c4637e | 1187 | enum pin_config_param param; |
906b545b | 1188 | unsigned int i, arg, index; |
77e18969 | 1189 | u32 cfg, off; |
ae5b425f | 1190 | int ret; |
77e18969 | 1191 | u8 bit; |
c4c4637e LP |
1192 | |
1193 | if (!pin_data) | |
1194 | return -EINVAL; | |
1195 | ||
77e18969 | 1196 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
04d231b9 | 1197 | cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); |
c4c4637e | 1198 | if (*pin_data & RZG2L_SINGLE_PIN) { |
04d231b9 | 1199 | bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); |
7f13a429 | 1200 | } else { |
7f13a429 LP |
1201 | bit = RZG2L_PIN_ID_TO_PIN(_pin); |
1202 | ||
1203 | if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) | |
1204 | return -EINVAL; | |
c4c4637e LP |
1205 | } |
1206 | ||
1207 | for (i = 0; i < num_configs; i++) { | |
1208 | param = pinconf_to_config_param(_configs[i]); | |
1209 | switch (param) { | |
906b545b CB |
1210 | case PIN_CONFIG_INPUT_ENABLE: |
1211 | arg = pinconf_to_config_argument(_configs[i]); | |
c4c4637e LP |
1212 | |
1213 | if (!(cfg & PIN_CFG_IEN)) | |
1214 | return -EINVAL; | |
1215 | ||
77e18969 | 1216 | rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); |
c4c4637e | 1217 | break; |
c4c4637e | 1218 | |
1bbc8ee4 CB |
1219 | case PIN_CONFIG_OUTPUT_ENABLE: |
1220 | arg = pinconf_to_config_argument(_configs[i]); | |
1221 | ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg); | |
1222 | if (ret) | |
1223 | return ret; | |
1224 | break; | |
c4c4637e | 1225 | |
ae5b425f CB |
1226 | case PIN_CONFIG_POWER_SOURCE: |
1227 | settings.power_source = pinconf_to_config_argument(_configs[i]); | |
c4c4637e | 1228 | break; |
adb613f8 | 1229 | |
906b545b CB |
1230 | case PIN_CONFIG_DRIVE_STRENGTH: |
1231 | arg = pinconf_to_config_argument(_configs[i]); | |
adb613f8 | 1232 | |
ae5b425f | 1233 | if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) |
adb613f8 LP |
1234 | return -EINVAL; |
1235 | ||
cca38201 CB |
1236 | for (index = RZG2L_IOLH_IDX_3V3; |
1237 | index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { | |
1238 | if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) | |
adb613f8 LP |
1239 | break; |
1240 | } | |
cca38201 | 1241 | if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) |
adb613f8 LP |
1242 | return -EINVAL; |
1243 | ||
77e18969 | 1244 | rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); |
adb613f8 | 1245 | break; |
adb613f8 | 1246 | |
ae5b425f CB |
1247 | case PIN_CONFIG_DRIVE_STRENGTH_UA: |
1248 | if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || | |
1249 | !hwcfg->drive_strength_ua) | |
1250 | return -EINVAL; | |
1251 | ||
1252 | settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); | |
1253 | break; | |
1254 | ||
906b545b CB |
1255 | case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: |
1256 | arg = pinconf_to_config_argument(_configs[i]); | |
adb613f8 | 1257 | |
ae5b425f | 1258 | if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) |
adb613f8 LP |
1259 | return -EINVAL; |
1260 | ||
cca38201 CB |
1261 | for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { |
1262 | if (arg == hwcfg->iolh_groupb_oi[index]) | |
adb613f8 LP |
1263 | break; |
1264 | } | |
cca38201 | 1265 | if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) |
adb613f8 LP |
1266 | return -EINVAL; |
1267 | ||
77e18969 | 1268 | rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); |
adb613f8 | 1269 | break; |
adb613f8 | 1270 | |
c4c4637e LP |
1271 | default: |
1272 | return -EOPNOTSUPP; | |
1273 | } | |
1274 | } | |
1275 | ||
ae5b425f CB |
1276 | /* Apply power source. */ |
1277 | if (settings.power_source != pctrl->settings[_pin].power_source) { | |
1278 | ret = rzg2l_ps_is_supported(settings.power_source); | |
1279 | if (!ret) | |
1280 | return -EINVAL; | |
1281 | ||
1282 | /* Apply power source. */ | |
1283 | ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); | |
1284 | if (ret) | |
1285 | return ret; | |
1286 | } | |
1287 | ||
1288 | /* Apply drive strength. */ | |
1289 | if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { | |
1290 | enum rzg2l_iolh_index iolh_idx; | |
1291 | int val; | |
1292 | ||
1293 | iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); | |
1294 | ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, | |
1295 | settings.drive_strength_ua); | |
1296 | if (!ret) | |
1297 | return -EINVAL; | |
1298 | ||
1299 | /* Get register value for this PS/DS tuple. */ | |
1300 | val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); | |
1301 | if (val < 0) | |
1302 | return val; | |
1303 | ||
1304 | /* Apply drive strength. */ | |
1305 | rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); | |
1306 | pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; | |
1307 | } | |
1308 | ||
c4c4637e LP |
1309 | return 0; |
1310 | } | |
1311 | ||
1312 | static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, | |
1313 | unsigned int group, | |
1314 | unsigned long *configs, | |
1315 | unsigned int num_configs) | |
1316 | { | |
1317 | const unsigned int *pins; | |
1318 | unsigned int i, npins; | |
1319 | int ret; | |
1320 | ||
1321 | ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); | |
1322 | if (ret) | |
1323 | return ret; | |
1324 | ||
1325 | for (i = 0; i < npins; i++) { | |
1326 | ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, | |
1327 | num_configs); | |
1328 | if (ret) | |
1329 | return ret; | |
1330 | } | |
1331 | ||
1332 | return 0; | |
1333 | }; | |
1334 | ||
1335 | static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, | |
1336 | unsigned int group, | |
1337 | unsigned long *config) | |
1338 | { | |
1339 | const unsigned int *pins; | |
1340 | unsigned int i, npins, prev_config = 0; | |
1341 | int ret; | |
1342 | ||
1343 | ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); | |
1344 | if (ret) | |
1345 | return ret; | |
1346 | ||
1347 | for (i = 0; i < npins; i++) { | |
1348 | ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); | |
1349 | if (ret) | |
1350 | return ret; | |
1351 | ||
1352 | /* Check config matching between to pin */ | |
1353 | if (i && prev_config != *config) | |
1354 | return -EOPNOTSUPP; | |
1355 | ||
1356 | prev_config = *config; | |
1357 | } | |
1358 | ||
1359 | return 0; | |
1360 | }; | |
1361 | ||
1362 | static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { | |
1363 | .get_groups_count = pinctrl_generic_get_group_count, | |
1364 | .get_group_name = pinctrl_generic_get_group_name, | |
1365 | .get_group_pins = pinctrl_generic_get_group_pins, | |
1366 | .dt_node_to_map = rzg2l_dt_node_to_map, | |
1367 | .dt_free_map = rzg2l_dt_free_map, | |
1368 | }; | |
1369 | ||
1370 | static const struct pinmux_ops rzg2l_pinctrl_pmxops = { | |
1371 | .get_functions_count = pinmux_generic_get_function_count, | |
1372 | .get_function_name = pinmux_generic_get_function_name, | |
1373 | .get_function_groups = pinmux_generic_get_function_groups, | |
1374 | .set_mux = rzg2l_pinctrl_set_mux, | |
1375 | .strict = true, | |
1376 | }; | |
1377 | ||
1378 | static const struct pinconf_ops rzg2l_pinctrl_confops = { | |
1379 | .is_generic = true, | |
1380 | .pin_config_get = rzg2l_pinctrl_pinconf_get, | |
1381 | .pin_config_set = rzg2l_pinctrl_pinconf_set, | |
1382 | .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, | |
1383 | .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, | |
1384 | .pin_config_config_dbg_show = pinconf_generic_dump_config, | |
1385 | }; | |
1386 | ||
1387 | static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) | |
1388 | { | |
1389 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); | |
c944d9de | 1390 | const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; |
15e4ae4f | 1391 | u64 *pin_data = pin_desc->drv_data; |
77e18969 | 1392 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
c4c4637e LP |
1393 | u32 port = RZG2L_PIN_ID_TO_PORT(offset); |
1394 | u8 bit = RZG2L_PIN_ID_TO_PIN(offset); | |
1395 | unsigned long flags; | |
1396 | u8 reg8; | |
1397 | int ret; | |
1398 | ||
c944d9de LP |
1399 | ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); |
1400 | if (ret) | |
1401 | return ret; | |
1402 | ||
acb38be6 | 1403 | ret = pinctrl_gpio_request(chip, offset); |
c4c4637e LP |
1404 | if (ret) |
1405 | return ret; | |
1406 | ||
1407 | spin_lock_irqsave(&pctrl->lock, flags); | |
1408 | ||
1409 | /* Select GPIO mode in PMC Register */ | |
77e18969 | 1410 | reg8 = readb(pctrl->base + PMC(off)); |
c4c4637e | 1411 | reg8 &= ~BIT(bit); |
77e18969 | 1412 | writeb(reg8, pctrl->base + PMC(off)); |
c4c4637e LP |
1413 | |
1414 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
77e18969 CB |
1419 | static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, |
1420 | bool output) | |
c4c4637e | 1421 | { |
77e18969 | 1422 | const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; |
15e4ae4f | 1423 | u64 *pin_data = pin_desc->drv_data; |
77e18969 CB |
1424 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
1425 | u8 bit = RZG2L_PIN_ID_TO_PIN(offset); | |
c4c4637e LP |
1426 | unsigned long flags; |
1427 | u16 reg16; | |
1428 | ||
1429 | spin_lock_irqsave(&pctrl->lock, flags); | |
1430 | ||
77e18969 | 1431 | reg16 = readw(pctrl->base + PM(off)); |
c4c4637e LP |
1432 | reg16 &= ~(PM_MASK << (bit * 2)); |
1433 | ||
1434 | reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); | |
77e18969 | 1435 | writew(reg16, pctrl->base + PM(off)); |
c4c4637e LP |
1436 | |
1437 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
1438 | } | |
1439 | ||
1440 | static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) | |
1441 | { | |
1442 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); | |
77e18969 | 1443 | const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; |
15e4ae4f | 1444 | u64 *pin_data = pin_desc->drv_data; |
77e18969 | 1445 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
c4c4637e LP |
1446 | u8 bit = RZG2L_PIN_ID_TO_PIN(offset); |
1447 | ||
77e18969 | 1448 | if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { |
c4c4637e LP |
1449 | u16 reg16; |
1450 | ||
77e18969 | 1451 | reg16 = readw(pctrl->base + PM(off)); |
c4c4637e LP |
1452 | reg16 = (reg16 >> (bit * 2)) & PM_MASK; |
1453 | if (reg16 == PM_OUTPUT) | |
1454 | return GPIO_LINE_DIRECTION_OUT; | |
1455 | } | |
1456 | ||
1457 | return GPIO_LINE_DIRECTION_IN; | |
1458 | } | |
1459 | ||
1460 | static int rzg2l_gpio_direction_input(struct gpio_chip *chip, | |
1461 | unsigned int offset) | |
1462 | { | |
1463 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); | |
c4c4637e | 1464 | |
77e18969 | 1465 | rzg2l_gpio_set_direction(pctrl, offset, false); |
c4c4637e LP |
1466 | |
1467 | return 0; | |
1468 | } | |
1469 | ||
1470 | static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
1471 | int value) | |
1472 | { | |
1473 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); | |
77e18969 | 1474 | const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; |
15e4ae4f | 1475 | u64 *pin_data = pin_desc->drv_data; |
77e18969 | 1476 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
c4c4637e LP |
1477 | u8 bit = RZG2L_PIN_ID_TO_PIN(offset); |
1478 | unsigned long flags; | |
1479 | u8 reg8; | |
1480 | ||
1481 | spin_lock_irqsave(&pctrl->lock, flags); | |
1482 | ||
77e18969 | 1483 | reg8 = readb(pctrl->base + P(off)); |
c4c4637e LP |
1484 | |
1485 | if (value) | |
77e18969 | 1486 | writeb(reg8 | BIT(bit), pctrl->base + P(off)); |
c4c4637e | 1487 | else |
77e18969 | 1488 | writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); |
c4c4637e LP |
1489 | |
1490 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
1491 | } | |
1492 | ||
1493 | static int rzg2l_gpio_direction_output(struct gpio_chip *chip, | |
1494 | unsigned int offset, int value) | |
1495 | { | |
1496 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); | |
c4c4637e LP |
1497 | |
1498 | rzg2l_gpio_set(chip, offset, value); | |
77e18969 | 1499 | rzg2l_gpio_set_direction(pctrl, offset, true); |
c4c4637e LP |
1500 | |
1501 | return 0; | |
1502 | } | |
1503 | ||
1504 | static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
1505 | { | |
1506 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); | |
77e18969 | 1507 | const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; |
15e4ae4f | 1508 | u64 *pin_data = pin_desc->drv_data; |
77e18969 | 1509 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
c4c4637e LP |
1510 | u8 bit = RZG2L_PIN_ID_TO_PIN(offset); |
1511 | u16 reg16; | |
1512 | ||
77e18969 | 1513 | reg16 = readw(pctrl->base + PM(off)); |
c4c4637e LP |
1514 | reg16 = (reg16 >> (bit * 2)) & PM_MASK; |
1515 | ||
1516 | if (reg16 == PM_INPUT) | |
77e18969 | 1517 | return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); |
c4c4637e | 1518 | else if (reg16 == PM_OUTPUT) |
77e18969 | 1519 | return !!(readb(pctrl->base + P(off)) & BIT(bit)); |
c4c4637e LP |
1520 | else |
1521 | return -EINVAL; | |
1522 | } | |
1523 | ||
1524 | static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) | |
1525 | { | |
db2e5f21 LP |
1526 | unsigned int virq; |
1527 | ||
4fccb263 | 1528 | pinctrl_gpio_free(chip, offset); |
c4c4637e | 1529 | |
db2e5f21 LP |
1530 | virq = irq_find_mapping(chip->irq.domain, offset); |
1531 | if (virq) | |
1532 | irq_dispose_mapping(virq); | |
1533 | ||
c4c4637e LP |
1534 | /* |
1535 | * Set the GPIO as an input to ensure that the next GPIO request won't | |
1536 | * drive the GPIO pin as an output. | |
1537 | */ | |
1538 | rzg2l_gpio_direction_input(chip, offset); | |
1539 | } | |
1540 | ||
1541 | static const char * const rzg2l_gpio_names[] = { | |
1542 | "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", | |
1543 | "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", | |
1544 | "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", | |
1545 | "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", | |
1546 | "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", | |
1547 | "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", | |
1548 | "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", | |
1549 | "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", | |
1550 | "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", | |
1551 | "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", | |
1552 | "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", | |
1553 | "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", | |
1554 | "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", | |
1555 | "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", | |
1556 | "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", | |
1557 | "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", | |
1558 | "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", | |
1559 | "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", | |
1560 | "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", | |
1561 | "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", | |
1562 | "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", | |
1563 | "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", | |
1564 | "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", | |
1565 | "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", | |
1566 | "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", | |
1567 | "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", | |
1568 | "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", | |
1569 | "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", | |
1570 | "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", | |
1571 | "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", | |
1572 | "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", | |
1573 | "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", | |
1574 | "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", | |
1575 | "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", | |
1576 | "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", | |
1577 | "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", | |
1578 | "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", | |
1579 | "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", | |
1580 | "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", | |
1581 | "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", | |
1582 | "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", | |
1583 | "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", | |
1584 | "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", | |
1585 | "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", | |
1586 | "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", | |
1587 | "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", | |
1588 | "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", | |
1589 | "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", | |
1590 | "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", | |
1591 | }; | |
1592 | ||
15e4ae4f | 1593 | static const u64 r9a07g044_gpio_configs[] = { |
c4c4637e LP |
1594 | RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), |
1595 | RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), | |
1596 | RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), | |
1597 | RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), | |
1598 | RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), | |
1599 | RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), | |
1600 | RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), | |
1601 | RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), | |
1602 | RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), | |
1603 | RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), | |
1604 | RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), | |
1605 | RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), | |
1606 | RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), | |
1607 | RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), | |
1608 | RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), | |
1609 | RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), | |
1610 | RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), | |
fcfb6314 | 1611 | RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), |
c4c4637e LP |
1612 | RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), |
1613 | RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), | |
22972a2d LP |
1614 | RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), |
1615 | RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1616 | RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1617 | RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1618 | RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1619 | RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1620 | RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1621 | RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1622 | RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1623 | RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1624 | RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1625 | RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1626 | RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1627 | RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1628 | RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1629 | RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1630 | RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1631 | RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
c4c4637e LP |
1632 | RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), |
1633 | RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), | |
1634 | RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), | |
1635 | RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), | |
1636 | RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), | |
1637 | RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), | |
1638 | RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), | |
1639 | RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), | |
1640 | RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), | |
1641 | RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), | |
1642 | RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), | |
1643 | }; | |
1644 | ||
15e4ae4f | 1645 | static const u64 r9a07g043_gpio_configs[] = { |
bfc69bdb BD |
1646 | RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), |
1647 | RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1648 | RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1649 | RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1650 | RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), | |
1651 | RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), | |
1652 | RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), | |
1653 | RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1654 | RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1655 | RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1656 | RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), | |
1657 | RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), | |
1658 | RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), | |
1659 | RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), | |
1660 | RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), | |
1661 | RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), | |
1662 | RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), | |
1663 | RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), | |
1664 | RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), | |
fea58424 LP |
1665 | #ifdef CONFIG_RISCV |
1666 | /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ | |
1667 | RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
1668 | PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | | |
1669 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ | |
1670 | RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */ | |
1671 | RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
1672 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ | |
1673 | RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | | |
1674 | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ | |
1675 | RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */ | |
1676 | RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */ | |
1677 | RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF | | |
1678 | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | | |
1679 | PIN_CFG_NOGPIO_INT), /* P25 */ | |
1680 | 0x0, /* P26 */ | |
1681 | 0x0, /* P27 */ | |
1682 | RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ | |
1683 | #endif | |
bfc69bdb BD |
1684 | }; |
1685 | ||
15e4ae4f | 1686 | static const u64 r9a08g045_gpio_configs[] = { |
c6a088e5 CB |
1687 | RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ |
1688 | RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | | |
1bbc8ee4 | 1689 | PIN_CFG_IO_VMC_ETH0)) | |
9e5889c6 | 1690 | PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ |
c6a088e5 CB |
1691 | RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | |
1692 | PIN_CFG_IO_VMC_ETH0)), /* P2 */ | |
1693 | RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | | |
1694 | PIN_CFG_IO_VMC_ETH0)), /* P3 */ | |
1695 | RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | | |
1696 | PIN_CFG_IO_VMC_ETH0)), /* P4 */ | |
1697 | RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ | |
1698 | RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ | |
1699 | RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | | |
1bbc8ee4 | 1700 | PIN_CFG_IO_VMC_ETH1)) | |
9e5889c6 | 1701 | PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ |
c6a088e5 CB |
1702 | RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | |
1703 | PIN_CFG_IO_VMC_ETH1)), /* P8 */ | |
1704 | RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | | |
1705 | PIN_CFG_IO_VMC_ETH1)), /* P9 */ | |
1706 | RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | | |
1707 | PIN_CFG_IO_VMC_ETH1)), /* P10 */ | |
1708 | RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ | |
1709 | RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ | |
1710 | RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ | |
1711 | RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ | |
1712 | RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ | |
1713 | RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ | |
1714 | RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ | |
1715 | RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ | |
1716 | }; | |
1717 | ||
84c580e9 | 1718 | static const struct { |
bfc69bdb BD |
1719 | struct rzg2l_dedicated_configs common[35]; |
1720 | struct rzg2l_dedicated_configs rzg2l_pins[7]; | |
1721 | } rzg2l_dedicated_pins = { | |
1722 | .common = { | |
1723 | { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, | |
1724 | (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, | |
1725 | { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, | |
f7bc5f52 | 1726 | (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, |
bfc69bdb BD |
1727 | { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, |
1728 | (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, | |
1729 | { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, | |
1730 | { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, | |
1731 | { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, | |
1732 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, | |
1733 | { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, | |
1734 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1735 | { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, | |
1736 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, | |
1737 | { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, | |
1738 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1739 | { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, | |
1740 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1741 | { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, | |
1742 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1743 | { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, | |
1744 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1745 | { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, | |
1746 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1747 | { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, | |
1748 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1749 | { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, | |
1750 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1751 | { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, | |
1752 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, | |
1753 | { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, | |
1754 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, | |
1755 | { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, | |
1756 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, | |
1757 | { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, | |
1758 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, | |
1759 | { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, | |
1760 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, | |
1761 | { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, | |
1762 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, | |
1763 | { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, | |
1764 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, | |
1765 | { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, | |
1766 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1767 | { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, | |
1768 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1769 | { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, | |
1770 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1771 | { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, | |
1772 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1773 | { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, | |
1774 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1775 | { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, | |
1776 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1777 | { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, | |
1778 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1779 | { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, | |
1780 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1781 | { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, | |
1782 | { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, | |
1783 | { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, | |
1784 | { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, | |
1785 | { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, | |
1786 | }, | |
1787 | .rzg2l_pins = { | |
1788 | { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1789 | { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, | |
1790 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1791 | { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, | |
1792 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1793 | { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, | |
1794 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1795 | { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, | |
1796 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1797 | { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, | |
1798 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1799 | { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, | |
1800 | (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, | |
1801 | } | |
c4c4637e LP |
1802 | }; |
1803 | ||
c6a088e5 CB |
1804 | static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { |
1805 | { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | | |
1806 | PIN_CFG_FILCLKSEL)) }, | |
1807 | { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | | |
1808 | PIN_CFG_SOFT_PS)) }, | |
1809 | { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, | |
1810 | { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, | |
1811 | { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, | |
1812 | { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1813 | PIN_CFG_IO_VMC_SD0)) }, | |
1814 | { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, | |
1815 | { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1816 | PIN_CFG_IO_VMC_SD0)) }, | |
1817 | { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1818 | PIN_CFG_IO_VMC_SD0)) }, | |
1819 | { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1820 | PIN_CFG_IO_VMC_SD0)) }, | |
1821 | { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1822 | PIN_CFG_IO_VMC_SD0)) }, | |
1823 | { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1824 | PIN_CFG_IO_VMC_SD0)) }, | |
1825 | { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1826 | PIN_CFG_IO_VMC_SD0)) }, | |
1827 | { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1828 | PIN_CFG_IO_VMC_SD0)) }, | |
1829 | { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1830 | PIN_CFG_IO_VMC_SD0)) }, | |
1831 | { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, | |
1832 | { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1833 | PIN_CFG_IO_VMC_SD1)) }, | |
1834 | { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1835 | PIN_CFG_IO_VMC_SD1)) }, | |
1836 | { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1837 | PIN_CFG_IO_VMC_SD1)) }, | |
1838 | { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1839 | PIN_CFG_IO_VMC_SD1)) }, | |
1840 | { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | | |
1841 | PIN_CFG_IO_VMC_SD1)) }, | |
1842 | }; | |
1843 | ||
fea58424 | 1844 | static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) |
db2e5f21 | 1845 | { |
fea58424 LP |
1846 | const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; |
1847 | const struct rzg2l_pinctrl_data *data = pctrl->data; | |
1848 | u64 *pin_data = pin_desc->drv_data; | |
db2e5f21 LP |
1849 | unsigned int gpioint; |
1850 | unsigned int i; | |
1851 | u32 port, bit; | |
1852 | ||
fea58424 LP |
1853 | if (*pin_data & PIN_CFG_NOGPIO_INT) |
1854 | return -EINVAL; | |
1855 | ||
db2e5f21 LP |
1856 | port = virq / 8; |
1857 | bit = virq % 8; | |
1858 | ||
00dfe298 | 1859 | if (port >= data->n_ports || |
15e4ae4f | 1860 | bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) |
db2e5f21 LP |
1861 | return -EINVAL; |
1862 | ||
1863 | gpioint = bit; | |
1864 | for (i = 0; i < port; i++) | |
15e4ae4f | 1865 | gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); |
db2e5f21 LP |
1866 | |
1867 | return gpioint; | |
1868 | } | |
1869 | ||
d3c49299 BD |
1870 | static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, |
1871 | unsigned int hwirq, bool enable) | |
db2e5f21 | 1872 | { |
77e18969 | 1873 | const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; |
15e4ae4f | 1874 | u64 *pin_data = pin_desc->drv_data; |
77e18969 CB |
1875 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); |
1876 | u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); | |
db2e5f21 LP |
1877 | unsigned long flags; |
1878 | void __iomem *addr; | |
db2e5f21 | 1879 | |
77e18969 | 1880 | addr = pctrl->base + ISEL(off); |
db2e5f21 LP |
1881 | if (bit >= 4) { |
1882 | bit -= 4; | |
1883 | addr += 4; | |
1884 | } | |
1885 | ||
1886 | spin_lock_irqsave(&pctrl->lock, flags); | |
d3c49299 BD |
1887 | if (enable) |
1888 | writel(readl(addr) | BIT(bit * 8), addr); | |
1889 | else | |
1890 | writel(readl(addr) & ~BIT(bit * 8), addr); | |
db2e5f21 | 1891 | spin_unlock_irqrestore(&pctrl->lock, flags); |
d3c49299 | 1892 | } |
db2e5f21 | 1893 | |
d3c49299 BD |
1894 | static void rzg2l_gpio_irq_disable(struct irq_data *d) |
1895 | { | |
1896 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
d3c49299 BD |
1897 | unsigned int hwirq = irqd_to_hwirq(d); |
1898 | ||
1899 | irq_chip_disable_parent(d); | |
db2e5f21 | 1900 | gpiochip_disable_irq(gc, hwirq); |
db2e5f21 LP |
1901 | } |
1902 | ||
1903 | static void rzg2l_gpio_irq_enable(struct irq_data *d) | |
1904 | { | |
1905 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
db2e5f21 | 1906 | unsigned int hwirq = irqd_to_hwirq(d); |
db2e5f21 LP |
1907 | |
1908 | gpiochip_enable_irq(gc, hwirq); | |
db2e5f21 LP |
1909 | irq_chip_enable_parent(d); |
1910 | } | |
1911 | ||
1912 | static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
1913 | { | |
1914 | return irq_chip_set_type_parent(d, type); | |
1915 | } | |
1916 | ||
1917 | static void rzg2l_gpio_irqc_eoi(struct irq_data *d) | |
1918 | { | |
1919 | irq_chip_eoi_parent(d); | |
1920 | } | |
1921 | ||
1922 | static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) | |
1923 | { | |
1924 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); | |
1925 | ||
1926 | seq_printf(p, dev_name(gc->parent)); | |
1927 | } | |
1928 | ||
254203f9 CB |
1929 | static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) |
1930 | { | |
1931 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); | |
1932 | struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); | |
1933 | int ret; | |
1934 | ||
1935 | /* It should not happen. */ | |
1936 | if (!data->parent_data) | |
1937 | return -EOPNOTSUPP; | |
1938 | ||
1939 | ret = irq_chip_set_wake_parent(data, on); | |
1940 | if (ret) | |
1941 | return ret; | |
1942 | ||
1943 | if (on) | |
1944 | atomic_inc(&pctrl->wakeup_path); | |
1945 | else | |
1946 | atomic_dec(&pctrl->wakeup_path); | |
1947 | ||
1948 | return 0; | |
1949 | } | |
1950 | ||
db2e5f21 LP |
1951 | static const struct irq_chip rzg2l_gpio_irqchip = { |
1952 | .name = "rzg2l-gpio", | |
1953 | .irq_disable = rzg2l_gpio_irq_disable, | |
1954 | .irq_enable = rzg2l_gpio_irq_enable, | |
1955 | .irq_mask = irq_chip_mask_parent, | |
1956 | .irq_unmask = irq_chip_unmask_parent, | |
1957 | .irq_set_type = rzg2l_gpio_irq_set_type, | |
1958 | .irq_eoi = rzg2l_gpio_irqc_eoi, | |
1959 | .irq_print_chip = rzg2l_gpio_irq_print_chip, | |
e4c3a81a | 1960 | .irq_set_affinity = irq_chip_set_affinity_parent, |
254203f9 | 1961 | .irq_set_wake = rzg2l_gpio_irq_set_wake, |
db2e5f21 LP |
1962 | .flags = IRQCHIP_IMMUTABLE, |
1963 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
1964 | }; | |
1965 | ||
2fd4fe19 BD |
1966 | static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) |
1967 | { | |
1968 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); | |
1969 | const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; | |
1970 | u64 *pin_data = pin_desc->drv_data; | |
1971 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | |
1972 | u8 bit = RZG2L_PIN_ID_TO_PIN(offset); | |
1973 | u8 reg8; | |
1974 | int ret; | |
1975 | ||
1976 | reg8 = readb(pctrl->base + PMC(off)); | |
1977 | if (reg8 & BIT(bit)) { | |
1978 | ret = rzg2l_gpio_request(chip, offset); | |
1979 | if (ret) | |
1980 | return ret; | |
1981 | } | |
1982 | ||
1983 | return rzg2l_gpio_direction_input(chip, offset); | |
1984 | } | |
1985 | ||
db2e5f21 LP |
1986 | static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, |
1987 | unsigned int child, | |
1988 | unsigned int child_type, | |
1989 | unsigned int *parent, | |
1990 | unsigned int *parent_type) | |
1991 | { | |
1992 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); | |
1993 | unsigned long flags; | |
1994 | int gpioint, irq; | |
2fd4fe19 | 1995 | int ret; |
db2e5f21 | 1996 | |
fea58424 | 1997 | gpioint = rzg2l_gpio_get_gpioint(child, pctrl); |
db2e5f21 LP |
1998 | if (gpioint < 0) |
1999 | return gpioint; | |
2000 | ||
2fd4fe19 BD |
2001 | ret = rzg2l_gpio_interrupt_input_mode(gc, child); |
2002 | if (ret) | |
2003 | return ret; | |
2004 | ||
db2e5f21 LP |
2005 | spin_lock_irqsave(&pctrl->bitmap_lock, flags); |
2006 | irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); | |
2007 | spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); | |
2fd4fe19 BD |
2008 | if (irq < 0) { |
2009 | ret = -ENOSPC; | |
2010 | goto err; | |
2011 | } | |
2012 | ||
1d2da797 | 2013 | rzg2l_gpio_irq_endisable(pctrl, child, true); |
db2e5f21 LP |
2014 | pctrl->hwirq[irq] = child; |
2015 | irq += RZG2L_TINT_IRQ_START_INDEX; | |
2016 | ||
2017 | /* All these interrupts are level high in the CPU */ | |
2018 | *parent_type = IRQ_TYPE_LEVEL_HIGH; | |
2019 | *parent = RZG2L_PACK_HWIRQ(gpioint, irq); | |
2020 | return 0; | |
2fd4fe19 BD |
2021 | |
2022 | err: | |
2023 | rzg2l_gpio_free(gc, child); | |
2024 | return ret; | |
db2e5f21 LP |
2025 | } |
2026 | ||
2027 | static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, | |
2028 | union gpio_irq_fwspec *gfwspec, | |
2029 | unsigned int parent_hwirq, | |
2030 | unsigned int parent_type) | |
2031 | { | |
2032 | struct irq_fwspec *fwspec = &gfwspec->fwspec; | |
2033 | ||
2034 | fwspec->fwnode = chip->irq.parent_domain->fwnode; | |
2035 | fwspec->param_count = 2; | |
2036 | fwspec->param[0] = parent_hwirq; | |
2037 | fwspec->param[1] = parent_type; | |
2038 | ||
2039 | return 0; | |
2040 | } | |
2041 | ||
254203f9 CB |
2042 | static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) |
2043 | { | |
2044 | struct irq_domain *domain = pctrl->gpio_chip.irq.domain; | |
2045 | ||
2046 | for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { | |
2047 | struct irq_data *data; | |
02cd2d3b | 2048 | unsigned long flags; |
254203f9 | 2049 | unsigned int virq; |
02cd2d3b | 2050 | int ret; |
254203f9 CB |
2051 | |
2052 | if (!pctrl->hwirq[i]) | |
2053 | continue; | |
2054 | ||
2055 | virq = irq_find_mapping(domain, pctrl->hwirq[i]); | |
2056 | if (!virq) { | |
2057 | dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", | |
2058 | pctrl->hwirq[i]); | |
2059 | continue; | |
2060 | } | |
2061 | ||
2062 | data = irq_domain_get_irq_data(domain, virq); | |
2063 | if (!data) { | |
2064 | dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); | |
2065 | continue; | |
2066 | } | |
2067 | ||
02cd2d3b CB |
2068 | /* |
2069 | * This has to be atomically executed to protect against a concurrent | |
2070 | * interrupt. | |
2071 | */ | |
2072 | raw_spin_lock_irqsave(&pctrl->lock.rlock, flags); | |
2073 | ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data)); | |
2074 | if (!ret && !irqd_irq_disabled(data)) | |
254203f9 | 2075 | rzg2l_gpio_irq_enable(data); |
02cd2d3b CB |
2076 | raw_spin_unlock_irqrestore(&pctrl->lock.rlock, flags); |
2077 | ||
2078 | if (ret) | |
2079 | dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); | |
254203f9 CB |
2080 | } |
2081 | } | |
2082 | ||
db2e5f21 LP |
2083 | static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
2084 | unsigned int nr_irqs) | |
2085 | { | |
2086 | struct irq_data *d; | |
2087 | ||
2088 | d = irq_domain_get_irq_data(domain, virq); | |
2089 | if (d) { | |
2090 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
2091 | struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); | |
2092 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
2093 | unsigned long flags; | |
2094 | unsigned int i; | |
2095 | ||
2096 | for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { | |
2097 | if (pctrl->hwirq[i] == hwirq) { | |
1d2da797 | 2098 | rzg2l_gpio_irq_endisable(pctrl, hwirq, false); |
2fd4fe19 | 2099 | rzg2l_gpio_free(gc, hwirq); |
db2e5f21 LP |
2100 | spin_lock_irqsave(&pctrl->bitmap_lock, flags); |
2101 | bitmap_release_region(pctrl->tint_slot, i, get_order(1)); | |
2102 | spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); | |
2103 | pctrl->hwirq[i] = 0; | |
2104 | break; | |
2105 | } | |
2106 | } | |
2107 | } | |
2108 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
2109 | } | |
2110 | ||
2111 | static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, | |
2112 | unsigned long *valid_mask, | |
2113 | unsigned int ngpios) | |
2114 | { | |
2115 | struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); | |
2116 | struct gpio_chip *chip = &pctrl->gpio_chip; | |
2117 | unsigned int offset; | |
2118 | ||
2119 | /* Forbid unused lines to be mapped as IRQs */ | |
2120 | for (offset = 0; offset < chip->ngpio; offset++) { | |
2121 | u32 port, bit; | |
2122 | ||
2123 | port = offset / 8; | |
2124 | bit = offset % 8; | |
2125 | ||
00dfe298 | 2126 | if (port >= pctrl->data->n_ports || |
15e4ae4f LP |
2127 | bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, |
2128 | pctrl->data->port_pin_configs[port]))) | |
db2e5f21 LP |
2129 | clear_bit(offset, valid_mask); |
2130 | } | |
2131 | } | |
2132 | ||
254203f9 CB |
2133 | static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) |
2134 | { | |
2135 | u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; | |
2136 | struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache; | |
2137 | ||
2138 | cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); | |
2139 | if (!cache) | |
2140 | return -ENOMEM; | |
2141 | ||
2142 | dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); | |
2143 | if (!dedicated_cache) | |
2144 | return -ENOMEM; | |
2145 | ||
2146 | cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); | |
2147 | if (!cache->p) | |
2148 | return -ENOMEM; | |
2149 | ||
2150 | cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); | |
2151 | if (!cache->pm) | |
2152 | return -ENOMEM; | |
2153 | ||
2154 | cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); | |
2155 | if (!cache->pmc) | |
2156 | return -ENOMEM; | |
2157 | ||
2158 | cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); | |
2159 | if (!cache->pfc) | |
2160 | return -ENOMEM; | |
2161 | ||
2162 | for (u8 i = 0; i < 2; i++) { | |
2163 | u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; | |
2164 | ||
2165 | cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), | |
2166 | GFP_KERNEL); | |
2167 | if (!cache->iolh[i]) | |
2168 | return -ENOMEM; | |
2169 | ||
2170 | cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), | |
2171 | GFP_KERNEL); | |
2172 | if (!cache->ien[i]) | |
2173 | return -ENOMEM; | |
2174 | ||
2175 | /* Allocate dedicated cache. */ | |
2176 | dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, | |
2177 | sizeof(*dedicated_cache->iolh[i]), | |
2178 | GFP_KERNEL); | |
2179 | if (!dedicated_cache->iolh[i]) | |
2180 | return -ENOMEM; | |
2181 | ||
2182 | dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, | |
2183 | sizeof(*dedicated_cache->ien[i]), | |
2184 | GFP_KERNEL); | |
2185 | if (!dedicated_cache->ien[i]) | |
2186 | return -ENOMEM; | |
2187 | } | |
2188 | ||
2189 | pctrl->cache = cache; | |
2190 | pctrl->dedicated_cache = dedicated_cache; | |
2191 | ||
2192 | return 0; | |
2193 | } | |
2194 | ||
c4c4637e LP |
2195 | static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) |
2196 | { | |
2197 | struct device_node *np = pctrl->dev->of_node; | |
2198 | struct gpio_chip *chip = &pctrl->gpio_chip; | |
2199 | const char *name = dev_name(pctrl->dev); | |
db2e5f21 | 2200 | struct irq_domain *parent_domain; |
c4c4637e | 2201 | struct of_phandle_args of_args; |
db2e5f21 LP |
2202 | struct device_node *parent_np; |
2203 | struct gpio_irq_chip *girq; | |
c4c4637e LP |
2204 | int ret; |
2205 | ||
db2e5f21 LP |
2206 | parent_np = of_irq_find_parent(np); |
2207 | if (!parent_np) | |
2208 | return -ENXIO; | |
2209 | ||
2210 | parent_domain = irq_find_host(parent_np); | |
2211 | of_node_put(parent_np); | |
2212 | if (!parent_domain) | |
2213 | return -EPROBE_DEFER; | |
2214 | ||
c4c4637e LP |
2215 | ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); |
2216 | if (ret) { | |
2217 | dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); | |
2218 | return ret; | |
2219 | } | |
2220 | ||
2221 | if (of_args.args[0] != 0 || of_args.args[1] != 0 || | |
2e08ab04 | 2222 | of_args.args[2] != pctrl->data->n_port_pins) { |
c4c4637e LP |
2223 | dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); |
2224 | return -EINVAL; | |
2225 | } | |
2226 | ||
2e08ab04 | 2227 | chip->names = pctrl->data->port_pins; |
c4c4637e LP |
2228 | chip->request = rzg2l_gpio_request; |
2229 | chip->free = rzg2l_gpio_free; | |
2230 | chip->get_direction = rzg2l_gpio_get_direction; | |
2231 | chip->direction_input = rzg2l_gpio_direction_input; | |
2232 | chip->direction_output = rzg2l_gpio_direction_output; | |
2233 | chip->get = rzg2l_gpio_get; | |
2234 | chip->set = rzg2l_gpio_set; | |
2235 | chip->label = name; | |
2236 | chip->parent = pctrl->dev; | |
2237 | chip->owner = THIS_MODULE; | |
2238 | chip->base = -1; | |
2239 | chip->ngpio = of_args.args[2]; | |
2240 | ||
db2e5f21 LP |
2241 | girq = &chip->irq; |
2242 | gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); | |
2243 | girq->fwnode = of_node_to_fwnode(np); | |
2244 | girq->parent_domain = parent_domain; | |
2245 | girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; | |
2246 | girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; | |
2247 | girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; | |
2248 | girq->init_valid_mask = rzg2l_init_irq_valid_mask; | |
2249 | ||
c4c4637e LP |
2250 | pctrl->gpio_range.id = 0; |
2251 | pctrl->gpio_range.pin_base = 0; | |
2252 | pctrl->gpio_range.base = 0; | |
2253 | pctrl->gpio_range.npins = chip->ngpio; | |
2254 | pctrl->gpio_range.name = chip->label; | |
2255 | pctrl->gpio_range.gc = chip; | |
2256 | ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); | |
2257 | if (ret) { | |
2258 | dev_err(pctrl->dev, "failed to add GPIO controller\n"); | |
2259 | return ret; | |
2260 | } | |
2261 | ||
2262 | dev_dbg(pctrl->dev, "Registered gpio controller\n"); | |
2263 | ||
2264 | return 0; | |
2265 | } | |
2266 | ||
2267 | static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) | |
2268 | { | |
ae5b425f | 2269 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; |
c4c4637e LP |
2270 | struct pinctrl_pin_desc *pins; |
2271 | unsigned int i, j; | |
15e4ae4f | 2272 | u64 *pin_data; |
c4c4637e LP |
2273 | int ret; |
2274 | ||
2275 | pctrl->desc.name = DRV_NAME; | |
2276 | pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; | |
2277 | pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; | |
2278 | pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; | |
2279 | pctrl->desc.confops = &rzg2l_pinctrl_confops; | |
2280 | pctrl->desc.owner = THIS_MODULE; | |
2281 | ||
2282 | pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); | |
2283 | if (!pins) | |
2284 | return -ENOMEM; | |
2285 | ||
2286 | pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, | |
2287 | sizeof(*pin_data), GFP_KERNEL); | |
2288 | if (!pin_data) | |
2289 | return -ENOMEM; | |
2290 | ||
2291 | pctrl->pins = pins; | |
2292 | pctrl->desc.pins = pins; | |
2293 | ||
2294 | for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { | |
2295 | pins[i].number = i; | |
2296 | pins[i].name = pctrl->data->port_pins[i]; | |
2297 | if (i && !(i % RZG2L_PINS_PER_PORT)) | |
2298 | j++; | |
2299 | pin_data[i] = pctrl->data->port_pin_configs[j]; | |
fea58424 LP |
2300 | #ifdef CONFIG_RISCV |
2301 | if (pin_data[i] & PIN_CFG_VARIABLE) | |
2302 | pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, | |
2303 | pin_data[i], | |
2304 | j, | |
2305 | i % RZG2L_PINS_PER_PORT); | |
2306 | #endif | |
c4c4637e LP |
2307 | pins[i].drv_data = &pin_data[i]; |
2308 | } | |
2309 | ||
2310 | for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { | |
2311 | unsigned int index = pctrl->data->n_port_pins + i; | |
2312 | ||
2313 | pins[index].number = index; | |
2314 | pins[index].name = pctrl->data->dedicated_pins[i].name; | |
2315 | pin_data[index] = pctrl->data->dedicated_pins[i].config; | |
2316 | pins[index].drv_data = &pin_data[index]; | |
2317 | } | |
2318 | ||
ae5b425f CB |
2319 | pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), |
2320 | GFP_KERNEL); | |
2321 | if (!pctrl->settings) | |
2322 | return -ENOMEM; | |
2323 | ||
2324 | for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { | |
2325 | if (pin_data[i] & PIN_CFG_SOFT_PS) { | |
2326 | pctrl->settings[i].power_source = 3300; | |
2327 | } else { | |
2328 | ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); | |
2329 | if (ret < 0) | |
2330 | continue; | |
2331 | pctrl->settings[i].power_source = ret; | |
2332 | } | |
2333 | } | |
2334 | ||
254203f9 CB |
2335 | ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); |
2336 | if (ret) | |
2337 | return ret; | |
2338 | ||
c4c4637e LP |
2339 | ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, |
2340 | &pctrl->pctl); | |
2341 | if (ret) { | |
2342 | dev_err(pctrl->dev, "pinctrl registration failed\n"); | |
2343 | return ret; | |
2344 | } | |
2345 | ||
2346 | ret = pinctrl_enable(pctrl->pctl); | |
2347 | if (ret) { | |
2348 | dev_err(pctrl->dev, "pinctrl enable failed\n"); | |
2349 | return ret; | |
2350 | } | |
2351 | ||
2352 | ret = rzg2l_gpio_register(pctrl); | |
2353 | if (ret) { | |
2354 | dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); | |
2355 | return ret; | |
2356 | } | |
2357 | ||
2358 | return 0; | |
2359 | } | |
2360 | ||
c4c4637e LP |
2361 | static int rzg2l_pinctrl_probe(struct platform_device *pdev) |
2362 | { | |
2363 | struct rzg2l_pinctrl *pctrl; | |
2364 | int ret; | |
2365 | ||
c3852566 | 2366 | BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > |
2d4a628c LP |
2367 | ARRAY_SIZE(rzg2l_gpio_names)); |
2368 | ||
2369 | BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > | |
2370 | ARRAY_SIZE(rzg2l_gpio_names)); | |
2371 | ||
c6a088e5 CB |
2372 | BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > |
2373 | ARRAY_SIZE(rzg2l_gpio_names)); | |
2374 | ||
c4c4637e LP |
2375 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); |
2376 | if (!pctrl) | |
2377 | return -ENOMEM; | |
2378 | ||
2379 | pctrl->dev = &pdev->dev; | |
2380 | ||
2381 | pctrl->data = of_device_get_match_data(&pdev->dev); | |
2382 | if (!pctrl->data) | |
2383 | return -EINVAL; | |
2384 | ||
2385 | pctrl->base = devm_platform_ioremap_resource(pdev, 0); | |
2386 | if (IS_ERR(pctrl->base)) | |
2387 | return PTR_ERR(pctrl->base); | |
2388 | ||
254203f9 CB |
2389 | pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); |
2390 | if (IS_ERR(pctrl->clk)) { | |
2391 | return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), | |
95eb1986 | 2392 | "failed to enable GPIO clk\n"); |
254203f9 | 2393 | } |
c4c4637e LP |
2394 | |
2395 | spin_lock_init(&pctrl->lock); | |
db2e5f21 | 2396 | spin_lock_init(&pctrl->bitmap_lock); |
661efa22 | 2397 | mutex_init(&pctrl->mutex); |
254203f9 | 2398 | atomic_set(&pctrl->wakeup_path, 0); |
c4c4637e LP |
2399 | |
2400 | platform_set_drvdata(pdev, pctrl); | |
2401 | ||
c4c4637e LP |
2402 | ret = rzg2l_pinctrl_register(pctrl); |
2403 | if (ret) | |
2404 | return ret; | |
2405 | ||
2406 | dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); | |
2407 | return 0; | |
2408 | } | |
2409 | ||
254203f9 CB |
2410 | static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) |
2411 | { | |
2412 | u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; | |
2413 | struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; | |
2414 | ||
2415 | for (u32 port = 0; port < nports; port++) { | |
2416 | bool has_iolh, has_ien; | |
2417 | u32 off, caps; | |
2418 | u8 pincnt; | |
2419 | u64 cfg; | |
2420 | ||
2421 | cfg = pctrl->data->port_pin_configs[port]; | |
2422 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); | |
2423 | pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); | |
2424 | ||
2425 | caps = FIELD_GET(PIN_CFG_MASK, cfg); | |
2426 | has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); | |
2427 | has_ien = !!(caps & PIN_CFG_IEN); | |
2428 | ||
2429 | if (suspend) | |
2430 | RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); | |
2431 | ||
2432 | /* | |
2433 | * Now cache the registers or set them in the order suggested by | |
2434 | * HW manual (section "Operation for GPIO Function"). | |
2435 | */ | |
2436 | RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); | |
2437 | if (has_iolh) { | |
2438 | RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), | |
2439 | cache->iolh[0][port]); | |
2440 | if (pincnt >= 4) { | |
2441 | RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, | |
2442 | cache->iolh[1][port]); | |
2443 | } | |
2444 | } | |
2445 | ||
2446 | RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); | |
2447 | RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); | |
2448 | ||
2449 | if (has_ien) { | |
2450 | RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), | |
2451 | cache->ien[0][port]); | |
2452 | if (pincnt >= 4) { | |
2453 | RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, | |
2454 | cache->ien[1][port]); | |
2455 | } | |
2456 | } | |
2457 | } | |
2458 | } | |
2459 | ||
2460 | static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) | |
2461 | { | |
2462 | struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; | |
2463 | ||
2464 | /* | |
2465 | * Make sure entries in pctrl->data->n_dedicated_pins[] having the same | |
2466 | * port offset are close together. | |
2467 | */ | |
2468 | for (u32 i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { | |
2469 | bool has_iolh, has_ien; | |
2470 | u32 off, next_off = 0; | |
2471 | u64 cfg, next_cfg; | |
2472 | u8 pincnt; | |
2473 | ||
2474 | cfg = pctrl->data->dedicated_pins[i].config; | |
2475 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); | |
2476 | if (i + 1 < pctrl->data->n_dedicated_pins) { | |
2477 | next_cfg = pctrl->data->dedicated_pins[i + 1].config; | |
2478 | next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg); | |
2479 | } | |
2480 | ||
2481 | if (off == next_off) { | |
2482 | /* Gather caps of all port pins. */ | |
2483 | caps |= FIELD_GET(PIN_CFG_MASK, cfg); | |
2484 | continue; | |
2485 | } | |
2486 | ||
2487 | /* And apply them in a single shot. */ | |
2488 | has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); | |
2489 | has_ien = !!(caps & PIN_CFG_IEN); | |
2490 | pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); | |
2491 | ||
2492 | if (has_iolh) { | |
2493 | RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), | |
2494 | cache->iolh[0][i]); | |
2495 | } | |
2496 | if (has_ien) { | |
2497 | RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), | |
2498 | cache->ien[0][i]); | |
2499 | } | |
2500 | ||
2501 | if (pincnt >= 4) { | |
2502 | if (has_iolh) { | |
2503 | RZG2L_PCTRL_REG_ACCESS32(suspend, | |
2504 | pctrl->base + IOLH(off) + 4, | |
2505 | cache->iolh[1][i]); | |
2506 | } | |
2507 | if (has_ien) { | |
2508 | RZG2L_PCTRL_REG_ACCESS32(suspend, | |
2509 | pctrl->base + IEN(off) + 4, | |
2510 | cache->ien[1][i]); | |
2511 | } | |
2512 | } | |
2513 | caps = 0; | |
2514 | } | |
2515 | } | |
2516 | ||
2517 | static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) | |
2518 | { | |
2519 | u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; | |
2520 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; | |
2521 | const struct rzg2l_register_offsets *regs = &hwcfg->regs; | |
2522 | ||
2523 | /* Set the PWPR register to allow PFC register to write. */ | |
2524 | writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ | |
2525 | writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ | |
2526 | ||
2527 | /* Restore port registers. */ | |
2528 | for (u32 port = 0; port < nports; port++) { | |
2529 | unsigned long pinmap; | |
2530 | u8 pmc = 0, max_pin; | |
2531 | u32 off, pfc = 0; | |
2532 | u64 cfg; | |
2533 | u16 pm; | |
2534 | u8 pin; | |
2535 | ||
2536 | cfg = pctrl->data->port_pin_configs[port]; | |
2537 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); | |
2538 | pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); | |
2539 | max_pin = fls(pinmap); | |
2540 | ||
2541 | pm = readw(pctrl->base + PM(off)); | |
2542 | for_each_set_bit(pin, &pinmap, max_pin) { | |
2543 | struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; | |
2544 | ||
2545 | /* Nothing to do if PFC was not configured before. */ | |
2546 | if (!(cache->pmc[port] & BIT(pin))) | |
2547 | continue; | |
2548 | ||
2549 | /* Set pin to 'Non-use (Hi-Z input protection)' */ | |
2550 | pm &= ~(PM_MASK << (pin * 2)); | |
2551 | writew(pm, pctrl->base + PM(off)); | |
2552 | ||
2553 | /* Temporarily switch to GPIO mode with PMC register */ | |
2554 | pmc &= ~BIT(pin); | |
2555 | writeb(pmc, pctrl->base + PMC(off)); | |
2556 | ||
2557 | /* Select Pin function mode. */ | |
2558 | pfc &= ~(PFC_MASK << (pin * 4)); | |
2559 | pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); | |
2560 | writel(pfc, pctrl->base + PFC(off)); | |
2561 | ||
2562 | /* Switch to Peripheral pin function. */ | |
2563 | pmc |= BIT(pin); | |
2564 | writeb(pmc, pctrl->base + PMC(off)); | |
2565 | } | |
2566 | } | |
2567 | ||
2568 | /* Set the PWPR register to be write-protected. */ | |
2569 | writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ | |
2570 | writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ | |
2571 | } | |
2572 | ||
2573 | static int rzg2l_pinctrl_suspend_noirq(struct device *dev) | |
2574 | { | |
2575 | struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); | |
2576 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; | |
2577 | const struct rzg2l_register_offsets *regs = &hwcfg->regs; | |
2578 | struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; | |
2579 | ||
2580 | rzg2l_pinctrl_pm_setup_regs(pctrl, true); | |
2581 | rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); | |
2582 | ||
2583 | for (u8 i = 0; i < 2; i++) { | |
2584 | cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); | |
2585 | cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); | |
2586 | } | |
2587 | ||
2588 | cache->qspi = readb(pctrl->base + QSPI); | |
2589 | cache->eth_mode = readb(pctrl->base + ETH_MODE); | |
2590 | ||
2591 | if (!atomic_read(&pctrl->wakeup_path)) | |
2592 | clk_disable_unprepare(pctrl->clk); | |
2593 | else | |
2594 | device_set_wakeup_path(dev); | |
2595 | ||
2596 | return 0; | |
2597 | } | |
2598 | ||
2599 | static int rzg2l_pinctrl_resume_noirq(struct device *dev) | |
2600 | { | |
2601 | struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); | |
2602 | const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; | |
2603 | const struct rzg2l_register_offsets *regs = &hwcfg->regs; | |
2604 | struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; | |
2605 | int ret; | |
2606 | ||
2607 | if (!atomic_read(&pctrl->wakeup_path)) { | |
2608 | ret = clk_prepare_enable(pctrl->clk); | |
2609 | if (ret) | |
2610 | return ret; | |
2611 | } | |
2612 | ||
2613 | writeb(cache->qspi, pctrl->base + QSPI); | |
2614 | writeb(cache->eth_mode, pctrl->base + ETH_MODE); | |
2615 | for (u8 i = 0; i < 2; i++) { | |
2616 | writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); | |
2617 | writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); | |
2618 | } | |
2619 | ||
2620 | rzg2l_pinctrl_pm_setup_pfc(pctrl); | |
2621 | rzg2l_pinctrl_pm_setup_regs(pctrl, false); | |
2622 | rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); | |
2623 | rzg2l_gpio_irq_restore(pctrl); | |
2624 | ||
2625 | return 0; | |
2626 | } | |
2627 | ||
1f89aa90 CB |
2628 | static const struct rzg2l_hwcfg rzg2l_hwcfg = { |
2629 | .regs = { | |
2630 | .pwpr = 0x3014, | |
2631 | .sd_ch = 0x3000, | |
51996952 | 2632 | .eth_poc = 0x300c, |
1f89aa90 | 2633 | }, |
cca38201 CB |
2634 | .iolh_groupa_ua = { |
2635 | /* 3v3 power source */ | |
2636 | [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, | |
2637 | }, | |
2638 | .iolh_groupb_oi = { 100, 66, 50, 33, }, | |
1f89aa90 CB |
2639 | }; |
2640 | ||
c6a088e5 CB |
2641 | static const struct rzg2l_hwcfg rzg3s_hwcfg = { |
2642 | .regs = { | |
2643 | .pwpr = 0x3000, | |
2644 | .sd_ch = 0x3004, | |
51996952 | 2645 | .eth_poc = 0x3010, |
c6a088e5 CB |
2646 | }, |
2647 | .iolh_groupa_ua = { | |
2648 | /* 1v8 power source */ | |
2649 | [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, | |
2650 | /* 3v3 power source */ | |
2651 | [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, | |
2652 | }, | |
2653 | .iolh_groupb_ua = { | |
2654 | /* 1v8 power source */ | |
2655 | [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, | |
2656 | /* 3v3 power source */ | |
2657 | [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, | |
2658 | }, | |
2659 | .iolh_groupc_ua = { | |
2660 | /* 1v8 power source */ | |
2661 | [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, | |
2662 | /* 2v5 source */ | |
2663 | [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, | |
2664 | /* 3v3 power source */ | |
2665 | [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, | |
2666 | }, | |
2667 | .drive_strength_ua = true, | |
2668 | .func_base = 1, | |
1bbc8ee4 CB |
2669 | .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ |
2670 | .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ | |
c6a088e5 CB |
2671 | }; |
2672 | ||
bfc69bdb BD |
2673 | static struct rzg2l_pinctrl_data r9a07g043_data = { |
2674 | .port_pins = rzg2l_gpio_names, | |
2675 | .port_pin_configs = r9a07g043_gpio_configs, | |
00dfe298 | 2676 | .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), |
bfc69bdb BD |
2677 | .dedicated_pins = rzg2l_dedicated_pins.common, |
2678 | .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, | |
2679 | .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), | |
1f89aa90 | 2680 | .hwcfg = &rzg2l_hwcfg, |
fea58424 LP |
2681 | #ifdef CONFIG_RISCV |
2682 | .variable_pin_cfg = r9a07g043f_variable_pin_cfg, | |
2683 | .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), | |
2684 | #endif | |
bfc69bdb BD |
2685 | }; |
2686 | ||
c4c4637e LP |
2687 | static struct rzg2l_pinctrl_data r9a07g044_data = { |
2688 | .port_pins = rzg2l_gpio_names, | |
c3852566 GU |
2689 | .port_pin_configs = r9a07g044_gpio_configs, |
2690 | .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), | |
bfc69bdb | 2691 | .dedicated_pins = rzg2l_dedicated_pins.common, |
c3852566 | 2692 | .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, |
bfc69bdb BD |
2693 | .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + |
2694 | ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), | |
1f89aa90 | 2695 | .hwcfg = &rzg2l_hwcfg, |
c4c4637e LP |
2696 | }; |
2697 | ||
c6a088e5 CB |
2698 | static struct rzg2l_pinctrl_data r9a08g045_data = { |
2699 | .port_pins = rzg2l_gpio_names, | |
2700 | .port_pin_configs = r9a08g045_gpio_configs, | |
2701 | .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), | |
2702 | .dedicated_pins = rzg3s_dedicated_pins, | |
2703 | .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, | |
2704 | .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), | |
2705 | .hwcfg = &rzg3s_hwcfg, | |
2706 | }; | |
2707 | ||
c4c4637e | 2708 | static const struct of_device_id rzg2l_pinctrl_of_table[] = { |
bfc69bdb BD |
2709 | { |
2710 | .compatible = "renesas,r9a07g043-pinctrl", | |
2711 | .data = &r9a07g043_data, | |
2712 | }, | |
c4c4637e LP |
2713 | { |
2714 | .compatible = "renesas,r9a07g044-pinctrl", | |
2715 | .data = &r9a07g044_data, | |
2716 | }, | |
c6a088e5 CB |
2717 | { |
2718 | .compatible = "renesas,r9a08g045-pinctrl", | |
2719 | .data = &r9a08g045_data, | |
2720 | }, | |
c4c4637e LP |
2721 | { /* sentinel */ } |
2722 | }; | |
2723 | ||
254203f9 CB |
2724 | static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = { |
2725 | NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq) | |
2726 | }; | |
2727 | ||
c4c4637e LP |
2728 | static struct platform_driver rzg2l_pinctrl_driver = { |
2729 | .driver = { | |
2730 | .name = DRV_NAME, | |
2731 | .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), | |
254203f9 | 2732 | .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops), |
c4c4637e LP |
2733 | }, |
2734 | .probe = rzg2l_pinctrl_probe, | |
2735 | }; | |
2736 | ||
2737 | static int __init rzg2l_pinctrl_init(void) | |
2738 | { | |
2739 | return platform_driver_register(&rzg2l_pinctrl_driver); | |
2740 | } | |
2741 | core_initcall(rzg2l_pinctrl_init); | |
2742 | ||
2743 | MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); | |
2744 | MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); |