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pinctrl: Include <linux/gpio/driver.h> nothing else
[linux-block.git] / drivers / pinctrl / qcom / pinctrl-spmi-gpio.c
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eadff302
II		 1/*
2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
1c5fb66a 14#include <linux/gpio/driver.h>
eadff302
II		 15#include <linux/module.h>
16#include <linux/of.h>
ab4256cf 17#include <linux/of_irq.h>
eadff302
II		 18#include <linux/pinctrl/pinconf-generic.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24#include <linux/types.h>
25
26#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
27
28#include "../core.h"
29#include "../pinctrl-utils.h"
30
31#define PMIC_GPIO_ADDRESS_RANGE 0x100
32
33/* type and subtype registers base address offsets */
34#define PMIC_GPIO_REG_TYPE 0x4
35#define PMIC_GPIO_REG_SUBTYPE 0x5
36
37/* GPIO peripheral type and subtype out_values */
38#define PMIC_GPIO_TYPE 0x10
39#define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
40#define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
41#define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
42#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
d7b5f5cc
FW		 43#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
44#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
eadff302
II		 45
46#define PMIC_MPP_REG_RT_STS 0x10
47#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
48
49/* control register base address offsets */
50#define PMIC_GPIO_REG_MODE_CTL 0x40
51#define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
52#define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
d7b5f5cc 53#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
223463fc 54#define PMIC_GPIO_REG_DIG_IN_CTL 0x43
eadff302
II		 55#define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
56#define PMIC_GPIO_REG_EN_CTL 0x46
d7b5f5cc 57#define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
eadff302
II		 58
59/* PMIC_GPIO_REG_MODE_CTL */
60#define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
61#define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
62#define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
63#define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
64#define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
65
d7b5f5cc
FW		 66#define PMIC_GPIO_MODE_DIGITAL_INPUT 0
67#define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
68#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
69#define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
70#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
71
eadff302
II		 72/* PMIC_GPIO_REG_DIG_VIN_CTL */
73#define PMIC_GPIO_REG_VIN_SHIFT 0
74#define PMIC_GPIO_REG_VIN_MASK 0x7
75
76/* PMIC_GPIO_REG_DIG_PULL_CTL */
77#define PMIC_GPIO_REG_PULL_SHIFT 0
78#define PMIC_GPIO_REG_PULL_MASK 0x7
79
80#define PMIC_GPIO_PULL_DOWN 4
81#define PMIC_GPIO_PULL_DISABLE 5
82
d7b5f5cc
FW		 83/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
84#define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
85#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
86#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
87
223463fc
FW		 88/* PMIC_GPIO_REG_DIG_IN_CTL */
89#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
90#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
91#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
92
eadff302
II		 93/* PMIC_GPIO_REG_DIG_OUT_CTL */
94#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
95#define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
96#define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
97#define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
98
99/*
100 * Output type - indicates pin should be configured as push-pull,
101 * open drain or open source.
102 */
103#define PMIC_GPIO_OUT_BUF_CMOS 0
104#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
105#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
106
107/* PMIC_GPIO_REG_EN_CTL */
108#define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
109
110#define PMIC_GPIO_PHYSICAL_OFFSET 1
111
d7b5f5cc
FW		 112/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
113#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
114
eadff302
II		 115/* Qualcomm specific pin configurations */
116#define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
117#define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
d7b5f5cc
FW		 118#define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
119#define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
223463fc 120#define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
d7b5f5cc
FW		 121
122/* The index of each function in pmic_gpio_functions[] array */
123enum pmic_gpio_func_index {
124 PMIC_GPIO_FUNC_INDEX_NORMAL,
125 PMIC_GPIO_FUNC_INDEX_PAIRED,
126 PMIC_GPIO_FUNC_INDEX_FUNC1,
127 PMIC_GPIO_FUNC_INDEX_FUNC2,
128 PMIC_GPIO_FUNC_INDEX_FUNC3,
129 PMIC_GPIO_FUNC_INDEX_FUNC4,
130 PMIC_GPIO_FUNC_INDEX_DTEST1,
131 PMIC_GPIO_FUNC_INDEX_DTEST2,
132 PMIC_GPIO_FUNC_INDEX_DTEST3,
133 PMIC_GPIO_FUNC_INDEX_DTEST4,
134};
eadff302
II		 135
136/**
137 * struct pmic_gpio_pad - keep current GPIO settings
138 * @base: Address base in SPMI device.
139 * @irq: IRQ number which this GPIO generate.
140 * @is_enabled: Set to false when GPIO should be put in high Z state.
141 * @out_value: Cached pin output value
142 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
143 * open-drain or open-source mode.
144 * @output_enabled: Set to true if GPIO output logic is enabled.
145 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
d7b5f5cc
FW		 146 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
147 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
eadff302
II		 148 * @num_sources: Number of power-sources supported by this GPIO.
149 * @power_source: Current power-source used.
150 * @buffer_type: Push-pull, open-drain or open-source.
151 * @pullup: Constant current which flow trough GPIO output buffer.
152 * @strength: No, Low, Medium, High
153 * @function: See pmic_gpio_functions[]
d7b5f5cc 154 * @atest: the ATEST selection for GPIO analog-pass-through mode
223463fc 155 * @dtest_buffer: the DTEST buffer selection for digital input mode.
eadff302
II		 156 */
157struct pmic_gpio_pad {
158 u16 base;
159 int irq;
160 bool is_enabled;
161 bool out_value;
162 bool have_buffer;
163 bool output_enabled;
164 bool input_enabled;
d7b5f5cc
FW		 165 bool analog_pass;
166 bool lv_mv_type;
eadff302
II		 167 unsigned int num_sources;
168 unsigned int power_source;
169 unsigned int buffer_type;
170 unsigned int pullup;
171 unsigned int strength;
172 unsigned int function;
d7b5f5cc 173 unsigned int atest;
223463fc 174 unsigned int dtest_buffer;
eadff302
II		 175};
176
177struct pmic_gpio_state {
178 struct device *dev;
179 struct regmap *map;
180 struct pinctrl_dev *ctrl;
181 struct gpio_chip chip;
182};
183
f684e4ac 184static const struct pinconf_generic_params pmic_gpio_bindings[] = {
7382b623
SB		 185 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
186 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
d7b5f5cc
FW		 187 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
188 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
223463fc 189 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
eadff302
II		 190};
191
4f06266a 192#ifdef CONFIG_DEBUG_FS
7382b623
SB		 193static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
194 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
195 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
d7b5f5cc
FW		 196 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
197 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
223463fc 198 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
eadff302 199};
4f06266a 200#endif
eadff302
II		 201
202static const char *const pmic_gpio_groups[] = {
203 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
204 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
205 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
206 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
207 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
208};
209
210static const char *const pmic_gpio_functions[] = {
d7b5f5cc
FW		 211 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
212 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
213 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
214 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
215 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
216 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
217 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
218 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
219 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
220 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
eadff302
II		 221};
222
eadff302
II		 223static int pmic_gpio_read(struct pmic_gpio_state *state,
224 struct pmic_gpio_pad *pad, unsigned int addr)
225{
226 unsigned int val;
227 int ret;
228
229 ret = regmap_read(state->map, pad->base + addr, &val);
230 if (ret < 0)
231 dev_err(state->dev, "read 0x%x failed\n", addr);
232 else
233 ret = val;
234
235 return ret;
236}
237
238static int pmic_gpio_write(struct pmic_gpio_state *state,
239 struct pmic_gpio_pad *pad, unsigned int addr,
240 unsigned int val)
241{
242 int ret;
243
244 ret = regmap_write(state->map, pad->base + addr, val);
245 if (ret < 0)
246 dev_err(state->dev, "write 0x%x failed\n", addr);
247
248 return ret;
249}
250
251static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
252{
253 /* Every PIN is a group */
254 return pctldev->desc->npins;
255}
256
257static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
258 unsigned pin)
259{
260 return pctldev->desc->pins[pin].name;
261}
262
263static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
264 const unsigned **pins, unsigned *num_pins)
265{
266 *pins = &pctldev->desc->pins[pin].number;
267 *num_pins = 1;
268 return 0;
269}
270
eadff302
II		 271static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
272 .get_groups_count = pmic_gpio_get_groups_count,
273 .get_group_name = pmic_gpio_get_group_name,
274 .get_group_pins = pmic_gpio_get_group_pins,
7382b623 275 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
d32f7fd3 276 .dt_free_map = pinctrl_utils_free_map,
eadff302
II		 277};
278
279static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
280{
281 return ARRAY_SIZE(pmic_gpio_functions);
282}
283
284static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
285 unsigned function)
286{
287 return pmic_gpio_functions[function];
288}
289
290static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
291 unsigned function,
292 const char *const **groups,
293 unsigned *const num_qgroups)
294{
295 *groups = pmic_gpio_groups;
296 *num_qgroups = pctldev->desc->npins;
297 return 0;
298}
299
300static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
301 unsigned pin)
302{
303 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
304 struct pmic_gpio_pad *pad;
305 unsigned int val;
306 int ret;
307
d7b5f5cc
FW		 308 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
309 pr_err("function: %d is not defined\n", function);
310 return -EINVAL;
311 }
312
eadff302 313 pad = pctldev->desc->pins[pin].drv_data;
d7b5f5cc
FW		 314 /*
315 * Non-LV/MV subtypes only support 2 special functions,
316 * offsetting the dtestx function values by 2
317 */
318 if (!pad->lv_mv_type) {
319 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
320 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
321 pr_err("LV/MV subtype doesn't have func3/func4\n");
322 return -EINVAL;
323 }
324 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
325 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
326 PMIC_GPIO_FUNC_INDEX_FUNC3);
327 }
eadff302
II		 328
329 pad->function = function;
330
d7b5f5cc
FW		 331 if (pad->analog_pass)
332 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
333 else if (pad->output_enabled && pad->input_enabled)
334 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
335 else if (pad->output_enabled)
336 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
337 else
338 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
eadff302 339
d7b5f5cc
FW		 340 if (pad->lv_mv_type) {
341 ret = pmic_gpio_write(state, pad,
342 PMIC_GPIO_REG_MODE_CTL, val);
343 if (ret < 0)
344 return ret;
eadff302 345
d7b5f5cc
FW		 346 val = pad->atest - 1;
347 ret = pmic_gpio_write(state, pad,
348 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
349 if (ret < 0)
350 return ret;
351
352 val = pad->out_value
353 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
354 val |= pad->function
355 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
356 ret = pmic_gpio_write(state, pad,
357 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
358 if (ret < 0)
359 return ret;
360 } else {
361 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
362 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
363 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
364
365 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
366 if (ret < 0)
367 return ret;
368 }
eadff302
II		 369
370 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
371
372 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
373}
374
375static const struct pinmux_ops pmic_gpio_pinmux_ops = {
376 .get_functions_count = pmic_gpio_get_functions_count,
377 .get_function_name = pmic_gpio_get_function_name,
378 .get_function_groups = pmic_gpio_get_function_groups,
379 .set_mux = pmic_gpio_set_mux,
380};
381
382static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
383 unsigned int pin, unsigned long *config)
384{
385 unsigned param = pinconf_to_config_param(*config);
386 struct pmic_gpio_pad *pad;
387 unsigned arg;
388
389 pad = pctldev->desc->pins[pin].drv_data;
390
391 switch (param) {
392 case PIN_CONFIG_DRIVE_PUSH_PULL:
1cf86bc2
DA		 393 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
394 return -EINVAL;
395 arg = 1;
eadff302
II		 396 break;
397 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1cf86bc2
DA		 398 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
399 return -EINVAL;
400 arg = 1;
eadff302
II		 401 break;
402 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
1cf86bc2
DA		 403 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
404 return -EINVAL;
405 arg = 1;
eadff302
II		 406 break;
407 case PIN_CONFIG_BIAS_PULL_DOWN:
1cf86bc2
DA		 408 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
409 return -EINVAL;
410 arg = 1;
eadff302
II		 411 break;
412 case PIN_CONFIG_BIAS_DISABLE:
1cf86bc2
DA		 413 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
414 return -EINVAL;
415 arg = 1;
eadff302
II		 416 break;
417 case PIN_CONFIG_BIAS_PULL_UP:
1cf86bc2
DA		 418 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
419 return -EINVAL;
420 arg = 1;
eadff302
II		 421 break;
422 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1cf86bc2
DA		 423 if (pad->is_enabled)
424 return -EINVAL;
425 arg = 1;
eadff302
II		 426 break;
427 case PIN_CONFIG_POWER_SOURCE:
428 arg = pad->power_source;
429 break;
430 case PIN_CONFIG_INPUT_ENABLE:
1cf86bc2
DA		 431 if (!pad->input_enabled)
432 return -EINVAL;
433 arg = 1;
eadff302
II		 434 break;
435 case PIN_CONFIG_OUTPUT:
436 arg = pad->out_value;
437 break;
438 case PMIC_GPIO_CONF_PULL_UP:
439 arg = pad->pullup;
440 break;
441 case PMIC_GPIO_CONF_STRENGTH:
442 arg = pad->strength;
443 break;
d7b5f5cc
FW		 444 case PMIC_GPIO_CONF_ATEST:
445 arg = pad->atest;
446 break;
447 case PMIC_GPIO_CONF_ANALOG_PASS:
448 arg = pad->analog_pass;
449 break;
223463fc
FW		 450 case PMIC_GPIO_CONF_DTEST_BUFFER:
451 arg = pad->dtest_buffer;
452 break;
eadff302
II		 453 default:
454 return -EINVAL;
455 }
456
457 *config = pinconf_to_config_packed(param, arg);
458 return 0;
459}
460
461static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
462 unsigned long *configs, unsigned nconfs)
463{
464 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
465 struct pmic_gpio_pad *pad;
466 unsigned param, arg;
467 unsigned int val;
468 int i, ret;
469
470 pad = pctldev->desc->pins[pin].drv_data;
471
6cb74f44 472 pad->is_enabled = true;
eadff302
II		 473 for (i = 0; i < nconfs; i++) {
474 param = pinconf_to_config_param(configs[i]);
475 arg = pinconf_to_config_argument(configs[i]);
476
477 switch (param) {
478 case PIN_CONFIG_DRIVE_PUSH_PULL:
479 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
480 break;
481 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
482 if (!pad->have_buffer)
483 return -EINVAL;
484 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
485 break;
486 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
487 if (!pad->have_buffer)
488 return -EINVAL;
489 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
490 break;
491 case PIN_CONFIG_BIAS_DISABLE:
492 pad->pullup = PMIC_GPIO_PULL_DISABLE;
493 break;
494 case PIN_CONFIG_BIAS_PULL_UP:
495 pad->pullup = PMIC_GPIO_PULL_UP_30;
496 break;
497 case PIN_CONFIG_BIAS_PULL_DOWN:
498 if (arg)
499 pad->pullup = PMIC_GPIO_PULL_DOWN;
500 else
501 pad->pullup = PMIC_GPIO_PULL_DISABLE;
502 break;
503 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
504 pad->is_enabled = false;
505 break;
506 case PIN_CONFIG_POWER_SOURCE:
4e83ac4c 507 if (arg >= pad->num_sources)
eadff302
II		 508 return -EINVAL;
509 pad->power_source = arg;
510 break;
511 case PIN_CONFIG_INPUT_ENABLE:
512 pad->input_enabled = arg ? true : false;
513 break;
514 case PIN_CONFIG_OUTPUT:
515 pad->output_enabled = true;
516 pad->out_value = arg;
517 break;
518 case PMIC_GPIO_CONF_PULL_UP:
519 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
520 return -EINVAL;
521 pad->pullup = arg;
522 break;
523 case PMIC_GPIO_CONF_STRENGTH:
524 if (arg > PMIC_GPIO_STRENGTH_LOW)
525 return -EINVAL;
526 pad->strength = arg;
527 break;
d7b5f5cc
FW		 528 case PMIC_GPIO_CONF_ATEST:
529 if (!pad->lv_mv_type || arg > 4)
530 return -EINVAL;
531 pad->atest = arg;
532 break;
533 case PMIC_GPIO_CONF_ANALOG_PASS:
534 if (!pad->lv_mv_type)
535 return -EINVAL;
536 pad->analog_pass = true;
537 break;
223463fc
FW		 538 case PMIC_GPIO_CONF_DTEST_BUFFER:
539 if (arg > 4)
540 return -EINVAL;
541 pad->dtest_buffer = arg;
542 break;
eadff302
II		 543 default:
544 return -EINVAL;
545 }
546 }
547
548 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
549
550 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
551 if (ret < 0)
552 return ret;
553
554 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
555
556 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
557 if (ret < 0)
558 return ret;
559
560 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
982df6ae 561 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
eadff302
II		 562
563 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
564 if (ret < 0)
565 return ret;
566
223463fc
FW		 567 if (pad->dtest_buffer == 0) {
568 val = 0;
569 } else {
570 if (pad->lv_mv_type) {
571 val = pad->dtest_buffer - 1;
572 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
573 } else {
574 val = BIT(pad->dtest_buffer - 1);
575 }
576 }
577 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
578 if (ret < 0)
579 return ret;
580
d7b5f5cc
FW		 581 if (pad->analog_pass)
582 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
583 else if (pad->output_enabled && pad->input_enabled)
584 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
585 else if (pad->output_enabled)
586 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
587 else
588 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
eadff302 589
d7b5f5cc
FW		 590 if (pad->lv_mv_type) {
591 ret = pmic_gpio_write(state, pad,
592 PMIC_GPIO_REG_MODE_CTL, val);
593 if (ret < 0)
594 return ret;
595
596 val = pad->atest - 1;
597 ret = pmic_gpio_write(state, pad,
598 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
599 if (ret < 0)
600 return ret;
601
602 val = pad->out_value
603 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
604 val |= pad->function
605 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
606 ret = pmic_gpio_write(state, pad,
607 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
608 if (ret < 0)
609 return ret;
610 } else {
611 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
612 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
613 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
eadff302 614
d7b5f5cc
FW		 615 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
616 if (ret < 0)
617 return ret;
618 }
619
6cb74f44
FW		 620 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
621
622 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
623
d7b5f5cc 624 return ret;
eadff302
II		 625}
626
627static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
628 struct seq_file *s, unsigned pin)
629{
630 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
631 struct pmic_gpio_pad *pad;
d7b5f5cc 632 int ret, val, function;
eadff302
II		 633
634 static const char *const biases[] = {
635 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
636 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
637 };
638 static const char *const buffer_types[] = {
639 "push-pull", "open-drain", "open-source"
640 };
641 static const char *const strengths[] = {
642 "no", "high", "medium", "low"
643 };
644
645 pad = pctldev->desc->pins[pin].drv_data;
646
647 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
648
649 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
650
651 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
652 seq_puts(s, " ---");
653 } else {
24a66618 654 if (pad->input_enabled) {
eadff302 655 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
24a66618
II		 656 if (ret < 0)
657 return;
658
659 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
660 pad->out_value = ret;
eadff302 661 }
d7b5f5cc
FW		 662 /*
663 * For the non-LV/MV subtypes only 2 special functions are
664 * available, offsetting the dtest function values by 2.
665 */
666 function = pad->function;
667 if (!pad->lv_mv_type &&
668 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
669 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
670 PMIC_GPIO_FUNC_INDEX_FUNC3;
671
672 if (pad->analog_pass)
673 seq_puts(s, " analog-pass");
674 else
675 seq_printf(s, " %-4s",
676 pad->output_enabled ? "out" : "in");
677 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
eadff302
II		 678 seq_printf(s, " vin-%d", pad->power_source);
679 seq_printf(s, " %-27s", biases[pad->pullup]);
680 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
681 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
682 seq_printf(s, " %-7s", strengths[pad->strength]);
d7b5f5cc 683 seq_printf(s, " atest-%d", pad->atest);
223463fc 684 seq_printf(s, " dtest-%d", pad->dtest_buffer);
eadff302
II		 685 }
686}
687
688static const struct pinconf_ops pmic_gpio_pinconf_ops = {
7382b623 689 .is_generic = true,
eadff302
II		 690 .pin_config_group_get = pmic_gpio_config_get,
691 .pin_config_group_set = pmic_gpio_config_set,
692 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
693};
694
695static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
696{
c52d9df1 697 struct pmic_gpio_state *state = gpiochip_get_data(chip);
eadff302
II		 698 unsigned long config;
699
700 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
701
702 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
703}
704
705static int pmic_gpio_direction_output(struct gpio_chip *chip,
706 unsigned pin, int val)
707{
c52d9df1 708 struct pmic_gpio_state *state = gpiochip_get_data(chip);
eadff302
II		 709 unsigned long config;
710
711 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
712
713 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
714}
715
716static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
717{
c52d9df1 718 struct pmic_gpio_state *state = gpiochip_get_data(chip);
eadff302
II		 719 struct pmic_gpio_pad *pad;
720 int ret;
721
722 pad = state->ctrl->desc->pins[pin].drv_data;
723
724 if (!pad->is_enabled)
725 return -EINVAL;
726
727 if (pad->input_enabled) {
728 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
729 if (ret < 0)
730 return ret;
731
732 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
733 }
734
86c1a219 735 return !!pad->out_value;
eadff302
II		 736}
737
738static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
739{
c52d9df1 740 struct pmic_gpio_state *state = gpiochip_get_data(chip);
eadff302
II		 741 unsigned long config;
742
743 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
744
745 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
746}
747
eadff302
II		 748static int pmic_gpio_of_xlate(struct gpio_chip *chip,
749 const struct of_phandle_args *gpio_desc,
750 u32 *flags)
751{
752 if (chip->of_gpio_n_cells < 2)
753 return -EINVAL;
754
755 if (flags)
756 *flags = gpio_desc->args[1];
757
758 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
759}
760
761static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
762{
c52d9df1 763 struct pmic_gpio_state *state = gpiochip_get_data(chip);
eadff302
II		 764 struct pmic_gpio_pad *pad;
765
766 pad = state->ctrl->desc->pins[pin].drv_data;
767
768 return pad->irq;
769}
770
771static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
772{
c52d9df1 773 struct pmic_gpio_state *state = gpiochip_get_data(chip);
eadff302
II		 774 unsigned i;
775
776 for (i = 0; i < chip->ngpio; i++) {
777 pmic_gpio_config_dbg_show(state->ctrl, s, i);
778 seq_puts(s, "\n");
779 }
780}
781
782static const struct gpio_chip pmic_gpio_gpio_template = {
783 .direction_input = pmic_gpio_direction_input,
784 .direction_output = pmic_gpio_direction_output,
785 .get = pmic_gpio_get,
786 .set = pmic_gpio_set,
98c85d58
JG		 787 .request = gpiochip_generic_request,
788 .free = gpiochip_generic_free,
eadff302
II		 789 .of_xlate = pmic_gpio_of_xlate,
790 .to_irq = pmic_gpio_to_irq,
791 .dbg_show = pmic_gpio_dbg_show,
792};
793
794static int pmic_gpio_populate(struct pmic_gpio_state *state,
795 struct pmic_gpio_pad *pad)
796{
797 int type, subtype, val, dir;
798
799 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
800 if (type < 0)
801 return type;
802
803 if (type != PMIC_GPIO_TYPE) {
804 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
805 type, pad->base);
806 return -ENODEV;
807 }
808
809 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
810 if (subtype < 0)
811 return subtype;
812
813 switch (subtype) {
814 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
815 pad->have_buffer = true;
816 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
817 pad->num_sources = 4;
818 break;
819 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
820 pad->have_buffer = true;
821 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
822 pad->num_sources = 8;
823 break;
d7b5f5cc
FW		 824 case PMIC_GPIO_SUBTYPE_GPIO_LV:
825 pad->num_sources = 1;
826 pad->have_buffer = true;
827 pad->lv_mv_type = true;
828 break;
829 case PMIC_GPIO_SUBTYPE_GPIO_MV:
830 pad->num_sources = 2;
831 pad->have_buffer = true;
832 pad->lv_mv_type = true;
833 break;
eadff302
II		 834 default:
835 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
836 return -ENODEV;
837 }
838
d7b5f5cc
FW		 839 if (pad->lv_mv_type) {
840 val = pmic_gpio_read(state, pad,
841 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
842 if (val < 0)
843 return val;
844
845 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
846 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
847
848 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
849 if (val < 0)
850 return val;
851
852 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
853 } else {
854 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
855 if (val < 0)
856 return val;
eadff302 857
d7b5f5cc
FW		 858 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
859
860 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
861 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
862 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
863 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
864 }
eadff302 865
eadff302 866 switch (dir) {
d7b5f5cc 867 case PMIC_GPIO_MODE_DIGITAL_INPUT:
eadff302
II		 868 pad->input_enabled = true;
869 pad->output_enabled = false;
870 break;
d7b5f5cc 871 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
eadff302
II		 872 pad->input_enabled = false;
873 pad->output_enabled = true;
874 break;
d7b5f5cc 875 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
eadff302
II		 876 pad->input_enabled = true;
877 pad->output_enabled = true;
878 break;
d7b5f5cc
FW		 879 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
880 if (!pad->lv_mv_type)
881 return -ENODEV;
882 pad->analog_pass = true;
883 break;
eadff302
II		 884 default:
885 dev_err(state->dev, "unknown GPIO direction\n");
886 return -ENODEV;
887 }
888
eadff302
II		 889 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
890 if (val < 0)
891 return val;
892
893 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
894 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
895
896 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
897 if (val < 0)
898 return val;
899
900 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
901 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
902
223463fc
FW		 903 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
904 if (val < 0)
905 return val;
906
907 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
908 pad->dtest_buffer =
909 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
910 else if (!pad->lv_mv_type)
911 pad->dtest_buffer = ffs(val);
912 else
913 pad->dtest_buffer = 0;
914
915 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
916 if (val < 0)
917 return val;
918
eadff302
II		 919 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
920 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
921
922 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
923 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
924
d7b5f5cc
FW		 925 if (pad->lv_mv_type) {
926 val = pmic_gpio_read(state, pad,
927 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
928 if (val < 0)
929 return val;
930 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
931 }
932
eadff302
II		 933 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
934 pad->is_enabled = true;
935 return 0;
936}
937
938static int pmic_gpio_probe(struct platform_device *pdev)
939{
940 struct device *dev = &pdev->dev;
941 struct pinctrl_pin_desc *pindesc;
942 struct pinctrl_desc *pctrldesc;
943 struct pmic_gpio_pad *pad, *pads;
944 struct pmic_gpio_state *state;
945 int ret, npins, i;
ab4256cf 946 u32 reg;
eadff302 947
ab4256cf 948 ret = of_property_read_u32(dev->of_node, "reg", &reg);
eadff302 949 if (ret < 0) {
ab4256cf 950 dev_err(dev, "missing base address");
eadff302
II		 951 return ret;
952 }
953
a5ea13f0 954 npins = platform_irq_count(pdev);
eadff302
II		 955 if (!npins)
956 return -EINVAL;
a5ea13f0
SB		 957 if (npins < 0)
958 return npins;
eadff302
II		 959
960 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
961
962 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
963 if (!state)
964 return -ENOMEM;
965
966 platform_set_drvdata(pdev, state);
967
968 state->dev = &pdev->dev;
969 state->map = dev_get_regmap(dev->parent, NULL);
970
971 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
972 if (!pindesc)
973 return -ENOMEM;
974
975 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
976 if (!pads)
977 return -ENOMEM;
978
979 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
980 if (!pctrldesc)
981 return -ENOMEM;
982
983 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
984 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
985 pctrldesc->confops = &pmic_gpio_pinconf_ops;
986 pctrldesc->owner = THIS_MODULE;
987 pctrldesc->name = dev_name(dev);
988 pctrldesc->pins = pindesc;
989 pctrldesc->npins = npins;
f684e4ac
LW		 990 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
991 pctrldesc->custom_params = pmic_gpio_bindings;
4f06266a 992#ifdef CONFIG_DEBUG_FS
f684e4ac 993 pctrldesc->custom_conf_items = pmic_conf_items;
4f06266a 994#endif
eadff302
II		 995
996 for (i = 0; i < npins; i++, pindesc++) {
997 pad = &pads[i];
998 pindesc->drv_data = pad;
999 pindesc->number = i;
1000 pindesc->name = pmic_gpio_groups[i];
1001
1002 pad->irq = platform_get_irq(pdev, i);
1003 if (pad->irq < 0)
1004 return pad->irq;
1005
ab4256cf 1006 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
eadff302
II		 1007
1008 ret = pmic_gpio_populate(state, pad);
1009 if (ret < 0)
1010 return ret;
1011 }
1012
1013 state->chip = pmic_gpio_gpio_template;
58383c78 1014 state->chip.parent = dev;
eadff302
II		 1015 state->chip.base = -1;
1016 state->chip.ngpio = npins;
1017 state->chip.label = dev_name(dev);
1018 state->chip.of_gpio_n_cells = 2;
1019 state->chip.can_sleep = false;
1020
b46ddfe6 1021 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
323de9ef
MY		 1022 if (IS_ERR(state->ctrl))
1023 return PTR_ERR(state->ctrl);
eadff302 1024
c52d9df1 1025 ret = gpiochip_add_data(&state->chip, state);
eadff302
II		 1026 if (ret) {
1027 dev_err(state->dev, "can't add gpio chip\n");
b46ddfe6 1028 return ret;
eadff302
II		 1029 }
1030
1031 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
1032 if (ret) {
1033 dev_err(dev, "failed to add pin range\n");
1034 goto err_range;
1035 }
1036
1037 return 0;
1038
1039err_range:
1040 gpiochip_remove(&state->chip);
eadff302
II		 1041 return ret;
1042}
1043
1044static int pmic_gpio_remove(struct platform_device *pdev)
1045{
1046 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1047
1048 gpiochip_remove(&state->chip);
eadff302
II		 1049 return 0;
1050}
1051
1052static const struct of_device_id pmic_gpio_of_match[] = {
7414b099 1053 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
eadff302 1054 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
016c2f4d 1055 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
8d6cfb14 1056 { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */
eadff302 1057 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
647dbd1e 1058 { .compatible = "qcom,spmi-gpio" }, /* Generic */
eadff302
II		 1059 { },
1060};
1061
1062MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1063
1064static struct platform_driver pmic_gpio_driver = {
1065 .driver = {
1066 .name = "qcom-spmi-gpio",
1067 .of_match_table = pmic_gpio_of_match,
1068 },
1069 .probe = pmic_gpio_probe,
1070 .remove = pmic_gpio_remove,
1071};
1072
1073module_platform_driver(pmic_gpio_driver);
1074
1075MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1076MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1077MODULE_ALIAS("platform:qcom-spmi-gpio");
1078MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)