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b915395c DT |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2018, The Linux Foundation. All rights reserved. | |
4 | * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com> | |
5 | */ | |
6 | ||
7 | #include <linux/module.h> | |
8 | #include <linux/of.h> | |
9 | #include <linux/platform_device.h> | |
10 | #include <linux/pinctrl/pinctrl.h> | |
11 | ||
12 | #include "pinctrl-msm.h" | |
13 | ||
14 | static const char * const sm7150_tiles[] = { | |
15 | "north", | |
16 | "south", | |
17 | "west", | |
18 | }; | |
19 | ||
20 | enum { | |
21 | NORTH, | |
22 | SOUTH, | |
23 | WEST | |
24 | }; | |
25 | ||
b915395c DT |
26 | #define REG_SIZE 0x1000 |
27 | ||
28 | #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ | |
29 | { \ | |
6a16d1a5 RA |
30 | .grp = PINCTRL_PINGROUP("gpio" #id, \ |
31 | gpio##id##_pins, \ | |
32 | ARRAY_SIZE(gpio##id##_pins)), \ | |
b915395c DT |
33 | .funcs = (int[]){ \ |
34 | msm_mux_gpio, /* gpio mode */ \ | |
35 | msm_mux_##f1, \ | |
36 | msm_mux_##f2, \ | |
37 | msm_mux_##f3, \ | |
38 | msm_mux_##f4, \ | |
39 | msm_mux_##f5, \ | |
40 | msm_mux_##f6, \ | |
41 | msm_mux_##f7, \ | |
42 | msm_mux_##f8, \ | |
43 | msm_mux_##f9 \ | |
44 | }, \ | |
45 | .nfuncs = 10, \ | |
46 | .ctl_reg = REG_SIZE * id, \ | |
47 | .io_reg = 0x4 + REG_SIZE * id, \ | |
48 | .intr_cfg_reg = 0x8 + REG_SIZE * id, \ | |
49 | .intr_status_reg = 0xc + REG_SIZE * id, \ | |
50 | .intr_target_reg = 0x8 + REG_SIZE * id, \ | |
51 | .tile = _tile, \ | |
52 | .mux_bit = 2, \ | |
53 | .pull_bit = 0, \ | |
54 | .drv_bit = 6, \ | |
55 | .oe_bit = 9, \ | |
56 | .in_bit = 0, \ | |
57 | .out_bit = 1, \ | |
58 | .intr_enable_bit = 0, \ | |
59 | .intr_status_bit = 0, \ | |
60 | .intr_target_bit = 5, \ | |
61 | .intr_target_kpss_val = 3, \ | |
62 | .intr_raw_status_bit = 4, \ | |
63 | .intr_polarity_bit = 1, \ | |
64 | .intr_detection_bit = 2, \ | |
65 | .intr_detection_width = 2, \ | |
66 | } | |
67 | ||
5ed79863 | 68 | #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ |
b915395c | 69 | { \ |
6a16d1a5 RA |
70 | .grp = PINCTRL_PINGROUP(#pg_name, \ |
71 | pg_name##_pins, \ | |
72 | ARRAY_SIZE(pg_name##_pins)), \ | |
b915395c DT |
73 | .ctl_reg = ctl, \ |
74 | .io_reg = 0, \ | |
75 | .intr_cfg_reg = 0, \ | |
76 | .intr_status_reg = 0, \ | |
77 | .intr_target_reg = 0, \ | |
5ed79863 | 78 | .tile = _tile, \ |
b915395c DT |
79 | .mux_bit = -1, \ |
80 | .pull_bit = pull, \ | |
81 | .drv_bit = drv, \ | |
82 | .oe_bit = -1, \ | |
83 | .in_bit = -1, \ | |
84 | .out_bit = -1, \ | |
85 | .intr_enable_bit = -1, \ | |
86 | .intr_status_bit = -1, \ | |
87 | .intr_target_bit = -1, \ | |
88 | .intr_raw_status_bit = -1, \ | |
89 | .intr_polarity_bit = -1, \ | |
90 | .intr_detection_bit = -1, \ | |
91 | .intr_detection_width = -1, \ | |
92 | } | |
93 | ||
94 | #define UFS_RESET(pg_name, offset) \ | |
95 | { \ | |
6a16d1a5 RA |
96 | .grp = PINCTRL_PINGROUP(#pg_name, \ |
97 | pg_name##_pins, \ | |
98 | ARRAY_SIZE(pg_name##_pins)), \ | |
b915395c DT |
99 | .ctl_reg = offset, \ |
100 | .io_reg = offset + 0x4, \ | |
101 | .intr_cfg_reg = 0, \ | |
102 | .intr_status_reg = 0, \ | |
103 | .intr_target_reg = 0, \ | |
5ed79863 | 104 | .tile = WEST, \ |
b915395c DT |
105 | .mux_bit = -1, \ |
106 | .pull_bit = 3, \ | |
107 | .drv_bit = 0, \ | |
108 | .oe_bit = -1, \ | |
109 | .in_bit = -1, \ | |
110 | .out_bit = 0, \ | |
111 | .intr_enable_bit = -1, \ | |
112 | .intr_status_bit = -1, \ | |
113 | .intr_target_bit = -1, \ | |
114 | .intr_raw_status_bit = -1, \ | |
115 | .intr_polarity_bit = -1, \ | |
116 | .intr_detection_bit = -1, \ | |
117 | .intr_detection_width = -1, \ | |
118 | } | |
119 | ||
120 | static const struct pinctrl_pin_desc sm7150_pins[] = { | |
121 | PINCTRL_PIN(0, "GPIO_0"), | |
122 | PINCTRL_PIN(1, "GPIO_1"), | |
123 | PINCTRL_PIN(2, "GPIO_2"), | |
124 | PINCTRL_PIN(3, "GPIO_3"), | |
125 | PINCTRL_PIN(4, "GPIO_4"), | |
126 | PINCTRL_PIN(5, "GPIO_5"), | |
127 | PINCTRL_PIN(6, "GPIO_6"), | |
128 | PINCTRL_PIN(7, "GPIO_7"), | |
129 | PINCTRL_PIN(8, "GPIO_8"), | |
130 | PINCTRL_PIN(9, "GPIO_9"), | |
131 | PINCTRL_PIN(10, "GPIO_10"), | |
132 | PINCTRL_PIN(11, "GPIO_11"), | |
133 | PINCTRL_PIN(12, "GPIO_12"), | |
134 | PINCTRL_PIN(13, "GPIO_13"), | |
135 | PINCTRL_PIN(14, "GPIO_14"), | |
136 | PINCTRL_PIN(15, "GPIO_15"), | |
137 | PINCTRL_PIN(16, "GPIO_16"), | |
138 | PINCTRL_PIN(17, "GPIO_17"), | |
139 | PINCTRL_PIN(18, "GPIO_18"), | |
140 | PINCTRL_PIN(19, "GPIO_19"), | |
141 | PINCTRL_PIN(20, "GPIO_20"), | |
142 | PINCTRL_PIN(21, "GPIO_21"), | |
143 | PINCTRL_PIN(22, "GPIO_22"), | |
144 | PINCTRL_PIN(23, "GPIO_23"), | |
145 | PINCTRL_PIN(24, "GPIO_24"), | |
146 | PINCTRL_PIN(25, "GPIO_25"), | |
147 | PINCTRL_PIN(26, "GPIO_26"), | |
148 | PINCTRL_PIN(27, "GPIO_27"), | |
149 | PINCTRL_PIN(28, "GPIO_28"), | |
150 | PINCTRL_PIN(29, "GPIO_29"), | |
151 | PINCTRL_PIN(30, "GPIO_30"), | |
152 | PINCTRL_PIN(31, "GPIO_31"), | |
153 | PINCTRL_PIN(32, "GPIO_32"), | |
154 | PINCTRL_PIN(33, "GPIO_33"), | |
155 | PINCTRL_PIN(34, "GPIO_34"), | |
156 | PINCTRL_PIN(35, "GPIO_35"), | |
157 | PINCTRL_PIN(36, "GPIO_36"), | |
158 | PINCTRL_PIN(37, "GPIO_37"), | |
159 | PINCTRL_PIN(38, "GPIO_38"), | |
160 | PINCTRL_PIN(39, "GPIO_39"), | |
161 | PINCTRL_PIN(40, "GPIO_40"), | |
162 | PINCTRL_PIN(41, "GPIO_41"), | |
163 | PINCTRL_PIN(42, "GPIO_42"), | |
164 | PINCTRL_PIN(43, "GPIO_43"), | |
165 | PINCTRL_PIN(44, "GPIO_44"), | |
166 | PINCTRL_PIN(45, "GPIO_45"), | |
167 | PINCTRL_PIN(46, "GPIO_46"), | |
168 | PINCTRL_PIN(47, "GPIO_47"), | |
169 | PINCTRL_PIN(48, "GPIO_48"), | |
170 | PINCTRL_PIN(49, "GPIO_49"), | |
171 | PINCTRL_PIN(50, "GPIO_50"), | |
172 | PINCTRL_PIN(51, "GPIO_51"), | |
173 | PINCTRL_PIN(52, "GPIO_52"), | |
174 | PINCTRL_PIN(53, "GPIO_53"), | |
175 | PINCTRL_PIN(54, "GPIO_54"), | |
176 | PINCTRL_PIN(55, "GPIO_55"), | |
177 | PINCTRL_PIN(56, "GPIO_56"), | |
178 | PINCTRL_PIN(57, "GPIO_57"), | |
179 | PINCTRL_PIN(58, "GPIO_58"), | |
180 | PINCTRL_PIN(59, "GPIO_59"), | |
181 | PINCTRL_PIN(60, "GPIO_60"), | |
182 | PINCTRL_PIN(61, "GPIO_61"), | |
183 | PINCTRL_PIN(62, "GPIO_62"), | |
184 | PINCTRL_PIN(63, "GPIO_63"), | |
185 | PINCTRL_PIN(64, "GPIO_64"), | |
186 | PINCTRL_PIN(65, "GPIO_65"), | |
187 | PINCTRL_PIN(66, "GPIO_66"), | |
188 | PINCTRL_PIN(67, "GPIO_67"), | |
189 | PINCTRL_PIN(68, "GPIO_68"), | |
190 | PINCTRL_PIN(69, "GPIO_69"), | |
191 | PINCTRL_PIN(70, "GPIO_70"), | |
192 | PINCTRL_PIN(71, "GPIO_71"), | |
193 | PINCTRL_PIN(72, "GPIO_72"), | |
194 | PINCTRL_PIN(73, "GPIO_73"), | |
195 | PINCTRL_PIN(74, "GPIO_74"), | |
196 | PINCTRL_PIN(75, "GPIO_75"), | |
197 | PINCTRL_PIN(76, "GPIO_76"), | |
198 | PINCTRL_PIN(77, "GPIO_77"), | |
199 | PINCTRL_PIN(78, "GPIO_78"), | |
200 | PINCTRL_PIN(79, "GPIO_79"), | |
201 | PINCTRL_PIN(80, "GPIO_80"), | |
202 | PINCTRL_PIN(81, "GPIO_81"), | |
203 | PINCTRL_PIN(82, "GPIO_82"), | |
204 | PINCTRL_PIN(83, "GPIO_83"), | |
205 | PINCTRL_PIN(84, "GPIO_84"), | |
206 | PINCTRL_PIN(85, "GPIO_85"), | |
207 | PINCTRL_PIN(86, "GPIO_86"), | |
208 | PINCTRL_PIN(87, "GPIO_87"), | |
209 | PINCTRL_PIN(88, "GPIO_88"), | |
210 | PINCTRL_PIN(89, "GPIO_89"), | |
211 | PINCTRL_PIN(90, "GPIO_90"), | |
212 | PINCTRL_PIN(91, "GPIO_91"), | |
213 | PINCTRL_PIN(92, "GPIO_92"), | |
214 | PINCTRL_PIN(93, "GPIO_93"), | |
215 | PINCTRL_PIN(94, "GPIO_94"), | |
216 | PINCTRL_PIN(95, "GPIO_95"), | |
217 | PINCTRL_PIN(96, "GPIO_96"), | |
218 | PINCTRL_PIN(97, "GPIO_97"), | |
219 | PINCTRL_PIN(98, "GPIO_98"), | |
220 | PINCTRL_PIN(99, "GPIO_99"), | |
221 | PINCTRL_PIN(100, "GPIO_100"), | |
222 | PINCTRL_PIN(101, "GPIO_101"), | |
223 | PINCTRL_PIN(102, "GPIO_102"), | |
224 | PINCTRL_PIN(103, "GPIO_103"), | |
225 | PINCTRL_PIN(104, "GPIO_104"), | |
226 | PINCTRL_PIN(105, "GPIO_105"), | |
227 | PINCTRL_PIN(106, "GPIO_106"), | |
228 | PINCTRL_PIN(107, "GPIO_107"), | |
229 | PINCTRL_PIN(108, "GPIO_108"), | |
230 | PINCTRL_PIN(109, "GPIO_109"), | |
231 | PINCTRL_PIN(110, "GPIO_110"), | |
232 | PINCTRL_PIN(111, "GPIO_111"), | |
233 | PINCTRL_PIN(112, "GPIO_112"), | |
234 | PINCTRL_PIN(113, "GPIO_113"), | |
235 | PINCTRL_PIN(114, "GPIO_114"), | |
236 | PINCTRL_PIN(115, "GPIO_115"), | |
237 | PINCTRL_PIN(116, "GPIO_116"), | |
238 | PINCTRL_PIN(117, "GPIO_117"), | |
239 | PINCTRL_PIN(118, "GPIO_118"), | |
240 | PINCTRL_PIN(119, "UFS_RESET"), | |
241 | PINCTRL_PIN(120, "SDC1_RCLK"), | |
242 | PINCTRL_PIN(121, "SDC1_CLK"), | |
243 | PINCTRL_PIN(122, "SDC1_CMD"), | |
244 | PINCTRL_PIN(123, "SDC1_DATA"), | |
245 | PINCTRL_PIN(124, "SDC2_CLK"), | |
246 | PINCTRL_PIN(125, "SDC2_CMD"), | |
247 | PINCTRL_PIN(126, "SDC2_DATA"), | |
248 | ||
249 | }; | |
250 | ||
251 | #define DECLARE_MSM_GPIO_PINS(pin) \ | |
252 | static const unsigned int gpio##pin##_pins[] = { pin } | |
253 | DECLARE_MSM_GPIO_PINS(0); | |
254 | DECLARE_MSM_GPIO_PINS(1); | |
255 | DECLARE_MSM_GPIO_PINS(2); | |
256 | DECLARE_MSM_GPIO_PINS(3); | |
257 | DECLARE_MSM_GPIO_PINS(4); | |
258 | DECLARE_MSM_GPIO_PINS(5); | |
259 | DECLARE_MSM_GPIO_PINS(6); | |
260 | DECLARE_MSM_GPIO_PINS(7); | |
261 | DECLARE_MSM_GPIO_PINS(8); | |
262 | DECLARE_MSM_GPIO_PINS(9); | |
263 | DECLARE_MSM_GPIO_PINS(10); | |
264 | DECLARE_MSM_GPIO_PINS(11); | |
265 | DECLARE_MSM_GPIO_PINS(12); | |
266 | DECLARE_MSM_GPIO_PINS(13); | |
267 | DECLARE_MSM_GPIO_PINS(14); | |
268 | DECLARE_MSM_GPIO_PINS(15); | |
269 | DECLARE_MSM_GPIO_PINS(16); | |
270 | DECLARE_MSM_GPIO_PINS(17); | |
271 | DECLARE_MSM_GPIO_PINS(18); | |
272 | DECLARE_MSM_GPIO_PINS(19); | |
273 | DECLARE_MSM_GPIO_PINS(20); | |
274 | DECLARE_MSM_GPIO_PINS(21); | |
275 | DECLARE_MSM_GPIO_PINS(22); | |
276 | DECLARE_MSM_GPIO_PINS(23); | |
277 | DECLARE_MSM_GPIO_PINS(24); | |
278 | DECLARE_MSM_GPIO_PINS(25); | |
279 | DECLARE_MSM_GPIO_PINS(26); | |
280 | DECLARE_MSM_GPIO_PINS(27); | |
281 | DECLARE_MSM_GPIO_PINS(28); | |
282 | DECLARE_MSM_GPIO_PINS(29); | |
283 | DECLARE_MSM_GPIO_PINS(30); | |
284 | DECLARE_MSM_GPIO_PINS(31); | |
285 | DECLARE_MSM_GPIO_PINS(32); | |
286 | DECLARE_MSM_GPIO_PINS(33); | |
287 | DECLARE_MSM_GPIO_PINS(34); | |
288 | DECLARE_MSM_GPIO_PINS(35); | |
289 | DECLARE_MSM_GPIO_PINS(36); | |
290 | DECLARE_MSM_GPIO_PINS(37); | |
291 | DECLARE_MSM_GPIO_PINS(38); | |
292 | DECLARE_MSM_GPIO_PINS(39); | |
293 | DECLARE_MSM_GPIO_PINS(40); | |
294 | DECLARE_MSM_GPIO_PINS(41); | |
295 | DECLARE_MSM_GPIO_PINS(42); | |
296 | DECLARE_MSM_GPIO_PINS(43); | |
297 | DECLARE_MSM_GPIO_PINS(44); | |
298 | DECLARE_MSM_GPIO_PINS(45); | |
299 | DECLARE_MSM_GPIO_PINS(46); | |
300 | DECLARE_MSM_GPIO_PINS(47); | |
301 | DECLARE_MSM_GPIO_PINS(48); | |
302 | DECLARE_MSM_GPIO_PINS(49); | |
303 | DECLARE_MSM_GPIO_PINS(50); | |
304 | DECLARE_MSM_GPIO_PINS(51); | |
305 | DECLARE_MSM_GPIO_PINS(52); | |
306 | DECLARE_MSM_GPIO_PINS(53); | |
307 | DECLARE_MSM_GPIO_PINS(54); | |
308 | DECLARE_MSM_GPIO_PINS(55); | |
309 | DECLARE_MSM_GPIO_PINS(56); | |
310 | DECLARE_MSM_GPIO_PINS(57); | |
311 | DECLARE_MSM_GPIO_PINS(58); | |
312 | DECLARE_MSM_GPIO_PINS(59); | |
313 | DECLARE_MSM_GPIO_PINS(60); | |
314 | DECLARE_MSM_GPIO_PINS(61); | |
315 | DECLARE_MSM_GPIO_PINS(62); | |
316 | DECLARE_MSM_GPIO_PINS(63); | |
317 | DECLARE_MSM_GPIO_PINS(64); | |
318 | DECLARE_MSM_GPIO_PINS(65); | |
319 | DECLARE_MSM_GPIO_PINS(66); | |
320 | DECLARE_MSM_GPIO_PINS(67); | |
321 | DECLARE_MSM_GPIO_PINS(68); | |
322 | DECLARE_MSM_GPIO_PINS(69); | |
323 | DECLARE_MSM_GPIO_PINS(70); | |
324 | DECLARE_MSM_GPIO_PINS(71); | |
325 | DECLARE_MSM_GPIO_PINS(72); | |
326 | DECLARE_MSM_GPIO_PINS(73); | |
327 | DECLARE_MSM_GPIO_PINS(74); | |
328 | DECLARE_MSM_GPIO_PINS(75); | |
329 | DECLARE_MSM_GPIO_PINS(76); | |
330 | DECLARE_MSM_GPIO_PINS(77); | |
331 | DECLARE_MSM_GPIO_PINS(78); | |
332 | DECLARE_MSM_GPIO_PINS(79); | |
333 | DECLARE_MSM_GPIO_PINS(80); | |
334 | DECLARE_MSM_GPIO_PINS(81); | |
335 | DECLARE_MSM_GPIO_PINS(82); | |
336 | DECLARE_MSM_GPIO_PINS(83); | |
337 | DECLARE_MSM_GPIO_PINS(84); | |
338 | DECLARE_MSM_GPIO_PINS(85); | |
339 | DECLARE_MSM_GPIO_PINS(86); | |
340 | DECLARE_MSM_GPIO_PINS(87); | |
341 | DECLARE_MSM_GPIO_PINS(88); | |
342 | DECLARE_MSM_GPIO_PINS(89); | |
343 | DECLARE_MSM_GPIO_PINS(90); | |
344 | DECLARE_MSM_GPIO_PINS(91); | |
345 | DECLARE_MSM_GPIO_PINS(92); | |
346 | DECLARE_MSM_GPIO_PINS(93); | |
347 | DECLARE_MSM_GPIO_PINS(94); | |
348 | DECLARE_MSM_GPIO_PINS(95); | |
349 | DECLARE_MSM_GPIO_PINS(96); | |
350 | DECLARE_MSM_GPIO_PINS(97); | |
351 | DECLARE_MSM_GPIO_PINS(98); | |
352 | DECLARE_MSM_GPIO_PINS(99); | |
353 | DECLARE_MSM_GPIO_PINS(100); | |
354 | DECLARE_MSM_GPIO_PINS(101); | |
355 | DECLARE_MSM_GPIO_PINS(102); | |
356 | DECLARE_MSM_GPIO_PINS(103); | |
357 | DECLARE_MSM_GPIO_PINS(104); | |
358 | DECLARE_MSM_GPIO_PINS(105); | |
359 | DECLARE_MSM_GPIO_PINS(106); | |
360 | DECLARE_MSM_GPIO_PINS(107); | |
361 | DECLARE_MSM_GPIO_PINS(108); | |
362 | DECLARE_MSM_GPIO_PINS(109); | |
363 | DECLARE_MSM_GPIO_PINS(110); | |
364 | DECLARE_MSM_GPIO_PINS(111); | |
365 | DECLARE_MSM_GPIO_PINS(112); | |
366 | DECLARE_MSM_GPIO_PINS(113); | |
367 | DECLARE_MSM_GPIO_PINS(114); | |
368 | DECLARE_MSM_GPIO_PINS(115); | |
369 | DECLARE_MSM_GPIO_PINS(116); | |
370 | DECLARE_MSM_GPIO_PINS(117); | |
371 | DECLARE_MSM_GPIO_PINS(118); | |
372 | ||
373 | static const unsigned int ufs_reset_pins[] = { 119 }; | |
374 | static const unsigned int sdc1_rclk_pins[] = { 120 }; | |
375 | static const unsigned int sdc1_clk_pins[] = { 121 }; | |
376 | static const unsigned int sdc1_cmd_pins[] = { 122 }; | |
377 | static const unsigned int sdc1_data_pins[] = { 123 }; | |
378 | static const unsigned int sdc2_clk_pins[] = { 124 }; | |
379 | static const unsigned int sdc2_cmd_pins[] = { 125 }; | |
380 | static const unsigned int sdc2_data_pins[] = { 126 }; | |
381 | ||
382 | enum sm7150_functions { | |
383 | msm_mux_gpio, | |
384 | msm_mux_adsp_ext, | |
385 | msm_mux_agera_pll, | |
386 | msm_mux_aoss_cti, | |
387 | msm_mux_atest_char, | |
388 | msm_mux_atest_tsens, | |
389 | msm_mux_atest_tsens2, | |
390 | msm_mux_atest_usb1, | |
391 | msm_mux_atest_usb2, | |
392 | msm_mux_cam_mclk, | |
393 | msm_mux_cci_async, | |
394 | msm_mux_cci_i2c, | |
395 | msm_mux_cci_timer0, | |
396 | msm_mux_cci_timer1, | |
397 | msm_mux_cci_timer2, | |
398 | msm_mux_cci_timer3, | |
399 | msm_mux_cci_timer4, | |
400 | msm_mux_dbg_out, | |
401 | msm_mux_ddr_bist, | |
402 | msm_mux_ddr_pxi0, | |
403 | msm_mux_ddr_pxi1, | |
404 | msm_mux_ddr_pxi2, | |
405 | msm_mux_ddr_pxi3, | |
406 | msm_mux_edp_hot, | |
407 | msm_mux_edp_lcd, | |
408 | msm_mux_gcc_gp1, | |
409 | msm_mux_gcc_gp2, | |
410 | msm_mux_gcc_gp3, | |
411 | msm_mux_gp_pdm0, | |
412 | msm_mux_gp_pdm1, | |
413 | msm_mux_gp_pdm2, | |
414 | msm_mux_gps_tx, | |
415 | msm_mux_jitter_bist, | |
416 | msm_mux_ldo_en, | |
417 | msm_mux_ldo_update, | |
418 | msm_mux_m_voc, | |
419 | msm_mux_mdp_vsync, | |
420 | msm_mux_mdp_vsync0, | |
421 | msm_mux_mdp_vsync1, | |
422 | msm_mux_mdp_vsync2, | |
423 | msm_mux_mdp_vsync3, | |
424 | msm_mux_mss_lte, | |
425 | msm_mux_nav_pps_in, | |
426 | msm_mux_nav_pps_out, | |
427 | msm_mux_pa_indicator, | |
428 | msm_mux_pci_e, | |
429 | msm_mux_phase_flag, | |
430 | msm_mux_pll_bist, | |
431 | msm_mux_pll_bypassnl, | |
432 | msm_mux_pll_reset, | |
433 | msm_mux_pri_mi2s, | |
434 | msm_mux_pri_mi2s_ws, | |
435 | msm_mux_prng_rosc, | |
436 | msm_mux_qdss, | |
437 | msm_mux_qdss_cti, | |
438 | msm_mux_qlink_enable, | |
439 | msm_mux_qlink_request, | |
440 | msm_mux_qua_mi2s, | |
441 | msm_mux_qup00, | |
442 | msm_mux_qup01, | |
443 | msm_mux_qup02, | |
444 | msm_mux_qup03, | |
445 | msm_mux_qup04, | |
446 | msm_mux_qup10, | |
447 | msm_mux_qup11, | |
448 | msm_mux_qup12, | |
449 | msm_mux_qup13, | |
450 | msm_mux_qup14, | |
451 | msm_mux_qup15, | |
452 | msm_mux_sd_write, | |
453 | msm_mux_sdc40, | |
454 | msm_mux_sdc41, | |
455 | msm_mux_sdc42, | |
456 | msm_mux_sdc43, | |
457 | msm_mux_sdc4_clk, | |
458 | msm_mux_sdc4_cmd, | |
459 | msm_mux_sec_mi2s, | |
460 | msm_mux_ter_mi2s, | |
461 | msm_mux_tgu_ch0, | |
462 | msm_mux_tgu_ch1, | |
463 | msm_mux_tgu_ch2, | |
464 | msm_mux_tgu_ch3, | |
465 | msm_mux_tsif1_clk, | |
466 | msm_mux_tsif1_data, | |
467 | msm_mux_tsif1_en, | |
468 | msm_mux_tsif1_error, | |
469 | msm_mux_tsif1_sync, | |
470 | msm_mux_tsif2_clk, | |
471 | msm_mux_tsif2_data, | |
472 | msm_mux_tsif2_en, | |
473 | msm_mux_tsif2_error, | |
474 | msm_mux_tsif2_sync, | |
475 | msm_mux_uim1_clk, | |
476 | msm_mux_uim1_data, | |
477 | msm_mux_uim1_present, | |
478 | msm_mux_uim1_reset, | |
479 | msm_mux_uim2_clk, | |
480 | msm_mux_uim2_data, | |
481 | msm_mux_uim2_present, | |
482 | msm_mux_uim2_reset, | |
483 | msm_mux_uim_batt, | |
484 | msm_mux_usb_phy, | |
485 | msm_mux_vfr_1, | |
486 | msm_mux_vsense_trigger, | |
487 | msm_mux_wlan1_adc0, | |
488 | msm_mux_wlan1_adc1, | |
489 | msm_mux_wlan2_adc0, | |
490 | msm_mux_wlan2_adc1, | |
491 | msm_mux_wsa_clk, | |
492 | msm_mux_wsa_data, | |
493 | msm_mux__, | |
494 | }; | |
495 | ||
496 | static const char * const gpio_groups[] = { | |
497 | "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", | |
498 | "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", | |
499 | "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", | |
500 | "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", | |
501 | "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", | |
502 | "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", | |
503 | "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", | |
504 | "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", | |
505 | "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", | |
506 | "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", | |
507 | "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", | |
508 | "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", | |
509 | "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", | |
510 | "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", | |
511 | "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", | |
512 | "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", | |
513 | "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", | |
514 | "gpio117", "gpio118", | |
515 | }; | |
516 | ||
517 | static const char * const adsp_ext_groups[] = { | |
518 | "gpio87", | |
519 | }; | |
520 | ||
521 | static const char * const agera_pll_groups[] = { | |
522 | "gpio28", | |
523 | }; | |
524 | ||
525 | static const char * const aoss_cti_groups[] = { | |
526 | "gpio85", | |
527 | }; | |
528 | ||
529 | static const char * const atest_char_groups[] = { | |
530 | "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", | |
531 | }; | |
532 | ||
533 | static const char * const atest_tsens_groups[] = { | |
534 | "gpio29", | |
535 | }; | |
536 | ||
537 | static const char * const atest_tsens2_groups[] = { | |
538 | "gpio7", | |
539 | }; | |
540 | ||
541 | static const char * const atest_usb1_groups[] = { | |
542 | "gpio7", "gpio10", "gpio11", "gpio39", "gpio44", | |
543 | }; | |
544 | ||
545 | static const char * const atest_usb2_groups[] = { | |
546 | "gpio51", "gpio52", "gpio53", "gpio54", "gpio55" | |
547 | }; | |
548 | ||
549 | static const char * const cam_mclk_groups[] = { | |
550 | "gpio13", "gpio14", "gpio15", "gpio16", | |
551 | }; | |
552 | ||
553 | static const char * const cci_async_groups[] = { | |
554 | "gpio24", "gpio25", "gpio26", | |
555 | }; | |
556 | ||
557 | static const char * const cci_i2c_groups[] = { | |
558 | "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28", | |
559 | }; | |
560 | ||
561 | static const char * const cci_timer0_groups[] = { | |
562 | "gpio21", | |
563 | }; | |
564 | ||
565 | static const char * const cci_timer1_groups[] = { | |
566 | "gpio22", | |
567 | }; | |
568 | ||
569 | static const char * const cci_timer2_groups[] = { | |
570 | "gpio23", | |
571 | }; | |
572 | ||
573 | static const char * const cci_timer3_groups[] = { | |
574 | "gpio24", | |
575 | }; | |
576 | ||
577 | static const char * const cci_timer4_groups[] = { | |
578 | "gpio25", | |
579 | }; | |
580 | ||
581 | static const char * const dbg_out_groups[] = { | |
582 | "gpio3", | |
583 | }; | |
584 | ||
585 | static const char * const ddr_bist_groups[] = { | |
586 | "gpio7", "gpio8", "gpio9", "gpio10", | |
587 | }; | |
588 | ||
589 | static const char * const ddr_pxi0_groups[] = { | |
590 | "gpio6", "gpio7", | |
591 | }; | |
592 | ||
593 | static const char * const ddr_pxi1_groups[] = { | |
594 | "gpio39", "gpio44", | |
595 | }; | |
596 | ||
597 | static const char * const ddr_pxi2_groups[] = { | |
598 | "gpio10", "gpio11", | |
599 | }; | |
600 | ||
601 | static const char * const ddr_pxi3_groups[] = { | |
602 | "gpio12", "gpio13", | |
603 | }; | |
604 | ||
605 | static const char * const edp_hot_groups[] = { | |
606 | "gpio85", | |
607 | }; | |
608 | ||
609 | static const char * const edp_lcd_groups[] = { | |
610 | "gpio11", | |
611 | }; | |
612 | ||
613 | static const char * const gcc_gp1_groups[] = { | |
614 | "gpio48", "gpio56", | |
615 | }; | |
616 | ||
617 | static const char * const gcc_gp2_groups[] = { | |
618 | "gpio21", | |
619 | }; | |
620 | ||
621 | static const char * const gcc_gp3_groups[] = { | |
622 | "gpio22", | |
623 | }; | |
624 | ||
625 | static const char * const gp_pdm0_groups[] = { | |
626 | "gpio37", "gpio68", | |
627 | }; | |
628 | ||
629 | static const char * const gp_pdm1_groups[] = { | |
630 | "gpio8", "gpio50", | |
631 | }; | |
632 | ||
633 | static const char * const gp_pdm2_groups[] = { | |
634 | "gpio57", | |
635 | }; | |
636 | ||
637 | static const char * const gps_tx_groups[] = { | |
638 | "gpio83", "gpio84", "gpio107", "gpio109", | |
639 | }; | |
640 | ||
641 | static const char * const jitter_bist_groups[] = { | |
642 | "gpio26", | |
643 | }; | |
644 | ||
645 | static const char * const ldo_en_groups[] = { | |
646 | "gpio70", | |
647 | }; | |
648 | ||
649 | static const char * const ldo_update_groups[] = { | |
650 | "gpio71", | |
651 | }; | |
652 | ||
653 | static const char * const m_voc_groups[] = { | |
654 | "gpio12", | |
655 | }; | |
656 | ||
657 | static const char * const mdp_vsync_groups[] = { | |
658 | "gpio10", "gpio11", "gpio12", "gpio70", "gpio71", | |
659 | }; | |
660 | ||
661 | static const char * const mdp_vsync0_groups[] = { | |
662 | "gpio63", | |
663 | }; | |
664 | ||
665 | static const char * const mdp_vsync1_groups[] = { | |
666 | "gpio63", | |
667 | }; | |
668 | ||
669 | static const char * const mdp_vsync2_groups[] = { | |
670 | "gpio63", | |
671 | }; | |
672 | ||
673 | static const char * const mdp_vsync3_groups[] = { | |
674 | "gpio63", | |
675 | }; | |
676 | ||
677 | static const char * const mss_lte_groups[] = { | |
678 | "gpio108", "gpio109", | |
679 | }; | |
680 | ||
681 | static const char * const nav_pps_in_groups[] = { | |
682 | "gpio83", "gpio84", "gpio107", | |
683 | }; | |
684 | ||
685 | static const char * const nav_pps_out_groups[] = { | |
686 | "gpio83", "gpio84", "gpio107", | |
687 | }; | |
688 | ||
689 | static const char * const pa_indicator_groups[] = { | |
690 | "gpio99", | |
691 | }; | |
692 | ||
693 | static const char * const pci_e_groups[] = { | |
694 | "gpio66", "gpio67", "gpio68", | |
695 | }; | |
696 | ||
697 | static const char * const phase_flag_groups[] = { | |
698 | "gpio0", "gpio1", "gpio2", "gpio6", "gpio7", "gpio10", "gpio11", | |
699 | "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio24", | |
700 | "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio35", | |
701 | "gpio36", "gpio37", "gpio38", "gpio39", "gpio43", "gpio44", "gpio56", | |
702 | "gpio57", "gpio60", "gpio61", "gpio62", | |
703 | }; | |
704 | ||
705 | static const char * const pll_bist_groups[] = { | |
706 | "gpio27", | |
707 | }; | |
708 | ||
709 | static const char * const pll_bypassnl_groups[] = { | |
710 | "gpio13", | |
711 | }; | |
712 | ||
713 | static const char * const pll_reset_groups[] = { | |
714 | "gpio14", | |
715 | }; | |
716 | ||
717 | static const char * const pri_mi2s_groups[] = { | |
718 | "gpio49", "gpio51", "gpio52", | |
719 | }; | |
720 | ||
721 | static const char * const pri_mi2s_ws_groups[] = { | |
722 | "gpio50", | |
723 | }; | |
724 | ||
725 | static const char * const prng_rosc_groups[] = { | |
726 | "gpio72", | |
727 | }; | |
728 | ||
729 | static const char * const qdss_groups[] = { | |
730 | "gpio13", "gpio86", "gpio14", "gpio87", "gpio15", "gpio88", "gpio16", | |
731 | "gpio89", "gpio17", "gpio90", "gpio18", "gpio91", "gpio19", "gpio34", | |
732 | "gpio20", "gpio35", "gpio21", "gpio53", "gpio22", "gpio30", "gpio23", | |
733 | "gpio54", "gpio24", "gpio55", "gpio25", "gpio57", "gpio26", "gpio31", | |
734 | "gpio27", "gpio56", "gpio28", "gpio36", "gpio29", "gpio37", "gpio93", | |
735 | "gpio104", | |
736 | }; | |
737 | ||
738 | static const char * const qdss_cti_groups[] = { | |
739 | "gpio4", "gpio5", "gpio32", "gpio44", "gpio45", "gpio63", | |
740 | }; | |
741 | ||
742 | static const char * const qlink_enable_groups[] = { | |
743 | "gpio97", | |
744 | }; | |
745 | ||
746 | static const char * const qlink_request_groups[] = { | |
747 | "gpio96", | |
748 | }; | |
749 | ||
750 | static const char * const qua_mi2s_groups[] = { | |
751 | "gpio58", | |
752 | }; | |
753 | ||
754 | static const char * const qup00_groups[] = { | |
755 | "gpio49", "gpio50", "gpio51", "gpio52", "gpio57", "gpio58", | |
756 | }; | |
757 | ||
758 | static const char * const qup01_groups[] = { | |
759 | "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio37", | |
760 | }; | |
761 | ||
762 | static const char * const qup02_groups[] = { | |
763 | "gpio34", "gpio35", | |
764 | }; | |
765 | ||
766 | static const char * const qup03_groups[] = { | |
767 | "gpio38", "gpio39", "gpio40", "gpio41", | |
768 | }; | |
769 | ||
770 | static const char * const qup04_groups[] = { | |
771 | "gpio53", "gpio54", "gpio55", "gpio56", | |
772 | }; | |
773 | ||
774 | static const char * const qup10_groups[] = { | |
775 | "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", | |
776 | }; | |
777 | ||
778 | static const char * const qup11_groups[] = { | |
779 | "gpio6", "gpio7", "gpio8", "gpio9", | |
780 | }; | |
781 | ||
782 | static const char * const qup12_groups[] = { | |
783 | "gpio42", "gpio43", "gpio44", "gpio45", | |
784 | }; | |
785 | ||
786 | static const char * const qup13_groups[] = { | |
787 | "gpio46", "gpio47", | |
788 | }; | |
789 | ||
790 | static const char * const qup14_groups[] = { | |
791 | "gpio110", "gpio111", "gpio112", "gpio113", | |
792 | }; | |
793 | ||
794 | static const char * const qup15_groups[] = { | |
795 | "gpio92", "gpio101", "gpio102", "gpio103", | |
796 | }; | |
797 | ||
798 | static const char * const sd_write_groups[] = { | |
799 | "gpio33", | |
800 | }; | |
801 | ||
802 | static const char * const sdc40_groups[] = { | |
803 | "gpio69", | |
804 | }; | |
805 | ||
806 | static const char * const sdc41_groups[] = { | |
807 | "gpio68", | |
808 | }; | |
809 | ||
810 | static const char * const sdc42_groups[] = { | |
811 | "gpio67", | |
812 | }; | |
813 | ||
814 | static const char * const sdc43_groups[] = { | |
815 | "gpio65", | |
816 | }; | |
817 | ||
818 | static const char * const sdc4_clk_groups[] = { | |
819 | "gpio66", | |
820 | }; | |
821 | ||
822 | static const char * const sdc4_cmd_groups[] = { | |
823 | "gpio64", | |
824 | }; | |
825 | ||
826 | static const char * const sec_mi2s_groups[] = { | |
827 | "gpio57", | |
828 | }; | |
829 | ||
830 | static const char * const ter_mi2s_groups[] = { | |
831 | "gpio53", "gpio54", "gpio55", "gpio56", | |
832 | }; | |
833 | ||
834 | static const char * const tgu_ch0_groups[] = { | |
835 | "gpio63", | |
836 | }; | |
837 | ||
838 | static const char * const tgu_ch1_groups[] = { | |
839 | "gpio64", | |
840 | }; | |
841 | ||
842 | static const char * const tgu_ch2_groups[] = { | |
843 | "gpio65", | |
844 | }; | |
845 | ||
846 | static const char * const tgu_ch3_groups[] = { | |
847 | "gpio62", | |
848 | }; | |
849 | ||
850 | static const char * const tsif1_clk_groups[] = { | |
851 | "gpio62", | |
852 | }; | |
853 | ||
854 | static const char * const tsif1_data_groups[] = { | |
855 | "gpio64", | |
856 | }; | |
857 | ||
858 | static const char * const tsif1_en_groups[] = { | |
859 | "gpio63", | |
860 | }; | |
861 | ||
862 | static const char * const tsif1_error_groups[] = { | |
863 | "gpio60", | |
864 | }; | |
865 | ||
866 | static const char * const tsif1_sync_groups[] = { | |
867 | "gpio61", | |
868 | }; | |
869 | ||
870 | static const char * const tsif2_clk_groups[] = { | |
871 | "gpio66", | |
872 | }; | |
873 | ||
874 | static const char * const tsif2_data_groups[] = { | |
875 | "gpio68", | |
876 | }; | |
877 | ||
878 | static const char * const tsif2_en_groups[] = { | |
879 | "gpio67", | |
880 | }; | |
881 | ||
882 | static const char * const tsif2_error_groups[] = { | |
883 | "gpio65", | |
884 | }; | |
885 | ||
886 | static const char * const tsif2_sync_groups[] = { | |
887 | "gpio69", | |
888 | }; | |
889 | ||
890 | static const char * const uim1_clk_groups[] = { | |
891 | "gpio80", | |
892 | }; | |
893 | ||
894 | static const char * const uim1_data_groups[] = { | |
895 | "gpio79", | |
896 | }; | |
897 | ||
898 | static const char * const uim1_present_groups[] = { | |
899 | "gpio82", | |
900 | }; | |
901 | ||
902 | static const char * const uim1_reset_groups[] = { | |
903 | "gpio81", | |
904 | }; | |
905 | ||
906 | static const char * const uim2_clk_groups[] = { | |
907 | "gpio76", | |
908 | }; | |
909 | ||
910 | static const char * const uim2_data_groups[] = { | |
911 | "gpio75", | |
912 | }; | |
913 | ||
914 | static const char * const uim2_present_groups[] = { | |
915 | "gpio78", | |
916 | }; | |
917 | ||
918 | static const char * const uim2_reset_groups[] = { | |
919 | "gpio77", | |
920 | }; | |
921 | ||
922 | static const char * const uim_batt_groups[] = { | |
923 | "gpio85", | |
924 | }; | |
925 | ||
926 | static const char * const usb_phy_groups[] = { | |
927 | "gpio104", | |
928 | }; | |
929 | ||
930 | static const char * const vfr_1_groups[] = { | |
931 | "gpio65", | |
932 | }; | |
933 | ||
934 | static const char * const vsense_trigger_groups[] = { | |
935 | "gpio7", | |
936 | }; | |
937 | ||
938 | static const char * const wlan1_adc0_groups[] = { | |
939 | "gpio39", | |
940 | }; | |
941 | ||
942 | static const char * const wlan1_adc1_groups[] = { | |
943 | "gpio44", | |
944 | }; | |
945 | ||
946 | static const char * const wlan2_adc0_groups[] = { | |
947 | "gpio11", | |
948 | }; | |
949 | ||
950 | static const char * const wlan2_adc1_groups[] = { | |
951 | "gpio10", | |
952 | }; | |
953 | ||
954 | static const char * const wsa_clk_groups[] = { | |
955 | "gpio49", | |
956 | }; | |
957 | ||
958 | static const char * const wsa_data_groups[] = { | |
959 | "gpio50", | |
960 | }; | |
961 | ||
c7a291db RA |
962 | static const struct pinfunction sm7150_functions[] = { |
963 | MSM_PIN_FUNCTION(gpio), | |
964 | MSM_PIN_FUNCTION(adsp_ext), | |
965 | MSM_PIN_FUNCTION(agera_pll), | |
966 | MSM_PIN_FUNCTION(aoss_cti), | |
967 | MSM_PIN_FUNCTION(atest_char), | |
968 | MSM_PIN_FUNCTION(atest_tsens), | |
969 | MSM_PIN_FUNCTION(atest_tsens2), | |
970 | MSM_PIN_FUNCTION(atest_usb1), | |
971 | MSM_PIN_FUNCTION(atest_usb2), | |
972 | MSM_PIN_FUNCTION(cam_mclk), | |
973 | MSM_PIN_FUNCTION(cci_async), | |
974 | MSM_PIN_FUNCTION(cci_i2c), | |
975 | MSM_PIN_FUNCTION(cci_timer0), | |
976 | MSM_PIN_FUNCTION(cci_timer1), | |
977 | MSM_PIN_FUNCTION(cci_timer2), | |
978 | MSM_PIN_FUNCTION(cci_timer3), | |
979 | MSM_PIN_FUNCTION(cci_timer4), | |
980 | MSM_PIN_FUNCTION(dbg_out), | |
981 | MSM_PIN_FUNCTION(ddr_bist), | |
982 | MSM_PIN_FUNCTION(ddr_pxi0), | |
983 | MSM_PIN_FUNCTION(ddr_pxi1), | |
984 | MSM_PIN_FUNCTION(ddr_pxi2), | |
985 | MSM_PIN_FUNCTION(ddr_pxi3), | |
986 | MSM_PIN_FUNCTION(edp_hot), | |
987 | MSM_PIN_FUNCTION(edp_lcd), | |
988 | MSM_PIN_FUNCTION(gcc_gp1), | |
989 | MSM_PIN_FUNCTION(gcc_gp2), | |
990 | MSM_PIN_FUNCTION(gcc_gp3), | |
991 | MSM_PIN_FUNCTION(gp_pdm0), | |
992 | MSM_PIN_FUNCTION(gp_pdm1), | |
993 | MSM_PIN_FUNCTION(gp_pdm2), | |
994 | MSM_PIN_FUNCTION(gps_tx), | |
995 | MSM_PIN_FUNCTION(jitter_bist), | |
996 | MSM_PIN_FUNCTION(ldo_en), | |
997 | MSM_PIN_FUNCTION(ldo_update), | |
998 | MSM_PIN_FUNCTION(m_voc), | |
999 | MSM_PIN_FUNCTION(mdp_vsync), | |
1000 | MSM_PIN_FUNCTION(mdp_vsync0), | |
1001 | MSM_PIN_FUNCTION(mdp_vsync1), | |
1002 | MSM_PIN_FUNCTION(mdp_vsync2), | |
1003 | MSM_PIN_FUNCTION(mdp_vsync3), | |
1004 | MSM_PIN_FUNCTION(mss_lte), | |
1005 | MSM_PIN_FUNCTION(nav_pps_in), | |
1006 | MSM_PIN_FUNCTION(nav_pps_out), | |
1007 | MSM_PIN_FUNCTION(pa_indicator), | |
1008 | MSM_PIN_FUNCTION(pci_e), | |
1009 | MSM_PIN_FUNCTION(phase_flag), | |
1010 | MSM_PIN_FUNCTION(pll_bist), | |
1011 | MSM_PIN_FUNCTION(pll_bypassnl), | |
1012 | MSM_PIN_FUNCTION(pll_reset), | |
1013 | MSM_PIN_FUNCTION(pri_mi2s), | |
1014 | MSM_PIN_FUNCTION(pri_mi2s_ws), | |
1015 | MSM_PIN_FUNCTION(prng_rosc), | |
1016 | MSM_PIN_FUNCTION(qdss_cti), | |
1017 | MSM_PIN_FUNCTION(qdss), | |
1018 | MSM_PIN_FUNCTION(qlink_enable), | |
1019 | MSM_PIN_FUNCTION(qlink_request), | |
1020 | MSM_PIN_FUNCTION(qua_mi2s), | |
1021 | MSM_PIN_FUNCTION(qup00), | |
1022 | MSM_PIN_FUNCTION(qup01), | |
1023 | MSM_PIN_FUNCTION(qup02), | |
1024 | MSM_PIN_FUNCTION(qup03), | |
1025 | MSM_PIN_FUNCTION(qup04), | |
1026 | MSM_PIN_FUNCTION(qup10), | |
1027 | MSM_PIN_FUNCTION(qup11), | |
1028 | MSM_PIN_FUNCTION(qup12), | |
1029 | MSM_PIN_FUNCTION(qup13), | |
1030 | MSM_PIN_FUNCTION(qup14), | |
1031 | MSM_PIN_FUNCTION(qup15), | |
1032 | MSM_PIN_FUNCTION(sd_write), | |
1033 | MSM_PIN_FUNCTION(sdc40), | |
1034 | MSM_PIN_FUNCTION(sdc41), | |
1035 | MSM_PIN_FUNCTION(sdc42), | |
1036 | MSM_PIN_FUNCTION(sdc43), | |
1037 | MSM_PIN_FUNCTION(sdc4_clk), | |
1038 | MSM_PIN_FUNCTION(sdc4_cmd), | |
1039 | MSM_PIN_FUNCTION(sec_mi2s), | |
1040 | MSM_PIN_FUNCTION(ter_mi2s), | |
1041 | MSM_PIN_FUNCTION(tgu_ch0), | |
1042 | MSM_PIN_FUNCTION(tgu_ch1), | |
1043 | MSM_PIN_FUNCTION(tgu_ch2), | |
1044 | MSM_PIN_FUNCTION(tgu_ch3), | |
1045 | MSM_PIN_FUNCTION(tsif1_clk), | |
1046 | MSM_PIN_FUNCTION(tsif1_data), | |
1047 | MSM_PIN_FUNCTION(tsif1_en), | |
1048 | MSM_PIN_FUNCTION(tsif1_error), | |
1049 | MSM_PIN_FUNCTION(tsif1_sync), | |
1050 | MSM_PIN_FUNCTION(tsif2_clk), | |
1051 | MSM_PIN_FUNCTION(tsif2_data), | |
1052 | MSM_PIN_FUNCTION(tsif2_en), | |
1053 | MSM_PIN_FUNCTION(tsif2_error), | |
1054 | MSM_PIN_FUNCTION(tsif2_sync), | |
1055 | MSM_PIN_FUNCTION(uim1_clk), | |
1056 | MSM_PIN_FUNCTION(uim1_data), | |
1057 | MSM_PIN_FUNCTION(uim1_present), | |
1058 | MSM_PIN_FUNCTION(uim1_reset), | |
1059 | MSM_PIN_FUNCTION(uim2_clk), | |
1060 | MSM_PIN_FUNCTION(uim2_data), | |
1061 | MSM_PIN_FUNCTION(uim2_present), | |
1062 | MSM_PIN_FUNCTION(uim2_reset), | |
1063 | MSM_PIN_FUNCTION(uim_batt), | |
1064 | MSM_PIN_FUNCTION(usb_phy), | |
1065 | MSM_PIN_FUNCTION(vfr_1), | |
1066 | MSM_PIN_FUNCTION(vsense_trigger), | |
1067 | MSM_PIN_FUNCTION(wlan1_adc0), | |
1068 | MSM_PIN_FUNCTION(wlan1_adc1), | |
1069 | MSM_PIN_FUNCTION(wlan2_adc0), | |
1070 | MSM_PIN_FUNCTION(wlan2_adc1), | |
1071 | MSM_PIN_FUNCTION(wsa_clk), | |
1072 | MSM_PIN_FUNCTION(wsa_data), | |
b915395c DT |
1073 | }; |
1074 | ||
1075 | /* | |
1076 | * Every pin is maintained as a single group, and missing or non-existing pin | |
1077 | * would be maintained as dummy group to synchronize pin group index with | |
1078 | * pin descriptor registered with pinctrl core. | |
1079 | * Clients would not be able to request these dummy pin groups. | |
1080 | */ | |
1081 | static const struct msm_pingroup sm7150_groups[] = { | |
1082 | [0] = PINGROUP(0, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), | |
1083 | [1] = PINGROUP(1, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), | |
1084 | [2] = PINGROUP(2, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), | |
1085 | [3] = PINGROUP(3, SOUTH, qup01, dbg_out, _, _, _, _, _, _, _), | |
1086 | [4] = PINGROUP(4, NORTH, _, qdss_cti, _, _, _, _, _, _, _), | |
1087 | [5] = PINGROUP(5, NORTH, _, qdss_cti, _, _, _, _, _, _, _), | |
1088 | [6] = PINGROUP(6, NORTH, qup11, _, phase_flag, ddr_pxi0, _, _, _, _, _), | |
1089 | [7] = PINGROUP(7, NORTH, qup11, ddr_bist, _, phase_flag, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _), | |
1090 | [8] = PINGROUP(8, NORTH, qup11, gp_pdm1, ddr_bist, _, _, _, _, _, _), | |
1091 | [9] = PINGROUP(9, NORTH, qup11, ddr_bist, _, _, _, _, _, _, _), | |
1092 | [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, phase_flag, wlan2_adc1, atest_usb1, ddr_pxi2, _, _), | |
1093 | [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, wlan2_adc0, atest_usb1, ddr_pxi2, _, _), | |
1094 | [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, ddr_pxi3, _, _, _), | |
1095 | [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, _, phase_flag, qdss, ddr_pxi3, _, _, _), | |
1096 | [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, _, phase_flag, qdss, _, _, _, _), | |
1097 | [15] = PINGROUP(15, SOUTH, cam_mclk, _, phase_flag, qdss, _, _, _, _, _), | |
1098 | [16] = PINGROUP(16, SOUTH, cam_mclk, _, phase_flag, qdss, _, _, _, _, _), | |
1099 | [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, _, _, _, _), | |
1100 | [18] = PINGROUP(18, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), | |
1101 | [19] = PINGROUP(19, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), | |
1102 | [20] = PINGROUP(20, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), | |
1103 | [21] = PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, _, qdss, _, _, _, _, _), | |
1104 | [22] = PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _), | |
1105 | [23] = PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _), | |
1106 | [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, _, phase_flag, qdss, _, _, _, _), | |
1107 | [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, _, phase_flag, qdss, _, _, _, _), | |
1108 | [26] = PINGROUP(26, SOUTH, cci_async, jitter_bist, _, phase_flag, qdss, _, _, _, _), | |
1109 | [27] = PINGROUP(27, SOUTH, cci_i2c, pll_bist, _, phase_flag, qdss, _, _, _, _), | |
1110 | [28] = PINGROUP(28, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, _, _, _, _), | |
1111 | [29] = PINGROUP(29, NORTH, _, _, phase_flag, qdss, atest_tsens, _, _, _, _), | |
1112 | [30] = PINGROUP(30, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), | |
1113 | [31] = PINGROUP(31, WEST, _, qdss, _, _, _, _, _, _, _), | |
1114 | [32] = PINGROUP(32, NORTH, qdss_cti, _, _, _, _, _, _, _, _), | |
1115 | [33] = PINGROUP(33, NORTH, sd_write, _, _, _, _, _, _, _, _), | |
1116 | [34] = PINGROUP(34, SOUTH, qup02, qdss, _, _, _, _, _, _, _), | |
1117 | [35] = PINGROUP(35, SOUTH, qup02, _, phase_flag, qdss, _, _, _, _, _), | |
1118 | [36] = PINGROUP(36, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), | |
1119 | [37] = PINGROUP(37, SOUTH, qup01, gp_pdm0, _, phase_flag, qdss, _, _, _, _), | |
1120 | [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _), | |
1121 | [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, _, wlan1_adc0, atest_usb1, ddr_pxi1, _, _), | |
1122 | [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _), | |
1123 | [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _), | |
1124 | [42] = PINGROUP(42, NORTH, qup12, _, _, _, _, _, _, _, _), | |
1125 | [43] = PINGROUP(43, NORTH, qup12, _, phase_flag, _, _, _, _, _, _), | |
1126 | [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, _, wlan1_adc1, atest_usb1, ddr_pxi1, _), | |
1127 | [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), | |
1128 | [46] = PINGROUP(46, NORTH, qup13, _, _, _, _, _, _, _, _), | |
1129 | [47] = PINGROUP(47, NORTH, qup13, _, _, _, _, _, _, _, _), | |
1130 | [48] = PINGROUP(48, WEST, gcc_gp1, _, _, _, _, _, _, _, _), | |
1131 | [49] = PINGROUP(49, WEST, pri_mi2s, qup00, wsa_clk, _, _, _, _, _, _), | |
1132 | [50] = PINGROUP(50, WEST, pri_mi2s_ws, qup00, wsa_data, gp_pdm1, _, _, _, _, _), | |
1133 | [51] = PINGROUP(51, WEST, pri_mi2s, qup00, atest_usb2, _, _, _, _, _, _), | |
1134 | [52] = PINGROUP(52, WEST, pri_mi2s, qup00, atest_usb2, _, _, _, _, _, _), | |
1135 | [53] = PINGROUP(53, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), | |
1136 | [54] = PINGROUP(54, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), | |
1137 | [55] = PINGROUP(55, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), | |
1138 | [56] = PINGROUP(56, WEST, ter_mi2s, qup04, gcc_gp1, _, phase_flag, qdss, _, _, _), | |
1139 | [57] = PINGROUP(57, WEST, sec_mi2s, qup00, gp_pdm2, _, phase_flag, qdss, _, _, _), | |
1140 | [58] = PINGROUP(58, WEST, qua_mi2s, qup00, _, _, _, _, _, _, _), | |
1141 | [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _), | |
1142 | [60] = PINGROUP(60, NORTH, qup10, tsif1_error, _, phase_flag, _, _, _, _, _), | |
1143 | [61] = PINGROUP(61, NORTH, qup10, tsif1_sync, _, phase_flag, _, _, _, _, _), | |
1144 | [62] = PINGROUP(62, NORTH, qup10, tsif1_clk, tgu_ch3, _, phase_flag, _, _, _, _), | |
1145 | [63] = PINGROUP(63, NORTH, tsif1_en, mdp_vsync0, qup10, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, qdss_cti, _), | |
1146 | [64] = PINGROUP(64, NORTH, tsif1_data, sdc4_cmd, qup10, tgu_ch1, _, _, _, _, _), | |
1147 | [65] = PINGROUP(65, NORTH, tsif2_error, sdc43, qup10, vfr_1, tgu_ch2, _, _, _, _), | |
1148 | [66] = PINGROUP(66, NORTH, tsif2_clk, sdc4_clk, pci_e, _, _, _, _, _, _), | |
1149 | [67] = PINGROUP(67, NORTH, tsif2_en, sdc42, pci_e, _, _, _, _, _, _), | |
1150 | [68] = PINGROUP(68, NORTH, tsif2_data, sdc41, pci_e, gp_pdm0, _, _, _, _, _), | |
1151 | [69] = PINGROUP(69, NORTH, tsif2_sync, sdc40, _, _, _, _, _, _, _), | |
1152 | [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _), | |
1153 | [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _), | |
1154 | [72] = PINGROUP(72, NORTH, prng_rosc, _, _, _, _, _, _, _, _), | |
1155 | [73] = PINGROUP(73, NORTH, _, _, _, _, _, _, _, _, _), | |
1156 | [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _), | |
1157 | [75] = PINGROUP(75, WEST, uim2_data, _, _, _, _, _, _, _, _), | |
1158 | [76] = PINGROUP(76, WEST, uim2_clk, _, _, _, _, _, _, _, _), | |
1159 | [77] = PINGROUP(77, WEST, uim2_reset, _, _, _, _, _, _, _, _), | |
1160 | [78] = PINGROUP(78, WEST, uim2_present, _, _, _, _, _, _, _, _), | |
1161 | [79] = PINGROUP(79, WEST, uim1_data, _, _, _, _, _, _, _, _), | |
1162 | [80] = PINGROUP(80, WEST, uim1_clk, _, _, _, _, _, _, _, _), | |
1163 | [81] = PINGROUP(81, WEST, uim1_reset, _, _, _, _, _, _, _, _), | |
1164 | [82] = PINGROUP(82, WEST, uim1_present, _, _, _, _, _, _, _, _), | |
1165 | [83] = PINGROUP(83, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), | |
1166 | [84] = PINGROUP(84, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), | |
1167 | [85] = PINGROUP(85, WEST, uim_batt, edp_hot, aoss_cti, _, _, _, _, _, _), | |
1168 | [86] = PINGROUP(86, NORTH, qdss, atest_char, _, _, _, _, _, _, _), | |
1169 | [87] = PINGROUP(87, NORTH, adsp_ext, qdss, atest_char, _, _, _, _, _, _), | |
1170 | [88] = PINGROUP(88, NORTH, qdss, atest_char, _, _, _, _, _, _, _), | |
1171 | [89] = PINGROUP(89, NORTH, qdss, atest_char, _, _, _, _, _, _, _), | |
1172 | [90] = PINGROUP(90, NORTH, qdss, atest_char, _, _, _, _, _, _, _), | |
1173 | [91] = PINGROUP(91, NORTH, qdss, _, _, _, _, _, _, _, _), | |
1174 | [92] = PINGROUP(92, NORTH, _, _, qup15, _, _, _, _, _, _), | |
1175 | [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _), | |
1176 | [94] = PINGROUP(94, SOUTH, _, _, _, _, _, _, _, _, _), | |
1177 | [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _), | |
1178 | [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _), | |
1179 | [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _), | |
1180 | [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _), | |
1181 | [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _), | |
1182 | [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _), | |
1183 | [101] = PINGROUP(101, NORTH, _, _, qup15, _, _, _, _, _, _), | |
1184 | [102] = PINGROUP(102, NORTH, _, _, qup15, _, _, _, _, _, _), | |
1185 | [103] = PINGROUP(103, NORTH, _, qup15, _, _, _, _, _, _, _), | |
1186 | [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _), | |
1187 | [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _), | |
1188 | [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _), | |
1189 | [107] = PINGROUP(107, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), | |
1190 | [108] = PINGROUP(108, SOUTH, mss_lte, _, _, _, _, _, _, _, _), | |
1191 | [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _), | |
1192 | [110] = PINGROUP(110, NORTH, _, _, qup14, _, _, _, _, _, _), | |
1193 | [111] = PINGROUP(111, NORTH, _, _, qup14, _, _, _, _, _, _), | |
1194 | [112] = PINGROUP(112, NORTH, _, qup14, _, _, _, _, _, _, _), | |
1195 | [113] = PINGROUP(113, NORTH, _, qup14, _, _, _, _, _, _, _), | |
1196 | [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _), | |
1197 | [115] = PINGROUP(115, NORTH, _, _, _, _, _, _, _, _, _), | |
1198 | [116] = PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _), | |
1199 | [117] = PINGROUP(117, NORTH, _, _, _, _, _, _, _, _, _), | |
1200 | [118] = PINGROUP(118, NORTH, _, _, _, _, _, _, _, _, _), | |
1201 | [119] = UFS_RESET(ufs_reset, 0x9f000), | |
5ed79863 DT |
1202 | [120] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x9a000, 15, 0), |
1203 | [121] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x9a000, 13, 6), | |
1204 | [122] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x9a000, 11, 3), | |
1205 | [123] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x9a000, 9, 0), | |
1206 | [124] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x98000, 14, 6), | |
1207 | [125] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x98000, 11, 3), | |
1208 | [126] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x98000, 9, 0), | |
b915395c DT |
1209 | }; |
1210 | ||
1211 | static const struct msm_gpio_wakeirq_map sm7150_pdc_map[] = { | |
1212 | {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 57}, | |
1213 | {10, 80}, {11, 51}, {22, 90}, {24, 61}, {26, 52}, {30, 56}, | |
1214 | {31, 33}, {32, 81}, {33, 62}, {34, 43}, {36, 91}, {37, 53}, | |
1215 | {38, 63}, {39, 72}, {41, 101}, {42, 35}, {43, 34}, {45, 73}, | |
1216 | {47, 82}, {48, 36}, {49, 37}, {50, 38}, {52, 39}, {53, 102}, | |
1217 | {55, 92}, {56, 45}, {57, 46}, {58, 83}, {59, 47}, {62, 48}, | |
1218 | {64, 74}, {65, 44}, {66, 93}, {67, 49}, {68, 55}, {69, 32}, | |
1219 | {70, 54}, {73, 64}, {74, 71}, {78, 31}, {82, 30}, {84, 58}, | |
1220 | {85, 103}, {86, 59}, {87, 60}, {88, 65}, {89, 66}, {90, 67}, | |
1221 | {91, 68}, {92, 69}, {93, 75}, {94, 84}, {95, 94}, {96, 76}, | |
1222 | {98, 77}, {101, 78}, {104, 99}, {109, 104}, {110, 79}, {113, 85}, | |
1223 | }; | |
1224 | ||
1225 | static const struct msm_pinctrl_soc_data sm7150_tlmm = { | |
1226 | .pins = sm7150_pins, | |
1227 | .npins = ARRAY_SIZE(sm7150_pins), | |
1228 | .functions = sm7150_functions, | |
1229 | .nfunctions = ARRAY_SIZE(sm7150_functions), | |
1230 | .groups = sm7150_groups, | |
1231 | .ngroups = ARRAY_SIZE(sm7150_groups), | |
1232 | .ngpios = 120, | |
1233 | .tiles = sm7150_tiles, | |
1234 | .ntiles = ARRAY_SIZE(sm7150_tiles), | |
1235 | .wakeirq_map = sm7150_pdc_map, | |
1236 | .nwakeirq_map = ARRAY_SIZE(sm7150_pdc_map), | |
1237 | .wakeirq_dual_edge_errata = true, | |
1238 | }; | |
1239 | ||
1240 | static int sm7150_tlmm_probe(struct platform_device *pdev) | |
1241 | { | |
1242 | return msm_pinctrl_probe(pdev, &sm7150_tlmm); | |
1243 | } | |
1244 | ||
1245 | static const struct of_device_id sm7150_tlmm_of_match[] = { | |
1246 | { .compatible = "qcom,sm7150-tlmm", }, | |
1247 | { }, | |
1248 | }; | |
abda4619 | 1249 | MODULE_DEVICE_TABLE(of, sm7150_tlmm_of_match); |
b915395c DT |
1250 | |
1251 | static struct platform_driver sm7150_tlmm_driver = { | |
1252 | .driver = { | |
1253 | .name = "sm7150-tlmm", | |
1254 | .pm = &msm_pinctrl_dev_pm_ops, | |
1255 | .of_match_table = sm7150_tlmm_of_match, | |
1256 | }, | |
1257 | .probe = sm7150_tlmm_probe, | |
22ee670a | 1258 | .remove_new = msm_pinctrl_remove, |
b915395c DT |
1259 | }; |
1260 | ||
1261 | static int __init sm7150_tlmm_init(void) | |
1262 | { | |
1263 | return platform_driver_register(&sm7150_tlmm_driver); | |
1264 | } | |
1265 | arch_initcall(sm7150_tlmm_init); | |
1266 | ||
1267 | static void __exit sm7150_tlmm_exit(void) | |
1268 | { | |
1269 | platform_driver_unregister(&sm7150_tlmm_driver); | |
1270 | } | |
1271 | module_exit(sm7150_tlmm_exit); | |
1272 | ||
1273 | MODULE_DESCRIPTION("Qualcomm SM7150 TLMM driver"); | |
1274 | MODULE_LICENSE("GPL"); |