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Merge tag 'v4.2-rc7' into drm-next
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-tegra-xusb.c
CommitLineData
dc0a3938
TR		 1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/phy/phy.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/platform_device.h>
22#include <linux/reset.h>
c61c2d70 23#include <linux/slab.h>
dc0a3938
TR		 24
25#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
26
27#include "core.h"
28#include "pinctrl-utils.h"
29
30#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
31#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
32#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
33#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
34
35#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
36#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
37#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
38#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
39
40#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
41#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
42#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
43#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
44
45#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
46#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
47#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
48#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
49#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
50#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
51
52#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
53#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
54#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
55
56struct tegra_xusb_padctl_function {
57 const char *name;
58 const char * const *groups;
59 unsigned int num_groups;
60};
61
dc0a3938
TR		 62struct tegra_xusb_padctl_soc {
63 const struct pinctrl_pin_desc *pins;
64 unsigned int num_pins;
65
66 const struct tegra_xusb_padctl_function *functions;
67 unsigned int num_functions;
68
69 const struct tegra_xusb_padctl_lane *lanes;
70 unsigned int num_lanes;
71};
72
73struct tegra_xusb_padctl_lane {
74 const char *name;
75
76 unsigned int offset;
77 unsigned int shift;
78 unsigned int mask;
79 unsigned int iddq;
80
81 const unsigned int *funcs;
82 unsigned int num_funcs;
83};
84
85struct tegra_xusb_padctl {
86 struct device *dev;
87 void __iomem *regs;
88 struct mutex lock;
89 struct reset_control *rst;
90
91 const struct tegra_xusb_padctl_soc *soc;
92 struct pinctrl_dev *pinctrl;
93 struct pinctrl_desc desc;
94
95 struct phy_provider *provider;
96 struct phy *phys[2];
97
98 unsigned int enable;
99};
100
101static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
102 unsigned long offset)
103{
104 writel(value, padctl->regs + offset);
105}
106
107static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
108 unsigned long offset)
109{
110 return readl(padctl->regs + offset);
111}
112
113static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
114{
115 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
116
117 return padctl->soc->num_pins;
118}
119
120static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
121 unsigned int group)
122{
123 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
124
125 return padctl->soc->pins[group].name;
126}
127
8480c2e7
JH		 128static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
129 unsigned group,
130 const unsigned **pins,
131 unsigned *num_pins)
132{
133 /*
134 * For the tegra-xusb pad controller groups are synonomous
135 * with lanes/pins and there is always one lane/pin per group.
136 */
137 *pins = &pinctrl->desc->pins[group].number;
138 *num_pins = 1;
139
140 return 0;
141}
142
dc0a3938
TR		 143enum tegra_xusb_padctl_param {
144 TEGRA_XUSB_PADCTL_IDDQ,
145};
146
147static const struct tegra_xusb_padctl_property {
148 const char *name;
149 enum tegra_xusb_padctl_param param;
150} properties[] = {
151 { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
152};
153
154#define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
155#define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
156#define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
157
158static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
159 struct device_node *np,
160 struct pinctrl_map **maps,
161 unsigned int *reserved_maps,
162 unsigned int *num_maps)
163{
164 unsigned int i, reserve = 0, num_configs = 0;
165 unsigned long config, *configs = NULL;
166 const char *function, *group;
167 struct property *prop;
168 int err = 0;
169 u32 value;
170
171 err = of_property_read_string(np, "nvidia,function", &function);
172 if (err < 0) {
173 if (err != -EINVAL)
174 return err;
175
176 function = NULL;
177 }
178
179 for (i = 0; i < ARRAY_SIZE(properties); i++) {
180 err = of_property_read_u32(np, properties[i].name, &value);
181 if (err < 0) {
182 if (err == -EINVAL)
183 continue;
184
c61c2d70 185 goto out;
dc0a3938
TR		 186 }
187
188 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
189
190 err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
191 &num_configs, config);
192 if (err < 0)
c61c2d70 193 goto out;
dc0a3938
TR		 194 }
195
196 if (function)
197 reserve++;
198
199 if (num_configs)
200 reserve++;
201
202 err = of_property_count_strings(np, "nvidia,lanes");
203 if (err < 0)
c61c2d70 204 goto out;
dc0a3938
TR		 205
206 reserve *= err;
207
208 err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
209 num_maps, reserve);
210 if (err < 0)
c61c2d70 211 goto out;
dc0a3938
TR		 212
213 of_property_for_each_string(np, "nvidia,lanes", prop, group) {
214 if (function) {
215 err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
216 reserved_maps, num_maps, group,
217 function);
218 if (err < 0)
c61c2d70 219 goto out;
dc0a3938
TR		 220 }
221
222 if (num_configs) {
223 err = pinctrl_utils_add_map_configs(padctl->pinctrl,
224 maps, reserved_maps, num_maps, group,
225 configs, num_configs,
226 PIN_MAP_TYPE_CONFIGS_GROUP);
227 if (err < 0)
c61c2d70 228 goto out;
dc0a3938
TR		 229 }
230 }
231
c61c2d70
TR		 232 err = 0;
233
234out:
235 kfree(configs);
236 return err;
dc0a3938
TR		 237}
238
239static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
240 struct device_node *parent,
241 struct pinctrl_map **maps,
242 unsigned int *num_maps)
243{
244 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
245 unsigned int reserved_maps = 0;
246 struct device_node *np;
247 int err;
248
249 *num_maps = 0;
250 *maps = NULL;
251
252 for_each_child_of_node(parent, np) {
253 err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
254 &reserved_maps,
255 num_maps);
256 if (err < 0)
257 return err;
258 }
259
260 return 0;
261}
262
263static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
264 .get_groups_count = tegra_xusb_padctl_get_groups_count,
265 .get_group_name = tegra_xusb_padctl_get_group_name,
8480c2e7 266 .get_group_pins = tegra_xusb_padctl_get_group_pins,
dc0a3938
TR		 267 .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
268 .dt_free_map = pinctrl_utils_dt_free_map,
269};
270
271static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
272{
273 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
274
275 return padctl->soc->num_functions;
276}
277
278static const char *
279tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
280 unsigned int function)
281{
282 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
283
284 return padctl->soc->functions[function].name;
285}
286
287static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
288 unsigned int function,
289 const char * const **groups,
290 unsigned * const num_groups)
291{
292 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
293
294 *num_groups = padctl->soc->functions[function].num_groups;
295 *groups = padctl->soc->functions[function].groups;
296
297 return 0;
298}
299
03e9f0ca
LW		 300static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
301 unsigned int function,
302 unsigned int group)
dc0a3938
TR		 303{
304 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
305 const struct tegra_xusb_padctl_lane *lane;
306 unsigned int i;
307 u32 value;
308
309 lane = &padctl->soc->lanes[group];
310
311 for (i = 0; i < lane->num_funcs; i++)
312 if (lane->funcs[i] == function)
313 break;
314
315 if (i >= lane->num_funcs)
316 return -EINVAL;
317
318 value = padctl_readl(padctl, lane->offset);
319 value &= ~(lane->mask << lane->shift);
320 value |= i << lane->shift;
321 padctl_writel(padctl, value, lane->offset);
322
323 return 0;
324}
325
326static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
327 .get_functions_count = tegra_xusb_padctl_get_functions_count,
328 .get_function_name = tegra_xusb_padctl_get_function_name,
329 .get_function_groups = tegra_xusb_padctl_get_function_groups,
03e9f0ca 330 .set_mux = tegra_xusb_padctl_pinmux_set,
dc0a3938
TR		 331};
332
333static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
334 unsigned int group,
335 unsigned long *config)
336{
337 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
338 const struct tegra_xusb_padctl_lane *lane;
339 enum tegra_xusb_padctl_param param;
340 u32 value;
341
342 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
343 lane = &padctl->soc->lanes[group];
344
345 switch (param) {
346 case TEGRA_XUSB_PADCTL_IDDQ:
347 /* lanes with iddq == 0 don't support this parameter */
348 if (lane->iddq == 0)
349 return -EINVAL;
350
351 value = padctl_readl(padctl, lane->offset);
352
353 if (value & BIT(lane->iddq))
354 value = 0;
355 else
356 value = 1;
357
358 *config = TEGRA_XUSB_PADCTL_PACK(param, value);
359 break;
360
361 default:
362 dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
363 param);
364 return -ENOTSUPP;
365 }
366
367 return 0;
368}
369
370static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
371 unsigned int group,
372 unsigned long *configs,
373 unsigned int num_configs)
374{
375 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
376 const struct tegra_xusb_padctl_lane *lane;
377 enum tegra_xusb_padctl_param param;
378 unsigned long value;
379 unsigned int i;
380 u32 regval;
381
382 lane = &padctl->soc->lanes[group];
383
384 for (i = 0; i < num_configs; i++) {
385 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
386 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
387
388 switch (param) {
389 case TEGRA_XUSB_PADCTL_IDDQ:
390 /* lanes with iddq == 0 don't support this parameter */
391 if (lane->iddq == 0)
392 return -EINVAL;
393
394 regval = padctl_readl(padctl, lane->offset);
395
396 if (value)
397 regval &= ~BIT(lane->iddq);
398 else
399 regval |= BIT(lane->iddq);
400
401 padctl_writel(padctl, regval, lane->offset);
402 break;
403
404 default:
405 dev_err(padctl->dev,
406 "invalid configuration parameter: %04x\n",
407 param);
408 return -ENOTSUPP;
409 }
410 }
411
412 return 0;
413}
414
415#ifdef CONFIG_DEBUG_FS
416static const char *strip_prefix(const char *s)
417{
418 const char *comma = strchr(s, ',');
419 if (!comma)
420 return s;
421
422 return comma + 1;
423}
424
425static void
426tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
427 struct seq_file *s,
428 unsigned int group)
429{
430 unsigned int i;
431
432 for (i = 0; i < ARRAY_SIZE(properties); i++) {
433 unsigned long config, value;
434 int err;
435
436 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
437
438 err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
439 &config);
440 if (err < 0)
441 continue;
442
443 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
444
445 seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
446 value);
447 }
448}
449
450static void
451tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
452 struct seq_file *s,
453 unsigned long config)
454{
455 enum tegra_xusb_padctl_param param;
456 const char *name = "unknown";
457 unsigned long value;
458 unsigned int i;
459
460 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
461 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
462
463 for (i = 0; i < ARRAY_SIZE(properties); i++) {
464 if (properties[i].param == param) {
465 name = properties[i].name;
466 break;
467 }
468 }
469
470 seq_printf(s, "%s=%lu", strip_prefix(name), value);
471}
472#endif
473
474static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
475 .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
476 .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
477#ifdef CONFIG_DEBUG_FS
478 .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
479 .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
480#endif
481};
482
483static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
484{
485 u32 value;
486
487 mutex_lock(&padctl->lock);
488
489 if (padctl->enable++ > 0)
490 goto out;
491
492 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
493 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
494 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
495
496 usleep_range(100, 200);
497
498 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
499 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
500 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
501
502 usleep_range(100, 200);
503
504 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
505 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
506 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
507
508out:
509 mutex_unlock(&padctl->lock);
510 return 0;
511}
512
513static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
514{
515 u32 value;
516
517 mutex_lock(&padctl->lock);
518
519 if (WARN_ON(padctl->enable == 0))
520 goto out;
521
522 if (--padctl->enable > 0)
523 goto out;
524
525 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
526 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
527 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
528
529 usleep_range(100, 200);
530
531 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
532 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
533 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
534
535 usleep_range(100, 200);
536
537 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
538 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
539 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
540
541out:
542 mutex_unlock(&padctl->lock);
543 return 0;
544}
545
546static int tegra_xusb_phy_init(struct phy *phy)
547{
548 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
549
550 return tegra_xusb_padctl_enable(padctl);
551}
552
553static int tegra_xusb_phy_exit(struct phy *phy)
554{
555 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
556
557 return tegra_xusb_padctl_disable(padctl);
558}
559
560static int pcie_phy_power_on(struct phy *phy)
561{
562 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
563 unsigned long timeout;
564 int err = -ETIMEDOUT;
565 u32 value;
566
567 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
568 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
569 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
570
571 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
572 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
573 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
574 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
575 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
576
577 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
578 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
579 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
580
581 timeout = jiffies + msecs_to_jiffies(50);
582
583 while (time_before(jiffies, timeout)) {
584 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
585 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
586 err = 0;
587 break;
588 }
589
590 usleep_range(100, 200);
591 }
592
593 return err;
594}
595
596static int pcie_phy_power_off(struct phy *phy)
597{
598 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
599 u32 value;
600
601 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
602 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
603 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
604
605 return 0;
606}
607
608static const struct phy_ops pcie_phy_ops = {
609 .init = tegra_xusb_phy_init,
610 .exit = tegra_xusb_phy_exit,
611 .power_on = pcie_phy_power_on,
612 .power_off = pcie_phy_power_off,
613 .owner = THIS_MODULE,
614};
615
616static int sata_phy_power_on(struct phy *phy)
617{
618 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
619 unsigned long timeout;
620 int err = -ETIMEDOUT;
621 u32 value;
622
623 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
624 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
625 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
626 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
627
628 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
629 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
630 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
631 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
632
633 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
634 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
635 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
636
637 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
638 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
639 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
640
641 timeout = jiffies + msecs_to_jiffies(50);
642
643 while (time_before(jiffies, timeout)) {
644 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
645 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
646 err = 0;
647 break;
648 }
649
650 usleep_range(100, 200);
651 }
652
653 return err;
654}
655
656static int sata_phy_power_off(struct phy *phy)
657{
658 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
659 u32 value;
660
661 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
662 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
663 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
664
665 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
666 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
667 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
668
669 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
670 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
671 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
672 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
673
674 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
675 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
676 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
677 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
678
679 return 0;
680}
681
682static const struct phy_ops sata_phy_ops = {
683 .init = tegra_xusb_phy_init,
684 .exit = tegra_xusb_phy_exit,
685 .power_on = sata_phy_power_on,
686 .power_off = sata_phy_power_off,
687 .owner = THIS_MODULE,
688};
689
690static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
691 struct of_phandle_args *args)
692{
693 struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
694 unsigned int index = args->args[0];
695
696 if (args->args_count <= 0)
697 return ERR_PTR(-EINVAL);
698
8e1594db 699 if (index >= ARRAY_SIZE(padctl->phys))
dc0a3938
TR		 700 return ERR_PTR(-EINVAL);
701
702 return padctl->phys[index];
703}
704
705#define PIN_OTG_0 0
706#define PIN_OTG_1 1
707#define PIN_OTG_2 2
708#define PIN_ULPI_0 3
709#define PIN_HSIC_0 4
710#define PIN_HSIC_1 5
711#define PIN_PCIE_0 6
712#define PIN_PCIE_1 7
713#define PIN_PCIE_2 8
714#define PIN_PCIE_3 9
715#define PIN_PCIE_4 10
716#define PIN_SATA_0 11
717
718static const struct pinctrl_pin_desc tegra124_pins[] = {
719 PINCTRL_PIN(PIN_OTG_0, "otg-0"),
720 PINCTRL_PIN(PIN_OTG_1, "otg-1"),
721 PINCTRL_PIN(PIN_OTG_2, "otg-2"),
722 PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
723 PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
724 PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
725 PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
726 PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
727 PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
728 PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
729 PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
730 PINCTRL_PIN(PIN_SATA_0, "sata-0"),
731};
732
733static const char * const tegra124_snps_groups[] = {
734 "otg-0",
735 "otg-1",
736 "otg-2",
737 "ulpi-0",
738 "hsic-0",
739 "hsic-1",
740};
741
742static const char * const tegra124_xusb_groups[] = {
743 "otg-0",
744 "otg-1",
745 "otg-2",
746 "ulpi-0",
747 "hsic-0",
748 "hsic-1",
749};
750
751static const char * const tegra124_uart_groups[] = {
752 "otg-0",
753 "otg-1",
754 "otg-2",
755};
756
757static const char * const tegra124_pcie_groups[] = {
758 "pcie-0",
759 "pcie-1",
760 "pcie-2",
761 "pcie-3",
762 "pcie-4",
763 "sata-0",
764};
765
766static const char * const tegra124_usb3_groups[] = {
767 "pcie-0",
768 "pcie-1",
769 "pcie-2",
770 "pcie-3",
771 "pcie-4",
772 "sata-0",
773};
774
775static const char * const tegra124_sata_groups[] = {
776 "pcie-0",
777 "pcie-1",
778 "pcie-2",
779 "pcie-3",
780 "pcie-4",
781 "sata-0",
782};
783
784static const char * const tegra124_rsvd_groups[] = {
785 "otg-0",
786 "otg-1",
787 "otg-2",
788 "pcie-0",
789 "pcie-1",
790 "pcie-2",
791 "pcie-3",
792 "pcie-4",
793 "sata-0",
794};
795
796#define TEGRA124_FUNCTION(_name) \
797 { \
798 .name = #_name, \
799 .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
800 .groups = tegra124_##_name##_groups, \
801 }
802
803static struct tegra_xusb_padctl_function tegra124_functions[] = {
804 TEGRA124_FUNCTION(snps),
805 TEGRA124_FUNCTION(xusb),
806 TEGRA124_FUNCTION(uart),
807 TEGRA124_FUNCTION(pcie),
808 TEGRA124_FUNCTION(usb3),
809 TEGRA124_FUNCTION(sata),
810 TEGRA124_FUNCTION(rsvd),
811};
812
813enum tegra124_function {
814 TEGRA124_FUNC_SNPS,
815 TEGRA124_FUNC_XUSB,
816 TEGRA124_FUNC_UART,
817 TEGRA124_FUNC_PCIE,
818 TEGRA124_FUNC_USB3,
819 TEGRA124_FUNC_SATA,
820 TEGRA124_FUNC_RSVD,
821};
822
823static const unsigned int tegra124_otg_functions[] = {
824 TEGRA124_FUNC_SNPS,
825 TEGRA124_FUNC_XUSB,
826 TEGRA124_FUNC_UART,
827 TEGRA124_FUNC_RSVD,
828};
829
830static const unsigned int tegra124_usb_functions[] = {
831 TEGRA124_FUNC_SNPS,
832 TEGRA124_FUNC_XUSB,
833};
834
835static const unsigned int tegra124_pci_functions[] = {
836 TEGRA124_FUNC_PCIE,
837 TEGRA124_FUNC_USB3,
838 TEGRA124_FUNC_SATA,
839 TEGRA124_FUNC_RSVD,
840};
841
842#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
843 { \
844 .name = _name, \
845 .offset = _offset, \
846 .shift = _shift, \
847 .mask = _mask, \
848 .iddq = _iddq, \
849 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
850 .funcs = tegra124_##_funcs##_functions, \
851 }
852
853static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
854 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
855 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
856 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
857 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
858 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
859 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
860 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
861 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
862 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
863 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
864 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
865 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
866};
867
868static const struct tegra_xusb_padctl_soc tegra124_soc = {
869 .num_pins = ARRAY_SIZE(tegra124_pins),
870 .pins = tegra124_pins,
871 .num_functions = ARRAY_SIZE(tegra124_functions),
872 .functions = tegra124_functions,
873 .num_lanes = ARRAY_SIZE(tegra124_lanes),
874 .lanes = tegra124_lanes,
875};
876
877static const struct of_device_id tegra_xusb_padctl_of_match[] = {
878 { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
879 { }
880};
881MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
882
883static int tegra_xusb_padctl_probe(struct platform_device *pdev)
884{
885 struct tegra_xusb_padctl *padctl;
886 const struct of_device_id *match;
887 struct resource *res;
888 struct phy *phy;
889 int err;
890
891 padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
892 if (!padctl)
893 return -ENOMEM;
894
895 platform_set_drvdata(pdev, padctl);
896 mutex_init(&padctl->lock);
897 padctl->dev = &pdev->dev;
898
899 match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
900 padctl->soc = match->data;
901
902 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
903 padctl->regs = devm_ioremap_resource(&pdev->dev, res);
904 if (IS_ERR(padctl->regs))
905 return PTR_ERR(padctl->regs);
906
907 padctl->rst = devm_reset_control_get(&pdev->dev, NULL);
908 if (IS_ERR(padctl->rst))
909 return PTR_ERR(padctl->rst);
910
911 err = reset_control_deassert(padctl->rst);
912 if (err < 0)
913 return err;
914
915 memset(&padctl->desc, 0, sizeof(padctl->desc));
916 padctl->desc.name = dev_name(padctl->dev);
8480c2e7
JH		 917 padctl->desc.pins = tegra124_pins;
918 padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
dc0a3938
TR		 919 padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
920 padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
921 padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
922 padctl->desc.owner = THIS_MODULE;
923
924 padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl);
323de9ef 925 if (IS_ERR(padctl->pinctrl)) {
dc0a3938 926 dev_err(&pdev->dev, "failed to register pincontrol\n");
323de9ef 927 err = PTR_ERR(padctl->pinctrl);
dc0a3938
TR		 928 goto reset;
929 }
930
dbc98635 931 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
dc0a3938
TR		 932 if (IS_ERR(phy)) {
933 err = PTR_ERR(phy);
934 goto unregister;
935 }
936
937 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
938 phy_set_drvdata(phy, padctl);
939
dbc98635 940 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
dc0a3938
TR		 941 if (IS_ERR(phy)) {
942 err = PTR_ERR(phy);
943 goto unregister;
944 }
945
946 padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
947 phy_set_drvdata(phy, padctl);
948
949 padctl->provider = devm_of_phy_provider_register(&pdev->dev,
950 tegra_xusb_padctl_xlate);
8a3cfb7c
DC		 951 if (IS_ERR(padctl->provider)) {
952 err = PTR_ERR(padctl->provider);
dc0a3938
TR		 953 dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
954 goto unregister;
955 }
956
957 return 0;
958
959unregister:
960 pinctrl_unregister(padctl->pinctrl);
961reset:
962 reset_control_assert(padctl->rst);
963 return err;
964}
965
966static int tegra_xusb_padctl_remove(struct platform_device *pdev)
967{
968 struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
969 int err;
970
971 pinctrl_unregister(padctl->pinctrl);
972
973 err = reset_control_assert(padctl->rst);
974 if (err < 0)
975 dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
976
977 return err;
978}
979
980static struct platform_driver tegra_xusb_padctl_driver = {
981 .driver = {
982 .name = "tegra-xusb-padctl",
983 .of_match_table = tegra_xusb_padctl_of_match,
984 },
985 .probe = tegra_xusb_padctl_probe,
986 .remove = tegra_xusb_padctl_remove,
987};
988module_platform_driver(tegra_xusb_padctl_driver);
989
990MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
991MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver");
992MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)