Commit | Line | Data |
---|---|---|
0e37f88d MR |
1 | /* |
2 | * Allwinner A1X SoCs pinctrl driver. | |
3 | * | |
4 | * Copyright (C) 2012 Maxime Ripard | |
5 | * | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/io.h> | |
08e9e614 | 14 | #include <linux/gpio.h> |
0e37f88d MR |
15 | #include <linux/module.h> |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_device.h> | |
19 | #include <linux/pinctrl/consumer.h> | |
20 | #include <linux/pinctrl/machine.h> | |
21 | #include <linux/pinctrl/pinctrl.h> | |
22 | #include <linux/pinctrl/pinconf-generic.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | ||
27 | #include "core.h" | |
28 | #include "pinctrl-sunxi.h" | |
29 | ||
9f5b6b30 MR |
30 | static const struct sunxi_desc_pin sun4i_a10_pins[] = { |
31 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, | |
32 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
33 | SUNXI_FUNCTION(0x1, "gpio_out"), |
34 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXD3 */ | |
35 | SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ | |
36 | SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ | |
9f5b6b30 MR |
37 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, |
38 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
39 | SUNXI_FUNCTION(0x1, "gpio_out"), |
40 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXD2 */ | |
41 | SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ | |
42 | SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ | |
9f5b6b30 MR |
43 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, |
44 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
45 | SUNXI_FUNCTION(0x1, "gpio_out"), |
46 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXD1 */ | |
47 | SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ | |
48 | SUNXI_FUNCTION(0x4, "uart2")), /* TX */ | |
9f5b6b30 MR |
49 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, |
50 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
51 | SUNXI_FUNCTION(0x1, "gpio_out"), |
52 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXD0 */ | |
53 | SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ | |
54 | SUNXI_FUNCTION(0x4, "uart2")), /* RX */ | |
9f5b6b30 MR |
55 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, |
56 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
57 | SUNXI_FUNCTION(0x1, "gpio_out"), |
58 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXD3 */ | |
59 | SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ | |
9f5b6b30 MR |
60 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, |
61 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
62 | SUNXI_FUNCTION(0x1, "gpio_out"), |
63 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXD2 */ | |
64 | SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ | |
9f5b6b30 MR |
65 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, |
66 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
67 | SUNXI_FUNCTION(0x1, "gpio_out"), |
68 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXD1 */ | |
69 | SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ | |
9f5b6b30 MR |
70 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, |
71 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
72 | SUNXI_FUNCTION(0x1, "gpio_out"), |
73 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXD0 */ | |
74 | SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ | |
9f5b6b30 MR |
75 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, |
76 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
77 | SUNXI_FUNCTION(0x1, "gpio_out"), |
78 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXCK */ | |
79 | SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ | |
9f5b6b30 MR |
80 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, |
81 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
82 | SUNXI_FUNCTION(0x1, "gpio_out"), |
83 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXERR */ | |
84 | SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ | |
9f5b6b30 MR |
85 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, |
86 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
87 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 | 88 | SUNXI_FUNCTION(0x2, "wemac"), /* ERXDV */ |
9f5b6b30 MR |
89 | SUNXI_FUNCTION(0x4, "uart1")), /* TX */ |
90 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, | |
91 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
92 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 | 93 | SUNXI_FUNCTION(0x2, "wemac"), /* EMDC */ |
9f5b6b30 MR |
94 | SUNXI_FUNCTION(0x4, "uart1")), /* RX */ |
95 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, | |
96 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
97 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 MR |
98 | SUNXI_FUNCTION(0x2, "wemac"), /* EMDIO */ |
99 | SUNXI_FUNCTION(0x3, "uart6"), /* TX */ | |
9f5b6b30 MR |
100 | SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ |
101 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, | |
102 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
103 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 MR |
104 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXEN */ |
105 | SUNXI_FUNCTION(0x3, "uart6"), /* RX */ | |
9f5b6b30 MR |
106 | SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ |
107 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, | |
108 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
109 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 MR |
110 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXCK */ |
111 | SUNXI_FUNCTION(0x3, "uart7"), /* TX */ | |
9f5b6b30 MR |
112 | SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ |
113 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, | |
114 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
115 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 MR |
116 | SUNXI_FUNCTION(0x2, "wemac"), /* ECRS */ |
117 | SUNXI_FUNCTION(0x3, "uart7"), /* RX */ | |
9f5b6b30 MR |
118 | SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ |
119 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, | |
120 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
121 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 MR |
122 | SUNXI_FUNCTION(0x2, "wemac"), /* ECOL */ |
123 | SUNXI_FUNCTION(0x3, "can"), /* TX */ | |
9f5b6b30 MR |
124 | SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ |
125 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, | |
126 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
127 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 MR |
128 | SUNXI_FUNCTION(0x2, "wemac"), /* ETXERR */ |
129 | SUNXI_FUNCTION(0x3, "can"), /* RX */ | |
9f5b6b30 MR |
130 | SUNXI_FUNCTION(0x4, "uart1")), /* RING */ |
131 | /* Hole */ | |
132 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, | |
133 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
134 | SUNXI_FUNCTION(0x1, "gpio_out"), |
135 | SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ | |
9f5b6b30 MR |
136 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, |
137 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
138 | SUNXI_FUNCTION(0x1, "gpio_out"), |
139 | SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ | |
9f5b6b30 MR |
140 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, |
141 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
142 | SUNXI_FUNCTION(0x1, "gpio_out"), |
143 | SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ | |
9f5b6b30 MR |
144 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, |
145 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
146 | SUNXI_FUNCTION(0x1, "gpio_out"), |
147 | SUNXI_FUNCTION(0x2, "ir0")), /* TX */ | |
9f5b6b30 MR |
148 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, |
149 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
150 | SUNXI_FUNCTION(0x1, "gpio_out"), |
151 | SUNXI_FUNCTION(0x2, "ir0")), /* RX */ | |
9f5b6b30 MR |
152 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, |
153 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
154 | SUNXI_FUNCTION(0x1, "gpio_out"), |
155 | SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ | |
156 | SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ | |
9f5b6b30 MR |
157 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, |
158 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
159 | SUNXI_FUNCTION(0x1, "gpio_out"), |
160 | SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ | |
161 | SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ | |
9f5b6b30 MR |
162 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, |
163 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
164 | SUNXI_FUNCTION(0x1, "gpio_out"), |
165 | SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ | |
166 | SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ | |
9f5b6b30 MR |
167 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, |
168 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
169 | SUNXI_FUNCTION(0x1, "gpio_out"), |
170 | SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ | |
171 | SUNXI_FUNCTION(0x3, "ac97")), /* DO */ | |
9f5b6b30 MR |
172 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, |
173 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
174 | SUNXI_FUNCTION(0x1, "gpio_out"), |
175 | SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ | |
9f5b6b30 MR |
176 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, |
177 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
178 | SUNXI_FUNCTION(0x1, "gpio_out"), |
179 | SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ | |
9f5b6b30 MR |
180 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, |
181 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
182 | SUNXI_FUNCTION(0x1, "gpio_out"), |
183 | SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ | |
9f5b6b30 MR |
184 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, |
185 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
186 | SUNXI_FUNCTION(0x1, "gpio_out"), |
187 | SUNXI_FUNCTION(0x2, "i2s"), /* DI */ | |
188 | SUNXI_FUNCTION(0x3, "ac97")), /* DI */ | |
9f5b6b30 MR |
189 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, |
190 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
191 | SUNXI_FUNCTION(0x1, "gpio_out"), |
192 | SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ | |
9f5b6b30 MR |
193 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, |
194 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
195 | SUNXI_FUNCTION(0x1, "gpio_out"), |
196 | SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ | |
197 | SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ | |
9f5b6b30 MR |
198 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, |
199 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
200 | SUNXI_FUNCTION(0x1, "gpio_out"), |
201 | SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ | |
202 | SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ | |
9f5b6b30 MR |
203 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, |
204 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
205 | SUNXI_FUNCTION(0x1, "gpio_out"), |
206 | SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ | |
207 | SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ | |
9f5b6b30 MR |
208 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, |
209 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
210 | SUNXI_FUNCTION(0x1, "gpio_out"), |
211 | SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ | |
212 | SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ | |
9f5b6b30 MR |
213 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, |
214 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
215 | SUNXI_FUNCTION(0x1, "gpio_out"), |
216 | SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ | |
9f5b6b30 MR |
217 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, |
218 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
219 | SUNXI_FUNCTION(0x1, "gpio_out"), |
220 | SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ | |
9f5b6b30 MR |
221 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, |
222 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
223 | SUNXI_FUNCTION(0x1, "gpio_out"), |
224 | SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ | |
9f5b6b30 MR |
225 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, |
226 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
227 | SUNXI_FUNCTION(0x1, "gpio_out"), |
228 | SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ | |
9f5b6b30 MR |
229 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, |
230 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
231 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 MR |
232 | SUNXI_FUNCTION(0x2, "uart0"), /* TX */ |
233 | SUNXI_FUNCTION(0x3, "ir1")), /* TX */ | |
9f5b6b30 MR |
234 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, |
235 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
236 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 MR |
237 | SUNXI_FUNCTION(0x2, "uart0"), /* RX */ |
238 | SUNXI_FUNCTION(0x3, "ir1")), /* RX */ | |
9f5b6b30 MR |
239 | /* Hole */ |
240 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, | |
241 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
242 | SUNXI_FUNCTION(0x1, "gpio_out"), |
243 | SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ | |
244 | SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ | |
9f5b6b30 MR |
245 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, |
246 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
247 | SUNXI_FUNCTION(0x1, "gpio_out"), |
248 | SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ | |
249 | SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ | |
9f5b6b30 MR |
250 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, |
251 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
252 | SUNXI_FUNCTION(0x1, "gpio_out"), |
253 | SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ | |
254 | SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ | |
9f5b6b30 MR |
255 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, |
256 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
257 | SUNXI_FUNCTION(0x1, "gpio_out"), |
258 | SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ | |
9f5b6b30 MR |
259 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, |
260 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
261 | SUNXI_FUNCTION(0x1, "gpio_out"), |
262 | SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ | |
9f5b6b30 MR |
263 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, |
264 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
265 | SUNXI_FUNCTION(0x1, "gpio_out"), |
266 | SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ | |
9f5b6b30 MR |
267 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, |
268 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
269 | SUNXI_FUNCTION(0x1, "gpio_out"), |
270 | SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ | |
271 | SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ | |
9f5b6b30 MR |
272 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, |
273 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
274 | SUNXI_FUNCTION(0x1, "gpio_out"), |
275 | SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ | |
276 | SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ | |
9f5b6b30 MR |
277 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, |
278 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
279 | SUNXI_FUNCTION(0x1, "gpio_out"), |
280 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ | |
281 | SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ | |
9f5b6b30 MR |
282 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, |
283 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
284 | SUNXI_FUNCTION(0x1, "gpio_out"), |
285 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ | |
286 | SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ | |
9f5b6b30 MR |
287 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, |
288 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
289 | SUNXI_FUNCTION(0x1, "gpio_out"), |
290 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ | |
291 | SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ | |
9f5b6b30 MR |
292 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, |
293 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
294 | SUNXI_FUNCTION(0x1, "gpio_out"), |
295 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ | |
296 | SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ | |
9f5b6b30 MR |
297 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, |
298 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
299 | SUNXI_FUNCTION(0x1, "gpio_out"), |
300 | SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ | |
9f5b6b30 MR |
301 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, |
302 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
303 | SUNXI_FUNCTION(0x1, "gpio_out"), |
304 | SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ | |
9f5b6b30 MR |
305 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, |
306 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
307 | SUNXI_FUNCTION(0x1, "gpio_out"), |
308 | SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ | |
9f5b6b30 MR |
309 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, |
310 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
311 | SUNXI_FUNCTION(0x1, "gpio_out"), |
312 | SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ | |
9f5b6b30 MR |
313 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, |
314 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
315 | SUNXI_FUNCTION(0x1, "gpio_out"), |
316 | SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ | |
9f5b6b30 MR |
317 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, |
318 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
319 | SUNXI_FUNCTION(0x1, "gpio_out"), |
320 | SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ | |
9f5b6b30 MR |
321 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, |
322 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
323 | SUNXI_FUNCTION(0x1, "gpio_out"), |
324 | SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ | |
9f5b6b30 MR |
325 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, |
326 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
327 | SUNXI_FUNCTION(0x1, "gpio_out"), |
328 | SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ | |
329 | SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ | |
9f5b6b30 MR |
330 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, |
331 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
332 | SUNXI_FUNCTION(0x1, "gpio_out"), |
333 | SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ | |
334 | SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ | |
9f5b6b30 MR |
335 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, |
336 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
337 | SUNXI_FUNCTION(0x1, "gpio_out"), |
338 | SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ | |
339 | SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ | |
9f5b6b30 MR |
340 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, |
341 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
342 | SUNXI_FUNCTION(0x1, "gpio_out"), |
343 | SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ | |
344 | SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ | |
9f5b6b30 MR |
345 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, |
346 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
347 | SUNXI_FUNCTION(0x1, "gpio_out"), |
348 | SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ | |
9f5b6b30 MR |
349 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, |
350 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
351 | SUNXI_FUNCTION(0x1, "gpio_out"), |
352 | SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ | |
9f5b6b30 MR |
353 | /* Hole */ |
354 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, | |
355 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
356 | SUNXI_FUNCTION(0x1, "gpio_out"), |
357 | SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ | |
358 | SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ | |
9f5b6b30 MR |
359 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, |
360 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
361 | SUNXI_FUNCTION(0x1, "gpio_out"), |
362 | SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ | |
363 | SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ | |
9f5b6b30 MR |
364 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, |
365 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
366 | SUNXI_FUNCTION(0x1, "gpio_out"), |
367 | SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ | |
368 | SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ | |
9f5b6b30 MR |
369 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, |
370 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
371 | SUNXI_FUNCTION(0x1, "gpio_out"), |
372 | SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ | |
373 | SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ | |
9f5b6b30 MR |
374 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, |
375 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
376 | SUNXI_FUNCTION(0x1, "gpio_out"), |
377 | SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ | |
378 | SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ | |
9f5b6b30 MR |
379 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, |
380 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
381 | SUNXI_FUNCTION(0x1, "gpio_out"), |
382 | SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ | |
383 | SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ | |
9f5b6b30 MR |
384 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, |
385 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
386 | SUNXI_FUNCTION(0x1, "gpio_out"), |
387 | SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ | |
388 | SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ | |
9f5b6b30 MR |
389 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, |
390 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
391 | SUNXI_FUNCTION(0x1, "gpio_out"), |
392 | SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ | |
393 | SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ | |
9f5b6b30 MR |
394 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, |
395 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
396 | SUNXI_FUNCTION(0x1, "gpio_out"), |
397 | SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ | |
398 | SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ | |
9f5b6b30 MR |
399 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, |
400 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
401 | SUNXI_FUNCTION(0x1, "gpio_out"), |
402 | SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ | |
403 | SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ | |
9f5b6b30 MR |
404 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, |
405 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
406 | SUNXI_FUNCTION(0x1, "gpio_out"), |
407 | SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ | |
408 | SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ | |
9f5b6b30 MR |
409 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, |
410 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
411 | SUNXI_FUNCTION(0x1, "gpio_out"), |
412 | SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ | |
413 | SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ | |
9f5b6b30 MR |
414 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, |
415 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
416 | SUNXI_FUNCTION(0x1, "gpio_out"), |
417 | SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ | |
418 | SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ | |
9f5b6b30 MR |
419 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, |
420 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
421 | SUNXI_FUNCTION(0x1, "gpio_out"), |
422 | SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ | |
423 | SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ | |
9f5b6b30 MR |
424 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, |
425 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
426 | SUNXI_FUNCTION(0x1, "gpio_out"), |
427 | SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ | |
428 | SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ | |
9f5b6b30 MR |
429 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, |
430 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
431 | SUNXI_FUNCTION(0x1, "gpio_out"), |
432 | SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ | |
433 | SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ | |
9f5b6b30 MR |
434 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, |
435 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
436 | SUNXI_FUNCTION(0x1, "gpio_out"), |
437 | SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ | |
438 | SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ | |
9f5b6b30 MR |
439 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, |
440 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
441 | SUNXI_FUNCTION(0x1, "gpio_out"), |
442 | SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ | |
443 | SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ | |
9f5b6b30 MR |
444 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, |
445 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
446 | SUNXI_FUNCTION(0x1, "gpio_out"), |
447 | SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ | |
448 | SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ | |
9f5b6b30 MR |
449 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, |
450 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
451 | SUNXI_FUNCTION(0x1, "gpio_out"), |
452 | SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ | |
453 | SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ | |
9f5b6b30 MR |
454 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, |
455 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
456 | SUNXI_FUNCTION(0x1, "gpio_out"), |
457 | SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ | |
458 | SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ | |
9f5b6b30 MR |
459 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, |
460 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
461 | SUNXI_FUNCTION(0x1, "gpio_out"), |
462 | SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ | |
463 | SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ | |
9f5b6b30 MR |
464 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, |
465 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
466 | SUNXI_FUNCTION(0x1, "gpio_out"), |
467 | SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ | |
468 | SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ | |
9f5b6b30 MR |
469 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, |
470 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
471 | SUNXI_FUNCTION(0x1, "gpio_out"), |
472 | SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ | |
473 | SUNXI_FUNCTION(0x3, "sim")), /* DET */ | |
9f5b6b30 MR |
474 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, |
475 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
476 | SUNXI_FUNCTION(0x1, "gpio_out"), |
477 | SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ | |
478 | SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ | |
9f5b6b30 MR |
479 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, |
480 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
481 | SUNXI_FUNCTION(0x1, "gpio_out"), |
482 | SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ | |
483 | SUNXI_FUNCTION(0x3, "sim")), /* RST */ | |
9f5b6b30 MR |
484 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, |
485 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
486 | SUNXI_FUNCTION(0x1, "gpio_out"), |
487 | SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ | |
488 | SUNXI_FUNCTION(0x3, "sim")), /* SCK */ | |
9f5b6b30 MR |
489 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, |
490 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
491 | SUNXI_FUNCTION(0x1, "gpio_out"), |
492 | SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ | |
493 | SUNXI_FUNCTION(0x3, "sim")), /* SDA */ | |
9f5b6b30 MR |
494 | /* Hole */ |
495 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, | |
496 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
497 | SUNXI_FUNCTION(0x1, "gpio_out"), |
498 | SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ | |
499 | SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ | |
9f5b6b30 MR |
500 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, |
501 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
502 | SUNXI_FUNCTION(0x1, "gpio_out"), |
503 | SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ | |
504 | SUNXI_FUNCTION(0x3, "csi0")), /* CK */ | |
9f5b6b30 MR |
505 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, |
506 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
507 | SUNXI_FUNCTION(0x1, "gpio_out"), |
508 | SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ | |
509 | SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ | |
9f5b6b30 MR |
510 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, |
511 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
512 | SUNXI_FUNCTION(0x1, "gpio_out"), |
513 | SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ | |
514 | SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ | |
9f5b6b30 MR |
515 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, |
516 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
517 | SUNXI_FUNCTION(0x1, "gpio_out"), |
518 | SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ | |
519 | SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ | |
9f5b6b30 MR |
520 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, |
521 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
522 | SUNXI_FUNCTION(0x1, "gpio_out"), |
523 | SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ | |
524 | SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ | |
525 | SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ | |
9f5b6b30 MR |
526 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, |
527 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
528 | SUNXI_FUNCTION(0x1, "gpio_out"), |
529 | SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ | |
530 | SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ | |
9f5b6b30 MR |
531 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, |
532 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
533 | SUNXI_FUNCTION(0x1, "gpio_out"), |
534 | SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ | |
535 | SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ | |
9f5b6b30 MR |
536 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, |
537 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
538 | SUNXI_FUNCTION(0x1, "gpio_out"), |
539 | SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ | |
540 | SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ | |
9f5b6b30 MR |
541 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, |
542 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
543 | SUNXI_FUNCTION(0x1, "gpio_out"), |
544 | SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ | |
545 | SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ | |
9f5b6b30 MR |
546 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, |
547 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
548 | SUNXI_FUNCTION(0x1, "gpio_out"), |
549 | SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ | |
550 | SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ | |
9f5b6b30 MR |
551 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, |
552 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
553 | SUNXI_FUNCTION(0x1, "gpio_out"), |
554 | SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ | |
555 | SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ | |
9f5b6b30 MR |
556 | /* Hole */ |
557 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, | |
558 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
559 | SUNXI_FUNCTION(0x1, "gpio_out"), |
560 | SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ | |
561 | SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ | |
9f5b6b30 MR |
562 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, |
563 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
564 | SUNXI_FUNCTION(0x1, "gpio_out"), |
565 | SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ | |
566 | SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ | |
9f5b6b30 MR |
567 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, |
568 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
569 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 | 570 | SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ |
9f5b6b30 MR |
571 | SUNXI_FUNCTION(0x4, "uart0")), /* TX */ |
572 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, | |
573 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
574 | SUNXI_FUNCTION(0x1, "gpio_out"), |
575 | SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ | |
576 | SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ | |
9f5b6b30 MR |
577 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, |
578 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
579 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
b5f50bf9 | 580 | SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ |
9f5b6b30 MR |
581 | SUNXI_FUNCTION(0x4, "uart0")), /* RX */ |
582 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, | |
583 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
584 | SUNXI_FUNCTION(0x1, "gpio_out"), |
585 | SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ | |
586 | SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ | |
9f5b6b30 MR |
587 | /* Hole */ |
588 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, | |
589 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
590 | SUNXI_FUNCTION(0x1, "gpio_out"), |
591 | SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ | |
592 | SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ | |
593 | SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ | |
9f5b6b30 MR |
594 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, |
595 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
596 | SUNXI_FUNCTION(0x1, "gpio_out"), |
597 | SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ | |
598 | SUNXI_FUNCTION(0x3, "csi1"), /* CK */ | |
599 | SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ | |
9f5b6b30 MR |
600 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, |
601 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
602 | SUNXI_FUNCTION(0x1, "gpio_out"), |
603 | SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ | |
604 | SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ | |
605 | SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ | |
9f5b6b30 MR |
606 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, |
607 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
608 | SUNXI_FUNCTION(0x1, "gpio_out"), |
609 | SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ | |
610 | SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ | |
611 | SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ | |
9f5b6b30 MR |
612 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, |
613 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
614 | SUNXI_FUNCTION(0x1, "gpio_out"), |
615 | SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ | |
616 | SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ | |
617 | SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ | |
618 | SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ | |
9f5b6b30 MR |
619 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, |
620 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
621 | SUNXI_FUNCTION(0x1, "gpio_out"), |
622 | SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ | |
623 | SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ | |
624 | SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ | |
625 | SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ | |
9f5b6b30 MR |
626 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, |
627 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
628 | SUNXI_FUNCTION(0x1, "gpio_out"), |
629 | SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ | |
630 | SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ | |
631 | SUNXI_FUNCTION(0x4, "uart3"), /* TX */ | |
632 | SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ | |
9f5b6b30 MR |
633 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, |
634 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
635 | SUNXI_FUNCTION(0x1, "gpio_out"), |
636 | SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ | |
637 | SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ | |
638 | SUNXI_FUNCTION(0x4, "uart3"), /* RX */ | |
639 | SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ | |
9f5b6b30 MR |
640 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, |
641 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
642 | SUNXI_FUNCTION(0x1, "gpio_out"), |
643 | SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ | |
644 | SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ | |
645 | SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ | |
646 | SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ | |
9f5b6b30 MR |
647 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, |
648 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
649 | SUNXI_FUNCTION(0x1, "gpio_out"), |
650 | SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ | |
651 | SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ | |
652 | SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ | |
653 | SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ | |
9f5b6b30 MR |
654 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, |
655 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
656 | SUNXI_FUNCTION(0x1, "gpio_out"), |
657 | SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ | |
658 | SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ | |
659 | SUNXI_FUNCTION(0x4, "uart4"), /* TX */ | |
660 | SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ | |
9f5b6b30 MR |
661 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, |
662 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
663 | SUNXI_FUNCTION(0x1, "gpio_out"), |
664 | SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ | |
665 | SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ | |
666 | SUNXI_FUNCTION(0x4, "uart4"), /* RX */ | |
667 | SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ | |
9f5b6b30 MR |
668 | /* Hole */ |
669 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, | |
670 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
671 | SUNXI_FUNCTION(0x1, "gpio_out"), |
672 | SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ | |
673 | SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ | |
674 | SUNXI_FUNCTION(0x4, "uart3"), /* TX */ | |
675 | SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ | |
9f5b6b30 MR |
676 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, |
677 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
678 | SUNXI_FUNCTION(0x1, "gpio_out"), |
679 | SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ | |
680 | SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ | |
681 | SUNXI_FUNCTION(0x4, "uart3"), /* RX */ | |
682 | SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ | |
9f5b6b30 MR |
683 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, |
684 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
685 | SUNXI_FUNCTION(0x1, "gpio_out"), |
686 | SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ | |
687 | SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ | |
688 | SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ | |
689 | SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ | |
9f5b6b30 MR |
690 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, |
691 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
692 | SUNXI_FUNCTION(0x1, "gpio_out"), |
693 | SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ | |
694 | SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ | |
695 | SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ | |
696 | SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ | |
9f5b6b30 MR |
697 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, |
698 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
699 | SUNXI_FUNCTION(0x1, "gpio_out"), |
700 | SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ | |
701 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ | |
702 | SUNXI_FUNCTION(0x4, "uart4"), /* TX */ | |
703 | SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ | |
9f5b6b30 MR |
704 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, |
705 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
706 | SUNXI_FUNCTION(0x1, "gpio_out"), |
707 | SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ | |
708 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ | |
709 | SUNXI_FUNCTION(0x4, "uart4"), /* RX */ | |
710 | SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ | |
9f5b6b30 MR |
711 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, |
712 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
713 | SUNXI_FUNCTION(0x1, "gpio_out"), |
714 | SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ | |
715 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ | |
716 | SUNXI_FUNCTION(0x4, "uart5"), /* TX */ | |
717 | SUNXI_FUNCTION(0x5, "ms"), /* BS */ | |
718 | SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ | |
9f5b6b30 MR |
719 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, |
720 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
721 | SUNXI_FUNCTION(0x1, "gpio_out"), |
722 | SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ | |
723 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ | |
724 | SUNXI_FUNCTION(0x4, "uart5"), /* RX */ | |
725 | SUNXI_FUNCTION(0x5, "ms"), /* CLK */ | |
726 | SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ | |
9f5b6b30 MR |
727 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, |
728 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
729 | SUNXI_FUNCTION(0x1, "gpio_out"), |
730 | SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ | |
731 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ | |
732 | SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ | |
733 | SUNXI_FUNCTION(0x5, "ms"), /* D0 */ | |
734 | SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ | |
9f5b6b30 MR |
735 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, |
736 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
737 | SUNXI_FUNCTION(0x1, "gpio_out"), |
738 | SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ | |
739 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ | |
740 | SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ | |
741 | SUNXI_FUNCTION(0x5, "ms"), /* D1 */ | |
742 | SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ | |
9f5b6b30 MR |
743 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, |
744 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
745 | SUNXI_FUNCTION(0x1, "gpio_out"), |
746 | SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ | |
747 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ | |
748 | SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ | |
749 | SUNXI_FUNCTION(0x5, "ms"), /* D2 */ | |
750 | SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ | |
9f5b6b30 MR |
751 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, |
752 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
753 | SUNXI_FUNCTION(0x1, "gpio_out"), |
754 | SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ | |
755 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ | |
756 | SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ | |
757 | SUNXI_FUNCTION(0x5, "ms"), /* D3 */ | |
758 | SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ | |
9f5b6b30 MR |
759 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, |
760 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
761 | SUNXI_FUNCTION(0x1, "gpio_out"), |
762 | SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ | |
763 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ | |
764 | SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ | |
765 | SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ | |
9f5b6b30 MR |
766 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, |
767 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
768 | SUNXI_FUNCTION(0x1, "gpio_out"), |
769 | SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ | |
770 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ | |
771 | SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ | |
772 | SUNXI_FUNCTION(0x5, "sim"), /* RST */ | |
773 | SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ | |
9f5b6b30 MR |
774 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, |
775 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
776 | SUNXI_FUNCTION(0x1, "gpio_out"), |
777 | SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ | |
778 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ | |
779 | SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ | |
780 | SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ | |
781 | SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ | |
9f5b6b30 MR |
782 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, |
783 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
784 | SUNXI_FUNCTION(0x1, "gpio_out"), |
785 | SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ | |
786 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ | |
787 | SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ | |
788 | SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ | |
789 | SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ | |
9f5b6b30 MR |
790 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, |
791 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
792 | SUNXI_FUNCTION(0x1, "gpio_out"), |
793 | SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ | |
794 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ | |
795 | SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ | |
796 | SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ | |
9f5b6b30 MR |
797 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, |
798 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
799 | SUNXI_FUNCTION(0x1, "gpio_out"), |
800 | SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ | |
801 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ | |
802 | SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ | |
803 | SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ | |
804 | SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ | |
9f5b6b30 MR |
805 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, |
806 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
807 | SUNXI_FUNCTION(0x1, "gpio_out"), |
808 | SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ | |
809 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ | |
810 | SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ | |
811 | SUNXI_FUNCTION(0x5, "sim"), /* SCK */ | |
812 | SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ | |
9f5b6b30 MR |
813 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, |
814 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
815 | SUNXI_FUNCTION(0x1, "gpio_out"), |
816 | SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ | |
817 | SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ | |
818 | SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ | |
819 | SUNXI_FUNCTION(0x5, "sim"), /* SDA */ | |
820 | SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ | |
9f5b6b30 MR |
821 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, |
822 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
823 | SUNXI_FUNCTION(0x1, "gpio_out"), |
824 | SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ | |
825 | SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ | |
826 | SUNXI_FUNCTION(0x4, "can"), /* TX */ | |
827 | SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ | |
9f5b6b30 MR |
828 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, |
829 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
830 | SUNXI_FUNCTION(0x1, "gpio_out"), |
831 | SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ | |
832 | SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ | |
833 | SUNXI_FUNCTION(0x4, "can"), /* RX */ | |
834 | SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ | |
9f5b6b30 MR |
835 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, |
836 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
837 | SUNXI_FUNCTION(0x1, "gpio_out"), |
838 | SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ | |
839 | SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ | |
840 | SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ | |
841 | SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ | |
842 | SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ | |
9f5b6b30 MR |
843 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, |
844 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
845 | SUNXI_FUNCTION(0x1, "gpio_out"), |
846 | SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ | |
847 | SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ | |
848 | SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ | |
849 | SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ | |
850 | SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ | |
9f5b6b30 MR |
851 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, |
852 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
853 | SUNXI_FUNCTION(0x1, "gpio_out"), |
854 | SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ | |
855 | SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ | |
856 | SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ | |
857 | SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ | |
858 | SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ | |
9f5b6b30 MR |
859 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, |
860 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
861 | SUNXI_FUNCTION(0x1, "gpio_out"), |
862 | SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ | |
863 | SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ | |
864 | SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ | |
865 | SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ | |
866 | SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ | |
9f5b6b30 MR |
867 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, |
868 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
869 | SUNXI_FUNCTION(0x1, "gpio_out"), |
870 | SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ | |
871 | SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ | |
872 | SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ | |
873 | SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ | |
874 | SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ | |
9f5b6b30 MR |
875 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, |
876 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
877 | SUNXI_FUNCTION(0x1, "gpio_out"), |
878 | SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ | |
879 | SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ | |
880 | SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ | |
881 | SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ | |
882 | SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ | |
9f5b6b30 MR |
883 | /* Hole */ |
884 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, | |
885 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
886 | SUNXI_FUNCTION(0x1, "gpio_out")), | |
887 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, | |
888 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
889 | SUNXI_FUNCTION(0x1, "gpio_out")), | |
890 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, | |
891 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
892 | SUNXI_FUNCTION(0x1, "gpio_out")), | |
893 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, | |
894 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
895 | SUNXI_FUNCTION(0x1, "gpio_out"), |
896 | SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ | |
9f5b6b30 MR |
897 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, |
898 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
899 | SUNXI_FUNCTION(0x1, "gpio_out"), |
900 | SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ | |
9f5b6b30 MR |
901 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, |
902 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
903 | SUNXI_FUNCTION(0x1, "gpio_out"), |
904 | SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ | |
9f5b6b30 MR |
905 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, |
906 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
907 | SUNXI_FUNCTION(0x1, "gpio_out"), |
908 | SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ | |
9f5b6b30 MR |
909 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, |
910 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
911 | SUNXI_FUNCTION(0x1, "gpio_out"), |
912 | SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ | |
9f5b6b30 MR |
913 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, |
914 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
915 | SUNXI_FUNCTION(0x1, "gpio_out"), |
916 | SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ | |
9f5b6b30 MR |
917 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, |
918 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
919 | SUNXI_FUNCTION(0x1, "gpio_out"), |
920 | SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ | |
9f5b6b30 MR |
921 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, |
922 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
923 | SUNXI_FUNCTION(0x1, "gpio_out"), |
924 | SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ | |
925 | SUNXI_FUNCTION(0x3, "uart5")), /* TX */ | |
9f5b6b30 MR |
926 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, |
927 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
928 | SUNXI_FUNCTION(0x1, "gpio_out"), |
929 | SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ | |
930 | SUNXI_FUNCTION(0x3, "uart5")), /* RX */ | |
9f5b6b30 MR |
931 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, |
932 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
933 | SUNXI_FUNCTION(0x1, "gpio_out"), |
934 | SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ | |
935 | SUNXI_FUNCTION(0x3, "uart6")), /* TX */ | |
9f5b6b30 MR |
936 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, |
937 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
938 | SUNXI_FUNCTION(0x1, "gpio_out"), |
939 | SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ | |
940 | SUNXI_FUNCTION(0x3, "uart6")), /* RX */ | |
9f5b6b30 MR |
941 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, |
942 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
943 | SUNXI_FUNCTION(0x1, "gpio_out"), |
944 | SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ | |
945 | SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ | |
946 | SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */ | |
9f5b6b30 MR |
947 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, |
948 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
949 | SUNXI_FUNCTION(0x1, "gpio_out"), |
950 | SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ | |
951 | SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ | |
952 | SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */ | |
9f5b6b30 MR |
953 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, |
954 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
955 | SUNXI_FUNCTION(0x1, "gpio_out"), |
956 | SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ | |
957 | SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ | |
9f5b6b30 MR |
958 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, |
959 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
960 | SUNXI_FUNCTION(0x1, "gpio_out"), |
961 | SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ | |
962 | SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ | |
9f5b6b30 MR |
963 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, |
964 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
965 | SUNXI_FUNCTION(0x1, "gpio_out"), |
966 | SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ | |
967 | SUNXI_FUNCTION(0x3, "uart2")), /* TX */ | |
9f5b6b30 MR |
968 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, |
969 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
970 | SUNXI_FUNCTION(0x1, "gpio_out"), |
971 | SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ | |
972 | SUNXI_FUNCTION(0x3, "uart2")), /* RX */ | |
9f5b6b30 MR |
973 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, |
974 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
975 | SUNXI_FUNCTION(0x1, "gpio_out"), |
976 | SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ | |
977 | SUNXI_FUNCTION(0x3, "uart7"), /* TX */ | |
978 | SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ | |
9f5b6b30 MR |
979 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, |
980 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
b5f50bf9 MR |
981 | SUNXI_FUNCTION(0x1, "gpio_out"), |
982 | SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ | |
983 | SUNXI_FUNCTION(0x3, "uart7"), /* RX */ | |
984 | SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ | |
9f5b6b30 MR |
985 | }; |
986 | ||
eaa3d848 MR |
987 | static const struct sunxi_desc_pin sun5i_a13_pins[] = { |
988 | /* Hole */ | |
989 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, | |
990 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
991 | SUNXI_FUNCTION(0x1, "gpio_out"), |
992 | SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ | |
eaa3d848 MR |
993 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, |
994 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
995 | SUNXI_FUNCTION(0x1, "gpio_out"), |
996 | SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ | |
eaa3d848 MR |
997 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, |
998 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
999 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1000 | SUNXI_FUNCTION(0x2, "pwm")), | |
eaa3d848 MR |
1001 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, |
1002 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1003 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1004 | SUNXI_FUNCTION(0x2, "ir0")), /* TX */ | |
eaa3d848 MR |
1005 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, |
1006 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1007 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1008 | SUNXI_FUNCTION(0x2, "ir0")), /* RX */ | |
eaa3d848 MR |
1009 | /* Hole */ |
1010 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, | |
1011 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1012 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1013 | SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ | |
eaa3d848 MR |
1014 | /* Hole */ |
1015 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, | |
1016 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1017 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1018 | SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ | |
eaa3d848 MR |
1019 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, |
1020 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1021 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1022 | SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ | |
eaa3d848 MR |
1023 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, |
1024 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1025 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1026 | SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ | |
eaa3d848 MR |
1027 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, |
1028 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1029 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1030 | SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ | |
eaa3d848 MR |
1031 | /* Hole */ |
1032 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, | |
1033 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1034 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1035 | SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ | |
1036 | SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ | |
eaa3d848 MR |
1037 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, |
1038 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1039 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1040 | SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ | |
1041 | SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ | |
eaa3d848 MR |
1042 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, |
1043 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1044 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1045 | SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ | |
1046 | SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ | |
eaa3d848 MR |
1047 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, |
1048 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1049 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1050 | SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ | |
1051 | SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ | |
eaa3d848 MR |
1052 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, |
1053 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1054 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1055 | SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ | |
eaa3d848 MR |
1056 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, |
1057 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1058 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1059 | SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ | |
eaa3d848 MR |
1060 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, |
1061 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1062 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1063 | SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ | |
1064 | SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ | |
eaa3d848 MR |
1065 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, |
1066 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1067 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1068 | SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ | |
1069 | SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ | |
eaa3d848 MR |
1070 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, |
1071 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1072 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1073 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ | |
1074 | SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ | |
eaa3d848 MR |
1075 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, |
1076 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1077 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1078 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ | |
1079 | SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ | |
eaa3d848 MR |
1080 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, |
1081 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1082 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1083 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ | |
1084 | SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ | |
eaa3d848 MR |
1085 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, |
1086 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1087 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1088 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ | |
1089 | SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ | |
eaa3d848 MR |
1090 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, |
1091 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1092 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1093 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ | |
1094 | SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ | |
eaa3d848 MR |
1095 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, |
1096 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1097 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1098 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ | |
1099 | SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ | |
eaa3d848 MR |
1100 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, |
1101 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1102 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1103 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ | |
1104 | SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ | |
eaa3d848 MR |
1105 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, |
1106 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1107 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1108 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ | |
1109 | SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ | |
eaa3d848 MR |
1110 | /* Hole */ |
1111 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, | |
1112 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1113 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1114 | SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ | |
1115 | SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ | |
eaa3d848 MR |
1116 | /* Hole */ |
1117 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, | |
1118 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1119 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1120 | SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ | |
eaa3d848 MR |
1121 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, |
1122 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1123 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1124 | SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ | |
eaa3d848 MR |
1125 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, |
1126 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1127 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1128 | SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ | |
eaa3d848 MR |
1129 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, |
1130 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1131 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1132 | SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ | |
eaa3d848 MR |
1133 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, |
1134 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1135 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1136 | SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ | |
eaa3d848 MR |
1137 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, |
1138 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1139 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1140 | SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ | |
eaa3d848 MR |
1141 | /* Hole */ |
1142 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, | |
1143 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1144 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1145 | SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ | |
eaa3d848 MR |
1146 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, |
1147 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1148 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1149 | SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ | |
eaa3d848 MR |
1150 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, |
1151 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1152 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1153 | SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ | |
eaa3d848 MR |
1154 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, |
1155 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1156 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1157 | SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ | |
eaa3d848 MR |
1158 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, |
1159 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1160 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1161 | SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ | |
eaa3d848 MR |
1162 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, |
1163 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1164 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1165 | SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ | |
eaa3d848 MR |
1166 | /* Hole */ |
1167 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, | |
1168 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1169 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1170 | SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ | |
eaa3d848 MR |
1171 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, |
1172 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1173 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1174 | SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ | |
eaa3d848 MR |
1175 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, |
1176 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1177 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1178 | SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ | |
eaa3d848 MR |
1179 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, |
1180 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1181 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1182 | SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ | |
eaa3d848 MR |
1183 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, |
1184 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1185 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1186 | SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ | |
eaa3d848 MR |
1187 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, |
1188 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1189 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1190 | SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ | |
eaa3d848 MR |
1191 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, |
1192 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1193 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1194 | SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ | |
eaa3d848 MR |
1195 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, |
1196 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1197 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1198 | SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ | |
eaa3d848 MR |
1199 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, |
1200 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1201 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1202 | SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ | |
eaa3d848 MR |
1203 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, |
1204 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1205 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1206 | SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ | |
eaa3d848 MR |
1207 | /* Hole */ |
1208 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, | |
1209 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1210 | SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ |
1211 | SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */ | |
eaa3d848 MR |
1212 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, |
1213 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1214 | SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ |
1215 | SUNXI_FUNCTION(0x4, "spi2")), /* CLK */ | |
eaa3d848 MR |
1216 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, |
1217 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1218 | SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ |
1219 | SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ | |
eaa3d848 MR |
1220 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, |
1221 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1222 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1223 | SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ | |
1224 | SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ | |
eaa3d848 MR |
1225 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, |
1226 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1227 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1228 | SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ | |
1229 | SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ | |
eaa3d848 MR |
1230 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, |
1231 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1232 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1233 | SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ | |
1234 | SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ | |
eaa3d848 MR |
1235 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, |
1236 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1237 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1238 | SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ | |
1239 | SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ | |
eaa3d848 MR |
1240 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, |
1241 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1242 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1243 | SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ | |
1244 | SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ | |
eaa3d848 MR |
1245 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, |
1246 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1247 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1248 | SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ | |
1249 | SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ | |
eaa3d848 MR |
1250 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, |
1251 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1252 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1253 | SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ | |
1254 | SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ | |
eaa3d848 MR |
1255 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, |
1256 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
1257 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
ee341a99 | 1258 | SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ |
ae1575f7 | 1259 | SUNXI_FUNCTION(0x4, "uart1")), /* TX */ |
eaa3d848 MR |
1260 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, |
1261 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
1262 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
ee341a99 | 1263 | SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ |
ae1575f7 | 1264 | SUNXI_FUNCTION(0x4, "uart1")), /* RX */ |
eaa3d848 MR |
1265 | /* Hole */ |
1266 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, | |
1267 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1268 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1269 | SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ | |
eaa3d848 MR |
1270 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, |
1271 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1272 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1273 | SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ | |
eaa3d848 MR |
1274 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, |
1275 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1276 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1277 | SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ | |
eaa3d848 MR |
1278 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, |
1279 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1280 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1281 | SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ | |
eaa3d848 MR |
1282 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, |
1283 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1284 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1285 | SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ | |
eaa3d848 MR |
1286 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, |
1287 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1288 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1289 | SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ | |
eaa3d848 MR |
1290 | /* Hole */ |
1291 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, | |
1292 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
1293 | SUNXI_FUNCTION(0x1, "gpio_out")), | |
1294 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, | |
1295 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
1296 | SUNXI_FUNCTION(0x1, "gpio_out")), | |
1297 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, | |
1298 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
1299 | SUNXI_FUNCTION(0x1, "gpio_out")), | |
1300 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, | |
1301 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
1302 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
ee341a99 | 1303 | SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ |
ae1575f7 | 1304 | SUNXI_FUNCTION(0x4, "uart1")), /* TX */ |
eaa3d848 MR |
1305 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, |
1306 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
1307 | SUNXI_FUNCTION(0x1, "gpio_out"), | |
ee341a99 | 1308 | SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ |
ae1575f7 | 1309 | SUNXI_FUNCTION(0x4, "uart1")), /* RX */ |
ee341a99 | 1310 | /* Hole */ |
eaa3d848 MR |
1311 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, |
1312 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1313 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1314 | SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ | |
1315 | SUNXI_FUNCTION(0x3, "uart3")), /* TX */ | |
eaa3d848 MR |
1316 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, |
1317 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1318 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1319 | SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ | |
1320 | SUNXI_FUNCTION(0x3, "uart3")), /* RX */ | |
eaa3d848 MR |
1321 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, |
1322 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1323 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1324 | SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ | |
1325 | SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ | |
eaa3d848 MR |
1326 | SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, |
1327 | SUNXI_FUNCTION(0x0, "gpio_in"), | |
ee341a99 MR |
1328 | SUNXI_FUNCTION(0x1, "gpio_out"), |
1329 | SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ | |
1330 | SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ | |
eaa3d848 MR |
1331 | }; |
1332 | ||
9f5b6b30 MR |
1333 | static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { |
1334 | .pins = sun4i_a10_pins, | |
1335 | .npins = ARRAY_SIZE(sun4i_a10_pins), | |
1336 | }; | |
1337 | ||
eaa3d848 MR |
1338 | static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { |
1339 | .pins = sun5i_a13_pins, | |
1340 | .npins = ARRAY_SIZE(sun5i_a13_pins), | |
1341 | }; | |
1342 | ||
0e37f88d MR |
1343 | static struct sunxi_pinctrl_group * |
1344 | sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) | |
1345 | { | |
1346 | int i; | |
1347 | ||
1348 | for (i = 0; i < pctl->ngroups; i++) { | |
1349 | struct sunxi_pinctrl_group *grp = pctl->groups + i; | |
1350 | ||
1351 | if (!strcmp(grp->name, group)) | |
1352 | return grp; | |
1353 | } | |
1354 | ||
1355 | return NULL; | |
1356 | } | |
1357 | ||
1358 | static struct sunxi_pinctrl_function * | |
1359 | sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, | |
1360 | const char *name) | |
1361 | { | |
1362 | struct sunxi_pinctrl_function *func = pctl->functions; | |
1363 | int i; | |
1364 | ||
1365 | for (i = 0; i < pctl->nfunctions; i++) { | |
1366 | if (!func[i].name) | |
1367 | break; | |
1368 | ||
1369 | if (!strcmp(func[i].name, name)) | |
1370 | return func + i; | |
1371 | } | |
1372 | ||
1373 | return NULL; | |
1374 | } | |
1375 | ||
1376 | static struct sunxi_desc_function * | |
1377 | sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, | |
1378 | const char *pin_name, | |
1379 | const char *func_name) | |
1380 | { | |
1381 | int i; | |
1382 | ||
1383 | for (i = 0; i < pctl->desc->npins; i++) { | |
1384 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
1385 | ||
1386 | if (!strcmp(pin->pin.name, pin_name)) { | |
1387 | struct sunxi_desc_function *func = pin->functions; | |
1388 | ||
1389 | while (func->name) { | |
1390 | if (!strcmp(func->name, func_name)) | |
1391 | return func; | |
1392 | ||
1393 | func++; | |
1394 | } | |
1395 | } | |
1396 | } | |
1397 | ||
1398 | return NULL; | |
1399 | } | |
1400 | ||
1401 | static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
1402 | { | |
1403 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1404 | ||
1405 | return pctl->ngroups; | |
1406 | } | |
1407 | ||
1408 | static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
1409 | unsigned group) | |
1410 | { | |
1411 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1412 | ||
1413 | return pctl->groups[group].name; | |
1414 | } | |
1415 | ||
1416 | static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
1417 | unsigned group, | |
1418 | const unsigned **pins, | |
1419 | unsigned *num_pins) | |
1420 | { | |
1421 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1422 | ||
1423 | *pins = (unsigned *)&pctl->groups[group].pin; | |
1424 | *num_pins = 1; | |
1425 | ||
1426 | return 0; | |
1427 | } | |
1428 | ||
1429 | static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
1430 | struct device_node *node, | |
1431 | struct pinctrl_map **map, | |
1432 | unsigned *num_maps) | |
1433 | { | |
1434 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1435 | unsigned long *pinconfig; | |
1436 | struct property *prop; | |
1437 | const char *function; | |
1438 | const char *group; | |
1439 | int ret, nmaps, i = 0; | |
1440 | u32 val; | |
1441 | ||
1442 | *map = NULL; | |
1443 | *num_maps = 0; | |
1444 | ||
1445 | ret = of_property_read_string(node, "allwinner,function", &function); | |
1446 | if (ret) { | |
1447 | dev_err(pctl->dev, | |
1448 | "missing allwinner,function property in node %s\n", | |
1449 | node->name); | |
1450 | return -EINVAL; | |
1451 | } | |
1452 | ||
1453 | nmaps = of_property_count_strings(node, "allwinner,pins") * 2; | |
1454 | if (nmaps < 0) { | |
1455 | dev_err(pctl->dev, | |
1456 | "missing allwinner,pins property in node %s\n", | |
1457 | node->name); | |
1458 | return -EINVAL; | |
1459 | } | |
1460 | ||
1461 | *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); | |
1462 | if (!map) | |
1463 | return -ENOMEM; | |
1464 | ||
1465 | of_property_for_each_string(node, "allwinner,pins", prop, group) { | |
1466 | struct sunxi_pinctrl_group *grp = | |
1467 | sunxi_pinctrl_find_group_by_name(pctl, group); | |
1468 | int j = 0, configlen = 0; | |
1469 | ||
1470 | if (!grp) { | |
1471 | dev_err(pctl->dev, "unknown pin %s", group); | |
1472 | continue; | |
1473 | } | |
1474 | ||
1475 | if (!sunxi_pinctrl_desc_find_function_by_name(pctl, | |
1476 | grp->name, | |
1477 | function)) { | |
1478 | dev_err(pctl->dev, "unsupported function %s on pin %s", | |
1479 | function, group); | |
1480 | continue; | |
1481 | } | |
1482 | ||
1483 | (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; | |
1484 | (*map)[i].data.mux.group = group; | |
1485 | (*map)[i].data.mux.function = function; | |
1486 | ||
1487 | i++; | |
1488 | ||
1489 | (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
1490 | (*map)[i].data.configs.group_or_pin = group; | |
1491 | ||
1492 | if (of_find_property(node, "allwinner,drive", NULL)) | |
1493 | configlen++; | |
1494 | if (of_find_property(node, "allwinner,pull", NULL)) | |
1495 | configlen++; | |
1496 | ||
1497 | pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); | |
1498 | ||
1499 | if (!of_property_read_u32(node, "allwinner,drive", &val)) { | |
1500 | u16 strength = (val + 1) * 10; | |
1501 | pinconfig[j++] = | |
1502 | pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, | |
1503 | strength); | |
1504 | } | |
1505 | ||
1506 | if (!of_property_read_u32(node, "allwinner,pull", &val)) { | |
1507 | enum pin_config_param pull = PIN_CONFIG_END; | |
1508 | if (val == 1) | |
1509 | pull = PIN_CONFIG_BIAS_PULL_UP; | |
1510 | else if (val == 2) | |
1511 | pull = PIN_CONFIG_BIAS_PULL_DOWN; | |
1512 | pinconfig[j++] = pinconf_to_config_packed(pull, 0); | |
1513 | } | |
1514 | ||
1515 | (*map)[i].data.configs.configs = pinconfig; | |
1516 | (*map)[i].data.configs.num_configs = configlen; | |
1517 | ||
1518 | i++; | |
1519 | } | |
1520 | ||
1521 | *num_maps = nmaps; | |
1522 | ||
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, | |
1527 | struct pinctrl_map *map, | |
1528 | unsigned num_maps) | |
1529 | { | |
1530 | int i; | |
1531 | ||
1532 | for (i = 0; i < num_maps; i++) { | |
1533 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) | |
1534 | kfree(map[i].data.configs.configs); | |
1535 | } | |
1536 | ||
1537 | kfree(map); | |
1538 | } | |
1539 | ||
022ab148 | 1540 | static const struct pinctrl_ops sunxi_pctrl_ops = { |
0e37f88d MR |
1541 | .dt_node_to_map = sunxi_pctrl_dt_node_to_map, |
1542 | .dt_free_map = sunxi_pctrl_dt_free_map, | |
1543 | .get_groups_count = sunxi_pctrl_get_groups_count, | |
1544 | .get_group_name = sunxi_pctrl_get_group_name, | |
1545 | .get_group_pins = sunxi_pctrl_get_group_pins, | |
1546 | }; | |
1547 | ||
1548 | static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, | |
1549 | unsigned group, | |
1550 | unsigned long *config) | |
1551 | { | |
1552 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1553 | ||
1554 | *config = pctl->groups[group].config; | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
1559 | static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, | |
1560 | unsigned group, | |
1561 | unsigned long config) | |
1562 | { | |
1563 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1564 | struct sunxi_pinctrl_group *g = &pctl->groups[group]; | |
1565 | u32 val, mask; | |
1566 | u16 strength; | |
1567 | u8 dlevel; | |
1568 | ||
1569 | switch (pinconf_to_config_param(config)) { | |
1570 | case PIN_CONFIG_DRIVE_STRENGTH: | |
1571 | strength = pinconf_to_config_argument(config); | |
1572 | if (strength > 40) | |
1573 | return -EINVAL; | |
1574 | /* | |
1575 | * We convert from mA to what the register expects: | |
1576 | * 0: 10mA | |
1577 | * 1: 20mA | |
1578 | * 2: 30mA | |
1579 | * 3: 40mA | |
1580 | */ | |
1581 | dlevel = strength / 10 - 1; | |
1582 | val = readl(pctl->membase + sunxi_dlevel_reg(g->pin)); | |
1583 | mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin); | |
1584 | writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin), | |
1585 | pctl->membase + sunxi_dlevel_reg(g->pin)); | |
1586 | break; | |
1587 | case PIN_CONFIG_BIAS_PULL_UP: | |
1588 | val = readl(pctl->membase + sunxi_pull_reg(g->pin)); | |
1589 | mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); | |
1590 | writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin), | |
1591 | pctl->membase + sunxi_pull_reg(g->pin)); | |
1592 | break; | |
1593 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1594 | val = readl(pctl->membase + sunxi_pull_reg(g->pin)); | |
1595 | mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin); | |
1596 | writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin), | |
1597 | pctl->membase + sunxi_pull_reg(g->pin)); | |
1598 | break; | |
1599 | default: | |
1600 | break; | |
1601 | } | |
1602 | ||
1603 | /* cache the config value */ | |
1604 | g->config = config; | |
1605 | ||
1606 | return 0; | |
1607 | } | |
1608 | ||
022ab148 | 1609 | static const struct pinconf_ops sunxi_pconf_ops = { |
0e37f88d MR |
1610 | .pin_config_group_get = sunxi_pconf_group_get, |
1611 | .pin_config_group_set = sunxi_pconf_group_set, | |
1612 | }; | |
1613 | ||
1614 | static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
1615 | { | |
1616 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1617 | ||
1618 | return pctl->nfunctions; | |
1619 | } | |
1620 | ||
1621 | static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1622 | unsigned function) | |
1623 | { | |
1624 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1625 | ||
1626 | return pctl->functions[function].name; | |
1627 | } | |
1628 | ||
1629 | static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1630 | unsigned function, | |
1631 | const char * const **groups, | |
1632 | unsigned * const num_groups) | |
1633 | { | |
1634 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1635 | ||
1636 | *groups = pctl->functions[function].groups; | |
1637 | *num_groups = pctl->functions[function].ngroups; | |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
1642 | static void sunxi_pmx_set(struct pinctrl_dev *pctldev, | |
1643 | unsigned pin, | |
1644 | u8 config) | |
1645 | { | |
1646 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1647 | ||
1648 | u32 val = readl(pctl->membase + sunxi_mux_reg(pin)); | |
1649 | u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); | |
1650 | writel((val & ~mask) | config << sunxi_mux_offset(pin), | |
1651 | pctl->membase + sunxi_mux_reg(pin)); | |
1652 | } | |
1653 | ||
1654 | static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, | |
1655 | unsigned function, | |
1656 | unsigned group) | |
1657 | { | |
1658 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1659 | struct sunxi_pinctrl_group *g = pctl->groups + group; | |
1660 | struct sunxi_pinctrl_function *func = pctl->functions + function; | |
1661 | struct sunxi_desc_function *desc = | |
1662 | sunxi_pinctrl_desc_find_function_by_name(pctl, | |
1663 | g->name, | |
1664 | func->name); | |
1665 | ||
1666 | if (!desc) | |
1667 | return -EINVAL; | |
1668 | ||
1669 | sunxi_pmx_set(pctldev, g->pin, desc->muxval); | |
1670 | ||
1671 | return 0; | |
1672 | } | |
1673 | ||
08e9e614 MR |
1674 | static int |
1675 | sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
1676 | struct pinctrl_gpio_range *range, | |
1677 | unsigned offset, | |
1678 | bool input) | |
1679 | { | |
1680 | struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
1681 | struct sunxi_desc_function *desc; | |
1682 | char pin_name[SUNXI_PIN_NAME_MAX_LEN]; | |
1683 | const char *func; | |
1684 | u8 bank, pin; | |
1685 | int ret; | |
1686 | ||
1687 | bank = (offset) / PINS_PER_BANK; | |
1688 | pin = (offset) % PINS_PER_BANK; | |
1689 | ||
1690 | ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin); | |
1691 | if (!ret) | |
1692 | goto error; | |
1693 | ||
1694 | if (input) | |
1695 | func = "gpio_in"; | |
1696 | else | |
1697 | func = "gpio_out"; | |
1698 | ||
1699 | desc = sunxi_pinctrl_desc_find_function_by_name(pctl, | |
1700 | pin_name, | |
1701 | func); | |
1702 | if (!desc) { | |
1703 | ret = -EINVAL; | |
1704 | goto error; | |
1705 | } | |
1706 | ||
1707 | sunxi_pmx_set(pctldev, offset, desc->muxval); | |
1708 | ||
1709 | ret = 0; | |
1710 | ||
1711 | error: | |
1712 | return ret; | |
1713 | } | |
1714 | ||
022ab148 | 1715 | static const struct pinmux_ops sunxi_pmx_ops = { |
0e37f88d MR |
1716 | .get_functions_count = sunxi_pmx_get_funcs_cnt, |
1717 | .get_function_name = sunxi_pmx_get_func_name, | |
1718 | .get_function_groups = sunxi_pmx_get_func_groups, | |
1719 | .enable = sunxi_pmx_enable, | |
08e9e614 | 1720 | .gpio_set_direction = sunxi_pmx_gpio_set_direction, |
0e37f88d MR |
1721 | }; |
1722 | ||
1723 | static struct pinctrl_desc sunxi_pctrl_desc = { | |
1724 | .confops = &sunxi_pconf_ops, | |
1725 | .pctlops = &sunxi_pctrl_ops, | |
1726 | .pmxops = &sunxi_pmx_ops, | |
1727 | }; | |
1728 | ||
08e9e614 MR |
1729 | static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) |
1730 | { | |
1731 | return pinctrl_request_gpio(chip->base + offset); | |
1732 | } | |
1733 | ||
1734 | static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1735 | { | |
1736 | pinctrl_free_gpio(chip->base + offset); | |
1737 | } | |
1738 | ||
1739 | static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, | |
1740 | unsigned offset) | |
1741 | { | |
1742 | return pinctrl_gpio_direction_input(chip->base + offset); | |
1743 | } | |
1744 | ||
1745 | static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1746 | { | |
1747 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
1748 | ||
1749 | u32 reg = sunxi_data_reg(offset); | |
1750 | u8 index = sunxi_data_offset(offset); | |
1751 | u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; | |
1752 | ||
1753 | return val; | |
1754 | } | |
1755 | ||
1756 | static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, | |
1757 | unsigned offset, int value) | |
1758 | { | |
1759 | return pinctrl_gpio_direction_output(chip->base + offset); | |
1760 | } | |
1761 | ||
1762 | static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, | |
1763 | unsigned offset, int value) | |
1764 | { | |
1765 | struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
1766 | u32 reg = sunxi_data_reg(offset); | |
1767 | u8 index = sunxi_data_offset(offset); | |
1768 | ||
1769 | writel((value & DATA_PINS_MASK) << index, pctl->membase + reg); | |
1770 | } | |
1771 | ||
a0d72094 MR |
1772 | static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, |
1773 | const struct of_phandle_args *gpiospec, | |
1774 | u32 *flags) | |
1775 | { | |
1776 | int pin, base; | |
1777 | ||
1778 | base = PINS_PER_BANK * gpiospec->args[0]; | |
1779 | pin = base + gpiospec->args[1]; | |
1780 | ||
1781 | if (pin > (gc->base + gc->ngpio)) | |
1782 | return -EINVAL; | |
1783 | ||
1784 | if (flags) | |
1785 | *flags = gpiospec->args[2]; | |
1786 | ||
1787 | return pin; | |
1788 | } | |
1789 | ||
08e9e614 MR |
1790 | static struct gpio_chip sunxi_pinctrl_gpio_chip = { |
1791 | .owner = THIS_MODULE, | |
1792 | .request = sunxi_pinctrl_gpio_request, | |
1793 | .free = sunxi_pinctrl_gpio_free, | |
1794 | .direction_input = sunxi_pinctrl_gpio_direction_input, | |
1795 | .direction_output = sunxi_pinctrl_gpio_direction_output, | |
1796 | .get = sunxi_pinctrl_gpio_get, | |
1797 | .set = sunxi_pinctrl_gpio_set, | |
a0d72094 MR |
1798 | .of_xlate = sunxi_pinctrl_gpio_of_xlate, |
1799 | .of_gpio_n_cells = 3, | |
08e9e614 MR |
1800 | .can_sleep = 0, |
1801 | }; | |
1802 | ||
0e37f88d | 1803 | static struct of_device_id sunxi_pinctrl_match[] = { |
9f5b6b30 | 1804 | { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data }, |
eaa3d848 | 1805 | { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data }, |
0e37f88d MR |
1806 | {} |
1807 | }; | |
1808 | MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match); | |
1809 | ||
1810 | static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, | |
1811 | const char *name) | |
1812 | { | |
1813 | struct sunxi_pinctrl_function *func = pctl->functions; | |
1814 | ||
1815 | while (func->name) { | |
1816 | /* function already there */ | |
1817 | if (strcmp(func->name, name) == 0) { | |
1818 | func->ngroups++; | |
1819 | return -EEXIST; | |
1820 | } | |
1821 | func++; | |
1822 | } | |
1823 | ||
1824 | func->name = name; | |
1825 | func->ngroups = 1; | |
1826 | ||
1827 | pctl->nfunctions++; | |
1828 | ||
1829 | return 0; | |
1830 | } | |
1831 | ||
1832 | static int sunxi_pinctrl_build_state(struct platform_device *pdev) | |
1833 | { | |
1834 | struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); | |
1835 | int i; | |
1836 | ||
1837 | pctl->ngroups = pctl->desc->npins; | |
1838 | ||
1839 | /* Allocate groups */ | |
1840 | pctl->groups = devm_kzalloc(&pdev->dev, | |
1841 | pctl->ngroups * sizeof(*pctl->groups), | |
1842 | GFP_KERNEL); | |
1843 | if (!pctl->groups) | |
1844 | return -ENOMEM; | |
1845 | ||
1846 | for (i = 0; i < pctl->desc->npins; i++) { | |
1847 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
1848 | struct sunxi_pinctrl_group *group = pctl->groups + i; | |
1849 | ||
1850 | group->name = pin->pin.name; | |
1851 | group->pin = pin->pin.number; | |
1852 | } | |
1853 | ||
1854 | /* | |
1855 | * We suppose that we won't have any more functions than pins, | |
1856 | * we'll reallocate that later anyway | |
1857 | */ | |
1858 | pctl->functions = devm_kzalloc(&pdev->dev, | |
1859 | pctl->desc->npins * sizeof(*pctl->functions), | |
1860 | GFP_KERNEL); | |
1861 | if (!pctl->functions) | |
1862 | return -ENOMEM; | |
1863 | ||
1864 | /* Count functions and their associated groups */ | |
1865 | for (i = 0; i < pctl->desc->npins; i++) { | |
1866 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
1867 | struct sunxi_desc_function *func = pin->functions; | |
1868 | ||
1869 | while (func->name) { | |
1870 | sunxi_pinctrl_add_function(pctl, func->name); | |
1871 | func++; | |
1872 | } | |
1873 | } | |
1874 | ||
1875 | pctl->functions = krealloc(pctl->functions, | |
1876 | pctl->nfunctions * sizeof(*pctl->functions), | |
1877 | GFP_KERNEL); | |
1878 | ||
1879 | for (i = 0; i < pctl->desc->npins; i++) { | |
1880 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
1881 | struct sunxi_desc_function *func = pin->functions; | |
1882 | ||
1883 | while (func->name) { | |
1884 | struct sunxi_pinctrl_function *func_item; | |
1885 | const char **func_grp; | |
1886 | ||
1887 | func_item = sunxi_pinctrl_find_function_by_name(pctl, | |
1888 | func->name); | |
1889 | if (!func_item) | |
1890 | return -EINVAL; | |
1891 | ||
1892 | if (!func_item->groups) { | |
1893 | func_item->groups = | |
1894 | devm_kzalloc(&pdev->dev, | |
1895 | func_item->ngroups * sizeof(*func_item->groups), | |
1896 | GFP_KERNEL); | |
1897 | if (!func_item->groups) | |
1898 | return -ENOMEM; | |
1899 | } | |
1900 | ||
1901 | func_grp = func_item->groups; | |
1902 | while (*func_grp) | |
1903 | func_grp++; | |
1904 | ||
1905 | *func_grp = pin->pin.name; | |
1906 | func++; | |
1907 | } | |
1908 | } | |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
1913 | static int sunxi_pinctrl_probe(struct platform_device *pdev) | |
1914 | { | |
1915 | struct device_node *node = pdev->dev.of_node; | |
1916 | const struct of_device_id *device; | |
1917 | struct pinctrl_pin_desc *pins; | |
1918 | struct sunxi_pinctrl *pctl; | |
08e9e614 | 1919 | int i, ret, last_pin; |
0e37f88d MR |
1920 | |
1921 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); | |
1922 | if (!pctl) | |
1923 | return -ENOMEM; | |
1924 | platform_set_drvdata(pdev, pctl); | |
1925 | ||
1926 | pctl->membase = of_iomap(node, 0); | |
1927 | if (!pctl->membase) | |
1928 | return -ENOMEM; | |
1929 | ||
1930 | device = of_match_device(sunxi_pinctrl_match, &pdev->dev); | |
1931 | if (!device) | |
1932 | return -ENODEV; | |
1933 | ||
1934 | pctl->desc = (struct sunxi_pinctrl_desc *)device->data; | |
1935 | ||
1936 | ret = sunxi_pinctrl_build_state(pdev); | |
1937 | if (ret) { | |
1938 | dev_err(&pdev->dev, "dt probe failed: %d\n", ret); | |
1939 | return ret; | |
1940 | } | |
1941 | ||
1942 | pins = devm_kzalloc(&pdev->dev, | |
1943 | pctl->desc->npins * sizeof(*pins), | |
1944 | GFP_KERNEL); | |
1945 | if (!pins) | |
1946 | return -ENOMEM; | |
1947 | ||
1948 | for (i = 0; i < pctl->desc->npins; i++) | |
1949 | pins[i] = pctl->desc->pins[i].pin; | |
1950 | ||
1951 | sunxi_pctrl_desc.name = dev_name(&pdev->dev); | |
1952 | sunxi_pctrl_desc.owner = THIS_MODULE; | |
1953 | sunxi_pctrl_desc.pins = pins; | |
1954 | sunxi_pctrl_desc.npins = pctl->desc->npins; | |
1955 | pctl->dev = &pdev->dev; | |
1956 | pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc, | |
1957 | &pdev->dev, pctl); | |
1958 | if (!pctl->pctl_dev) { | |
1959 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); | |
1960 | return -EINVAL; | |
1961 | } | |
1962 | ||
08e9e614 MR |
1963 | pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); |
1964 | if (!pctl->chip) { | |
1965 | ret = -ENOMEM; | |
1966 | goto pinctrl_error; | |
1967 | } | |
1968 | ||
1969 | last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; | |
1970 | pctl->chip = &sunxi_pinctrl_gpio_chip; | |
1971 | pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK); | |
1972 | pctl->chip->label = dev_name(&pdev->dev); | |
1973 | pctl->chip->dev = &pdev->dev; | |
1974 | pctl->chip->base = 0; | |
1975 | ||
1976 | ret = gpiochip_add(pctl->chip); | |
1977 | if (ret) | |
1978 | goto pinctrl_error; | |
1979 | ||
1980 | for (i = 0; i < pctl->desc->npins; i++) { | |
1981 | const struct sunxi_desc_pin *pin = pctl->desc->pins + i; | |
1982 | ||
1983 | ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), | |
1984 | pin->pin.number, | |
1985 | pin->pin.number, 1); | |
1986 | if (ret) | |
1987 | goto gpiochip_error; | |
1988 | } | |
1989 | ||
1990 | dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); | |
0e37f88d MR |
1991 | |
1992 | return 0; | |
08e9e614 MR |
1993 | |
1994 | gpiochip_error: | |
1995 | ret = gpiochip_remove(pctl->chip); | |
1996 | pinctrl_error: | |
1997 | pinctrl_unregister(pctl->pctl_dev); | |
1998 | return ret; | |
0e37f88d MR |
1999 | } |
2000 | ||
2001 | static struct platform_driver sunxi_pinctrl_driver = { | |
2002 | .probe = sunxi_pinctrl_probe, | |
2003 | .driver = { | |
2004 | .name = "sunxi-pinctrl", | |
2005 | .owner = THIS_MODULE, | |
2006 | .of_match_table = sunxi_pinctrl_match, | |
2007 | }, | |
2008 | }; | |
2009 | module_platform_driver(sunxi_pinctrl_driver); | |
2010 | ||
2011 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); | |
2012 | MODULE_DESCRIPTION("Allwinner A1X pinctrl driver"); | |
2013 | MODULE_LICENSE("GPL"); |