projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pinctrl: sunxi: Add Allwinner A31 pins set
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-sunxi.c
CommitLineData
0e37f88d
MR		 1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/io.h>
950707c0 14#include <linux/clk.h>
08e9e614 15#include <linux/gpio.h>
60242db1 16#include <linux/irqdomain.h>
0e37f88d
MR		 17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
60242db1 21#include <linux/of_irq.h>
0e37f88d
MR		 22#include <linux/pinctrl/consumer.h>
23#include <linux/pinctrl/machine.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/pinctrl/pinmux.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29
30#include "core.h"
31#include "pinctrl-sunxi.h"
44abb933 32#include "pinctrl-sunxi-pins.h"
eaa3d848 33
0e37f88d
MR		 34static struct sunxi_pinctrl_group *
35sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
36{
37 int i;
38
39 for (i = 0; i < pctl->ngroups; i++) {
40 struct sunxi_pinctrl_group *grp = pctl->groups + i;
41
42 if (!strcmp(grp->name, group))
43 return grp;
44 }
45
46 return NULL;
47}
48
49static struct sunxi_pinctrl_function *
50sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
51 const char *name)
52{
53 struct sunxi_pinctrl_function *func = pctl->functions;
54 int i;
55
56 for (i = 0; i < pctl->nfunctions; i++) {
57 if (!func[i].name)
58 break;
59
60 if (!strcmp(func[i].name, name))
61 return func + i;
62 }
63
64 return NULL;
65}
66
67static struct sunxi_desc_function *
68sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
69 const char *pin_name,
70 const char *func_name)
71{
72 int i;
73
74 for (i = 0; i < pctl->desc->npins; i++) {
75 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
76
77 if (!strcmp(pin->pin.name, pin_name)) {
78 struct sunxi_desc_function *func = pin->functions;
79
80 while (func->name) {
81 if (!strcmp(func->name, func_name))
82 return func;
83
84 func++;
85 }
86 }
87 }
88
89 return NULL;
90}
91
814d4f2e
MR		 92static struct sunxi_desc_function *
93sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
94 const u16 pin_num,
95 const char *func_name)
96{
97 int i;
98
99 for (i = 0; i < pctl->desc->npins; i++) {
100 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
101
102 if (pin->pin.number == pin_num) {
103 struct sunxi_desc_function *func = pin->functions;
104
105 while (func->name) {
106 if (!strcmp(func->name, func_name))
107 return func;
108
109 func++;
110 }
111 }
112 }
113
114 return NULL;
115}
116
0e37f88d
MR		 117static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
118{
119 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
120
121 return pctl->ngroups;
122}
123
124static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
125 unsigned group)
126{
127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
128
129 return pctl->groups[group].name;
130}
131
132static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
133 unsigned group,
134 const unsigned **pins,
135 unsigned *num_pins)
136{
137 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
138
139 *pins = (unsigned *)&pctl->groups[group].pin;
140 *num_pins = 1;
141
142 return 0;
143}
144
145static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
146 struct device_node *node,
147 struct pinctrl_map **map,
148 unsigned *num_maps)
149{
150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
151 unsigned long *pinconfig;
152 struct property *prop;
153 const char *function;
154 const char *group;
155 int ret, nmaps, i = 0;
156 u32 val;
157
158 *map = NULL;
159 *num_maps = 0;
160
161 ret = of_property_read_string(node, "allwinner,function", &function);
162 if (ret) {
163 dev_err(pctl->dev,
164 "missing allwinner,function property in node %s\n",
165 node->name);
166 return -EINVAL;
167 }
168
169 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
170 if (nmaps < 0) {
171 dev_err(pctl->dev,
172 "missing allwinner,pins property in node %s\n",
173 node->name);
174 return -EINVAL;
175 }
176
177 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
3efa921d 178 if (!*map)
0e37f88d
MR		 179 return -ENOMEM;
180
181 of_property_for_each_string(node, "allwinner,pins", prop, group) {
182 struct sunxi_pinctrl_group *grp =
183 sunxi_pinctrl_find_group_by_name(pctl, group);
184 int j = 0, configlen = 0;
185
186 if (!grp) {
187 dev_err(pctl->dev, "unknown pin %s", group);
188 continue;
189 }
190
191 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
192 grp->name,
193 function)) {
194 dev_err(pctl->dev, "unsupported function %s on pin %s",
195 function, group);
196 continue;
197 }
198
199 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
200 (*map)[i].data.mux.group = group;
201 (*map)[i].data.mux.function = function;
202
203 i++;
204
205 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
206 (*map)[i].data.configs.group_or_pin = group;
207
208 if (of_find_property(node, "allwinner,drive", NULL))
209 configlen++;
210 if (of_find_property(node, "allwinner,pull", NULL))
211 configlen++;
212
213 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
214
215 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
216 u16 strength = (val + 1) * 10;
217 pinconfig[j++] =
218 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
219 strength);
220 }
221
222 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
223 enum pin_config_param pull = PIN_CONFIG_END;
224 if (val == 1)
225 pull = PIN_CONFIG_BIAS_PULL_UP;
226 else if (val == 2)
227 pull = PIN_CONFIG_BIAS_PULL_DOWN;
228 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
229 }
230
231 (*map)[i].data.configs.configs = pinconfig;
232 (*map)[i].data.configs.num_configs = configlen;
233
234 i++;
235 }
236
237 *num_maps = nmaps;
238
239 return 0;
240}
241
242static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
243 struct pinctrl_map *map,
244 unsigned num_maps)
245{
246 int i;
247
248 for (i = 0; i < num_maps; i++) {
249 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
250 kfree(map[i].data.configs.configs);
251 }
252
253 kfree(map);
254}
255
022ab148 256static const struct pinctrl_ops sunxi_pctrl_ops = {
0e37f88d
MR		 257 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
258 .dt_free_map = sunxi_pctrl_dt_free_map,
259 .get_groups_count = sunxi_pctrl_get_groups_count,
260 .get_group_name = sunxi_pctrl_get_group_name,
261 .get_group_pins = sunxi_pctrl_get_group_pins,
262};
263
264static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
265 unsigned group,
266 unsigned long *config)
267{
268 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
269
270 *config = pctl->groups[group].config;
271
272 return 0;
273}
274
275static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
276 unsigned group,
277 unsigned long config)
278{
279 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
280 struct sunxi_pinctrl_group *g = &pctl->groups[group];
281 u32 val, mask;
282 u16 strength;
283 u8 dlevel;
284
285 switch (pinconf_to_config_param(config)) {
286 case PIN_CONFIG_DRIVE_STRENGTH:
287 strength = pinconf_to_config_argument(config);
288 if (strength > 40)
289 return -EINVAL;
290 /*
291 * We convert from mA to what the register expects:
292 * 0: 10mA
293 * 1: 20mA
294 * 2: 30mA
295 * 3: 40mA
296 */
297 dlevel = strength / 10 - 1;
298 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
299 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
300 writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
301 pctl->membase + sunxi_dlevel_reg(g->pin));
302 break;
303 case PIN_CONFIG_BIAS_PULL_UP:
304 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
305 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
306 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
307 pctl->membase + sunxi_pull_reg(g->pin));
308 break;
309 case PIN_CONFIG_BIAS_PULL_DOWN:
310 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
311 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
312 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
313 pctl->membase + sunxi_pull_reg(g->pin));
314 break;
315 default:
316 break;
317 }
318
319 /* cache the config value */
320 g->config = config;
321
322 return 0;
323}
324
022ab148 325static const struct pinconf_ops sunxi_pconf_ops = {
0e37f88d
MR		 326 .pin_config_group_get = sunxi_pconf_group_get,
327 .pin_config_group_set = sunxi_pconf_group_set,
328};
329
330static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
331{
332 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
333
334 return pctl->nfunctions;
335}
336
337static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
338 unsigned function)
339{
340 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
341
342 return pctl->functions[function].name;
343}
344
345static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
346 unsigned function,
347 const char * const **groups,
348 unsigned * const num_groups)
349{
350 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
351
352 *groups = pctl->functions[function].groups;
353 *num_groups = pctl->functions[function].ngroups;
354
355 return 0;
356}
357
358static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
359 unsigned pin,
360 u8 config)
361{
362 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
363
364 u32 val = readl(pctl->membase + sunxi_mux_reg(pin));
365 u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
366 writel((val & ~mask) | config << sunxi_mux_offset(pin),
367 pctl->membase + sunxi_mux_reg(pin));
368}
369
370static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
371 unsigned function,
372 unsigned group)
373{
374 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
375 struct sunxi_pinctrl_group *g = pctl->groups + group;
376 struct sunxi_pinctrl_function *func = pctl->functions + function;
377 struct sunxi_desc_function *desc =
378 sunxi_pinctrl_desc_find_function_by_name(pctl,
379 g->name,
380 func->name);
381
382 if (!desc)
383 return -EINVAL;
384
385 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
386
387 return 0;
388}
389
08e9e614
MR		 390static int
391sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
392 struct pinctrl_gpio_range *range,
393 unsigned offset,
394 bool input)
395{
396 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
397 struct sunxi_desc_function *desc;
08e9e614 398 const char *func;
08e9e614
MR		 399
400 if (input)
401 func = "gpio_in";
402 else
403 func = "gpio_out";
404
814d4f2e
MR		 405 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
406 if (!desc)
407 return -EINVAL;
08e9e614
MR		 408
409 sunxi_pmx_set(pctldev, offset, desc->muxval);
410
814d4f2e 411 return 0;
08e9e614
MR		 412}
413
022ab148 414static const struct pinmux_ops sunxi_pmx_ops = {
0e37f88d
MR		 415 .get_functions_count = sunxi_pmx_get_funcs_cnt,
416 .get_function_name = sunxi_pmx_get_func_name,
417 .get_function_groups = sunxi_pmx_get_func_groups,
418 .enable = sunxi_pmx_enable,
08e9e614 419 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
0e37f88d
MR		 420};
421
422static struct pinctrl_desc sunxi_pctrl_desc = {
423 .confops = &sunxi_pconf_ops,
424 .pctlops = &sunxi_pctrl_ops,
425 .pmxops = &sunxi_pmx_ops,
426};
427
08e9e614
MR		 428static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
429{
430 return pinctrl_request_gpio(chip->base + offset);
431}
432
433static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
434{
435 pinctrl_free_gpio(chip->base + offset);
436}
437
438static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
439 unsigned offset)
440{
441 return pinctrl_gpio_direction_input(chip->base + offset);
442}
443
444static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
445{
446 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
447
448 u32 reg = sunxi_data_reg(offset);
449 u8 index = sunxi_data_offset(offset);
450 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
451
452 return val;
453}
454
455static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
456 unsigned offset, int value)
457{
458 return pinctrl_gpio_direction_output(chip->base + offset);
459}
460
461static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
462 unsigned offset, int value)
463{
464 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
465 u32 reg = sunxi_data_reg(offset);
466 u8 index = sunxi_data_offset(offset);
467
468 writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
469}
470
a0d72094
MR		 471static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
472 const struct of_phandle_args *gpiospec,
473 u32 *flags)
474{
475 int pin, base;
476
477 base = PINS_PER_BANK * gpiospec->args[0];
478 pin = base + gpiospec->args[1];
479
480 if (pin > (gc->base + gc->ngpio))
481 return -EINVAL;
482
483 if (flags)
484 *flags = gpiospec->args[2];
485
486 return pin;
487}
488
60242db1
MR		 489static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
490{
491 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
492 struct sunxi_desc_function *desc;
493
494 if (offset > chip->ngpio)
495 return -ENXIO;
496
497 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
498 if (!desc)
499 return -EINVAL;
500
501 pctl->irq_array[desc->irqnum] = offset;
502
503 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
504 chip->label, offset + chip->base, desc->irqnum);
505
506 return irq_find_mapping(pctl->domain, desc->irqnum);
507}
508
08e9e614
MR		 509static struct gpio_chip sunxi_pinctrl_gpio_chip = {
510 .owner = THIS_MODULE,
511 .request = sunxi_pinctrl_gpio_request,
512 .free = sunxi_pinctrl_gpio_free,
513 .direction_input = sunxi_pinctrl_gpio_direction_input,
514 .direction_output = sunxi_pinctrl_gpio_direction_output,
515 .get = sunxi_pinctrl_gpio_get,
516 .set = sunxi_pinctrl_gpio_set,
a0d72094 517 .of_xlate = sunxi_pinctrl_gpio_of_xlate,
60242db1 518 .to_irq = sunxi_pinctrl_gpio_to_irq,
a0d72094 519 .of_gpio_n_cells = 3,
08e9e614
MR		 520 .can_sleep = 0,
521};
522
60242db1
MR		 523static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
524 unsigned int type)
525{
526 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
527 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
528 u8 index = sunxi_irq_cfg_offset(d->hwirq);
529 u8 mode;
530
531 switch (type) {
532 case IRQ_TYPE_EDGE_RISING:
533 mode = IRQ_EDGE_RISING;
534 break;
535 case IRQ_TYPE_EDGE_FALLING:
536 mode = IRQ_EDGE_FALLING;
537 break;
538 case IRQ_TYPE_EDGE_BOTH:
539 mode = IRQ_EDGE_BOTH;
540 break;
541 case IRQ_TYPE_LEVEL_HIGH:
542 mode = IRQ_LEVEL_HIGH;
543 break;
544 case IRQ_TYPE_LEVEL_LOW:
545 mode = IRQ_LEVEL_LOW;
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg);
552
553 return 0;
554}
555
556static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
557{
558 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
559 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
560 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
561 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
562 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
563 u32 val;
564
565 /* Mask the IRQ */
566 val = readl(pctl->membase + ctrl_reg);
567 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
568
569 /* Clear the IRQ */
570 writel(1 << status_idx, pctl->membase + status_reg);
571}
572
573static void sunxi_pinctrl_irq_mask(struct irq_data *d)
574{
575 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
576 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
577 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
578 u32 val;
579
580 /* Mask the IRQ */
581 val = readl(pctl->membase + reg);
582 writel(val & ~(1 << idx), pctl->membase + reg);
583}
584
585static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
586{
587 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
588 struct sunxi_desc_function *func;
589 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
590 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
591 u32 val;
592
593 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
594 pctl->irq_array[d->hwirq],
595 "irq");
596
597 /* Change muxing to INT mode */
598 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
599
600 /* Unmask the IRQ */
601 val = readl(pctl->membase + reg);
602 writel(val | (1 << idx), pctl->membase + reg);
603}
604
605static struct irq_chip sunxi_pinctrl_irq_chip = {
606 .irq_mask = sunxi_pinctrl_irq_mask,
607 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
608 .irq_unmask = sunxi_pinctrl_irq_unmask,
609 .irq_set_type = sunxi_pinctrl_irq_set_type,
610};
611
612static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
613{
614 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
615 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
616
617 /* Clear all interrupts */
618 writel(reg, pctl->membase + IRQ_STATUS_REG);
619
620 if (reg) {
621 int irqoffset;
622
623 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) {
624 int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
625 generic_handle_irq(pin_irq);
626 }
627 }
628}
629
0e37f88d 630static struct of_device_id sunxi_pinctrl_match[] = {
9f5b6b30 631 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
ac689366 632 { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
eaa3d848 633 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
de0c9029 634 { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
0e37f88d
MR		 635 {}
636};
637MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
638
639static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
640 const char *name)
641{
642 struct sunxi_pinctrl_function *func = pctl->functions;
643
644 while (func->name) {
645 /* function already there */
646 if (strcmp(func->name, name) == 0) {
647 func->ngroups++;
648 return -EEXIST;
649 }
650 func++;
651 }
652
653 func->name = name;
654 func->ngroups = 1;
655
656 pctl->nfunctions++;
657
658 return 0;
659}
660
661static int sunxi_pinctrl_build_state(struct platform_device *pdev)
662{
663 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
664 int i;
665
666 pctl->ngroups = pctl->desc->npins;
667
668 /* Allocate groups */
669 pctl->groups = devm_kzalloc(&pdev->dev,
670 pctl->ngroups * sizeof(*pctl->groups),
671 GFP_KERNEL);
672 if (!pctl->groups)
673 return -ENOMEM;
674
675 for (i = 0; i < pctl->desc->npins; i++) {
676 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
677 struct sunxi_pinctrl_group *group = pctl->groups + i;
678
679 group->name = pin->pin.name;
680 group->pin = pin->pin.number;
681 }
682
683 /*
684 * We suppose that we won't have any more functions than pins,
685 * we'll reallocate that later anyway
686 */
687 pctl->functions = devm_kzalloc(&pdev->dev,
688 pctl->desc->npins * sizeof(*pctl->functions),
689 GFP_KERNEL);
690 if (!pctl->functions)
691 return -ENOMEM;
692
693 /* Count functions and their associated groups */
694 for (i = 0; i < pctl->desc->npins; i++) {
695 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
696 struct sunxi_desc_function *func = pin->functions;
697
698 while (func->name) {
699 sunxi_pinctrl_add_function(pctl, func->name);
700 func++;
701 }
702 }
703
704 pctl->functions = krealloc(pctl->functions,
705 pctl->nfunctions * sizeof(*pctl->functions),
706 GFP_KERNEL);
707
708 for (i = 0; i < pctl->desc->npins; i++) {
709 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
710 struct sunxi_desc_function *func = pin->functions;
711
712 while (func->name) {
713 struct sunxi_pinctrl_function *func_item;
714 const char **func_grp;
715
716 func_item = sunxi_pinctrl_find_function_by_name(pctl,
717 func->name);
718 if (!func_item)
719 return -EINVAL;
720
721 if (!func_item->groups) {
722 func_item->groups =
723 devm_kzalloc(&pdev->dev,
724 func_item->ngroups * sizeof(*func_item->groups),
725 GFP_KERNEL);
726 if (!func_item->groups)
727 return -ENOMEM;
728 }
729
730 func_grp = func_item->groups;
731 while (*func_grp)
732 func_grp++;
733
734 *func_grp = pin->pin.name;
735 func++;
736 }
737 }
738
739 return 0;
740}
741
742static int sunxi_pinctrl_probe(struct platform_device *pdev)
743{
744 struct device_node *node = pdev->dev.of_node;
745 const struct of_device_id *device;
746 struct pinctrl_pin_desc *pins;
747 struct sunxi_pinctrl *pctl;
08e9e614 748 int i, ret, last_pin;
950707c0 749 struct clk *clk;
0e37f88d
MR		 750
751 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
752 if (!pctl)
753 return -ENOMEM;
754 platform_set_drvdata(pdev, pctl);
755
756 pctl->membase = of_iomap(node, 0);
757 if (!pctl->membase)
758 return -ENOMEM;
759
760 device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
761 if (!device)
762 return -ENODEV;
763
764 pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
765
766 ret = sunxi_pinctrl_build_state(pdev);
767 if (ret) {
768 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
769 return ret;
770 }
771
772 pins = devm_kzalloc(&pdev->dev,
773 pctl->desc->npins * sizeof(*pins),
774 GFP_KERNEL);
775 if (!pins)
776 return -ENOMEM;
777
778 for (i = 0; i < pctl->desc->npins; i++)
779 pins[i] = pctl->desc->pins[i].pin;
780
781 sunxi_pctrl_desc.name = dev_name(&pdev->dev);
782 sunxi_pctrl_desc.owner = THIS_MODULE;
783 sunxi_pctrl_desc.pins = pins;
784 sunxi_pctrl_desc.npins = pctl->desc->npins;
785 pctl->dev = &pdev->dev;
786 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
787 &pdev->dev, pctl);
788 if (!pctl->pctl_dev) {
789 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
790 return -EINVAL;
791 }
792
08e9e614
MR		 793 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
794 if (!pctl->chip) {
795 ret = -ENOMEM;
796 goto pinctrl_error;
797 }
798
799 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
800 pctl->chip = &sunxi_pinctrl_gpio_chip;
801 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
802 pctl->chip->label = dev_name(&pdev->dev);
803 pctl->chip->dev = &pdev->dev;
804 pctl->chip->base = 0;
805
806 ret = gpiochip_add(pctl->chip);
807 if (ret)
808 goto pinctrl_error;
809
810 for (i = 0; i < pctl->desc->npins; i++) {
811 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
812
813 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
814 pin->pin.number,
815 pin->pin.number, 1);
816 if (ret)
817 goto gpiochip_error;
818 }
819
950707c0 820 clk = devm_clk_get(&pdev->dev, NULL);
d72f88a4
WY		 821 if (IS_ERR(clk)) {
822 ret = PTR_ERR(clk);
950707c0 823 goto gpiochip_error;
d72f88a4 824 }
950707c0
EL		 825
826 clk_prepare_enable(clk);
827
60242db1
MR		 828 pctl->irq = irq_of_parse_and_map(node, 0);
829 if (!pctl->irq) {
830 ret = -EINVAL;
831 goto gpiochip_error;
832 }
833
834 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
835 &irq_domain_simple_ops, NULL);
836 if (!pctl->domain) {
837 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
838 ret = -ENOMEM;
839 goto gpiochip_error;
840 }
841
842 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
843 int irqno = irq_create_mapping(pctl->domain, i);
844
845 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
846 handle_simple_irq);
847 irq_set_chip_data(irqno, pctl);
848 };
849
850 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
851 irq_set_handler_data(pctl->irq, pctl);
852
08e9e614 853 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
0e37f88d
MR		 854
855 return 0;
08e9e614
MR		 856
857gpiochip_error:
97fc4637
AL		 858 if (gpiochip_remove(pctl->chip))
859 dev_err(&pdev->dev, "failed to remove gpio chip\n");
08e9e614
MR		 860pinctrl_error:
861 pinctrl_unregister(pctl->pctl_dev);
862 return ret;
0e37f88d
MR		 863}
864
865static struct platform_driver sunxi_pinctrl_driver = {
866 .probe = sunxi_pinctrl_probe,
867 .driver = {
868 .name = "sunxi-pinctrl",
869 .owner = THIS_MODULE,
870 .of_match_table = sunxi_pinctrl_match,
871 },
872};
873module_platform_driver(sunxi_pinctrl_driver);
874
875MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
876MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
877MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)