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pinctrl: rockchip: Implement .request() and .free() callbacks
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-sunxi.c
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0e37f88d
MR		 1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/io.h>
950707c0 14#include <linux/clk.h>
08e9e614 15#include <linux/gpio.h>
60242db1 16#include <linux/irqdomain.h>
0e37f88d
MR		 17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
60242db1 21#include <linux/of_irq.h>
0e37f88d
MR		 22#include <linux/pinctrl/consumer.h>
23#include <linux/pinctrl/machine.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/pinctrl/pinmux.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29
30#include "core.h"
31#include "pinctrl-sunxi.h"
44abb933 32#include "pinctrl-sunxi-pins.h"
eaa3d848 33
0e37f88d
MR		 34static struct sunxi_pinctrl_group *
35sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
36{
37 int i;
38
39 for (i = 0; i < pctl->ngroups; i++) {
40 struct sunxi_pinctrl_group *grp = pctl->groups + i;
41
42 if (!strcmp(grp->name, group))
43 return grp;
44 }
45
46 return NULL;
47}
48
49static struct sunxi_pinctrl_function *
50sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
51 const char *name)
52{
53 struct sunxi_pinctrl_function *func = pctl->functions;
54 int i;
55
56 for (i = 0; i < pctl->nfunctions; i++) {
57 if (!func[i].name)
58 break;
59
60 if (!strcmp(func[i].name, name))
61 return func + i;
62 }
63
64 return NULL;
65}
66
67static struct sunxi_desc_function *
68sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
69 const char *pin_name,
70 const char *func_name)
71{
72 int i;
73
74 for (i = 0; i < pctl->desc->npins; i++) {
75 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
76
77 if (!strcmp(pin->pin.name, pin_name)) {
78 struct sunxi_desc_function *func = pin->functions;
79
80 while (func->name) {
81 if (!strcmp(func->name, func_name))
82 return func;
83
84 func++;
85 }
86 }
87 }
88
89 return NULL;
90}
91
814d4f2e
MR		 92static struct sunxi_desc_function *
93sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
94 const u16 pin_num,
95 const char *func_name)
96{
97 int i;
98
99 for (i = 0; i < pctl->desc->npins; i++) {
100 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
101
102 if (pin->pin.number == pin_num) {
103 struct sunxi_desc_function *func = pin->functions;
104
105 while (func->name) {
106 if (!strcmp(func->name, func_name))
107 return func;
108
109 func++;
110 }
111 }
112 }
113
114 return NULL;
115}
116
0e37f88d
MR		 117static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
118{
119 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
120
121 return pctl->ngroups;
122}
123
124static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
125 unsigned group)
126{
127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
128
129 return pctl->groups[group].name;
130}
131
132static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
133 unsigned group,
134 const unsigned **pins,
135 unsigned *num_pins)
136{
137 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
138
139 *pins = (unsigned *)&pctl->groups[group].pin;
140 *num_pins = 1;
141
142 return 0;
143}
144
145static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
146 struct device_node *node,
147 struct pinctrl_map **map,
148 unsigned *num_maps)
149{
150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
151 unsigned long *pinconfig;
152 struct property *prop;
153 const char *function;
154 const char *group;
155 int ret, nmaps, i = 0;
156 u32 val;
157
158 *map = NULL;
159 *num_maps = 0;
160
161 ret = of_property_read_string(node, "allwinner,function", &function);
162 if (ret) {
163 dev_err(pctl->dev,
164 "missing allwinner,function property in node %s\n",
165 node->name);
166 return -EINVAL;
167 }
168
169 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
170 if (nmaps < 0) {
171 dev_err(pctl->dev,
172 "missing allwinner,pins property in node %s\n",
173 node->name);
174 return -EINVAL;
175 }
176
177 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
3efa921d 178 if (!*map)
0e37f88d
MR		 179 return -ENOMEM;
180
181 of_property_for_each_string(node, "allwinner,pins", prop, group) {
182 struct sunxi_pinctrl_group *grp =
183 sunxi_pinctrl_find_group_by_name(pctl, group);
184 int j = 0, configlen = 0;
185
186 if (!grp) {
187 dev_err(pctl->dev, "unknown pin %s", group);
188 continue;
189 }
190
191 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
192 grp->name,
193 function)) {
194 dev_err(pctl->dev, "unsupported function %s on pin %s",
195 function, group);
196 continue;
197 }
198
199 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
200 (*map)[i].data.mux.group = group;
201 (*map)[i].data.mux.function = function;
202
203 i++;
204
205 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
206 (*map)[i].data.configs.group_or_pin = group;
207
208 if (of_find_property(node, "allwinner,drive", NULL))
209 configlen++;
210 if (of_find_property(node, "allwinner,pull", NULL))
211 configlen++;
212
213 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
214
215 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
216 u16 strength = (val + 1) * 10;
217 pinconfig[j++] =
218 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
219 strength);
220 }
221
222 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
223 enum pin_config_param pull = PIN_CONFIG_END;
224 if (val == 1)
225 pull = PIN_CONFIG_BIAS_PULL_UP;
226 else if (val == 2)
227 pull = PIN_CONFIG_BIAS_PULL_DOWN;
228 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
229 }
230
231 (*map)[i].data.configs.configs = pinconfig;
232 (*map)[i].data.configs.num_configs = configlen;
233
234 i++;
235 }
236
237 *num_maps = nmaps;
238
239 return 0;
240}
241
242static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
243 struct pinctrl_map *map,
244 unsigned num_maps)
245{
246 int i;
247
248 for (i = 0; i < num_maps; i++) {
249 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
250 kfree(map[i].data.configs.configs);
251 }
252
253 kfree(map);
254}
255
022ab148 256static const struct pinctrl_ops sunxi_pctrl_ops = {
0e37f88d
MR		 257 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
258 .dt_free_map = sunxi_pctrl_dt_free_map,
259 .get_groups_count = sunxi_pctrl_get_groups_count,
260 .get_group_name = sunxi_pctrl_get_group_name,
261 .get_group_pins = sunxi_pctrl_get_group_pins,
262};
263
264static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
265 unsigned group,
266 unsigned long *config)
267{
268 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
269
270 *config = pctl->groups[group].config;
271
272 return 0;
273}
274
275static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
276 unsigned group,
03b054e9
SY		 277 unsigned long *configs,
278 unsigned num_configs)
0e37f88d
MR		 279{
280 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
281 struct sunxi_pinctrl_group *g = &pctl->groups[group];
282 u32 val, mask;
283 u16 strength;
284 u8 dlevel;
03b054e9 285 int i;
0e37f88d 286
03b054e9
SY		 287 for (i = 0; i < num_configs; i++) {
288 switch (pinconf_to_config_param(configs[i])) {
289 case PIN_CONFIG_DRIVE_STRENGTH:
290 strength = pinconf_to_config_argument(configs[i]);
291 if (strength > 40)
292 return -EINVAL;
293 /*
294 * We convert from mA to what the register expects:
295 * 0: 10mA
296 * 1: 20mA
297 * 2: 30mA
298 * 3: 40mA
299 */
300 dlevel = strength / 10 - 1;
301 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
302 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
303 writel((val & ~mask)
304 | dlevel << sunxi_dlevel_offset(g->pin),
305 pctl->membase + sunxi_dlevel_reg(g->pin));
306 break;
307 case PIN_CONFIG_BIAS_PULL_UP:
308 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
309 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
310 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
311 pctl->membase + sunxi_pull_reg(g->pin));
312 break;
313 case PIN_CONFIG_BIAS_PULL_DOWN:
314 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
315 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
316 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
317 pctl->membase + sunxi_pull_reg(g->pin));
318 break;
319 default:
320 break;
321 }
0e37f88d 322
03b054e9
SY		 323 /* cache the config value */
324 g->config = configs[i];
325 } /* for each config */
0e37f88d
MR		 326
327 return 0;
328}
329
022ab148 330static const struct pinconf_ops sunxi_pconf_ops = {
0e37f88d
MR		 331 .pin_config_group_get = sunxi_pconf_group_get,
332 .pin_config_group_set = sunxi_pconf_group_set,
333};
334
335static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
336{
337 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
338
339 return pctl->nfunctions;
340}
341
342static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
343 unsigned function)
344{
345 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
346
347 return pctl->functions[function].name;
348}
349
350static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
351 unsigned function,
352 const char * const **groups,
353 unsigned * const num_groups)
354{
355 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
356
357 *groups = pctl->functions[function].groups;
358 *num_groups = pctl->functions[function].ngroups;
359
360 return 0;
361}
362
363static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
364 unsigned pin,
365 u8 config)
366{
367 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
368
369 u32 val = readl(pctl->membase + sunxi_mux_reg(pin));
370 u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
371 writel((val & ~mask) | config << sunxi_mux_offset(pin),
372 pctl->membase + sunxi_mux_reg(pin));
373}
374
375static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
376 unsigned function,
377 unsigned group)
378{
379 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
380 struct sunxi_pinctrl_group *g = pctl->groups + group;
381 struct sunxi_pinctrl_function *func = pctl->functions + function;
382 struct sunxi_desc_function *desc =
383 sunxi_pinctrl_desc_find_function_by_name(pctl,
384 g->name,
385 func->name);
386
387 if (!desc)
388 return -EINVAL;
389
390 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
391
392 return 0;
393}
394
08e9e614
MR		 395static int
396sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
397 struct pinctrl_gpio_range *range,
398 unsigned offset,
399 bool input)
400{
401 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
402 struct sunxi_desc_function *desc;
08e9e614 403 const char *func;
08e9e614
MR		 404
405 if (input)
406 func = "gpio_in";
407 else
408 func = "gpio_out";
409
814d4f2e
MR		 410 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
411 if (!desc)
412 return -EINVAL;
08e9e614
MR		 413
414 sunxi_pmx_set(pctldev, offset, desc->muxval);
415
814d4f2e 416 return 0;
08e9e614
MR		 417}
418
022ab148 419static const struct pinmux_ops sunxi_pmx_ops = {
0e37f88d
MR		 420 .get_functions_count = sunxi_pmx_get_funcs_cnt,
421 .get_function_name = sunxi_pmx_get_func_name,
422 .get_function_groups = sunxi_pmx_get_func_groups,
423 .enable = sunxi_pmx_enable,
08e9e614 424 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
0e37f88d
MR		 425};
426
427static struct pinctrl_desc sunxi_pctrl_desc = {
428 .confops = &sunxi_pconf_ops,
429 .pctlops = &sunxi_pctrl_ops,
430 .pmxops = &sunxi_pmx_ops,
431};
432
08e9e614
MR		 433static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
434{
435 return pinctrl_request_gpio(chip->base + offset);
436}
437
438static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
439{
440 pinctrl_free_gpio(chip->base + offset);
441}
442
443static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
444 unsigned offset)
445{
446 return pinctrl_gpio_direction_input(chip->base + offset);
447}
448
449static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
450{
451 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
452
453 u32 reg = sunxi_data_reg(offset);
454 u8 index = sunxi_data_offset(offset);
455 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
456
457 return val;
458}
459
460static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
461 unsigned offset, int value)
462{
463 return pinctrl_gpio_direction_output(chip->base + offset);
464}
465
466static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
467 unsigned offset, int value)
468{
469 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
470 u32 reg = sunxi_data_reg(offset);
471 u8 index = sunxi_data_offset(offset);
472
473 writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
474}
475
a0d72094
MR		 476static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
477 const struct of_phandle_args *gpiospec,
478 u32 *flags)
479{
480 int pin, base;
481
482 base = PINS_PER_BANK * gpiospec->args[0];
483 pin = base + gpiospec->args[1];
484
485 if (pin > (gc->base + gc->ngpio))
486 return -EINVAL;
487
488 if (flags)
489 *flags = gpiospec->args[2];
490
491 return pin;
492}
493
60242db1
MR		 494static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
495{
496 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
497 struct sunxi_desc_function *desc;
498
499 if (offset > chip->ngpio)
500 return -ENXIO;
501
502 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
503 if (!desc)
504 return -EINVAL;
505
506 pctl->irq_array[desc->irqnum] = offset;
507
508 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
509 chip->label, offset + chip->base, desc->irqnum);
510
511 return irq_find_mapping(pctl->domain, desc->irqnum);
512}
513
08e9e614
MR		 514static struct gpio_chip sunxi_pinctrl_gpio_chip = {
515 .owner = THIS_MODULE,
516 .request = sunxi_pinctrl_gpio_request,
517 .free = sunxi_pinctrl_gpio_free,
518 .direction_input = sunxi_pinctrl_gpio_direction_input,
519 .direction_output = sunxi_pinctrl_gpio_direction_output,
520 .get = sunxi_pinctrl_gpio_get,
521 .set = sunxi_pinctrl_gpio_set,
a0d72094 522 .of_xlate = sunxi_pinctrl_gpio_of_xlate,
60242db1 523 .to_irq = sunxi_pinctrl_gpio_to_irq,
a0d72094 524 .of_gpio_n_cells = 3,
08e9e614
MR		 525 .can_sleep = 0,
526};
527
60242db1
MR		 528static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
529 unsigned int type)
530{
531 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
532 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
533 u8 index = sunxi_irq_cfg_offset(d->hwirq);
534 u8 mode;
535
536 switch (type) {
537 case IRQ_TYPE_EDGE_RISING:
538 mode = IRQ_EDGE_RISING;
539 break;
540 case IRQ_TYPE_EDGE_FALLING:
541 mode = IRQ_EDGE_FALLING;
542 break;
543 case IRQ_TYPE_EDGE_BOTH:
544 mode = IRQ_EDGE_BOTH;
545 break;
546 case IRQ_TYPE_LEVEL_HIGH:
547 mode = IRQ_LEVEL_HIGH;
548 break;
549 case IRQ_TYPE_LEVEL_LOW:
550 mode = IRQ_LEVEL_LOW;
551 break;
552 default:
553 return -EINVAL;
554 }
555
556 writel((mode & IRQ_CFG_IRQ_MASK) << index, pctl->membase + reg);
557
558 return 0;
559}
560
561static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
562{
563 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
564 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
565 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
566 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
567 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
568 u32 val;
569
570 /* Mask the IRQ */
571 val = readl(pctl->membase + ctrl_reg);
572 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
573
574 /* Clear the IRQ */
575 writel(1 << status_idx, pctl->membase + status_reg);
576}
577
578static void sunxi_pinctrl_irq_mask(struct irq_data *d)
579{
580 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
581 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
582 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
583 u32 val;
584
585 /* Mask the IRQ */
586 val = readl(pctl->membase + reg);
587 writel(val & ~(1 << idx), pctl->membase + reg);
588}
589
590static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
591{
592 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
593 struct sunxi_desc_function *func;
594 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
595 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
596 u32 val;
597
598 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
599 pctl->irq_array[d->hwirq],
600 "irq");
601
602 /* Change muxing to INT mode */
603 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
604
605 /* Unmask the IRQ */
606 val = readl(pctl->membase + reg);
607 writel(val | (1 << idx), pctl->membase + reg);
608}
609
610static struct irq_chip sunxi_pinctrl_irq_chip = {
611 .irq_mask = sunxi_pinctrl_irq_mask,
612 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
613 .irq_unmask = sunxi_pinctrl_irq_unmask,
614 .irq_set_type = sunxi_pinctrl_irq_set_type,
615};
616
617static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
618{
619 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
620 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
621
622 /* Clear all interrupts */
623 writel(reg, pctl->membase + IRQ_STATUS_REG);
624
625 if (reg) {
626 int irqoffset;
627
628 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) {
629 int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
630 generic_handle_irq(pin_irq);
631 }
632 }
633}
634
0e37f88d 635static struct of_device_id sunxi_pinctrl_match[] = {
9f5b6b30 636 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
ac689366 637 { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
eaa3d848 638 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
de0c9029 639 { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
23ac6df4 640 { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
0e37f88d
MR		 641 {}
642};
643MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
644
645static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
646 const char *name)
647{
648 struct sunxi_pinctrl_function *func = pctl->functions;
649
650 while (func->name) {
651 /* function already there */
652 if (strcmp(func->name, name) == 0) {
653 func->ngroups++;
654 return -EEXIST;
655 }
656 func++;
657 }
658
659 func->name = name;
660 func->ngroups = 1;
661
662 pctl->nfunctions++;
663
664 return 0;
665}
666
667static int sunxi_pinctrl_build_state(struct platform_device *pdev)
668{
669 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
670 int i;
671
672 pctl->ngroups = pctl->desc->npins;
673
674 /* Allocate groups */
675 pctl->groups = devm_kzalloc(&pdev->dev,
676 pctl->ngroups * sizeof(*pctl->groups),
677 GFP_KERNEL);
678 if (!pctl->groups)
679 return -ENOMEM;
680
681 for (i = 0; i < pctl->desc->npins; i++) {
682 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
683 struct sunxi_pinctrl_group *group = pctl->groups + i;
684
685 group->name = pin->pin.name;
686 group->pin = pin->pin.number;
687 }
688
689 /*
690 * We suppose that we won't have any more functions than pins,
691 * we'll reallocate that later anyway
692 */
693 pctl->functions = devm_kzalloc(&pdev->dev,
694 pctl->desc->npins * sizeof(*pctl->functions),
695 GFP_KERNEL);
696 if (!pctl->functions)
697 return -ENOMEM;
698
699 /* Count functions and their associated groups */
700 for (i = 0; i < pctl->desc->npins; i++) {
701 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
702 struct sunxi_desc_function *func = pin->functions;
703
704 while (func->name) {
705 sunxi_pinctrl_add_function(pctl, func->name);
706 func++;
707 }
708 }
709
710 pctl->functions = krealloc(pctl->functions,
711 pctl->nfunctions * sizeof(*pctl->functions),
712 GFP_KERNEL);
713
714 for (i = 0; i < pctl->desc->npins; i++) {
715 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
716 struct sunxi_desc_function *func = pin->functions;
717
718 while (func->name) {
719 struct sunxi_pinctrl_function *func_item;
720 const char **func_grp;
721
722 func_item = sunxi_pinctrl_find_function_by_name(pctl,
723 func->name);
724 if (!func_item)
725 return -EINVAL;
726
727 if (!func_item->groups) {
728 func_item->groups =
729 devm_kzalloc(&pdev->dev,
730 func_item->ngroups * sizeof(*func_item->groups),
731 GFP_KERNEL);
732 if (!func_item->groups)
733 return -ENOMEM;
734 }
735
736 func_grp = func_item->groups;
737 while (*func_grp)
738 func_grp++;
739
740 *func_grp = pin->pin.name;
741 func++;
742 }
743 }
744
745 return 0;
746}
747
748static int sunxi_pinctrl_probe(struct platform_device *pdev)
749{
750 struct device_node *node = pdev->dev.of_node;
751 const struct of_device_id *device;
752 struct pinctrl_pin_desc *pins;
753 struct sunxi_pinctrl *pctl;
08e9e614 754 int i, ret, last_pin;
950707c0 755 struct clk *clk;
0e37f88d
MR		 756
757 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
758 if (!pctl)
759 return -ENOMEM;
760 platform_set_drvdata(pdev, pctl);
761
762 pctl->membase = of_iomap(node, 0);
763 if (!pctl->membase)
764 return -ENOMEM;
765
766 device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
767 if (!device)
768 return -ENODEV;
769
770 pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
771
772 ret = sunxi_pinctrl_build_state(pdev);
773 if (ret) {
774 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
775 return ret;
776 }
777
778 pins = devm_kzalloc(&pdev->dev,
779 pctl->desc->npins * sizeof(*pins),
780 GFP_KERNEL);
781 if (!pins)
782 return -ENOMEM;
783
784 for (i = 0; i < pctl->desc->npins; i++)
785 pins[i] = pctl->desc->pins[i].pin;
786
787 sunxi_pctrl_desc.name = dev_name(&pdev->dev);
788 sunxi_pctrl_desc.owner = THIS_MODULE;
789 sunxi_pctrl_desc.pins = pins;
790 sunxi_pctrl_desc.npins = pctl->desc->npins;
791 pctl->dev = &pdev->dev;
792 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
793 &pdev->dev, pctl);
794 if (!pctl->pctl_dev) {
795 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
796 return -EINVAL;
797 }
798
08e9e614
MR		 799 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
800 if (!pctl->chip) {
801 ret = -ENOMEM;
802 goto pinctrl_error;
803 }
804
805 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
806 pctl->chip = &sunxi_pinctrl_gpio_chip;
807 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
808 pctl->chip->label = dev_name(&pdev->dev);
809 pctl->chip->dev = &pdev->dev;
810 pctl->chip->base = 0;
811
812 ret = gpiochip_add(pctl->chip);
813 if (ret)
814 goto pinctrl_error;
815
816 for (i = 0; i < pctl->desc->npins; i++) {
817 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
818
819 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
820 pin->pin.number,
821 pin->pin.number, 1);
822 if (ret)
823 goto gpiochip_error;
824 }
825
950707c0 826 clk = devm_clk_get(&pdev->dev, NULL);
d72f88a4
WY		 827 if (IS_ERR(clk)) {
828 ret = PTR_ERR(clk);
950707c0 829 goto gpiochip_error;
d72f88a4 830 }
950707c0
EL		 831
832 clk_prepare_enable(clk);
833
60242db1
MR		 834 pctl->irq = irq_of_parse_and_map(node, 0);
835 if (!pctl->irq) {
836 ret = -EINVAL;
837 goto gpiochip_error;
838 }
839
840 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
841 &irq_domain_simple_ops, NULL);
842 if (!pctl->domain) {
843 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
844 ret = -ENOMEM;
845 goto gpiochip_error;
846 }
847
848 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
849 int irqno = irq_create_mapping(pctl->domain, i);
850
851 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
852 handle_simple_irq);
853 irq_set_chip_data(irqno, pctl);
854 };
855
856 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
857 irq_set_handler_data(pctl->irq, pctl);
858
08e9e614 859 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
0e37f88d
MR		 860
861 return 0;
08e9e614
MR		 862
863gpiochip_error:
97fc4637
AL		 864 if (gpiochip_remove(pctl->chip))
865 dev_err(&pdev->dev, "failed to remove gpio chip\n");
08e9e614
MR		 866pinctrl_error:
867 pinctrl_unregister(pctl->pctl_dev);
868 return ret;
0e37f88d
MR		 869}
870
871static struct platform_driver sunxi_pinctrl_driver = {
872 .probe = sunxi_pinctrl_probe,
873 .driver = {
874 .name = "sunxi-pinctrl",
875 .owner = THIS_MODULE,
876 .of_match_table = sunxi_pinctrl_match,
877 },
878};
879module_platform_driver(sunxi_pinctrl_driver);
880
881MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
882MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
883MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)