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pinctrl: Kconfig: Fix STMFX GPIO expander Pinctrl/GPIO driver dependencies
[linux-2.6-block.git] / drivers / pinctrl / pinctrl-stmfx.c
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AD		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
4 *
5 * Copyright (C) 2019 STMicroelectronics
6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
7 */
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/mfd/stmfx.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/pinctrl/pinconf.h>
14#include <linux/pinctrl/pinmux.h>
15
16#include "core.h"
17#include "pinctrl-utils.h"
18
19/* GPIOs expander */
20/* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
21#define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */
22/* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
23#define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */
24/* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
25#define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */
26/* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
27#define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */
28/* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
29#define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */
30/* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
31#define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */
32/* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */
33#define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */
34/* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */
35#define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */
36/* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */
37#define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */
38/* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/
39#define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */
40/* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */
41#define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */
42
43#define NR_GPIO_REGS 3
44#define NR_GPIOS_PER_REG 8
45#define get_reg(offset) ((offset) / NR_GPIOS_PER_REG)
46#define get_shift(offset) ((offset) % NR_GPIOS_PER_REG)
47#define get_mask(offset) (BIT(get_shift(offset)))
48
49/*
50 * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used.
51 * Pins availability is managed thanks to gpio-ranges property.
52 */
53static const struct pinctrl_pin_desc stmfx_pins[] = {
54 PINCTRL_PIN(0, "gpio0"),
55 PINCTRL_PIN(1, "gpio1"),
56 PINCTRL_PIN(2, "gpio2"),
57 PINCTRL_PIN(3, "gpio3"),
58 PINCTRL_PIN(4, "gpio4"),
59 PINCTRL_PIN(5, "gpio5"),
60 PINCTRL_PIN(6, "gpio6"),
61 PINCTRL_PIN(7, "gpio7"),
62 PINCTRL_PIN(8, "gpio8"),
63 PINCTRL_PIN(9, "gpio9"),
64 PINCTRL_PIN(10, "gpio10"),
65 PINCTRL_PIN(11, "gpio11"),
66 PINCTRL_PIN(12, "gpio12"),
67 PINCTRL_PIN(13, "gpio13"),
68 PINCTRL_PIN(14, "gpio14"),
69 PINCTRL_PIN(15, "gpio15"),
70 PINCTRL_PIN(16, "agpio0"),
71 PINCTRL_PIN(17, "agpio1"),
72 PINCTRL_PIN(18, "agpio2"),
73 PINCTRL_PIN(19, "agpio3"),
74 PINCTRL_PIN(20, "agpio4"),
75 PINCTRL_PIN(21, "agpio5"),
76 PINCTRL_PIN(22, "agpio6"),
77 PINCTRL_PIN(23, "agpio7"),
78};
79
80struct stmfx_pinctrl {
81 struct device *dev;
82 struct stmfx *stmfx;
83 struct pinctrl_dev *pctl_dev;
84 struct pinctrl_desc pctl_desc;
85 struct gpio_chip gpio_chip;
86 struct irq_chip irq_chip;
87 struct mutex lock; /* IRQ bus lock */
88 unsigned long gpio_valid_mask;
89 /* Cache of IRQ_GPI_* registers for bus_lock */
90 u8 irq_gpi_src[NR_GPIO_REGS];
91 u8 irq_gpi_type[NR_GPIO_REGS];
92 u8 irq_gpi_evt[NR_GPIO_REGS];
93 u8 irq_toggle_edge[NR_GPIO_REGS];
94#ifdef CONFIG_PM
95 /* Backup of GPIO_* registers for suspend/resume */
96 u8 bkp_gpio_state[NR_GPIO_REGS];
97 u8 bkp_gpio_dir[NR_GPIO_REGS];
98 u8 bkp_gpio_type[NR_GPIO_REGS];
99 u8 bkp_gpio_pupd[NR_GPIO_REGS];
100#endif
101};
102
103static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
104{
105 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
106 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
107 u32 mask = get_mask(offset);
108 u32 value;
109 int ret;
110
111 ret = regmap_read(pctl->stmfx->map, reg, &value);
112
113 return ret ? ret : !!(value & mask);
114}
115
116static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
117{
118 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
119 u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
120 u32 mask = get_mask(offset);
121
122 regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
123 mask, mask);
124}
125
126static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
127{
128 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
129 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
130 u32 mask = get_mask(offset);
131 u32 val;
132 int ret;
133
134 ret = regmap_read(pctl->stmfx->map, reg, &val);
135 /*
136 * On stmfx, gpio pins direction is (0)input, (1)output.
137 * .get_direction returns 0=out, 1=in
138 */
139
140 return ret ? ret : !(val & mask);
141}
142
143static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
144{
145 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
146 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
147 u32 mask = get_mask(offset);
148
149 return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
150}
151
152static int stmfx_gpio_direction_output(struct gpio_chip *gc,
153 unsigned int offset, int value)
154{
155 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
156 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
157 u32 mask = get_mask(offset);
158
159 stmfx_gpio_set(gc, offset, value);
160
161 return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
162}
163
164static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl,
165 unsigned int offset)
166{
167 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
168 u32 pupd, mask = get_mask(offset);
169 int ret;
170
171 ret = regmap_read(pctl->stmfx->map, reg, &pupd);
172 if (ret)
173 return ret;
174
175 return !!(pupd & mask);
176}
177
178static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl,
179 unsigned int offset, u32 pupd)
180{
181 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
182 u32 mask = get_mask(offset);
183
184 return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0);
185}
186
187static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl,
188 unsigned int offset)
189{
190 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
191 u32 type, mask = get_mask(offset);
192 int ret;
193
194 ret = regmap_read(pctl->stmfx->map, reg, &type);
195 if (ret)
196 return ret;
197
198 return !!(type & mask);
199}
200
201static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl,
202 unsigned int offset, u32 type)
203{
204 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
205 u32 mask = get_mask(offset);
206
207 return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0);
208}
209
210static int stmfx_pinconf_get(struct pinctrl_dev *pctldev,
211 unsigned int pin, unsigned long *config)
212{
213 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
214 u32 param = pinconf_to_config_param(*config);
215 struct pinctrl_gpio_range *range;
216 u32 dir, type, pupd;
217 u32 arg = 0;
218 int ret;
219
220 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
221 if (!range)
222 return -EINVAL;
223
224 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
225 if (dir < 0)
226 return dir;
227 type = stmfx_pinconf_get_type(pctl, pin);
228 if (type < 0)
229 return type;
230 pupd = stmfx_pinconf_get_pupd(pctl, pin);
231 if (pupd < 0)
232 return pupd;
233
234 switch (param) {
235 case PIN_CONFIG_BIAS_DISABLE:
236 if ((!dir && (!type || !pupd)) || (dir && !type))
237 arg = 1;
238 break;
239 case PIN_CONFIG_BIAS_PULL_DOWN:
240 if (dir && type && !pupd)
241 arg = 1;
242 break;
243 case PIN_CONFIG_BIAS_PULL_UP:
244 if (type && pupd)
245 arg = 1;
246 break;
247 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
248 if ((!dir && type) || (dir && !type))
249 arg = 1;
250 break;
251 case PIN_CONFIG_DRIVE_PUSH_PULL:
252 if ((!dir && !type) || (dir && type))
253 arg = 1;
254 break;
255 case PIN_CONFIG_OUTPUT:
256 if (dir)
257 return -EINVAL;
258
259 ret = stmfx_gpio_get(&pctl->gpio_chip, pin);
260 if (ret < 0)
261 return ret;
262
263 arg = ret;
264 break;
265 default:
266 return -ENOTSUPP;
267 }
268
269 *config = pinconf_to_config_packed(param, arg);
270
271 return 0;
272}
273
274static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
275 unsigned long *configs, unsigned int num_configs)
276{
277 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
278 struct pinctrl_gpio_range *range;
279 enum pin_config_param param;
280 u32 arg;
281 int dir, i, ret;
282
283 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
284 if (!range) {
285 dev_err(pctldev->dev, "pin %d is not available\n", pin);
286 return -EINVAL;
287 }
288
289 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
290 if (dir < 0)
291 return dir;
292
293 for (i = 0; i < num_configs; i++) {
294 param = pinconf_to_config_param(configs[i]);
295 arg = pinconf_to_config_argument(configs[i]);
296
297 switch (param) {
298 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
299 case PIN_CONFIG_BIAS_DISABLE:
300 case PIN_CONFIG_BIAS_PULL_DOWN:
301 ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
302 if (ret)
303 return ret;
304 break;
305 case PIN_CONFIG_BIAS_PULL_UP:
306 ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
307 if (ret)
308 return ret;
309 break;
310 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
311 if (!dir)
312 ret = stmfx_pinconf_set_type(pctl, pin, 1);
313 else
314 ret = stmfx_pinconf_set_type(pctl, pin, 0);
315 if (ret)
316 return ret;
317 break;
318 case PIN_CONFIG_DRIVE_PUSH_PULL:
319 if (!dir)
320 ret = stmfx_pinconf_set_type(pctl, pin, 0);
321 else
322 ret = stmfx_pinconf_set_type(pctl, pin, 1);
323 if (ret)
324 return ret;
325 break;
326 case PIN_CONFIG_OUTPUT:
327 ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
328 pin, arg);
329 if (ret)
330 return ret;
331 break;
332 default:
333 return -ENOTSUPP;
334 }
335 }
336
337 return 0;
338}
339
340static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
341 struct seq_file *s, unsigned int offset)
342{
343 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
344 struct pinctrl_gpio_range *range;
345 int dir, type, pupd, val;
346
347 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset);
348 if (!range)
349 return;
350
351 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset);
352 if (dir < 0)
353 return;
354 type = stmfx_pinconf_get_type(pctl, offset);
355 if (type < 0)
356 return;
357 pupd = stmfx_pinconf_get_pupd(pctl, offset);
358 if (pupd < 0)
359 return;
360 val = stmfx_gpio_get(&pctl->gpio_chip, offset);
361 if (val < 0)
362 return;
363
364 if (!dir) {
365 seq_printf(s, "output %s ", val ? "high" : "low");
366 if (type)
367 seq_printf(s, "open drain %s internal pull-up ",
368 pupd ? "with" : "without");
369 else
370 seq_puts(s, "push pull no pull ");
371 } else {
372 seq_printf(s, "input %s ", val ? "high" : "low");
373 if (type)
374 seq_printf(s, "with internal pull-%s ",
375 pupd ? "up" : "down");
376 else
377 seq_printf(s, "%s ", pupd ? "floating" : "analog");
378 }
379}
380
381static const struct pinconf_ops stmfx_pinconf_ops = {
382 .pin_config_get = stmfx_pinconf_get,
383 .pin_config_set = stmfx_pinconf_set,
384 .pin_config_dbg_show = stmfx_pinconf_dbg_show,
385};
386
387static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
388{
389 return 0;
390}
391
392static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
393 unsigned int selector)
394{
395 return NULL;
396}
397
398static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
399 unsigned int selector,
400 const unsigned int **pins,
401 unsigned int *num_pins)
402{
403 return -ENOTSUPP;
404}
405
406static const struct pinctrl_ops stmfx_pinctrl_ops = {
407 .get_groups_count = stmfx_pinctrl_get_groups_count,
408 .get_group_name = stmfx_pinctrl_get_group_name,
409 .get_group_pins = stmfx_pinctrl_get_group_pins,
410 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
411 .dt_free_map = pinctrl_utils_free_map,
412};
413
414static void stmfx_pinctrl_irq_mask(struct irq_data *data)
415{
416 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
417 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
418 u32 reg = get_reg(data->hwirq);
419 u32 mask = get_mask(data->hwirq);
420
421 pctl->irq_gpi_src[reg] &= ~mask;
422}
423
424static void stmfx_pinctrl_irq_unmask(struct irq_data *data)
425{
426 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
427 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
428 u32 reg = get_reg(data->hwirq);
429 u32 mask = get_mask(data->hwirq);
430
431 pctl->irq_gpi_src[reg] |= mask;
432}
433
434static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type)
435{
436 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
437 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
438 u32 reg = get_reg(data->hwirq);
439 u32 mask = get_mask(data->hwirq);
440
441 if (type & IRQ_TYPE_NONE)
442 return -EINVAL;
443
444 if (type & IRQ_TYPE_EDGE_BOTH) {
445 pctl->irq_gpi_evt[reg] |= mask;
446 irq_set_handler_locked(data, handle_edge_irq);
447 } else {
448 pctl->irq_gpi_evt[reg] &= ~mask;
449 irq_set_handler_locked(data, handle_level_irq);
450 }
451
452 if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH))
453 pctl->irq_gpi_type[reg] |= mask;
454 else
455 pctl->irq_gpi_type[reg] &= ~mask;
456
457 /*
458 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current
459 * GPIO value to set the right edge trigger. But in atomic context
460 * here we can't access registers over I2C. That's why (type &
461 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock.
462 */
463
464 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
465 pctl->irq_toggle_edge[reg] |= mask;
466 else
467 pctl->irq_toggle_edge[reg] &= mask;
468
469 return 0;
470}
471
472static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data)
473{
474 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
475 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
476
477 mutex_lock(&pctl->lock);
478}
479
480static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data)
481{
482 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
483 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
484 u32 reg = get_reg(data->hwirq);
485 u32 mask = get_mask(data->hwirq);
486
487 /*
488 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value
489 * (this couldn't be done in .irq_set_type because of atomic context)
490 * to set the right irq trigger type.
491 */
492 if (pctl->irq_toggle_edge[reg] & mask) {
493 if (stmfx_gpio_get(gpio_chip, data->hwirq))
494 pctl->irq_gpi_type[reg] &= ~mask;
495 else
496 pctl->irq_gpi_type[reg] |= mask;
497 }
498
499 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
500 pctl->irq_gpi_evt, NR_GPIO_REGS);
501 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
502 pctl->irq_gpi_type, NR_GPIO_REGS);
503 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
504 pctl->irq_gpi_src, NR_GPIO_REGS);
505
506 mutex_unlock(&pctl->lock);
507}
508
509static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
510 unsigned int offset)
511{
512 u32 reg = get_reg(offset);
513 u32 mask = get_mask(offset);
514 int val;
515
516 if (!(pctl->irq_toggle_edge[reg] & mask))
517 return;
518
519 val = stmfx_gpio_get(&pctl->gpio_chip, offset);
520 if (val < 0)
521 return;
522
523 if (val) {
524 pctl->irq_gpi_type[reg] &= mask;
525 regmap_write_bits(pctl->stmfx->map,
526 STMFX_REG_IRQ_GPI_TYPE + reg,
527 mask, 0);
528
529 } else {
530 pctl->irq_gpi_type[reg] |= mask;
531 regmap_write_bits(pctl->stmfx->map,
532 STMFX_REG_IRQ_GPI_TYPE + reg,
533 mask, mask);
534 }
535}
536
537static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
538{
539 struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id;
540 struct gpio_chip *gc = &pctl->gpio_chip;
541 u8 pending[NR_GPIO_REGS];
542 u8 src[NR_GPIO_REGS] = {0, 0, 0};
543 unsigned long n, status;
544 int ret;
545
546 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
547 &pending, NR_GPIO_REGS);
548 if (ret)
549 return IRQ_NONE;
550
551 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
552 src, NR_GPIO_REGS);
553
554 status = *(unsigned long *)pending;
555 for_each_set_bit(n, &status, gc->ngpio) {
556 handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
557 stmfx_pinctrl_irq_toggle_trigger(pctl, n);
558 }
559
560 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
561 pctl->irq_gpi_src, NR_GPIO_REGS);
562
563 return IRQ_HANDLED;
564}
565
566static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
567{
568 struct pinctrl_gpio_range *gpio_range;
569 struct pinctrl_dev *pctl_dev = pctl->pctl_dev;
570 u32 func = STMFX_FUNC_GPIO;
571
572 pctl->gpio_valid_mask = GENMASK(15, 0);
573
574 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16);
575 if (gpio_range) {
576 func |= STMFX_FUNC_ALTGPIO_LOW;
577 pctl->gpio_valid_mask |= GENMASK(19, 16);
578 }
579
580 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20);
581 if (gpio_range) {
582 func |= STMFX_FUNC_ALTGPIO_HIGH;
583 pctl->gpio_valid_mask |= GENMASK(23, 20);
584 }
585
586 return stmfx_function_enable(pctl->stmfx, func);
587}
588
589static int stmfx_pinctrl_probe(struct platform_device *pdev)
590{
591 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
592 struct device_node *np = pdev->dev.of_node;
593 struct stmfx_pinctrl *pctl;
594 u32 n;
595 int irq, ret;
596
597 pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
598 if (!pctl)
599 return -ENOMEM;
600
601 platform_set_drvdata(pdev, pctl);
602
603 pctl->dev = &pdev->dev;
604 pctl->stmfx = stmfx;
605
606 if (!of_find_property(np, "gpio-ranges", NULL)) {
607 dev_err(pctl->dev, "missing required gpio-ranges property\n");
608 return -EINVAL;
609 }
610
611 irq = platform_get_irq(pdev, 0);
612 if (irq <= 0) {
613 dev_err(pctl->dev, "failed to get irq\n");
614 return -ENXIO;
615 }
616
617 mutex_init(&pctl->lock);
618
619 /* Register pin controller */
620 pctl->pctl_desc.name = "stmfx-pinctrl";
621 pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops;
622 pctl->pctl_desc.confops = &stmfx_pinconf_ops;
623 pctl->pctl_desc.pins = stmfx_pins;
624 pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
625 pctl->pctl_desc.owner = THIS_MODULE;
626
627 ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
628 pctl, &pctl->pctl_dev);
629 if (ret) {
630 dev_err(pctl->dev, "pinctrl registration failed\n");
631 return ret;
632 }
633
634 ret = pinctrl_enable(pctl->pctl_dev);
635 if (ret) {
636 dev_err(pctl->dev, "pinctrl enable failed\n");
637 return ret;
638 }
639
640 /* Register gpio controller */
641 pctl->gpio_chip.label = "stmfx-gpio";
642 pctl->gpio_chip.parent = pctl->dev;
643 pctl->gpio_chip.get_direction = stmfx_gpio_get_direction;
644 pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
645 pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
646 pctl->gpio_chip.get = stmfx_gpio_get;
647 pctl->gpio_chip.set = stmfx_gpio_set;
648 pctl->gpio_chip.set_config = gpiochip_generic_config;
649 pctl->gpio_chip.base = -1;
650 pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
651 pctl->gpio_chip.can_sleep = true;
652 pctl->gpio_chip.of_node = np;
653 pctl->gpio_chip.need_valid_mask = true;
654
655 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
656 if (ret) {
657 dev_err(pctl->dev, "gpio_chip registration failed\n");
658 return ret;
659 }
660
661 ret = stmfx_pinctrl_gpio_function_enable(pctl);
662 if (ret)
663 return ret;
664
665 pctl->irq_chip.name = dev_name(pctl->dev);
666 pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask;
667 pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask;
668 pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type;
669 pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock;
670 pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock;
671 for_each_clear_bit(n, &pctl->gpio_valid_mask, pctl->gpio_chip.ngpio)
672 clear_bit(n, pctl->gpio_chip.valid_mask);
673
674 ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip,
675 0, handle_bad_irq, IRQ_TYPE_NONE);
676 if (ret) {
677 dev_err(pctl->dev, "cannot add irqchip to gpiochip\n");
678 return ret;
679 }
680
681 ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
682 stmfx_pinctrl_irq_thread_fn,
683 IRQF_ONESHOT,
684 pctl->irq_chip.name, pctl);
685 if (ret) {
686 dev_err(pctl->dev, "cannot request irq%d\n", irq);
687 return ret;
688 }
689
690 gpiochip_set_nested_irqchip(&pctl->gpio_chip, &pctl->irq_chip, irq);
691
692 dev_info(pctl->dev,
693 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
694
695 return 0;
696}
697
698static int stmfx_pinctrl_remove(struct platform_device *pdev)
699{
700 struct stmfx *stmfx = dev_get_platdata(&pdev->dev);
701
702 return stmfx_function_disable(stmfx,
703 STMFX_FUNC_GPIO |
704 STMFX_FUNC_ALTGPIO_LOW |
705 STMFX_FUNC_ALTGPIO_HIGH);
706}
707
708#ifdef CONFIG_PM_SLEEP
709static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl)
710{
711 int ret;
712
713 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE,
714 &pctl->bkp_gpio_state, NR_GPIO_REGS);
715 if (ret)
716 return ret;
717 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
718 &pctl->bkp_gpio_dir, NR_GPIO_REGS);
719 if (ret)
720 return ret;
721 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
722 &pctl->bkp_gpio_type, NR_GPIO_REGS);
723 if (ret)
724 return ret;
725 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
726 &pctl->bkp_gpio_pupd, NR_GPIO_REGS);
727 if (ret)
728 return ret;
729
730 return 0;
731}
732
733static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl)
734{
735 int ret;
736
737 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
738 pctl->bkp_gpio_dir, NR_GPIO_REGS);
739 if (ret)
740 return ret;
741 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
742 pctl->bkp_gpio_type, NR_GPIO_REGS);
743 if (ret)
744 return ret;
745 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
746 pctl->bkp_gpio_pupd, NR_GPIO_REGS);
747 if (ret)
748 return ret;
749 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET,
750 pctl->bkp_gpio_state, NR_GPIO_REGS);
751 if (ret)
752 return ret;
753 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
754 pctl->irq_gpi_evt, NR_GPIO_REGS);
755 if (ret)
756 return ret;
757 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
758 pctl->irq_gpi_type, NR_GPIO_REGS);
759 if (ret)
760 return ret;
761 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
762 pctl->irq_gpi_src, NR_GPIO_REGS);
763 if (ret)
764 return ret;
765
766 return 0;
767}
768
769static int stmfx_pinctrl_suspend(struct device *dev)
770{
771 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
772 int ret;
773
774 ret = stmfx_pinctrl_backup_regs(pctl);
775 if (ret) {
776 dev_err(pctl->dev, "registers backup failure\n");
777 return ret;
778 }
779
780 return 0;
781}
782
783static int stmfx_pinctrl_resume(struct device *dev)
784{
785 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
786 int ret;
787
788 ret = stmfx_pinctrl_restore_regs(pctl);
789 if (ret) {
790 dev_err(pctl->dev, "registers restoration failure\n");
791 return ret;
792 }
793
794 return 0;
795}
796#endif
797
798static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops,
799 stmfx_pinctrl_suspend, stmfx_pinctrl_resume);
800
801static const struct of_device_id stmfx_pinctrl_of_match[] = {
802 { .compatible = "st,stmfx-0300-pinctrl", },
803 {},
804};
805MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match);
806
807static struct platform_driver stmfx_pinctrl_driver = {
808 .driver = {
809 .name = "stmfx-pinctrl",
810 .of_match_table = stmfx_pinctrl_of_match,
811 .pm = &stmfx_pinctrl_dev_pm_ops,
812 },
813 .probe = stmfx_pinctrl_probe,
814 .remove = stmfx_pinctrl_remove,
815};
816module_platform_driver(stmfx_pinctrl_driver);
817
818MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver");
819MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
820MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)